WO2021035811A1 - 一种可变动码率与更正能力内存控制方法 - Google Patents

一种可变动码率与更正能力内存控制方法 Download PDF

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WO2021035811A1
WO2021035811A1 PCT/CN2019/105621 CN2019105621W WO2021035811A1 WO 2021035811 A1 WO2021035811 A1 WO 2021035811A1 CN 2019105621 W CN2019105621 W CN 2019105621W WO 2021035811 A1 WO2021035811 A1 WO 2021035811A1
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module
data
inline ecc
control method
inline
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French (fr)
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吴恒毅
魏智汎
洪振洲
陈育鸣
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江苏华存电子科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error

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  • the invention relates to the technical field of memory control methods, in particular to a memory control method with variable code rate and correction capability.
  • the DDR4 memory control method can read and write 8bytes of data at the same time because the width of a channel is 64bit. If it is a memory controller with ECC function and an ECC memory module, then 1 channel The width is 72 bits, and the extra 8 bits are redundant particles, which increases the cost. Therefore, an improved technology is urgently needed to solve this problem in the prior art.
  • the purpose of the present invention is to provide a memory control method for variable bit rate and correction capability to solve the above-mentioned problems in the background art.
  • a memory control method for variable bit rate and correction capability including the following steps:
  • Step 1 Design an error correction Inline ECC module between the traditional DRAM controller and the original application controller;
  • Step 2 The Inline ECC module receives the data packet sent by the application controller
  • Step 3 The Inline ECC module uses the received data to generate 32 sub-packets
  • Step 4 The Inline ECC module is coded by the internal coding module.
  • the coding steps are: write commands when idle, data input, input complete, data output, and then enter the idle state again after confirming that the output is complete;
  • Step 5 The Inline ECC module is decoded by the internal decoding module.
  • the decoding steps are: read command when idle, data input, read data completion, error detection and correction, complete error correction of all sub-packets, data output, and confirm data output completion Then re-enter the idle state;
  • Step 6 Data decoded by the Inline ECC module of the address map in the DRAM.
  • the Inline ECC module implements an AXI-lite control process to connect to a traditional DRAM control module in series, and the Inline ECC module implements a simple R/W Interface to connect to general SoC connection module applications.
  • the encoding module is provided with an encoding state machine, an encoding calculation module, a check code register, and a write data buffer area.
  • a decoding state machine, a decoding calculation module, a read data buffer area and an error correction information register are installed inside the decoding module door.
  • the SOC memory controller needs to have an automatic error correction mechanism. Unlike the mainstream practice that uses additional memory particles as an error correction coding mechanism, this control method provides a method that does not require additional Particles, and can achieve SoC implementation mechanisms that go beyond redundant particle coding, thereby saving costs.
  • Figure 1 is a schematic diagram of the Inline ECC module using a simple read/write interface to connect to the original application controller (GCM_TOP), and the realization of the AXI-lite interface to serially connect the traditional DRAM control module.
  • Figure 2 is a schematic diagram of the Inline ECC module receiving the data packet sent by GCM_TOP.
  • Figure 3 is a schematic diagram of Inline ECC using the received data to generate 32 sub-packets.
  • Figure 4 is a schematic diagram of the encoding state machine flow of Inline ECC.
  • Figure 5 is a schematic diagram of the internal coding module structure of Inline ECC.
  • Fig. 6 is a schematic diagram of the decoding state machine flow of Inline ECC.
  • Figure 7 is a schematic diagram of the internal decoding module structure of Inline ECC.
  • Figure 8 is a schematic diagram of the address mapping in the DRAM.
  • Figure 9 shows the effect of two modes of HC inline ECC on RBER/UBER.
  • the curve from left to right is the schematic diagram of the implementation effect of standard specifications DDR4 (64/72), DDR5 (32/40), HC inline ECC mode1/inline ECC mode2.
  • encoding module 100 state machine 101, encoding calculation module 102, check code register 103, write data buffer area 104, decoding module 200, decoding state machine 201, decoding calculation module 202, read data buffer area 203, error correction Information register 204.
  • the present invention provides a technical solution: a memory control method for variable code rate and correction capability, including the following steps:
  • Step 1 As shown in Figure 1, design an error correction Inline ECC module between the traditional DRAM controller and the original application controller;
  • Step 2 The Inline ECC module receives the data packet sent by the application controller
  • Step 3 The Inline ECC module uses the received data to generate 32 sub-packets
  • Step 4 The Inline ECC module is coded by the internal coding module.
  • the coding steps are: write commands when idle, data input, input complete, data output, and then enter the idle state again after confirming that the output is complete;
  • Step 5 The Inline ECC module is decoded by the internal decoding module.
  • the decoding steps are: read command when idle, data input, read data completion, error detection and correction, complete error correction of all sub-packets, data output, and confirm data output completion Then re-enter the idle state;
  • Step 6 Data decoded by the Inline ECC module of the address map in the DRAM.
  • the Inline ECC module implements the AXI-lite control flow to connect to the traditional DRAM control module in series, and the Inline ECC module implements a simple R/W Interface to connect to the general SoC connection module application.
  • the encoding module is provided with an encoding state machine, an encoding calculation module, a check code register, and a write data buffer area.
  • step 5 a decoding state machine, a decoding calculation module, a read data buffer area and an error correction information register are installed inside the decoding module door.
  • each coding substructure packet is not limited to 1Kbit coding, and can be 2Kbit/3Kbit/..., and there is no limitation to fixed-length coding.
  • Each encoded packet is not limited to 32 1Kbit arrangements. It can be 16/64/128 and other codes with unlimited number of subpackets.
  • the correction capability of each substructure packet is not limited to mode1 (4bit correction capability)/mode2 (8bit correction capability), and can be a random number of correction capability codes.
  • HC Inline ECC supports the encoding of data packets in multiple formats: variable data length; variable metadata length.
  • Inline ECC in this example supports data lengths of 4096 bytes and 4160 bytes, and metadata lengths of 4 to 32 bytes.
  • HC Inline ECC redistributes the received data packets.
  • Inline ECC divides the data into 32 sub-packets, and each sub-packet can generate an independent check code, which is stored immediately after the corresponding sub-packet data.
  • the 4096-byte data packet can be divided into 32 1024-byte sub-packets; for the 4160-byte data packet, the extra 64-byte data is evenly distributed among the first 4 sub-packets, so that both It does not waste the computing power of the encoder, but also makes the bit rate of each sub-packet more even.
  • the encoding state machine of Inline ECC has three states: idle, data input, and data output.
  • the data input and encoding are performed at the same time in this example, so there is no special encoding state in the state machine.
  • Idle state Inline ECC can receive a new write command, and enter the data input stage when the write command is received;
  • Inline ECC can receive the input of the data packet, and the encoder can calculate the check code. As shown in Figure 3, each sub-packet has a check code, and the data packet input is completed (Inline ECC generates a total of 32 check codes). Code verification) then enter the data output stage;
  • Inline ECC output data packet + check code + metadata, output in the order of "sub-packet data, check code, sub-packet data, check code --, and finally output metadata, in this example, Inline ECC supports separate storage of data and metadata, and enters an idle state after the output is completed.
  • HC Inline ECC coding module design.
  • the encoding module 100 is composed of four parts: an encoding state machine 101, an encoding calculation module 102, a check code register 103, and a write data buffer area 104.
  • the encoding state machine 101 controls the encoding process of the data packet: GCM_TOP inputs the data packet, calculates the check code, and outputs the data and the check code to the DRAM control module;
  • the code calculation module 102 calculates and outputs a check code according to the input data, and the check code is stored in the check code register 103;
  • the check code register 103 stores the check codes of 32 sub-packets in the data input stage, and the output is controlled by the state machine in the data output stage;
  • the write data buffer area 104 stores the entire data packet in the data input stage, and the output is controlled by the state machine in the data output stage;
  • the sequence of data output is "sub-packet data, check code, sub-packet data, check code" and finally output metadata.
  • the decoding state machine of Inline ECC has 4 states: idle, data input, error detection and correction, and data output.
  • Idle state Inline ECC can receive a new read command, and enter the data input stage after receiving the read command;
  • Inline ECC sends a data read command to the DRAM controller through the AXI-lite interface, and receives the read data (including data, check code and metadata) returned by the DRAM controller, and then Inline ECC through the AXI-lite interface Send the read metadata command to the DRAM controller, and receive the metadata returned by the DRAM controller, and enter the error detection and correction stage after the acceptance is completed;
  • Error detection and correction write a sub-packet into the decoding calculation module in the order of "sub-packet data, check code", and save the error correction information output by it in the error correction information buffer area, after collecting the error correction information Perform error correction operations on this sub-packet. After the error correction of 32 sub-packets is completed in this way, it enters the data output stage;
  • Inline ECC outputs a data packet composed of 32 sub-packets (not including check code) to GCM_TOP, the data packet is followed by metadata, and the output is completed and enters the idle state.
  • the decoding module 200 is composed of 4 partial blocks: a decoding state machine 201, a decoding calculation module 202, a read data buffer area 203, and an error correction information register 204.
  • the decoding state machine 201 controls the decoding process of the data packet: parsing the read command issued by GCM_TOP, reading the codeword and metadata from the DRAM, checking and correcting the codeword error, and outputting the decoded data and metadata to GCM_TOP;
  • the decoding calculation module 202 calculates and outputs the error detection result and error correction information according to the input sub-codeword, and the error detection information is stored in the error correction information register 204;
  • the read data buffer area 203 stores the entire code word in the data input stage, the state machine controls the output code word or error correction in the error detection and error correction stage, and outputs the data under the control of the state machine in the data output stage (the check code is not output);
  • the error correction information memory 204 stores the error correction information in the error detection and correction stage, and outputs the error correction information under the control of the state machine 201 to correct the codewords in the read data buffer area 203.
  • the address offset is 0, so the first sub-packet storage address is the data starting address.
  • the first sub-packet storage address needs to be sent, and the subsequent data and verification The code storage addresses are all added on their basis.
  • each sub-codeword is "sub-packet + check code", and the decoding process is also input to the decoding calculation module in this order.
  • inline ECC mode 1 and inline ECC mode 2 are selected for comparison with the traditional ECC control method.
  • HC inline ECC mode1 uses a correction codec engine that can protect 8bit random error correction capabilities per 1Kbit.
  • HC inline ECC mode2 uses a correction codec engine that can protect 4bit random error correction capabilities per 1Kbit.
  • the DDR4 ECC/DDR5 ECC encoding method can only reduce UBER to E-10.5 and E-11, but the inline ECC mode2 encoding mechanism of the present invention can reduce UBER more effectively. To around E-13.8.
  • the DDR4 ECC/DDR5 ECC encoding method can only reduce the UBER to E-8.5 and E-9.5, but the inline-ECC mode1 encoding mechanism of the present invention can more effectively reduce the UBER Drop to around E-18.
  • HC inline ECC uses fewer redundants, but achieves a lower bit error rate in the application of SoC chips.

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Abstract

一种可变动码率与更正能力内存控制方法，在传统DRAM控制器与原本应用控制器中间设计一个错误更正的Inline ECC模块，该控制方法不同于主流作法使用额外内存颗粒来做为错误更正编译码机制，该控制方法提供一种无须额外颗粒，而能够达到超越冗余颗粒编码法的SoC实现机制，从而节省了成本。

Description

一种可变动码率与更正能力内存控制方法 技术领域
本发明涉及内存控制方法技术领域，具体为一种可变动码率与更正能力内存控制方法。
背景技术
以目前的计算机系统与SOC来说，DDR4内存控制方法因为1组channel的宽度为64bit，所以能够同时读写8byte的数据，如果是具有ECC功能的内存控制器和ECC内存模块，那么1组channel的宽度就是72bit，额外的8bit即是冗余颗粒，使得成本增加，因此，亟待一种改进的技术来解决现有技术中所存在的这一问题。
发明内容
本发明的目的在于提供一种可变动码率与更正能力内存控制方法，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：一种可变动码率与更正能力内存控制方法，包括以下步骤：
步骤一：在传统DRAM控制器与原本应用控制器中间设计一个错误更正的Inline ECC模块；
步骤二：Inline ECC模块接收到应用控制器发送的数据包；
步骤三：Inline ECC模块用收到的数据生成32个子封包；
步骤四：Inline ECC模块通过内部的编码模块进行编码，编码步骤为：空闲时写命令，数据输入，输入完成，数据输出，确认输出完成后重新进入空闲状态；
步骤五：Inline ECC模块通过内部的解码模块进行解码，解码步骤为：空闲时读命令，数据输入，读数据完成，检错纠错，完成所有子封包的纠错，数据输出，确认数据输出完成后重新进入空闲状态；
步骤六：DRAM中地址映像Inline ECC模块解码的数据。
优选的，所述步骤一中Inline ECC模块实现了AXI-lite控制流程以串接传统DRAM控制模块，所述Inline ECC模块实现了简单的R/W Interface来连接一般SoC的连接模块应用。
优选的，所述步骤四中编码模块内部设置有编码状态机、编码计算模块、校验码寄存器及写数据缓存区。
优选的，所述步骤五中解码模块门内部安装有解码状态机、解码计算模块、读数据缓存区及纠错信息寄存器。
与现有技术相比，本发明的有益效果是：
当内存的容量与制程随时间一直推演进步时，SOC内存控制器须要有自动错误更正的机制，不同于主流作法使用额外内存颗粒来做为错误更正编译码机制，本控制方法提供一种无须额外颗粒，而能够达到超越冗余颗粒编码法的SoC实现机制，从而节省了成本。
附图说明
图1为Inline ECC模组用简单的读/写接口连接原本的应用控制器(GCM_TOP)，并实现了用AXI-lite接口串接传统DRAM控制模组示意图。
图2为Inline ECC模组接收GCM_TOP发送的数据包示意图。
图3为Inline ECC用收到的数据生成32个子封包示意图。
图4为Inline ECC的编码状态机流程示意图。
图5为Inline ECC的内部编码模块结构示意图。
图6为Inline ECC的解码状态机流程示意图。
图7为Inline ECC的内部解码模块结构示意图。
图8为DRAM中的地址映像示意图。
图9为HC inline ECC其中两个mode针对RBER/UBER的效果。曲线由左至右分别为标准规格DDR4(64/72),DDR5(32/40)，HC inline ECC mode1/inline ECC mode2的实现效果示意图。
图中：编码模块100、状态机101、编码计算模块102、校验码寄存器103、写数据缓存区104、解码模块200、解码状态机201、解码计算模块202、读数据缓存区203、纠错信息寄存器204。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明提供一种技术方案：一种可变动码率与更正能力内存控制方法，包括以下步骤：
步骤一：如图1所示，在传统DRAM控制器与原本应用控制器中间设计一个错误更正的Inline ECC模块；
步骤二：Inline ECC模块接收到应用控制器发送的数据包；
步骤三：Inline ECC模块用收到的数据生成32个子封包；
步骤四：Inline ECC模块通过内部的编码模块进行编码，编码步骤为：空闲时写命令，数据输入，输入完成，数据输出，确认输出完成后重新进入空闲状态；
步骤五：Inline ECC模块通过内部的解码模块进行解码，解码步骤为：空闲时读命令，数据输入，读数据完成，检错纠错，完成所有子封包的纠错，数据输出，确认数据输出完成后重新进入空闲状态；
步骤六：DRAM中地址映像Inline ECC模块解码的数据。
其中，步骤一中Inline ECC模块实现了AXI-lite控制流程以串 接传统DRAM控制模块，Inline ECC模块实现了简单的R/W Interface来连接一般SoC的连接模块应用。
其中，步骤四中编码模块内部设置有编码状态机、编码计算模块、校验码寄存器及写数据缓存区。
其中，步骤五中解码模块门内部安装有解码状态机、解码计算模块、读数据缓存区及纠错信息寄存器。
其中，编码数据结构与流程中，每个编码子结构封包并不限于1Kbit编码，可以是2Kbit/3Kbit/…，不限固定长度的编码。每个编码封包并不限于32个1Kbit排列。可以是16/64/128等不限子封包个数的编码。每个子结构封包更正能力并不限于mode1(4bit更正能力)/mode2(8bit更正能力)，可以是随机数量更正能力的编码。
实施例的：
如图2所示，HC Inline ECC支持多种格式数据包的编码：可变动的数据长度；可变动的元数据长度。
本例中的Inline ECC支持数据长度为4096字节和4160字节，元数据长度为4～32字节。
如图3所示，HC Inline ECC对接收到的数据包进行再分配。
本例中Inline ECC将数据分成32个子封包，每个子封包可生成独立的校验码，保存时紧随其对应的子封包数据之后。本例中对4096 字节的数据包可以分成32个1024字节的子封包；对于4160字节的数据包，将其多出的64字节数据平均分配在前4个分包内，这样既可以不浪费编码器的算力，又能使每个子封包的码率更平均。
如图4所示，HC Inline ECC的编码状态机。
本例中Inline ECC的编码状态机有三个状态：空闲、数据输入、数据输出。为了提高数据包的处理速度，本例中数据输入与编码同时进行，因此状态机中没有特别设立编码状态。
空闲状态：Inline ECC可以接收新的写命令，接收到写命令则进入数据输入阶段；
数据输入状态：Inline ECC可以接收数据包的输入，同时编码器可以计算校验码，如图3所示，每个子封包分别有一笔校验码，数据包输入完成(Inline ECC共生成32笔校验码)则进入数据输出阶段；
数据输出状态：Inline ECC输出数据包+校验码+元数据，按照“子封包数据、校验码、子封包数据、校验码……”的顺序输出，最后输出元数据，本例中Inline ECC支持数据与元数据分开存储，输出完成后进入空闲状态。
如图5所示，,HC Inline ECC编码模块设计。
本例中编码模块100共有4个部分组成：编码状态机101、编码 计算模块102、校验码寄存器103和写数据缓存区104。
编码状态机101控制数据包的编码过程：GCM_TOP输入数据包，校验码的计算，输出数据和校验码至DRAM控制模块；
编码计算模块102根据输入的数据计算并输出校验码，校验码保存在校验码寄存器103中；
校验码寄存器103在数据输入阶段存储32个子封包的校验码，在数据输出阶段由状态机控制输出；
写数据缓存区104在数据输入阶段存储整个数据包，在数据输出阶段由状态机控制输出；
数据输出的顺序为“子封包数据、校验码、子封包数据、校验码……”最后输出元数据。
如图6所示，HC Inline ECC的解码状态机。
本例中Inline ECC的解码状态机有4个状态：空闲、数据输入、检错纠错、数据输出。
空闲状态：Inline ECC可以接收新的读命令，接收到读命令后进入数据输入阶段；
数据输入状态：Inline ECC通过AXI-lite接口给DRAM控制器发送读数据命令，并接收DRAM控制器返回的读数据(包含数据和校验码和元数据)，然后Inline ECC，通过AXI-lite接口给DRAM控 制器发送读元数据命令，并接收DRAM控制器返回的元数据，接受完成后进入检错纠错阶段；
检错纠错：将一个子封包按照“子封包数据、校验码”的顺序写入解码计算模块，并将其输出的纠错信息保存在纠错信息缓存区内，收集纠错信息完成后对该子封包进行纠错操作。以这种方式对32个子封包纠错完成后，进入数据输出阶段；
数据输出：Inline ECC将32笔子封包(不包括校验码)组成的数据包输出至GCM_TOP，数据包后面接元数据，输出完成进入空闲状态。
如图7所示，Inline ECC解码模块设计。
本例中解码模块200共由4个部分块组成：解码状态机201、解码计算模块202、读数据缓存区203和纠错信息寄存器204。
解码状态机201控制数据包的解码过程：解析GCM_TOP发出的读命令、从DRAM读出码字和元数据、对码字检错纠错、输出解码后的数据和元数据至GCM_TOP；
解码计算模块202根据输入的子码字计算并输出检错结果和纠错信息，检错信息保存在纠错信息寄存器204中；
读数据缓存区203在数据输入阶段存储整个码字，在检错纠错阶段由状态机控制输出码字或纠错，在数据输出阶段在状态机控制下 输出数据(不输出校验码)；
纠错信息存储器204在检错纠错阶段存储纠错信息，并由状态机201控制下输出纠错信息对读数据缓存区203内的码字纠错。
如图8所示，DRAM中的地址映像。
本例中地址偏移量为0，因此第一笔子封包存储地址即为数据起始地址，事实上，实际操作中只需发送第一笔子封包存储地址即可，之后的数据及校验码存储地址都是在其基础上相加得到。
如图中所示，每一笔子码字的格式都是“子封包+校验码”，在译码过程也是按此顺序输入解码计算模块。
实施例的，选用inline ECC mode1和inline ECC mode2与传统ECC控制方法作对比。
HC inline ECC mode1使用每1Kbit能够保护8bit随机错误更正能力的更正编译码引擎。
HC inline ECC mode2使用每1Kbit能够保护4bit随机错误更正能力的更正编译码引擎。
如图9所示，分别列出目前标准内存ECC控制方法中DDR4/DDR5的效果，与本发明中inline ECC编码法的差异。
当原始的DRAM颗粒RBER为0.5E-4时，DDR4 ECC/DDR5 ECC编码法只能将UBER降到E-10.5与E-11，但本发明的inline ECC mode2 编码机制可以更有效的将UBER降到E-13.8左右。
当原始的DRAM颗粒RBER为1.5E-4时，DDR4 ECC/DDR5 ECC编码法只能将UBER降到E-8.5与E-9.5，但本发明的inline-ECC mode1编码机制可以更有效的将UBER降到E-18左右。
由redundant bit来看，DDR4有8/72＝11％。
由redundant bit来看，DDR5有8/40＝20％。
由redundant bit来看，HC inline ECC mode1有44/(1024+44)＝4.12％。
由redundant bit来看，HC inline ECC mode2有88/(1024+88)＝7.9％。
HC inline ECC使用了更少的redundant，但实现出了更底的误码率在SoC芯片的应用上。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同物限定。

Claims (4)

  1. 一种可变动码率与更正能力内存控制方法，其特征在于：包括以下步骤：
    步骤一：在传统DRAM控制器与原本应用控制器中间设计一个错误更正的Inline ECC模块；
    步骤二：Inline ECC模块接收到应用控制器发送的数据包；
    步骤三：Inline ECC模块用收到的数据生成32个子封包；
    步骤四：Inline ECC模块通过内部的编码模块进行编码，空闲时写命令，数据输入，输入完成，数据输出，确认输出完成后重新进入空闲状态；
    步骤五：Inline ECC模块通过内部的解码模块进行解码，空闲时读命令，数据输入，读数据完成，检错纠错，完成所有子封包的纠错，数据输出，确认数据输出完成后重新进入空闲状态；
    步骤六：DRAM中地址映像Inline ECC模块解码的数据。
  2. 根据权利要求1所述的一种可变动码率与更正能力内存控制方法，其特征在于：所述步骤一中Inline ECC模块实现了AXI-lite控制流程以串接传统DRAM控制模块，所述Inline ECC模块实现了简单的R/W Interface来连接一般SoC的连接模块应用。
  3. 根据权利要求1所述的一种可变动码率与更正能力内存控制方法，其特征在于：所述步骤四中编码模块内部设置有编码状态机、 编码计算模块、校验码寄存器及写数据缓存区。
  4. 根据权利要求1所述的一种可变动码率与更正能力内存控制方法，其特征在于：所述步骤五中解码模块门内部安装有解码状态机、解码计算模块、读数据缓存区及纠错信息寄存器。
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