WO2021031808A1

WO2021031808A1 - Drive circuit, drive method, transient enhanced ldo circuit, cmos driver power supply circuit and laser system

Info

Publication number: WO2021031808A1
Application number: PCT/CN2020/105255
Authority: WO
Inventors: 刘建峰; 向少卿
Original assignee: 上海禾赛光电科技有限公司
Priority date: 2019-08-20
Filing date: 2020-07-28
Publication date: 2021-02-25

Abstract

Disclosed are a drive circuit (200, 300, 400), a drive method (500) and a laser system (100). The drive circuit (200, 300, 400) comprises: a narrow pulse generator (210) configured to generate a first narrow pulse (22) on the basis of an input pulse (20), wherein the pulse width of the first narrow pulse (22) is smaller than the pulse width of the input pulse (20); a voltage adjuster (220) configured to be capable of generating an adjustable output voltage; and a drive unit (230) coupled to the narrow pulse generator (210) and the voltage adjuster (220) and configured to form a second narrow pulse (24) on the basis of the first narrow pulse (22) and the output voltage, wherein the second narrow pulse (24) is suitable for driving a switch transistor (240), the pulse width is approximately equal to the pulse width of the first narrow pulse (22), and the amplitude of the second narrow pulse (24) depends on the magnitude of the output voltage of the voltage adjuster (220). Thus, an output pulse with independently adjustable pulse width and amplitude can be formed. When such an output pulse is used for driving a laser (252), the light emission energy of the laser (252) can be quickly adjusted in a large dynamic range.

Description

Drive circuit, drive method, transient enhanced LDO circuit, CMOS driver power supply circuit and laser system

Technical field

The present disclosure generally relates to the technical field of circuits, and more specifically, to a driving circuit, a driving method, a transient enhanced LDO circuit, a power supply circuit of a CMOS driver, and a laser system.

Background technique

In the application of laser light source systems, it is often necessary to consider the physical characteristics of laser light sources such as laser diodes (LDs), which require very high driving currents for laser diodes, and must be a constant current source with low noise and high stability. With a stable power drive, the laser pulse waveform can be stable, and to make the laser pulse work stably, a precise pulse generator is required.

The working principle of lidar is to transmit a detection signal (laser beam or light signal) to the target, and then compare the received signal (target echo) from the target with the transmitted detection signal, and after appropriate processing, it can be Obtain information about the target, such as distance and bearing. In order to achieve high ranging accuracy, long detection distance, and high scanning rate, a laser is required to generate a laser pulse signal with fast leading edge, high peak current, and narrow pulse width, which is used as a detection signal. If the leading edge of the laser beam is fast, the time error is small, and the equivalent distance error is small. The higher the peak current of the laser pulse, the longer the distance at which the energy decays to zero, and the narrower the pulse width, the more laser pulses can be emitted continuously in the same time interval. In order to ensure that there is no saturation distortion for long, medium and short-range detection, it is required that the luminous energy of the laser can be dynamically adjusted in a wide range. For example, a pulse signal with large energy can be emitted at a long distance, and a pulse signal with a large energy can be emitted at a long distance. Transmit a small energy pulse signal at distance. Since the performance of the laser source itself is generally good enough to fully meet the requirements of fast leading edge, high peak current, and narrow pulse width, the main factor affecting the signal quality of the laser pulse output by the laser radar is the performance of the laser radar drive circuit.

Figure 1 illustrates a schematic diagram of a laser system 100 in the prior art, in which the laser diode LD is grounded through a power FET, and the power FET is turned on and off through the gate of the power FET. It is controlled by a gate driver 110 coupled to the pole. The input of the gate driver 110 is the input pulse 112, and the pulse width of the input pulse 112 ultimately determines the pulse width of the laser pulse emitted by the laser diode LD. The conduction state of the power FET and the power supply voltage HV of the laser diode LD can be used to control the luminous energy of the laser diode LD. In the laser system 100 shown in FIG. 1, generally, the luminous energy value of the finally emitted laser pulse is changed by controlling the width of the input pulse of the driver or the power supply voltage of the high voltage HV. The luminous energy is equal to the luminous power multiplied by the duration of the pulse (ie pulse width), and the luminous power is proportional to the current through the laser diode LD. Therefore, according to the inventor’s knowledge, there are generally two ways to change the luminescence of the laser diode LD energy of.

In the first way, the luminous energy can be changed proportionally by changing the pulse width of the input pulse of the driver. However, the method of changing the pulse width of the input pulse to change the luminous energy will cause the optical signal output pulse of the laser diode to become wider, and the pulse width will limit the interval between adjacent pulses, which will increase the measurement deadlock. It is impossible to achieve higher frequency laser pulse emission due to limited time. At the same time, only through this method, because the peak current of the pulse does not change, the detection distance corresponding to the unsaturated distortion does not change, so it is impossible to realize the long-distance, medium-distance and short-distance unsaturated distortion detection at the same time.

In the second method, assuming that the on-resistance of the laser diode LD and the power FET is a fixed value, the current flowing into the laser diode can be changed by changing the HV, thereby realizing the change of the luminous energy. However, for the method of changing the HV to change the luminous energy, one problem is that the HV is generated by the booster circuit, and the HV needs to be changed by controlling the booster circuit. However, the switching rate of the booster circuit is low, which will cause a problem between two adjustments. A long stabilization time is left, that is, rapid adjustment cannot be achieved. Another problem is that in a multi-channel lidar system, HV is generally shared by multiple channels. If HV is used to independently control the luminous energy of each channel, the system needs to have multiple independent boost circuits, which greatly increases System complexity.

Low-dropout linear regulators (LDOs), due to their low output noise, low voltage drop, and low cost, have been widely used in portable electronic products. In the high-speed digital circuit regulated by LDO, the main frequency is getting higher and higher, even reaching several GHz. The instantaneous jump of the level in the digital circuit will cause the instantaneous jump of the current. Regarding the digital circuit as the load of the LDO, the instantaneous jump of the load current will affect the output voltage of the LDO. The transient response of LDO includes linear transient response and load transient response. The linear transient response refers to the response of the LDO output voltage when the input voltage step changes suddenly; the load transient response refers to the LDO output response when the load current step changes suddenly.

With the development of the electronics industry and the progress of the society, there continues to be a need to improve the transient response of the LDO circuit.

The content of the background technology is only the technology known to the public, and does not of course represent the existing technology in the field.

Summary of the invention

In view of at least one of the defects in the prior art, one of the objectives of the technical solutions described in the present disclosure is to provide an improved driving circuit.

In one aspect, a drive circuit is provided, which includes: a narrow pulse generator configured to generate a first narrow pulse based on an input pulse, the pulse width of the first narrow pulse being smaller than that of the input pulse; voltage adjustment A device configured to generate an adjustable output voltage; and a driving unit, coupled to the narrow pulse generator and the voltage regulator, and configured to be based on the first narrow pulse and the output voltage To form a second narrow pulse, wherein the second narrow pulse is suitable for driving the switch tube, the pulse width is approximately equal to the pulse width of the first narrow pulse, and the amplitude of the second narrow pulse depends on the output voltage of the voltage regulator. According to this driving circuit, it is possible to form an output pulse whose pulse width and amplitude are independently adjustable. When such an output pulse is used to drive a laser radar, the luminous energy of the semiconductor laser can be quickly adjusted in a large dynamic range.

In one embodiment, the voltage regulator may include: a voltage-type digital-to-analog converter configured to receive digitally controlled input from a voltage DAC and generate an analog voltage; a voltage follower, and the voltage-type digital-to-analog converter The analog converter and the driving unit are coupled, and are configured to stabilize the analog voltage output by the voltage-type digital-to-analog converter and output the adjustable output voltage.

In one embodiment, the voltage follower may include an operational amplifier, a first PMOS transistor (M0), and a capacitor (C1). The inverting input terminal of the operational amplifier is coupled to the voltage-type digital-to-analog converter, the non-inverting input terminal of the operational amplifier is coupled to the drain of the first PMOS transistor (M0), and the output terminal of the operational amplifier is coupled to the first PMOS transistor (M0). The gate of a PMOS transistor (M0) is coupled. The source of the first PMOS transistor (M0) is coupled to the power supply voltage (VDD), and the drain of the first PMOS transistor (M0) is grounded through the capacitor (C1).

In one embodiment, the narrow pulse generator may include: a current-type digital-to-analog converter configured to receive a current DAC digitally controlled input and generate an output current; a current control delay unit configured to receive the input pulse and be coupled to the The current-type digital-to-analog converter to delay the input pulse according to the output current of the current-type digital-to-analog converter; an in-phase buffer configured to temporarily store the input pulse; and a logical AND gate, which The first input terminal is connected to the current control delay unit, and the second input terminal is connected to the in-phase buffer (I2), and is configured to generate the first input pulse based on the delayed input pulse and the temporarily stored input pulse. Narrow pulse, wherein the pulse width of the first narrow pulse is the delay difference between the temporarily stored input pulse and the delayed input pulse.

In one embodiment, the driving unit may include: a second PMOS transistor (M1) and a first NMOS transistor (M2). The gate of the second PMOS transistor (M1) is connected to the gate of the first NMOS transistor (M2), and is configured to receive the first narrow pulse output by the narrow pulse generator. The source of the second PMOS transistor (M1) is connected to the voltage regulator and is configured to receive the output voltage of the voltage regulator, and the source of the first NMOS transistor (M2) is grounded. The drain of the second PMOS transistor (M1) is connected to the drain of the first NMOS transistor (M2) and is configured to output the second narrow pulse.

In one embodiment, the driving unit may further include: a pre-driving unit, the input terminal of which is connected to the output terminal of the narrow pulse generator, and is configured to measure the current driving capability of the received first narrow pulse. Level or multi-level amplification.

In one embodiment, the pre-driving unit may include cascaded multi-stage inverting amplifiers.

In another aspect, a driving method is provided, which includes: generating a first narrow pulse based on an input pulse, the first narrow pulse having a pulse width smaller than that of the input pulse; generating an adjustable output voltage; and The first narrow pulse and the output voltage generate a second narrow pulse, wherein the pulse width of the second narrow pulse is approximately equal to the pulse width of the first narrow pulse, and the amplitude of the second narrow pulse depends on For the size of the adjustable output voltage.

In one embodiment, said generating an adjustable output voltage further includes: receiving a digitally controlled input through a voltage-type digital-to-analog converter and generating an analog voltage; and performing a stabilizing operation on the analog voltage output by the voltage-type digital-to-analog converter , To produce the adjustable output voltage.

In one embodiment, the generating of the first narrow pulse based on the input pulse further includes: receiving the input pulse, temporarily storing the input pulse; receiving a digitally controlled input through a current-type digital-to-analog converter and generating an output current; receiving the Input pulse, delay the input pulse according to the output current of the current-type digital-analog converter; and generate the first narrow pulse based on the delayed input pulse and the temporarily stored input pulse.

In an embodiment, the generating a second narrow pulse based on the first narrow pulse and the output voltage further includes: performing one-stage or multi-stage amplification on the current driving capability of the received first narrow pulse .

In yet another aspect, a laser system is provided, including: the aforementioned narrow pulse drive circuit; a laser, and a transistor, the gate of which is coupled to the output end of the narrow pulse high-power device drive circuit, and the second narrow pulse is used for To control the switching of the transistor, its source is grounded, and its drain is coupled to the laser.

In an embodiment, the laser further includes: a laser diode, a resistor, a second capacitor, and a freewheeling diode, and the transistor is an NMOS high-power transistor. The cathode of the laser diode is coupled to the drain of the NMOS high-power transistor, the anode of the laser diode passes through the first end of the resistor, and the second end of the resistor is coupled to a second supply voltage (HV) , The anode of the freewheeling diode is coupled to the cathode of the laser diode, the cathode of the freewheeling diode is coupled to the second end of the resistor, and between the second end of the resistor and ground The second capacitor is arranged in between.

The advantages of the embodiments of the present disclosure are at least manifested in the following aspects:

1. Both the pulse width of the first narrow pulse and the amplitude of the current flowing through the laser diode can be adjusted digitally, which makes it easy to adjust the luminous energy of the laser quickly and with a large dynamic range.

2. The pulse width of the first narrow pulse and the amplitude of the current flowing through the laser diode are two independently adjustable quantities, which can be adjusted according to the needs of the system. For example, the pulse width can be kept at 3ns, and the current peak value can be changed to ensure the emission at the same time. The pulse width of the laser pulse is narrow, the leading edge is fast, the luminous energy can be adjusted in a large range, and it does not exceed the laser energy threshold specified by human eye safety.

3. By adjusting the MOSFET gate voltage range, a very high output current control ratio range can be obtained. For example, the input voltage changes 4 times (0.95V～6.2V), and the output current can change 389 times (202mA～78.67A).

One of the objectives of the technical solutions described in the present disclosure is to provide a transient enhanced LDO circuit, which can improve the transient response of the LDO circuit.

According to one aspect of the present disclosure, there is provided a transient enhanced LDO circuit, including: an amplifier, one of the input terminals of the amplifier can receive a reference voltage; a power regulator tube, coupled to the output of the amplifier, and output The output voltage of the transient enhanced LDO circuit is used to drive a load; a voltage divider is coupled to the power regulator tube, and the terminal of the power regulator tube that outputs the output voltage is coupled to another input terminal of the amplifier And a sink current absorption circuit, coupled to the output voltage of the amplifier and the output terminal of the power regulator tube, and conducts and absorbs the output voltage according to the fluctuation of the output voltage Sink current.

In one embodiment, the sink current sink circuit may include a comparator and a pull-down NMOS transistor driven by the comparator, wherein one input terminal of the comparator receives an input signal reflecting the fluctuation of the output voltage, and the comparison The other input terminal of the device receives a threshold signal corresponding to the input signal reflecting the fluctuation of the output voltage, the pull-down NMOS tube is coupled to the output terminal of the power regulator tube and the comparator, wherein when the When the output voltage fluctuates, the pull-down NMOS transistor is turned on and absorbs the sink current of the output voltage; when the output voltage does not fluctuate, the pull-down NMOS transistor is turned off.

Further, the comparator may be a current comparator, the one input terminal of the comparator is connected to the intermediate stage of the amplifier to receive a current reflecting the fluctuation of the output voltage, and the other input terminal is connected to With reference to the current signal, the output terminal is connected to the gate of the pull-down NMOS transistor.

Further, the inverting input terminal of the amplifier is used to connect to a reference voltage, the non-inverting input terminal is coupled to the output terminal of the power regulating tube through the voltage divider, and the amplifier output terminal is connected to the power regulating tube through a buffer.的Grid. The voltage divider is a resistance voltage divider, which includes a first resistor and a second resistor connected in series, the source of the power regulator is used to connect to a voltage source (VDD), and the drain of the power regulator outputs the output voltage , And grounded through the voltage divider. The drain of the pull-down NMOS transistor is coupled to the drain of the power regulator, and the source is grounded.

In an embodiment, the transient enhanced LDO circuit may further include a first capacitor and a third resistor connected in parallel with the voltage divider.

Further, the amplifier (A1) can adopt a folded cascode structure.

In one embodiment, the amplifier (A1) includes: a first PMOS tube (MP1), a second PMOS tube (MP2), a third PMOS tube (MP3), a fourth PMOS tube (MP4), and a fifth PMOS tube (MP5). ), sixth PMOS tube (MP6), seventh PMOS tube (MP7), eighth PMOS tube (MP8), first NMOS tube (MN1), second NMOS tube (MN2), third NMOS tube (MN3), And the fourth NMOS tube (MN4). The first PMOS tube (MP1) and the second PMOS tube (MP2) form a differential input pair tube. The gate of the first PMOS tube (MP1) is used as the inverting input terminal of the error amplifier (A1) for connecting the reference voltage, The gate of the second PMOS tube (MP2) is used as the non-inverting input terminal of the error amplifier (A1). The third PMOS tube (MP3) and the fourth PMOS tube (MP4) constitute a cascode current source, and the drain of the fourth PMOS tube (MP4) is connected to the drain of the first PMOS tube (MP1) and the second PMOS tube (MP2) drain. The first NMOS tube (MN1), the second NMOS tube (MN2), the third NMOS tube (MN3) and the fourth NMOS tube (MN4) form a cascode current source, and the source of the second NMOS tube (MN2) is connected To the drain of the first NMOS tube (MN1) and connected to the drain of the second PMOS tube (MP2), the source of the fourth NMOS tube (MN4) is interconnected with the drain of the third NMOS tube (MN3), connected To the drain of the first PMOS tube (MP1) and used as the first intermediate output terminal. The fifth PMOS tube (MP5), the sixth PMOS tube (MP6), the seventh PMOS tube (MP7) and the eighth PMOS tube (MP8) constitute a cascode current mirror load, the fifth PMOS tube (MP5) and the seventh The gate of the PMOS tube (MP7) is interconnected and connected to the drain of the second NMOS tube (MN2), and used as the second intermediate output terminal; the sixth PMOS tube (MP6) and the eighth PMOS tube (MP8) The gates are interconnected and used as the third intermediate output terminal. The drains of the eighth PMOS tube (MP8) and the fourth NMOS tube (MN4) are interconnected and used as the output terminal of the error amplifier (A1).

In an embodiment, the comparator may include: a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a ninth PMOS transistor (MP9), and a tenth PMOS transistor (MP10). The fifth NMOS tube (MN5) and the sixth NMOS tube (MN6) form a cascode structure and serve as the threshold current terminal of the current comparator (A3). The ninth PMOS tube (MP9) and the tenth PMOS tube (MP10) form a cascode structure and are used as the signal current terminal of the current comparator (A3). The drain of the tenth PMOS transistor (MP10) is connected to the drain of the sixth NMOS transistor (MN6) and is used to connect to the gate of the pull-down NMOS transistor (MN0).

In another aspect of the present disclosure, there is also provided a power supply circuit for a CMOS driver, which includes: the transient enhancement type LDO circuit described in any one of the foregoing; and a voltage-type digital-to-analog converter connected to the LDO circuit and configured In order to convert the received digital control input into an analog voltage, it is used as the reference voltage of the error amplifier (A1) of the LDO circuit.

In another aspect of the present disclosure, there is also provided a laser system, which includes: the aforementioned power supply circuit; and a laser connected to the power supply circuit.

The embodiment of the present disclosure proposes a transient enhanced LDO circuit structure, which can be used to power a CMOS driver by being combined with a power supply. This LDO can achieve high-speed charge extraction or injection by connecting a large capacitor outside the chip, and can quickly recover the voltage overshoot on the LDO output capacitor through the transient response enhancement technology.

The features and advantages described in the specification are not all, in particular, many additional features and advantages will be apparent to those of ordinary skill in the art in conjunction with the drawings and the specification. In addition, it should be pointed out that the terms used in this specification are mainly selected for readability and instructional purposes, and may not be selected to describe or limit the inventive technical solution.

Description of the drawings

The drawings constituting a part of the present disclosure are used to provide a further understanding of the present disclosure, and the exemplary embodiments and descriptions of the present disclosure are used to explain the present disclosure, and do not constitute an improper limitation of the present disclosure. In the attached picture:

Figure 1 illustrates a schematic diagram of a laser system in the prior art;

FIG. 2 schematically shows a structural diagram of a circuit system that uses a driving circuit according to an embodiment of the present invention to drive an external device;

FIG. 3 schematically shows a structural diagram of a circuit system that uses a driving circuit according to another embodiment of the present invention to drive an external device;

FIG. 4 schematically shows a schematic diagram of a specific implementation of a circuit system that uses a driving circuit according to an embodiment of the present invention to drive an external device;

FIG. 5 schematically shows a waveform diagram of a simulation result of the circuit system of the embodiment shown in FIG. 4, where the simulation condition is a single input pulse and multiple reference voltages;

FIG. 6 schematically shows a waveform diagram of a simulation result of the circuit system of the embodiment shown in FIG. 4, where the simulation conditions are two input pulses and two reference voltages;

Fig. 7 schematically shows a simulation waveform diagram of the peak current flowing through the laser diode as a function of the reference voltage;

Fig. 8 schematically shows a driving method according to an embodiment of the present invention;

Fig. 9 schematically shows a structural block diagram of a transient enhanced LDO circuit according to an embodiment of the present invention;

FIG. 10 schematically shows a schematic diagram of a circuit structure of a transient enhanced LDO circuit for supplying power to a CMOS device according to an embodiment of the present invention;

Fig. 11 schematically shows an implementation circuit diagram of a transient enhanced LDO circuit according to an embodiment of the present invention;

FIG. 12 shows a simulation graph of the current or voltage of each node according to the circuit shown in FIG. 11;

FIG. 13 shows a comparison simulation graph of the current or voltage of each node under different parameters according to the circuit shown in FIG. 11; and

Figure 14 shows a laser system according to the present invention.

detailed description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

The flowcharts and block diagrams in the drawings illustrate the possible implementation of the system architecture, functions, and operations of the devices, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, program segment, or part of code, and the module, program segment, or part of code contains one or more logic for implementing predetermined Function executable instructions. It should be noted that, in some alternative implementations, the functions noted in the block may also occur in a different order than that noted in the drawings. For example, two blocks shown in succession can actually be executed substantially in parallel, or they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and/or flowchart, and the combination of blocks in the block diagram and/or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or It can be realized by a combination of dedicated hardware and computer instructions.

In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " "Back", "Left", "Right", "Straight", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise" and other directions or The positional relationship is based on the position or positional relationship shown in the drawings, which is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the pointed device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it cannot be understood as a limitation of this disclosure. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, "plurality" means two or more than two unless specifically defined otherwise.

In the description of the present disclosure, it should be noted that, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it may be a fixed connection or an optional Disassembly connection, or integral connection: it can be mechanical connection, it can be electrical connection or it can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the mutual communication of two components Role relationship. For those of ordinary skill in the art, the specific meaning of the above-mentioned terms in the present disclosure can be understood according to specific circumstances. For example, the term "coupling" is used in this disclosure to indicate that the connection between two terminals can be direct connection, or indirect connection through an intermediate medium, and can be an electrical wired connection or a wireless connection.

In the present disclosure, unless otherwise clearly defined and defined, the "above" or "below" of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them. Moreover, "above", "above" and "above" the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature. The “below”, “below” and “below” of the first feature of the second feature include the first feature directly above and diagonally above the second feature, or it simply means that the level of the first feature is smaller than the second feature.

The following disclosure provides many different embodiments or examples for realizing different structures of the present disclosure. To simplify the disclosure of the present disclosure, components and settings of specific examples are described below. Of course, they are only examples, and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numerals and/or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and/or settings discussed. In addition, the present disclosure provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and/or the use of other materials.

It should be noted that, unless otherwise specified, the technical or scientific terms used in the present disclosure should have the usual meanings understood by those skilled in the art to which the present invention belongs.

The specific embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure.

first

Fig. 2 schematically shows a structural diagram of a circuit system that uses a driving circuit 200 according to an embodiment of the present invention to drive an external device. Referring to FIG. 2, the driving circuit 200 includes a narrow pulse generator 210, a voltage regulator 220 and a driving unit 230. The device driven by the driving circuit 200 includes a switch tube 240 and a load 250, and the switch tube 240 is used as a power switch for the load 250.

The narrow pulse generator 210 is configured to generate a first narrow pulse 22 based on the input pulse 20, and the pulse width of the first narrow pulse 22 is smaller than the pulse width of the input pulse 20. The voltage regulator 220 is configured to generate an adjustable output voltage. The driving unit 230 is coupled to the narrow pulse generator 210 and the voltage regulator 220 and is configured to form the second narrow pulse 24 based on the output voltage of the first narrow pulse 22 and the voltage regulator 220. The second narrow pulse 24 is suitable for driving an external switch tube 240. The switching tube 240 is coupled to the load 250. When the switching tube 240 is turned on, the load 250 is powered, and when the switching tube 240 is turned off, no current flows through the load 250. According to the embodiment of the present invention, the pulse width of the second narrow pulse is approximately equal to the pulse width of the first narrow pulse, and the amplitude of the second narrow pulse depends on the output voltage of the voltage regulator. The output voltage of the voltage regulator 220 is adjustable between zero and a preset value, so that the amplitude of the second narrow pulse formed by the driving circuit 200 can be changed between zero and a preset value.

FIG. 3 schematically shows a structure diagram of a circuit system that uses a driving circuit 300 according to another embodiment of the present invention to drive an external device. 3, the driving circuit 300 includes: a narrow pulse generator 210, a pre-driving unit 232, a final driver 234, a voltage-type digital-to-analog converter 222, and a voltage follower 224. The driving circuit 300 can be used to drive a field effect transistor (MOSFET) 242 and control the semiconductor laser 252 through the MOSFET 242.

The narrow pulse generator 210 is configured to generate a first narrow pulse 22 based on the input pulse 20, and the pulse width of the first narrow pulse 22 is smaller than the pulse width of the input pulse 20.

The input terminal of the pre-drive unit 232 is coupled to the output terminal of the narrow pulse generator 210, and is configured to amplify the current drive capability of the first narrow pulse received in one or more stages, so as to satisfy the coupling The drive requirements of the device connected to its output. In the cascade amplification process of the pre-driving unit 232, inverting amplification of the input pulse may also be involved. The input terminal of the final driver 234 is coupled with the output terminal of the pre-driving unit 232 to perform final amplification to meet the driving requirements of the MOSFET coupled to the driving circuit 300. The final driver 234 may also involve inverting the received input pulse to adapt to the driving requirements of the coupled MOSFET.

The voltage-type digital-to-analog converter 222 is configured to receive the digitally controlled input of the voltage DAC and generate an analog voltage. As the numerical control input of the voltage DAC changes, the voltage-type digital-to-analog converter 222 can output an adjustable output voltage as the reference voltage V _REF or the control voltage of the driving unit. The input terminal of the voltage follower 224 is coupled to the output terminal of the voltage-type digital-to-analog converter 222, and is configured to regulate the analog voltage output by the voltage-type digital-to-analog converter. The output terminal of the voltage follower 224 is coupled to the final driver 234 to provide an adjustable output voltage to the final driver, as the power supply voltage of the final driver, for controlling the second narrow pulse 24 formed by the final driver 234 Amplitude. According to the embodiment of the present invention, the pulse width of the second narrow pulse 24 is approximately equal to the pulse width of the first narrow pulse 22, and the amplitude of the second narrow pulse 24 depends on the magnitude of the output voltage of the voltage follower 224. Thus, the pulse width and amplitude of the second narrow pulse 24 are independently adjustable.

The light-emitting process of one laser pulse of the circuit system described in FIG. 3 is as follows. The narrow pulse generator 210 can adjust the pulse width of the input pulse 20 to the order of several nanoseconds (ns), and output the first narrow pulse 22. Then, the first narrow pulse 22 is output to the final driver 234 through the pre-drive unit 232. The power supply voltage of the final driver 234 is provided by the voltage follower 224, and the input voltage of the voltage follower 224 comes from the reference voltage V _REF generated by the voltage-type digital-to-analog converter 222, which is the high level value of the output pulse of the final driver 234 Is V _REF . The second narrow pulse 24 formed by the final driver 234 is used to drive the gate of the MOSFET tube 242. After the MOSFET tube 242 is turned on, the semiconductor laser 252 (such as a laser diode LD) is activated to generate a laser pulse. According to the embodiment of the present invention, by changing the digitally controlled input voltage, the digital-to-analog converter 222 outputs an adjustable reference voltage V _REF , and the amplitude of the drive pulse output to the gate of the MOSFET tube 242 varies with the amplitude of the reference voltage V _REF Furthermore, the current peak value of the laser pulse emitted by the semiconductor laser 252 may also vary within a certain range.

On the one hand, by changing the voltage DAC numerical control input, the gate voltage of the MOSFET can be changed, which can change the peak current flowing through the semiconductor laser. On the other hand, the narrow pulse generator 210 is used to generate laser driving pulses with a narrower pulse width, so that higher frequency laser pulse emission can be achieved.

In one embodiment, the pre-driving unit 232 includes cascaded multi-stage inverting amplifiers, wherein the input-to-output ratio of the inverting amplifiers of each stage can be between 1:3 and 1:5, that is, the N+1th stage The drive capability of the inverting amplifier is approximately 3 to 5 times that of the Nth stage inverting amplifier. The size (amplification capability) of the inverter at the output end of the pre-drive unit 232 may be, for example, 1/3 of the size of the final driver 234.

FIG. 4 schematically shows a schematic diagram of a specific implementation of a circuit system that uses a driving circuit 400 according to an embodiment of the present invention to drive an external device.

4, the narrow pulse generator 210 may include: a current-type digital-to-analog converter I0, a current control delay unit I1, a non-inverting buffer I2, and a logical AND gate I3. The current-type digital-to-analog converter I0 can be configured to receive a current DAC digitally controlled input (not shown) and generate an output current. The current control delay unit I1 may be configured to receive the input pulse 20 and be coupled to the current-type digital-to-analog converter I0 to delay the input pulse 20 according to the output current of the current-type digital-to-analog converter. The non-inverting buffer I2 is configured to temporarily store the input pulse 20. The first input terminal of the logic AND gate I3 is coupled to the output terminal of the current control delay unit I1, and the second input terminal is coupled to the output terminal of the non-inverting buffer I2, and is configured to be based on the delayed input pulse and temporary storage The input pulse produces the first narrow pulse. The pulse width of the first narrow pulse is the delay difference between the temporarily stored input pulse and the delayed input pulse. Therefore, the narrow pulse generator 210 generates a narrow pulse with a narrower pulse width than the input pulse 20 at the output terminal (point B). In one embodiment, the pulse width of the first narrow pulse generated by the narrow pulse generator 210 is adjusted in a range of 1 ns to 1 μs. According to the embodiment of the present invention, the current-type digital-to-analog converter is used to adjust the controllable delay unit, which can realize digitally regulated narrow pulse output.

In FIG. 4, the pre-driving unit 232 includes a cascaded multi-stage inverting amplifier.

Referring to FIG. 4, the voltage follower 224 may include an operational amplifier (OPA) A1, a first PMOS transistor M0, and a capacitor C1. The inverting input terminal of the operational amplifier A1 is coupled to the output terminal (point D) of the voltage-type digital-to-analog converter 222, the non-inverting input terminal of the operational amplifier is coupled to the drain of the first PMOS transistor M0, and the output of the operational amplifier The terminal is coupled to the gate of the first PMOS transistor M0. The source of the first PMOS transistor M0 is connected to the supply voltage VDD, and the drain of the first PMOS transistor M0 is used as the output terminal of the voltage follower 224 and is grounded through the capacitor C1.

In an embodiment, the unity gain bandwidth of the operational amplifier A1 may range from 1 MHz to 1 GHz. In an embodiment, the value range of the capacitor C1 may be 1 nF to 100 nF. In one embodiment, the amplitude range of the adjustable output voltage output by the voltage follower 224 is from 0V to 5V, so that the amplitude range of the second narrow pulse generated by the final driver 234 is from 0V to 5V.

Referring to FIG. 4, the final driver 234 may include: a PMOS transistor M1 and an NMOS transistor M2. The gate of the PMOS transistor M1 is connected to the gate of the NMOS transistor M2, and is configured to receive the first narrow pulse output by the narrow pulse generator 210 amplified by the pre-driving unit 232. The source of the PMOS transistor M1 is coupled to the output terminal of the voltage regulator 224, and is configured to receive the output voltage of the voltage regulator (point E). The source of the NMOS transistor M2 is grounded. The drain of the PMOS transistor M1 is coupled to the drain of the NMOS transistor M2 (point C). The final driver 234 is configured to form a second narrow pulse based on the input current pulse and the output voltage of the voltage regulator, and the second narrow pulse is suitable for driving the MOSFET connected to it.

The output terminal of the driving circuit 400 is coupled to the gate of the MOSFET. The source of the MOSFET is grounded, and the drain is connected to the cathode of the laser diode LD. The schematic circuit diagram of the semiconductor laser 252 may include a laser diode LD, a freewheeling diode D1, a filter capacitor C2, a wiring parasitic capacitance Rp, and a high voltage source HV. In Figure 4, the MOSFET tube uses an enhanced power transistor GaN NMOS FET (eGaN FET). In one embodiment, the supply voltage HV has a value range of 10V to 100V, and the filter capacitor C2 has a value range of 0.1 nF to 100 nF.

Refer to Figure 4 to describe its working principle. The voltage-type digital-to-analog converter 222 is configured to receive the digitally controlled input of the voltage DAC and generate the reference voltage V _REF (point D). In the voltage follower 224, according to the principle of the operational amplifier, when negative feedback is established, the voltage of the non-inverting input terminal and the inverting input terminal of the operational amplifier A1 are equal, and at the same time, the non-inverting input terminal of the operational amplifier A1 and the drain of the PMOS tube M0 Connected, the output current capability is greatly enhanced, and it can better drive the final driver 234 module. The narrow pulse generator 210 can adjust the output delay of the current control delay unit I1 by adjusting the output current of the current-type digital-to-analog converter I0. The temporarily stored in-phase signal and the delayed inverted signal of the input pulse 20 are output to the logic AND gate I3, so the pulse width of the logic AND gate I3 output is the delay difference between I1 and I2, that is, a narrow pulse excitation ( Point B, the first narrow pulse). The narrow pulse excitation is amplified by a pre-drive unit 232 or an intermediate drive link constituted by a cascade of multi-stage inverters to be suitable for driving the final stage driver 234. A second narrow pulse (point C) whose amplitude can vary with the reference voltage (point D) is formed at the output terminal of the final driver 234 for driving the MOSFET tube 242 coupled to it and the semiconductor laser 252 as a load. In one embodiment, the adjustment range of the gate drive voltage for driving the MOSFET is 1.2V to 5V.

Referring to Fig. 4, when the voltage V _{A of the} input pulse 20 is 0V, the voltage at point B is V _B =0V, and the voltage at point C is V _C =0V. At this time, the MOSFET tube 242 is in the off state, no current flows through the semiconductor laser 252, and the laser diode LD does not emit light. When the input of the pulse voltage V _A 20 = 5V, B point voltage V _B = 5V, C point voltage V _C at point E equal to the voltage V _E, the point D is also equal to voltage V _D, i.e., the reference voltage V _REF. Therefore, at this time, the current of the laser diode LD is determined by the volt-ampere characteristic (IV characteristic) of the MOSFET tube 242.

Assuming that the threshold voltage of the MOSFET 242 is Vth, when the reference voltage V _{REF is} less than Vth, the MOSFET is in the off state; when the reference voltage V _{REF is} greater than the threshold voltage Vth, the MOSFET 242 enters the sub-threshold region and flows through the MOSFET 242 The current and voltage difference (V _REF- Vth) increases exponentially; when the reference voltage V _{REF is} greater than the threshold voltage Vth by several tens of millivolts (mV) or more, the MOSFET 242 enters the saturation region, and the current I _LD flowing through the photodiode is :

I _LD ＝β(V _REF -V _th ) ²

Among them, β is the current coefficient when the MOSFET tube works in the saturation region.

At the same time, according to the current characteristics of the HV branch from top to bottom, the voltage difference between the drain and source of the MOSFET is:

V _DS ＝HV-I _LD ×(R _P +R _LD )

Among them, R _P is the parasitic resistance of the wiring between the drain of the MOSFET and HV, and R _LD is the impedance when the laser diode is turned on. As _{the value of I LD} gradually increases, the drain-source voltage of the MOSFET V _DS Decrease gradually, when the overdrive voltage (V _REF -Vth) of the _{MOSFET is greater than V DS} , the working state of the MOSFET changes from the saturation region to the linear region. The maximum value (peak current) _{of the current I LD} flowing through the photodiode is approximately equal to:

R _DS,on is the impedance when the MOSFET is working in the linear region, and its value is approximately:

According to the embodiment of the present invention, the current-type digital-to-analog converter is used to adjust the controllable delay unit, which can realize digitally regulated narrow pulse output. According to the embodiment of the present invention, a voltage-type digital-to-analog converter is used to realize the digitally regulated reference voltage, and combined with the back-end voltage follower and driver, the digitally regulated gate drive voltage of the MOSFET can be realized, thereby realizing the laser diode Digital control of output current.

In one embodiment, the constituent devices of the voltage-type digital-to-analog converter 222, the voltage follower 224, the narrow pulse generator 210, the pre-drive unit 232, and the final driver 234 are all low-voltage devices. For example, if the power supply voltage is lower than 5V, the MOS transistors M0, M1, and M2 are 5V silicon CMOS devices. The MOSFET tube 242 and the laser diode are high-voltage devices, for example, the power supply voltage HV is 60V.

The MOSFET tube can use an enhanced power transistor, which uses GaN material, has high electron mobility and withstand voltage performance, the drain-source voltage V _DS supports up to 100V, and the current flowing through the laser diode I _LD supports up to 75A. The gate-source voltage V _GS can be controlled by 0-5V, and the threshold voltage Vth=1V. The current threshold Ith of the laser diode LD in the semiconductor laser is 0.75A. Under typical conditions, it can input current 30A, output 75W optical power, peak input current 40A, and peak optical output power 90W.

It should be understood that the voltage-type digital-to-analog converter 222, the voltage follower 224, the narrow pulse generator 210, the pre-drive unit 232, and the final driver 234 can be implemented by the same semiconductor process, and therefore can be integrated in one chip.

FIG. 5 schematically shows a waveform diagram of a simulation result of the circuit system of the embodiment shown in FIG. 4. The condition of the simulation is that an input pulse 20 is input to the driving circuit 400, and at the same time, the code value of the numerical control input of the voltage DAC is a plurality of varying values. The waveform of the voltage of the input pulse 20 (ie, the voltage VA at point A in FIG. 4) is as shown in the waveform 51 in FIG. 5, and the pulse width of the VA waveform is 10 ns. The digital input code value of the voltage DAC varies from 000000 to 111111, so that the output voltage V _D of the voltage-type digital-to-analog converter 222 is a different value, resulting in 64 adjustable voltage waveforms in the voltage range of 1.2V to 5V. This is shown by the waveform 54 in Figure 5. Therefore, the voltage waveform at point E is also adjustable, as shown by waveform 55 in FIG. 5.

In Figure 5, the

waveforms

52, 53, and 56 shown from top to bottom are the waveforms of the voltage V _B at point B under the excitation of the input pulse 20 and the continuously changing code value of the voltage DAC digital input. 52. A superimposed view of the waveform 53 of the voltage V _C at point C and the waveform 56 of _{the current I LD of the laser diode LD.} It can be easily seen that with the change of the code value of the voltage DAC numerical control input (corresponding to the change of the reference voltage (V _D )), the voltage waveform of the output pulse of the driving circuit 400 (the waveform 53 _{of the voltage V C at point C)} The waveform 56 of the current I _{LD of the laser diode LD changes accordingly.}

The pulse width of the voltage waveform of the voltage V _A of the input pulse 20 is 10 ns, and the pulse width of the voltage waveform of the voltage V _B generated after passing through the narrow pulse generator 210 becomes 3 ns, as shown by the waveform 52 in FIG. 5. The high level of the voltage VB is fixed at about 5V, and does not change with the change of the voltage value of the _{reference voltage V D.}

Narrow pulse to generate an output voltage of the voltage V _B 210 through a voltage V _C after 234 pre-driver unit 232 and a final drive pulse broadband V _C of the waveform is substantially equal to the pulse width of the waveform of the voltage V _B of, or V _C The amplitude of the waveform changes _{with the reference voltage V D.}

The voltage V _C controls the gate of the MOSFET tube 242, thereby controlling the on and off of the MOSFET tube 242. When the MOSFET tube 242 is turned on, a current I _LD is formed in the laser diode LD. The current waveform of the current I _{LD follows} The reference voltage V _D changes.

FIG. 6 schematically shows a waveform diagram of a simulation result of the circuit system of the embodiment shown in FIG. 4. The condition of the simulation is that the driving circuit 400 is input with two input pulses 20 successively, one input pulse is at 50 μs, and the other input pulse is at 50.4 μs. At the same time, the code value of the voltage DAC numerical control input is adjusted correspondingly. The voltage of the reference voltage V _D is reduced from 5V at the arrival time of the previous input pulse to 2.7V at the arrival time of the next input pulse. It can be seen from the simulation results in Fig. 6 that the output voltage V _E of the voltage follower changes with the reference voltage V _D _{, the pulse width of the current I LD} flowing through the laser diode LD depends on the pulse width of the input pulse, and Its peak current is controlled by the reference voltage V _D.

Fig. 7 schematically shows the simulation result of the peak current of the laser diode LD varying with the reference voltage V _D. When the reference voltage changes from 1.2V to 5V, the current peak value changes from 202mA to 78.67A. The relationship between current and voltage changes is as in the previous analysis. First, as the voltage rises, the current increases exponentially; then as the reference voltage rises to greater than After the threshold voltage Vth of the MOSFET is tens of mV, the MOSFET enters the saturation region, and the current curve rises according to the quadratic curve with the opening upward; when the drain-source voltage V _DS of the MOSFET is equal to the overdrive voltage (V _REF -Vth) When the MOSFET tube gradually transitions to the linear region, the current curve gradually changes according to the quadratic curve with the opening downward until it no longer increases, until it reaches the maximum current value.

In one embodiment, the current threshold of the selected laser diode is 1A, and the maximum current is 40A. Therefore, when the reference voltage V _D changes from 0.95V to 6.2V, the range of the MOSFET output current can fully meet the laser diode input current demand.

As shown in FIG. 8, the present disclosure also provides a driving method 500, which is implemented by the

aforementioned driving circuits

200, 300, 400, for example.

The driving method 500 includes: step S1: generating a first narrow pulse based on an input pulse, the pulse width of the first narrow pulse is smaller than that of the input pulse; step S2: generating an adjustable output voltage; and step S3: A second narrow pulse is generated based on the first narrow pulse and the output voltage, wherein the pulse width of the second narrow pulse is approximately equal to the pulse width of the first narrow pulse, and the amplitude of the second narrow pulse Depends on the size of the adjustable output voltage.

Further, step S2 may further include: receiving a digitally controlled input through a voltage-type digital-to-analog converter and generating an analog voltage; performing a voltage stabilization operation on the analog voltage output by the voltage-type digital-to-analog converter to generate the adjustable output Voltage.

Further, step S1 may further include: receiving the input pulse, temporarily storing the input pulse; receiving a numerical control input through a current-type digital-to-analog converter and generating an output current; receiving the input pulse, according to the current-type digital-analog converter The output current of the converter delays the input pulse; and the first narrow pulse is generated based on the delayed input pulse and the temporarily stored input pulse.

Further, step S3 may further include: performing one-stage or multi-stage amplification on the current driving capability of the received first narrow pulse.

The present disclosure also provides a laser system, including: the aforementioned narrow pulse drive circuit; a laser, and a transistor, the gate of which is coupled to the output end of the narrow pulse high-power device drive circuit, and the second narrow pulse is used for control When the transistor is switched on and off, its source is grounded, and its drain is coupled to the laser.

2. The pulse width of the first narrow pulse and the amplitude of the current flowing through the laser diode are two independently adjustable quantities, which can ensure the optimal performance according to the needs of the system. For example, the pulse width can be kept at 3ns, and the current peak value can be changed at the same time. It is guaranteed that the pulse width of the emitted laser pulse is narrow, the leading edge is fast, the luminous energy adjustable range is large, and it does not exceed the laser energy threshold specified by human eye safety.

3. By adjusting the gate voltage of the MOSFET, a high output current control ratio can be obtained. For example, the input voltage changes 4 times (0.95V～6.2V), and the output current can change 389 times (202mA～78.67A).

Second aspect

Example one

In lasers, an LDO circuit is often used to provide power to the CMOS driver. By controlling the input reference voltage V _REF of the LDO circuit, the output level V _{OUT of the} LDO circuit is changed to realize the adjustable output level of the CMOS driver. The CMOS driver outputs an adjustable level to control the gate of the GaN switch tube to achieve large dynamic modulation of the drain output current of the GaN switch tube, and by modulating the GaN drain output current, the laser diode light intensity modulation is achieved.

Ideally, according to the light intensity of the laser diode at a time needs to determine a good V _REF, V _OUT is linearly determined according to V _REF, and then has been held steady at a certain value, thus current of the laser diode (light intensity) Make modulation. However, because the CMOS driver rapidly draws or sinks current _{from the V OUT} _{port, V OUT} will not be ideally stable.

At present, when V _OUT changes from large to small (corresponding to a current source for LDO), a large current source can be provided through an external capacitor Co. The main problem is that when V _OUT grows from small to large (for LDO, corresponding to sink current), it needs to quickly release and pull down a part of the current.

In the present invention, by adding a sink current absorption circuit, specifically a current comparator capable of sensing voltage fluctuations and a pull-down NMOS tube, a part of the current can be pulled down quickly and effectively.

FIG. 9 schematically shows a structural block diagram of a transient enhanced LDO circuit 600 according to an embodiment of the present invention. As shown in FIG. 9, the transient enhanced LDO circuit 600 includes: an error amplifier A1, a power regulator tube MP0, a voltage divider including resistors R1 and R2, and a sink current sink circuit 605. Among them, one of the input terminals of the error amplifier A1 (as shown in Figure 9, for example, its inverting input terminal) is used to receive the reference voltage V _REF , and the output terminal is coupled to the gate of the power regulator MP0 for driving Power adjustment tube MP0. The drain of the power regulator MP0 is used as the output terminal of the transient enhanced LDO circuit 600 to output the voltage V _OUT to drive the load connected to it, such as the CMOS driver of the laser radar. The voltage output terminal (ie drain) of the power regulator MP0 is also coupled to the non-inverting input terminal of the error amplifier A1 through a voltage divider including resistors R1 and R2, thereby feeding back the divided voltage on the resistor R1 to the non-inverting input of the error amplifier A1 end. The sink current absorbing circuit 605 is coupled to the output terminal of the power regulating tube MP0, that is, to the output voltage of the drain of the power regulating tube MP0, and is used to adjust the output voltage V _OUT according to the fluctuation of the _{output voltage V OUT (especially when V OUT increases} from small to large) Turn on and absorb the sink current caused by fluctuations in the _{output voltage V OUT.} The fluctuation of the output voltage V _OUT is usually caused by the changing demand of the load current.

9 shows that the sink current absorption circuit 605 is only coupled to the drain of the power regulator MP0. Those skilled in the art can easily understand that the sink current absorption circuit 605 may also include a path for releasing the sink current, such as a ground path. So after it is turned on, the sink current is quickly led into the ground path and released.

The working principle of the transient enhancement type LDO circuit 600 shown in FIG. 9 is described below.

The error amplifier A1 is an ideal amplifier, so the voltage at the non-inverting input terminal and the inverting input terminal are equal. _{The reference voltage V REF} at the inverting input terminal of the error amplifier is negatively amplified by the error amplifier A1 and reversely amplified by the power regulator MP0 to output the voltage V _OUT . V _OUT is fed back to the non-inverting input of the error amplifier A1 through the voltage division of R2 and R1. The entire feedback loop is negatively amplified. The non-inverting input terminal and the inverting input terminal of the error amplifier A1 maintain the same voltage, that is, V _N =V _P =V _REF , so the output V _OUT of the LDO is:

When the output voltage V _OUT fluctuates, as described above, the sink current absorbing circuit 605 can be _{turned on according to the fluctuation of the output voltage V OUT} and absorb the sink current to the LDO circuit. The sink current sink circuit 605 is, for example, coupled to one of the terminals (such as the non-inverting input) or pin of the error amplifier A1, so that when the output voltage V _OUT fluctuates, the output voltage V _OUT is divided by the voltage divider (R1, R2) _{The voltage causes the voltage V P} of the non-inverting input terminal of the error amplifier A1 to fluctuate beyond a certain preset threshold. _{The sink current absorbing circuit 605 can sense the fluctuation of the output voltage V OUT} through one of the terminals or pins of the error amplifier A1 connected to the sink current absorbing circuit 605 to be turned on, thereby quickly absorbing the sink current caused by the fluctuation of _{the output voltage V OUT.} According to a preferred embodiment, the sink current sink circuit 605 is, for example, connected to the non-inverting input terminal of the error amplifier A1 to be directly triggered by the fluctuation of the _{output voltage V OUT.} Those skilled in the art can also conceive that the sink current sink circuit 605 is connected to other pins of the error amplifier A1.

When the LDO circuit is used to drive the CMOS driver of the laser radar, the LDO circuit is required to have a high charge extraction or injection capability in a very short time. For example, it is required to provide a charge extraction capability of 5.6nC within 2ns. The LDO structure of the on-chip capacitor of 80pF is impossible to realize, because the internal charge of the on-chip capacitor 0.448nC is less than 5.6nC (Q=80pF*5.6V=0.448nC). Therefore, it is necessary to adopt an LDO structure including off-chip capacitors to realize the power supply of the CMOS driver. LDO circuits using off-chip capacitors need to charge or discharge the voltage on the off-chip capacitors through other parts of the LDO circuit after the transient draw or charge injection. For example, when a large charge is poured into a CMOS driver, a large amount of charge is accumulated on the off-chip capacitor of the LDO, and a transient enhancement LDO circuit is required to perform rapid discharge to reduce the voltage. The sink current absorption circuit 605 in the above technical solution of the present disclosure provides an effective and rapid discharge channel. When the output voltage V _OUT fluctuates to a certain threshold, the sink current absorption circuit 605 is turned on, which provides a fast discharge channel for the sink current, and quickly reduces the charge and voltage on the off-chip capacitor. Using the sink current absorption circuit 605 for discharge, the discharge speed is significantly faster than that of only discharging through the voltage divider (R1, R2).

Those skilled in the art can easily understand that in the present invention, the sink current sink circuit 605 can be _{turned on according to the fluctuation of the output voltage V OUT} , including a variety of specific implementation methods. For example, the sink current absorbing circuit 605 can sense the current change in one branch of the amplifier A1 caused by the fluctuation of the _{output voltage V OUT} , and can also directly sense the fluctuation of the _{output voltage V OUT and turn on.} It can be turned on by sensing changes in other circuit parameters caused by fluctuations in _{V OUT.} In other words, _{the fluctuation of the output voltage V OUT} will trigger the conduction of the sink current sink circuit 605. These are all within the protection scope of the present invention.

It should be understood that the device selection in FIG. 9 and the device selection in the following are only exemplary. Those skilled in the art can flexibly select components of appropriate specifications and types based on the inventive concept of the present disclosure and in combination with actual needs. Reasonable connections to achieve the purpose of the embodiments of the present invention should all fall within the protection scope of the present invention.

Example two

FIG. 10 schematically shows a circuit structure diagram of a transient enhanced LDO circuit 600 for supplying power to a CMOS driver according to an embodiment of the present invention, and FIG. 10 also shows a preferred embodiment of the sink current sink circuit 605 .

In Figure 10, U0 represents the voltage analog-to-digital converter DAC, and the reference voltage V _REF is output through the digital control code DIN. U1 represents the transient enhanced LDO circuit 600, including the error amplifier A1, the buffer stage A2, the power regulator MP0, and the A voltage divider of resistors R2 and R1, an external capacitor Co, a compensation resistor R3 connected in series with Co, a current comparator A3, and a pull-down NMOS tube MN0, U2 represents a CMOS driver, and its load capacitance is CL. The transient enhanced LDO circuit 600 is used to power the CMOS driver U2.

10, the sink current sink circuit 605 includes a comparator A3 and a pull-down NMOS transistor MN0 driven by the comparator. Wherein A3 phase comparator with an input for receiving an input signal reflecting the output voltage V _OUT and the inverting input of comparator A3 for receiving the input signal and the reflected output voltage V _OUT corresponding to the threshold signal I _th. Among them, the pull-down NMOS transistor is coupled between the output voltage V _OUT output terminal of the power regulator MP0 (ie the drain of the power regulator MP0) and the comparator A3, and the source of the pull-down NMOS transistor MN0 is grounded. The sink current sink circuit 605 is configured to turn on the pull-down NMOS tube and absorb the sink current caused by the output voltage when the output voltage fluctuates by a certain threshold; and when the output voltage does not fluctuate beyond a certain threshold, the pull-down NMOS tube shut down. In Figure 10, the capacitor Co is an external capacitor, and the resistor R3 is a compensation resistor.

According to a preferred embodiment of the present disclosure, the comparator A3 is a current comparator, and its inverting input terminal receives a threshold current signal, and its non-inverting input terminal receives a current signal that can reflect _{fluctuations in the output voltage V OUT} (for example, the first in FIG. 11 and FIG. 12 Nine current of the branch where the PMOS tube MP9 is located). The comparator A3 receives the current signal and compares it with the threshold current signal. When there is a certain difference between the two, the output voltage V _GNO flips to a high level, so that the pull-down NMOS tube MN0 is turned on to provide a fast discharge channel for the sink current.

According to a preferred embodiment of the present invention, the inverting input terminal of the error amplifier A1 of the transient enhanced LDO circuit 600 is used to connect to the voltage-type digital-to-analog converter U0. The voltage-type digital-to-analog converter U0 can receive the digital control code DIN, and generate different reference voltages V _REF according to the different digital control codes DIN. Since the error amplifier A1 is an ideal error amplifier, its non-inverting input terminal and the inverting input terminal have the same voltage, both of which are V _REF . The voltage divider (R1, R2) is connected to the non-inverting input terminal of the error amplifier A1, so the voltage of the resistor R1 is also V _REF , according to the formula of the voltage divider, V _OUT =V _REF *(R1+R2)/R1. Therefore, by changing the digital control code DIN of the voltage-type digital-to-analog converter U0, the output voltage V _OUT of the transient enhanced LDO circuit 600 of the present invention can be changed.

According to a preferred embodiment of the present invention, as shown in FIG. 10, the transient enhanced LDO circuit 600 further includes a buffer stage A2 connected between the error amplifier A1 and the power amplifier tube MP0 for buffering the error amplifier A1 The output voltage improves the capacity with load. In addition, in order to ensure that the LDO has a small leakage voltage, the width-to-length ratio of the power regulator MP0 is usually larger, ranging from 1,000 to 100,000, so the gate of the power regulator MP0 has a larger parasitic capacitance. The use of buffer stage A2 can prevent the large capacitance of the gate of the power regulator tube MP0 from pulling down the output pole of the error amplifier A1, and the buffer stage A2 is used to isolate the output of the error amplifier A1 from the gate of the power regulator tube MP0. Preferably, the buffer stage A2 has a smaller input capacitance and a lower output impedance. The input capacitance is, for example, between 100 fF and 1 pF, and the output impedance is, for example, between 10 and 200 Ω, so that after the buffer stage A2 is added, the error amplifier A1 The output pole becomes higher, and the pole formed by the output of the buffer stage A2 and the input capacitance of the power regulator MP0 is much larger than the unity gain bandwidth.

The working principle of the circuit of Fig. 10 is as follows. When the output voltage V _OUT fluctuates, through the voltage divider (R1, R2), a voltage fluctuation is generated at the non-inverting input terminal of the error amplifier A1. The non-inverting input terminal of the comparator A3 receives a signal that reflects the fluctuation of the output voltage, such as a current signal, and compares it with the threshold current signal I _th . When there is a certain difference between the two, the output V _{GN0 of the} comparator A3 turns to a high level , Making the pull-down NMOS transistor MN0 turn on. After the pull-down NMOS tube MN0 is turned on, it can quickly absorb the sink current from the external load.

In one embodiment of the present disclosure, the transient enhancement LDO circuit is used to supply power to the CMOS device, and the CMOS device is, for example, a CMOS driver in a laser radar transmitting circuit.

In the laser radar transmitter circuit, a CMOS driver is required to drive a high-power GaN (gallium nitride) switch tube. GaN switch tubes are used to provide large transient currents for laser diodes. The GaN switch tube has a very high input capacitance (for example, 80pF-1.5nF) and gate charge (for example, about 0.5-5nC), and its gate control voltage is generally 0-10V. Therefore, at the moment of CMOS driver switching (from low to high) Level, or from high to low), the amount of charge that needs to be injected or drawn into the GaN switch tube reaches tens of nC. The amount of charge injected or drawn by the CMOS driver comes from the power supply terminal of the CMOS driver. Therefore, the LDO circuit at the power terminal is required to have the ability to draw or inject large charges in a transient state.

According to the embodiment of the present invention, the transient enhanced LDO circuit 600 is used to provide power for the CMOS drive. By controlling the input reference voltage V _REF , the output level of the transient enhanced LDO circuit 600 is changed to realize the high level output of the CMOS driver. adjust. The GaN switch gate is controlled by different CMOS driver high levels to achieve large dynamic modulation of the GaN switch drain output current, and the GaN drain output current is modulated to realize the laser diode light emphasis control.

The leading edge of the output signal of the CMOS driver of the laser radar is generally very fast, and the range is about 1ns-3ns. Therefore, the LDO is required to provide up to tens of nC in a time of about 1.9ns. It is assumed that the current waveform provided by the LDO for the CMOS driver is 1ns With the triangular waveforms of the leading edge and the trailing edge of 1 ns, the current peak value is several ampere hours, and the charge amount of the current pulse is tens of nC.

It provides a charge drawing capability of tens of nC within 2 ns, which cannot be achieved with an LDO structure using on-chip capacitors because the amount of charge of the on-chip capacitor is less than tens of nC. So need to adopt the LDO structure of the off-chip capacitance to realize the power supply of CMOS driver. LDO circuits with off-chip capacitors need to be charged or discharged through other parts of the LDO circuit to replenish the amount of charge after the transient draw or charge injection. Through the transient enhancement type LDO circuit 600 shown in FIG. 10 of the present invention, when the output voltage V _OUT fluctuates, for example, when there is a large sink current, the comparator A3 can turn on the pull-down NMOS transistor MN0 and quickly absorb The speed of sinking current is much faster than that of sinking current only through resistors R1 and R2.

The basic working principle of the circuit shown in FIG. 10 is as follows, in which the flow direction of the source current of the LDO circuit is shown in the form of a solid arrow, and the flow direction of the sink current of the LDO circuit is shown in the form of a broken line arrow.

By controlling the code value of the digital control code DIN, the DAC U0 can output the reference voltage V _REF to the inverting input terminal of the _{error amplifier A1. V REF} is negatively amplified by the error amplifier A1, the buffer stage A2 follows the same phase, and the power regulator MP0 reverses. After amplifying, it is fed back to the non-inverting input terminal of A1 through the partial pressure of R2 and R1. For the DAC output, the entire feedback loop is a negative amplification. Therefore, the non-inverting input terminal and the inverting input terminal of A1 can keep the voltage equal, that is, VN=VP=VREF, so the output V _OUT of the LDO is:

V _OUT uses an external capacitor Co to ensure that the LDO can provide a large transient charge (tens of nC). Therefore, the value of Co is such that the amount of charge in the steady state is much greater than tens of nC, for example, above 16 nF. When a large capacitor is selected _{for the output, the output pole of V OUT} is selected as the main pole. To ensure the phase margin, a _{small resistor R3 is connected in series between V OUT} and Co, so that the zero formed by R3 and Co can affect the secondary output of the error amplifier. Point for phase compensation, and finally make the phase margin greater than 45°.

To ensure that the LDO has a small leakage voltage, the power regulator MP0 usually takes a larger value, so the gate of MP0 has a larger parasitic capacitance. Therefore, in order to prevent the large capacitance of the MP0 grid from pulling down the output pole of the error amplifier A1, a buffer stage A2 is used to isolate the output of the error amplifier A1 from the MP0 grid. Buffer A2 is set to have a smaller input capacitance and lower output impedance, so that after adding A2, the output pole of A1 becomes higher, while the pole formed by the output of A2 and the input capacitance of MP0 is much larger than the unity gain bandwidth. A2 also needs to have smaller power consumption.

When the CMOS driver is working, the power of U2 is provided by the output V _{OUT of} LDO U2. U2 works on the rising edge (or falling edge) of ns level, and instantaneously extracts (or injects) the peak current pulse _{from V OUT. The width of the current pulse is} The rising edge (or falling edge) of U2 is equivalent. The amount of charge of the current pulse depends on the voltage amplitude ΔV output by U2 and the load capacitance CL of U2. When considering extreme conditions, the amount of charge drawn by U2 is tens of nC, that is, the current draw capability of LDO U2 can meet the requirements of Lidar CMOS driver requirements.

Example three

Referring to FIG. 11, it schematically shows a circuit structure diagram of a specific implementation of a transient enhanced LDO circuit according to an embodiment of the present invention. Referring to Figure 11, the power terminal of U2 can be equivalent to an ideal current source I0.

In the circuit diagram of an implementation of the technical scheme of the present invention as shown in FIG. 11, the error amplifier A1 adopts a folded cascode structure and includes eight PMOS transistors, namely the first PMOS transistor MP1, the second PMOS transistor MP2, and the second PMOS transistor. Three PMOS tubes MP3, fourth PMOS tubes MP4, fifth PMOS tubes MP5, sixth PMOS tubes MP6, seventh PMOS tubes MP7, and eighth PMOS tubes MP8. The error amplifier A1 also includes four NMOS transistors MN1-MN4, namely a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4.

The first PMOS tube MP1 and the second PMOS tube MP2 form a differential input pair tube. The gate of the first PMOS tube MP1 is used as the inverting input terminal of the error amplifier A1 for connecting the reference voltage V _REF and the second PMOS tube MP2 The gate serves as the non-inverting input of the error amplifier A1. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 constitute a cascode current source, and the drain of the fourth PMOS transistor MP4 is connected to the drain of the first PMOS transistor MP1 and the drain of the second PMOS transistor MP2.

The first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, and the fourth NMOS tube MN4 constitute a cascode current source. The source of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1 and to the drain of the second PMOS transistor MP2. The source of the fourth NMOS transistor MN4 is interconnected with the drain of the third NMOS transistor MN3, is connected to the drain of the first PMOS transistor MP1, and serves as a first intermediate output terminal.

The fifth PMOS tube MP5, the sixth PMOS tube MP6, the seventh PMOS tube MP7, and the eighth PMOS tube MP8 constitute a cascode current mirror load. The gates of the fifth PMOS transistor MP5 and the seventh PMOS transistor MP7 are interconnected, and connected to the drain of the second NMOS transistor MN2, and serve as a second intermediate output terminal. The gates of the sixth PMOS transistor MP6 and the eighth PMOS transistor MP8 are interconnected and used as the third intermediate output terminal.

The drains of the eighth PMOS tube MP8 and the fourth NMOS tube MN4 are interconnected and used as the output terminal of the error amplifier A1.

In FIG. 11, Vbp1 and Vbp2 represent the voltage bias of the third PMOS tube MP3 and the fourth PMOS tube MP4, respectively. Vbn1 and Vbn2 represent the voltage bias of the first NMOS transistor MN1 and the second NMOS transistor MN2, respectively. The current of the NMOS tube MN1 is the sum of the currents of the PMOS tube MP2 and MP5, the current of the NMOS tube MN3 is the sum of the currents of the PMOS tube MP1 and MP7, and the current of the PMOS tube MP3 is the sum of the currents of the PMOS tube MP1 and the PMOS tube MP2.

The buffer stage A2 can be realized by a source follower structure composed of a PMOS tube MP11 and a PMOS tube MP12 (not shown).

In the circuit diagram of an implementation of the technical solution of the present invention as shown in FIG. 11, the comparator A3 is a load current mirror structure through the cascode in the mirror error amplifier A1, which includes: a fifth NMOS tube (MN5), The sixth NMOS tube (MN6), the ninth PMOS tube (MP9), and the tenth PMOS tube (MP10). The fifth NMOS tube (MN5) and the sixth NMOS tube (MN6) form a cascode structure and serve as the threshold current terminal of the current comparator (A3). The ninth PMOS tube (MP9) and the tenth PMOS tube (MP10) form a cascode structure and are used as the signal current terminal of the current comparator (A3). The drain of the tenth PMOS transistor (MP10) is connected to the drain of the sixth NMOS transistor (MN6) and is used to connect to the gate of the pull-down NMOS transistor (MN0).

In another implementation, the output of the current comparator A3 can be connected to the gate of the pull-down NMOS transistor MN0 through a source follower (not shown) composed of the NMOS transistor MN7, NMOS transistors MN8, and R4.

The drain of the pull-down NMOS tube MN0 is connected to the LDO output terminal V _OUT , and the divided voltage of R2 and R1 is fed back to the non-inverting input terminal of the error amplifier, that is, the gate of the PMOS tube MP2.

FIG. 12 shows a simulation graph of the current or voltage of each node according to the circuit shown in FIG. 11, which shows the waveform diagram of each key node in the process of the primary current source I0 injecting charge into the LDO. Waveform shown in FIG. 12, top to bottom order of the current waveform of the current sources I0, the gate voltage waveform of the pull-down NMOS transistor MN0, the drain of NMOS pull-down current waveform of MN0, the LDO external capacitor voltage V _CAP waveform.

The current waveform of the current source I0 can be provided by an ideal source, with a rising edge of 1ns, a falling edge of 1ns, and a peak value of 5A, so the total injected charge is 5.6nC, and the injection time is 60us. Set the DAC output voltage V _REF to 2V, the LDO power supply VDD=5.6V, the feedback network resistance R2=R1, for example, tens of kΩ, and the loop bandwidth of the LDO 1MHz, then the _{output value of V OUT} in the steady state is 4V. When a large charge is injected into the LDO output terminal instantaneously, because the loop bandwidth of the LDO is small, the V _OUT output terminal will not discharge, and V _OUT will rise from the current value (4V), so the feedback resistor network R2 and R1 divide The voltage will also increase, resulting in an increase in the voltage at the non-inverting input terminal VP of the error amplifier A1, that is, the current in the branch where MP2 is located decreases, causing the current in the branch where MP9 is located to increase beyond the current threshold of MN5, the current comparator flips and compares The device outputs a voltage pulse signal to the gate of MN0. After the gate voltage of MN0 increases, the drain of MN0 _{draws current from the V OUT} terminal, causing the LDO output terminal voltage V _OUT and the off-chip capacitor voltage V _CAP to decrease. From the charge injection from I0 to the turn-on of the MN0 tube, the delay time is about 60ns, and the maximum current output by the drain of MN0 is 86mA. After MN0 discharge is over, _{the voltage overshoot value on V CAP} is reduced from 86.5mV to 15mV, that is, 83% of the charge is pumped away through MN0, so as to achieve LDO transient pull-down enhancement.

Figure 13 shows a comparison simulation graph of the current or voltage of each node under different parameters according to the circuit shown in Figure 11, where the transient pull-down _{of V OUT} and V _{CAP under two parameters is shown in the same display window} For comparison graphs of enhancement effects, the first parameter is the waveform result presented by the structure of the pull-down enhancement circuit in this application, and the second parameter is the waveform result presented by the circuit shown in FIG. 12.

The waveforms from top to bottom shown in FIG. 13 are the current waveform of the current source I0, the voltage waveform of the LDO output terminal V _OUT _{, and the voltage waveform of the V CAP} on the external capacitor at the LDO output terminal.

The voltage waveform of the LDO output terminal V _OUT includes the waveforms represented by VOUT wo MN0 and VOUT wi MN0, respectively. VOUT wo MN0 represents the waveform that does not use the pull-down enhancement circuit structure in this application, which is represented by the dashed line in Figure 13 . VOUT wi MN0 represents the waveform after adopting the pull-down enhancement circuit structure in this application, and is represented by a solid line in FIG. 13.

_{The voltage waveforms of V CAP} on the external capacitor at the LDO output terminal are represented by VCAP wo MN0 and VCAP wi MN0, respectively. VCAP wo MN0 represents a waveform that does not use the pull-down enhancement circuit structure in this application, which is represented by a dotted line in FIG. 13. VCAP wi MN0 represents the waveform after adopting the pull-down enhancement circuit structure in this application, and is represented by a solid line in FIG. 13.

As shown in Figure 13, the I0 current source extracts several tens of nC of charge into the LDO at 10us and injects 5.6nC into the LDO in the form of a pulse. Due to the isolation of the buffer stage A2, the gate of MP0 can be quickly drawn or injected. When a charge of 5.6nC is injected at the time of 10us, both V _OUT and V _CAP can quickly recover to the initial value, and the time spent is about 9us. The maximum overshoot of _{V CAP is about 20mV.} At 60us, when the pull-down enhancement circuit structure in this application is not used, _{the recovery time of V CAP} is about 87us, and the maximum overshoot is about 206mV; when the pull-down enhancement circuit structure in this application is used, the V _CAP 's The recovery time can be shortened to 10us, and the maximum overshoot is about 80mV.

Therefore, after adopting the transient enhancement circuit in this paper, _{the recovery time of V CAP} can be reduced to about 11% of the original, and the maximum overshoot attenuation is less than 40% of the original. Therefore, the effect of the pull-down enhancement circuit structure according to the embodiment of the present invention is very significant.

The second aspect of the present disclosure also relates to a power supply circuit of a CMOS driver, including: the transient enhancement type LDO circuit of any one of the foregoing; and a voltage-type digital-to-analog converter connected to the LDO circuit and configured to receive the digital control The input is converted into an analog voltage as the reference voltage of the error amplifier (A1) of the LDO circuit.

FIG. 14 shows a laser system 700 according to the third aspect of the present disclosure, including the aforementioned power supply circuit. As shown in FIG. 14, the laser system 700 includes the aforementioned power supply circuit, CMOS driver U2, GaN switch tube U5, and laser diode LD (laser), wherein the power supply circuit is based on the transient enhancement type LDO circuit 600 of the present invention and the voltage type digital circuit. The analog converter U0 is used as the power supply of the CMOS driver and provides the driving voltage V _OUT for the CMOS driver. The CMOS driver drives the GaN switch tube, and the GaN switch tube provides a transient high current for the laser diode to drive the laser diode to emit laser light.

It should be understood that the foregoing various exemplary methods may be implemented in various ways. For example, in some embodiments, the foregoing various methods may be implemented using software and/or firmware modules, or may also be implemented using hardware modules. Other methods currently known or developed in the future are also feasible, and the scope of the present invention is not limited in this respect. In particular, in addition to the hardware implementation, the implementation of the present invention may be implemented in the form of a computer program product.

It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. Those of ordinary skill in the art can understand that the above-mentioned devices and methods can be implemented using computer-executable instructions and/or included in processor control codes, for example, on a carrier medium such as a disk, CD or DVD-ROM, such as a read-only memory. Such codes are provided on a programmable memory (firmware) or a data carrier such as an optical or electronic signal carrier. The device and its modules of the present invention can be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., It can also be implemented by software executed by various types of processors, or can be implemented by a combination of the above hardware circuit and software, such as firmware.

It should be noted that although several modules or sub-modules of the device are mentioned in the above detailed description, this division is only not mandatory. In fact, according to the embodiments of the present invention, the features and functions of two or more modules described above can be implemented in one module. Conversely, the features and functions of a module described above can be further divided into multiple modules to be embodied.

Although the present invention has been described with reference to the currently considered embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims conforms to the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

The foregoing descriptions are only preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Although the present disclosure has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still compare the foregoing embodiments. The recorded technical solutions are modified, or some of the technical features are equivalently replaced. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

A driving circuit, including:

A narrow pulse generator configured to generate a first narrow pulse based on an input pulse, the pulse width of the first narrow pulse being smaller than the pulse width of the input pulse;

Voltage regulator, configured to produce adjustable output voltage;

The driving unit is coupled to the narrow pulse generator and the voltage regulator, and is configured to form a second narrow pulse based on the first narrow pulse and the output voltage, wherein the second narrow pulse Suitable for driving a switch tube, the pulse width of the second narrow pulse is approximately equal to the pulse width of the first narrow pulse, and the amplitude of the second narrow pulse depends on the output voltage of the voltage regulator.
The driving circuit according to claim 1, wherein the voltage regulator comprises:

A voltage-type digital-to-analog converter configured to receive digitally controlled input from a voltage DAC and generate an analog voltage; and

A voltage follower, coupled to the voltage-type digital-to-analog converter and the drive unit, is configured to stabilize the analog voltage output by the voltage-type digital-to-analog converter, and output the adjustable output Voltage.
The driving circuit according to claim 2, wherein the voltage follower comprises an operational amplifier, a first PMOS transistor (M0) and a capacitor (C1),

Wherein, the inverting input terminal of the operational amplifier is coupled to the voltage-type digital-to-analog converter, the non-inverting input terminal of the operational amplifier is coupled to the drain of the first PMOS transistor (M0), and the operational amplifier The output terminal is coupled to the gate of the first PMOS transistor (M0),

Wherein, the source of the first PMOS transistor (M0) is coupled to the supply voltage (VDD), and the drain of the first PMOS transistor (M0) is grounded through the capacitor (C1).
The driving circuit according to any one of claims 1-3, wherein the narrow pulse generator comprises:

Current-type digital-to-analog converter, configured to receive current DAC numerical control input and generate output current;

A current-controlled delay unit configured to receive the input pulse and be coupled to the current-type digital-to-analog converter to delay the input pulse according to the output current of the current-type digital-to-analog converter;

The non-inverting buffer is configured to temporarily store the input pulse; and

A logic AND gate, the first input terminal of which is connected to the current control delay unit, and the second input terminal is connected to the in-phase buffer, configured to generate the said delayed input pulse and the temporarily stored input pulse The first narrow pulse, wherein the pulse width of the first narrow pulse is the delay difference between the temporarily stored input pulse and the delayed input pulse.
The driving circuit according to any one of claims 1 to 3, wherein the driving unit comprises: a second PMOS transistor (M1) and a first NMOS transistor (M2),

Wherein the gate of the second PMOS transistor (M1) is connected to the gate of the first NMOS transistor (M2) and is configured to receive the first narrow pulse output by the narrow pulse generator,

Wherein, the source of the second PMOS transistor (M1) is connected to the voltage regulator and is configured to receive the output voltage of the voltage regulator, and the source of the first NMOS transistor (M2) is grounded,

Wherein, the drain of the second PMOS transistor (M1) is connected to the drain of the first NMOS transistor (M2), and is configured to output the second narrow pulse.
The driving circuit according to claim 5, wherein the driving unit further comprises:

The pre-drive unit has its input terminal connected to the output terminal of the narrow pulse generator and is configured to amplify the current drive capability of the received first narrow pulse in one or more stages.
7. The driving circuit according to claim 6, wherein the pre-driving unit comprises a cascaded multi-stage inverting amplifier.
A driving method includes:

Generating a first narrow pulse based on the input pulse, the pulse width of the first narrow pulse is smaller than the pulse width of the input pulse;

Produce an adjustable output voltage; and

A second narrow pulse is generated based on the first narrow pulse and the output voltage, wherein the pulse width of the second narrow pulse is approximately equal to the pulse width of the first narrow pulse, and the amplitude of the second narrow pulse is The value depends on the size of the adjustable output voltage.
8. The driving method according to claim 8, wherein said generating an adjustable output voltage further comprises:

Receive numerical control input through voltage-type digital-to-analog converter and generate analog voltage; and

The analog voltage output by the voltage-type digital-to-analog converter is regulated to generate the adjustable output voltage.
The driving method according to claim 8 or 9, wherein the generating the first narrow pulse based on the input pulse further comprises:

Receiving the input pulse and temporarily storing the input pulse;

Receive numerical control input through current-type digital-to-analog converter and generate output current;

Receiving the input pulse, and delaying the input pulse according to the output current of the current-type digital-to-analog converter; and

The first narrow pulse is generated based on the delayed input pulse and the temporarily stored input pulse.
The driving method according to claim 8 or 9, wherein the generating a second narrow pulse based on the first narrow pulse and the output voltage further comprises:

The current driving capability of the received first narrow pulse is amplified in one or more stages.
A laser system includes:

The drive circuit according to any one of claims 1-7;

Laser; and

The gate of the transistor is coupled to the output terminal of the driving circuit, the second narrow pulse is used to control the opening and closing of the transistor, the source of the transistor is grounded, and the drain is coupled to the laser.
The laser system according to claim 12, wherein the laser further comprises: a laser diode, a resistor, a second capacitor, and a freewheeling diode, and the transistor is an NMOS high-power transistor,

Wherein, the cathode of the laser diode is coupled to the drain of the NMOS high-power transistor, the anode of the laser diode passes through the first end of the resistor, and the second end of the resistor is coupled to a second power supply Voltage (HV), the anode of the freewheeling diode is coupled to the cathode of the laser diode, the cathode of the freewheeling diode is coupled to the second end of the resistor, and the second end of the resistor The second capacitor is arranged between the terminal and the ground.
A transient enhanced LDO circuit, including:

An amplifier, one of the input terminals of the amplifier can receive a reference voltage;

A power regulator tube, coupled to the output of the amplifier, and outputting the output voltage of the transient enhanced LDO circuit through the output terminal;

A voltage divider, coupled to the power regulator tube, to couple the output voltage to the other input terminal of the amplifier; and

The sink current absorption circuit is coupled to the output end of the power regulator tube, and is adapted to conduct and absorb the sink current to the LDO circuit according to the fluctuation of the output voltage.
The transient enhancement type LDO circuit according to claim 14, wherein the sink current sink circuit includes a comparator and a pull-down NMOS tube driven by the comparator, wherein one input terminal of the comparator receives and reflects the A fluctuating input signal of the output voltage, the other input terminal of the comparator receives a threshold signal corresponding to the input signal reflecting the fluctuation of the output voltage, and the pull-down NMOS tube is coupled to the output of the power regulator tube Terminal and the output terminal of the comparator, wherein when the output voltage fluctuation amplitude exceeds the voltage amplitude corresponding to the threshold signal, the pull-down NMOS transistor is turned on and absorbs the sink current to the LDO circuit; when the output When the voltage fluctuation amplitude is less than or equal to the voltage amplitude corresponding to the threshold signal, the pull-down NMOS transistor is turned off.
The transient enhancement type LDO circuit according to claim 15, wherein the comparator is a current comparator, and one input terminal of the comparator is connected to an intermediate stage of the amplifier to receive a signal reflecting the output voltage For fluctuating current, the other input terminal is connected to the reference current signal, and the output terminal is connected to the gate of the pull-down NMOS transistor.
The transient enhancement type LDO circuit of claim 15, wherein the inverting input terminal of the amplifier is used to receive the reference voltage, and the non-inverting input terminal of the amplifier is coupled to the power through the voltage divider. An output terminal of the regulator tube, the output terminal of the amplifier is connected to the grid of the power regulator tube;

The voltage divider is a resistance voltage divider, including a first resistor and a second resistor connected in series, the source of the power regulator tube is used to connect to a voltage source (VDD), and the drain of the power regulator tube outputs the Output voltage and be grounded through the voltage divider;

The drain of the pull-down NMOS transistor is coupled to the drain of the power regulator, and the source of the pull-down NMOS transistor is grounded.
The transient enhancement type LDO circuit according to claim 17, further comprising a first capacitor and a third resistor connected in parallel with the voltage divider.
The transient enhancement LDO circuit according to claim 14 or 15, wherein the amplifier (A1) adopts a folded cascode structure.
The transient enhancement LDO circuit according to claim 19, wherein the amplifier (A1) is an error amplifier, and the error amplifier comprises: a first PMOS tube (MP1), a second PMOS tube (MP2), and a third PMOS tube (MP3), fourth PMOS tube (MP4), fifth PMOS tube (MP5), sixth PMOS tube (MP6), seventh PMOS tube (MP7), eighth PMOS tube (MP8), first NMOS tube (MN1), the second NMOS tube (MN2), the third NMOS tube (MN3), and the fourth NMOS tube (MN4);

Among them, the first PMOS tube (MP1) and the second PMOS tube (MP2) form a differential input pair tube, and the gate of the first PMOS tube (MP1) is used as the inverting input terminal of the error amplifier (A1) for Receiving the reference voltage, the gate of the second PMOS tube (MP2) is used as the non-inverting input terminal of the error amplifier (A1);

The third PMOS tube (MP3) and the fourth PMOS tube (MP4) constitute a cascode current source, and the drain of the fourth PMOS tube (MP4) is connected to the drain of the first PMOS tube (MP1) and the second PMOS tube (MP2) drain;

The first NMOS tube (MN1), the second NMOS tube (MN2), the third NMOS tube (MN3) and the fourth NMOS tube (MN4) form a cascode current source, and the source of the second NMOS tube (MN2) is connected To the drain of the first NMOS tube (MN1) and connected to the drain of the second PMOS tube (MP2), the source of the fourth NMOS tube (MN4) is interconnected with the drain of the third NMOS tube (MN3), connected To the drain of the first PMOS tube (MP1) and used as the first intermediate output terminal;

The fifth PMOS tube (MP5), the sixth PMOS tube (MP6), the seventh PMOS tube (MP7) and the eighth PMOS tube (MP8) constitute a cascode current mirror load, the fifth PMOS tube (MP5) and the seventh The gate of the PMOS tube (MP7) is interconnected and connected to the drain of the second NMOS tube (MN2), and used as the second intermediate output terminal; the sixth PMOS tube (MP6) and the eighth PMOS tube (MP8) The gate is interconnected and used as the third intermediate output terminal;

The drains of the eighth PMOS tube (MP8) and the fourth NMOS tube (MN4) are interconnected and used as the output terminal of the error amplifier (A1).
The transient enhancement type LDO circuit according to any one of claims 15-18, wherein the comparator comprises: a fifth NMOS tube (MN5), a sixth NMOS tube (MN6), a ninth PMOS tube (MP9) ) And the tenth PMOS tube (MP10),

Among them, the fifth NMOS tube (MN5) and the sixth NMOS tube (MN6) form a cascode structure and are used as the threshold current terminal of the current comparator (A3).

The ninth PMOS tube (MP9) and the tenth PMOS tube (MP10) form a cascode structure and are used as the signal current terminal of the current comparator (A3).

The drain of the tenth PMOS transistor (MP10) is connected to the drain of the sixth NMOS transistor (MN6) and is used to connect to the gate of the pull-down NMOS transistor (MN0).
The transient enhancement type LDO circuit according to any one of claims 14-18, wherein the input terminal of the amplifier receiving the reference voltage is used to connect to a voltage-type digital-to-analog converter, and according to the voltage-type digital-to-analog converter The output of the converter changes the output voltage of the power regulator; and/or

The transient enhanced LDO circuit further includes a buffer connected between the output terminal of the amplifier and the power regulator tube.
A power circuit of CMOS driver, including:

The transient enhanced LDO circuit according to any one of claims 14-22; and

A voltage-type digital-to-analog converter is connected to the transient enhanced LDO circuit and is configured to convert the received digitally controlled input into an analog voltage as a reference voltage for the amplifier (A1) of the transient enhanced LDO circuit.
A laser system, comprising the power supply circuit, CMOS driver, switch tube and laser as claimed in claim 23;

The power supply circuit is adapted to provide the driving voltage of the CMOS driver;

One end of the CMOS driver receives the driving voltage, and the other end is coupled to the switch tube to control the on and off of the switch tube;

One end of the switch tube is coupled to the CMOS driver and is suitable for modulating the power supply current of the laser.