WO2021031075A1

WO2021031075A1 - Pulse width modulation control circuit, switching power supply, and pulse width modulation control device

Info

Publication number: WO2021031075A1
Application number: PCT/CN2019/101405
Authority: WO
Inventors: 彭布科; 张瑜; 赵德琦; 吴壬华
Original assignee: 深圳欣锐科技股份有限公司
Priority date: 2019-08-19
Filing date: 2019-08-19
Publication date: 2021-02-25
Also published as: CN111418139A

Abstract

A pulse width modulation control circuit, a switching power supply, and a pulse width modulation control device. The pulse width modulation control circuit comprises: a voltage control circuit, a transformer and a rectification circuit, wherein the voltage control circuit comprises a first field-effect transistor (Q1) and a second field-effect transistor (Q2); a gate electrode of the first field-effect transistor is connected to a first driving signal; a gate electrode of the second field-effect transistor is connected to a second driving signal; the frequencies of the first driving signal and the second driving signal are the same and are preset fixed frequencies; and duty cycles of the first driving signal and the second driving signal are the same and are preset fixed duty cycles. The circuit has a simplified control means, and can set, insofar as stable circuit output is ensured, the frequencies and the duty cycles of the first field-effect transistor and the second field-effect transistor as appropriate fixed frequencies and fixed duty cycles, thereby improving the efficiency of the entire machine in terms of circuit control.

Description

Pulse width modulation control circuit, switching power supply and equipment

Technical field

This application relates to the technical field of circuit structures, and in particular to a pulse width modulation control circuit, a switching power supply and a device.

Background technique

With the development of new energy vehicle power supply technology, higher requirements are put forward for the safety of electric vehicles, which requires the DC converter to have the function of bidirectional operation; in the existing topology, boost + logic link control (Boost+ LLC) or boost+shift full bridge (Boost+PSFB) is the most commonly used circuit architecture. Its control method is stepwise control. In traditional control, when the current direction is positive for the field effect transistor, the Pulse width modulation control (Pulse Width Modulation, PWM) is performed on the driving signal of the drive signal, which is controlled as a boost signal to keep the VCbulk voltage constant at a certain value; then the latter stage of LLC is controlled by frequency modulation or PSFB is controlled by phase-shifting PWM to make The output voltage VO remains constant. The same is true in the reverse direction, but the front-end boost circuit is changed to a buck circuit, and the PWM control signal is changed from a boost signal to a buck signal. It can be seen that the secondary drive control signal is quite complicated. How to solve the problem of complicated control of the whole machine, thereby improving efficiency, is a problem being studied by those skilled in the art.

Summary of the invention

The embodiment of the application discloses a pulse width modulation control circuit, a switching power supply, and a pulse width modulation control device, which can solve the problem of complicated control of the whole machine, thereby improving efficiency.

In the first aspect, an embodiment of the present application provides a pulse width modulation control circuit, including: a voltage control circuit, a transformer, and a rectifier circuit. The primary coil of the transformer is connected to the voltage control circuit, and the secondary coil of the transformer is connected to the rectifier circuit. among them:

The voltage control circuit includes a first field effect tube and a second field effect tube, the source of the first field effect tube and the drain of the second field effect tube, and the first coil of the primary coil of the transformer. Terminal connection, the source of the second field effect tube is connected to the second terminal of the primary coil of the transformer;

The gate of the first field effect tube is connected to a first driving signal, and the gate of the second field effect tube is connected to a second driving signal, and the frequency of the first driving signal and the second driving signal are the same And it is a preset fixed frequency, and the duty ratios of the first driving signal and the second driving signal are the same and are the preset fixed duty ratios.

Based on the first aspect, in one of the optional implementation manners, the voltage control circuit further includes a third field effect tube and a fourth field effect tube, wherein:

The source of the third field effect transistor is connected to the drain of the fourth field effect transistor and the second end of the primary coil of the transformer, and the drain of the third field effect transistor is connected to the first The drain of the FET is connected, the source of the fourth FET is connected to the source of the second FET, and the source of the first FET is connected to the source of the second FET. The drain is connected to the first end of the primary coil of the transformer;

The grid of the third field effect tube is connected to a third driving signal, and the grid of the fourth field effect tube is connected to a fourth driving signal. The frequencies of the third driving signal and the fourth driving signal are sum The duty cycle is both the preset fixed frequency and the preset fixed duty cycle.

Based on the first aspect, in one of the optional implementation manners, the voltage control circuit further includes a fifth field effect transistor, a sixth field effect transistor, a first capacitor, a second capacitor, a third capacitor, and a first inductor. And the second inductor, where:

The first end of the first capacitor is connected to the first end of the first inductor, and the second end of the first inductor is connected to the drain of the fifth field effect transistor and the sixth field effect transistor. The source is connected, the drain of the sixth field effect transistor is connected to the first end of the second capacitor and the drain of the first field effect transistor, and the source of the first field effect transistor is connected to the The drain of the second field effect transistor is connected to the first end of the second inductor, and the second end of the second inductor is connected to the first end of the primary coil of the transformer. The second end of the third capacitor is connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the source of the second field effect transistor, the second end of the second capacitor, and the first end of the third capacitor. The source of the field effect transistor and the second end of the first capacitor are connected;

The gate of the fifth field effect transistor is connected to a fifth drive signal, and the gate of the sixth field effect transistor is connected to a sixth drive signal; the fifth drive signal is a pulse width modulation signal; the sixth The driving signal is a pulse width modulation signal.

Based on the first aspect, in one of the optional implementation manners, the rectifier circuit includes: a seventh field effect tube, an eighth field effect tube, a ninth field effect tube, a tenth field effect tube, and a fourth capacitor, among them:

The first port of the rectifier circuit is connected to the source of the seventh field effect transistor and the drain of the eighth field effect transistor, and the second port of the rectifier circuit is connected to the source of the ninth field effect transistor. Is connected to the drain of the tenth field effect transistor, the drain of the seventh field effect transistor is connected to the drain of the eighth field effect transistor and the first port of the fourth capacitor, and the The source of the eight field effect transistor is connected to the source of the tenth field effect transistor and the second port of the fourth capacitor;

The grid of the seventh field effect tube and the grid of the tenth field effect tube are connected to a seventh drive signal, and the grid of the eighth field effect tube is connected to the grid of the ninth field effect tube. Enter the eighth drive signal.

Based on the first aspect, in one of the optional implementation manners, the voltage control circuit further includes a first port, the first port and the first port of the first inductor, and the first port of the first capacitor. One port connection;

The rectifier circuit further includes a second port connected to the drain of the seventh field effect transistor, the drain of the ninth field effect transistor, and the first port of the fourth capacitor.

Based on the first aspect, in one of the optional implementation manners, when the first port provides a first direction current to the voltage control circuit, if the value of the first direction current changes, adjust the The duty cycle of the fifth driving signal to maintain a constant voltage at the second port of the rectifier circuit;

When the second port provides current in the second direction for the rectifier circuit, if the second voltage changes, the duty cycle of the sixth driving signal is adjusted to maintain the first port of the voltage control circuit The voltage of the current is constant, and the current direction of the current in the second direction is opposite to the current direction of the current in the first direction.

Based on the first aspect, in one of the optional implementation manners, when the first port provides the first-direction current for the voltage control circuit, the seventh drive signal is in the first drive signal The first drive signal is turned off after the preset time interval after the turn-on is turned on, and the first drive signal is turned off after the preset time interval after the seventh drive signal is turned off; the eighth drive signal is turned off at the first The second driving signal is turned on after a predetermined time interval after the second driving signal is turned on, and the second driving signal is turned off after the predetermined time interval after the eighth driving signal is turned off.

Based on the first aspect, in one of the optional implementation manners, when the second port provides the current in the second direction for the rectifier circuit, the seventh drive signal turns off when the first drive signal is turned off. Turn off after a preset time interval after turning off, and the first drive signal turns on after the preset time interval after the seventh drive signal turns on; the eighth drive signal turns on after the second The driving signal is turned off after a predetermined time interval after the driving signal is turned off, and the second driving signal is turned on after the predetermined time interval after the eighth driving signal is turned on.

In a second aspect, an embodiment of the present application provides a switching power supply, wherein the switching power supply includes the pulse width modulation control circuit as described in the first aspect.

In a third aspect, an embodiment of the present application provides a pulse width modulation control device, wherein the pulse width modulation control device includes the pulse width modulation control circuit described in the first aspect or the switching power supply described in the second aspect .

In the above embodiment, compared to the shifted PWM control circuit through frequency modulation control or shifted full bridge, the embodiment of this application simplifies the control method. Under the condition that the circuit output is stable, the first FET and the second The frequency and duty cycle of the second field effect tube are set to an appropriate fixed frequency and fixed duty cycle, which greatly improves the efficiency of the whole machine in terms of circuit control.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the embodiments.

FIG. 1 is a schematic structural diagram of a pulse width modulation control circuit provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a voltage control circuit provided by an embodiment of the present application;

3 is a schematic structural diagram of another voltage control circuit provided by an embodiment of the present application;

FIG. 4 is a schematic structural diagram of another pulse width modulation control circuit provided by an embodiment of the present application.

detailed description

The technical solutions in the embodiments of the present application will be described clearly and in detail below in conjunction with the drawings in the embodiments of the present application.

It should be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit the application. The reference to "embodiments" in the specification of this application means that a specific feature, structure or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art clearly and implicitly understand that the embodiments described herein can be combined with other embodiments.

The terms "including" and "having" appearing in the description, claims, and drawings of this solution and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes unlisted steps or units, or optionally also includes Other steps or units inherent to these processes, methods, products or equipment. In addition, the terms "first", "second", "third", etc. are used to distinguish different objects, but not to describe a specific sequence.

It should also be understood that the term "and/or" used in the specification and appended claims of this application refers to any combination of one or more of the items listed in the associated and all possible combinations, and includes these combinations.

The detailed description will be given below in conjunction with the figure.

Figure 1 is a schematic structural diagram of a pulse width modulation control circuit provided by an embodiment of this solution. As shown in Figure 1, the pulse width modulation control circuit includes: a voltage control circuit, a transformer, and a rectifier circuit. The primary coil and voltage of the transformer The control circuit is connected, and the secondary coil of the transformer is connected to the rectifier circuit. Among them, the driving signals of the two field effect tubes in the voltage control circuit adopt a fixed frequency and a fixed duty cycle, and the driving signals of the other two field effect tubes are controlled by PWM, and the output is maintained stable through a transformer and a rectifier circuit. Compared with the shifted PWM control circuit through frequency modulation control or shifted full bridge, the embodiment of the present application simplifies the control method, and greatly improves the efficiency of the whole machine in terms of circuit control while ensuring the stability of the circuit output.

Next, firstly, the voltage control circuit in the pulse width modulation control circuit of the embodiment of the present application will be described. FIG. 2 is a schematic structural diagram of a voltage control circuit provided by an embodiment of this solution. As shown in FIG. 2, the voltage control circuit includes a first The field effect tube Q1 and the second field effect tube Q2, the source of the first field effect tube Q1 is connected to the drain of the second field effect tube Q2 and the first end of the primary coil of the transformer, and the second field effect tube Q2 The source electrode of the transformer is connected to the second end of the primary coil; wherein the gate of the first FET Q1 is connected to the first driving signal, and the gate of the second FET Q2 is connected to the second driving signal, the first The frequency of the driving signal and the second driving signal are the same and the preset fixed frequency, the duty cycle of the first driving signal and the second driving signal are the same and the preset fixed duty cycle; after a lot of experiments and data calculations, the preset Assuming that the fixed frequency is set to be consistent with the resonant frequency of the voltage control circuit, the preset fixed duty cycle can be set close to 50%.

It can be seen that, compared with the shifted PWM control circuit through frequency modulation control or shifted full bridge, the embodiment of the present application simplifies the control method. Under the condition that the circuit output is stable, the first FET Q1 and the second The frequency and duty cycle of the FET Q2 are set to a suitable fixed frequency and fixed duty cycle, which greatly improves the efficiency of the whole machine in terms of circuit control.

The above-mentioned voltage control circuit is a shifted half-bridge circuit. In one of the embodiments, the voltage control circuit may also be a phase shifted full bridge circuit, and further includes a third field effect transistor Q3 and a fourth field effect transistor Q4, Specifically, please refer to FIG. 3. FIG. 3 is a schematic structural diagram of another voltage control circuit provided by an embodiment of this solution. As shown in FIG. 3, the source of the third field effect transistor Q3 and the fourth field effect transistor Q4 The drain is connected to the second end of the primary coil of the transformer, the drain of the third field effect transistor Q3 is connected to the drain of the first field effect transistor Q1, and the source of the fourth field effect transistor Q4 is connected to the second field The source of the effect transistor Q2 is connected, the source of the first FET Q1 is connected to the drain of the second FET Q2 and the first end of the primary coil of the transformer; wherein, the gate of the third FET Q3 The third driving signal is connected, and the gate of the fourth field effect transistor Q4 is connected to the fourth driving signal. The frequency and duty cycle of the third driving signal and the fourth driving signal are both a preset fixed frequency and a preset fixed duty. That is, the preset fixed frequency is set to be consistent with the resonance frequency of the voltage control circuit, and the preset fixed duty cycle can be set to be close to 50%, which is the same as the first drive signal and the second drive signal.

In one of the embodiments, further, the voltage control circuit may further include a fifth field effect transistor Q5, a sixth field effect transistor Q6, a first capacitor, a second capacitor, a third capacitor, a first inductor and a second inductor , Wherein the first end of the first capacitor is connected to the first end of the first inductor, and the second end of the first inductor is connected to the drain of the fifth field effect transistor Q5 and the source of the sixth field effect transistor Q6. The drain of the six field effect transistor Q6 is connected to the first end of the second capacitor and the drain of the first field effect transistor Q1, the source of the first field effect transistor Q1 and the drain of the second field effect transistor Q2 and the second The first end of the inductor is connected, the second end of the second inductor is connected to the first end of the primary coil of the transformer, and the second end of the transformer’s primary coil is connected to the first end of the third capacitor. The two ends are connected to the source of the second field effect transistor Q2, the second end of the second capacitor, the source of the first field effect transistor Q1, and the second end of the first capacitor;

The gate of the fifth field effect transistor Q5 is connected to the fifth drive signal, and the gate of the sixth field effect transistor Q6 is connected to the sixth drive signal; the fifth drive signal is a PWM signal; and the sixth drive signal is a PWM signal.

In one of the embodiments, the rectifier circuit includes a seventh field effect tube, an eighth field effect tube, a ninth field effect tube, a tenth field effect tube, and a fourth capacitor, wherein the first port of the rectifier circuit and the seventh field effect tube The source of the effect tube is connected to the drain of the eighth field effect tube, the second port of the rectifier circuit is connected to the source of the ninth field effect tube and the drain of the tenth field effect tube, and the drain of the seventh field effect tube is connected. Connected with the drain of the eighth field effect transistor and the first port of the fourth capacitor, and the source of the eighth field effect transistor is connected with the source of the tenth field effect transistor and the second port of the fourth capacitor;

The grid of the seventh field effect tube and the grid of the tenth field effect tube are connected to the seventh driving signal, and the grid of the eighth field effect tube and the grid of the ninth field effect tube are connected to the eighth driving signal.

The voltage control circuit further includes a first port, the first port is respectively connected to the first port of the first inductor and the first port of the first capacitor; the rectifier circuit also includes a second port, the second port is respectively connected to the seventh field effect transistor The drain, the drain of the ninth field effect transistor, and the first port of the fourth capacitor are connected;

When the first port provides current in the first direction for the voltage control circuit, if the value of the current in the first direction changes, the duty cycle of the fifth driving signal is adjusted to maintain a constant voltage at the second port of the rectifier circuit.

When the second port provides current in the second direction for the rectifier circuit, if the second voltage changes, adjust the duty cycle of the sixth drive signal to maintain a constant voltage at the first port of the voltage control circuit and the current in the second direction The direction is opposite to that of the current in the first direction.

When the first port provides current in the first direction for the voltage control circuit, the seventh drive signal is turned on after a preset time interval after the first drive signal is turned on, and the first drive signal is turned on after the seventh drive signal is turned off. Turn off after a preset time interval; the eighth drive signal turns on after a preset time interval after the second drive signal turns on, and the second drive signal turns off after a preset time interval after the eighth drive signal turns off .

When the second port provides current in the second direction for the rectifier circuit, the seventh drive signal is turned off after a preset time interval after the first drive signal is turned off, and the first drive signal is pre-set after the seventh drive signal is turned on. It is assumed to be turned on after a time interval; the eighth driving signal is turned off after a preset time interval after the second driving signal is turned off, and the second driving signal is turned on after a preset time interval after the eighth driving signal is turned on.

For example, take FIG. 4 as an example. FIG. 4 is a schematic structural diagram of another pulse width modulation control circuit provided by an embodiment of this solution. As shown in FIG. 4, the first port is the input/output terminal VIN, and the second port Is the input/output terminal VO, the first inductance is L1, the first capacitor is CIN, the voltage of a node between Q1 and Q6 is VCbulk, and the voltage of a node between Q7 and Q9 is VO, it can be understood VO is proportional to VCbulk, VO=VCbulk*Ns/Np, where Ns is the number of turns of the secondary winding of the transformer, and Np is the number of turns of the primary winding of the transformer. When the VIN terminal outputs a forward current, then The current direction of the circuit is the first current direction. The front-end Q5 and Q6 field effect transistors are in boost mode, and the fifth drive signal is PWM controlled. When VIN changes, the duty cycle of the fifth drive signal of Q5 is adjusted, Keep VCbulk constant, thereby maintaining VO stability; when the VO terminal outputs a forward current, the current direction of the circuit is the second current direction, and the sixth drive signal is PWM controlled, VO changes, and VCbulk changes in proportion to VO , The front-end Q5 and Q6 field effect transistors are in the step-down mode, and the duty cycle of the sixth driving signal of Q6 is adjusted to maintain VIN stability.

In the output rectification part of the latter stage, full-bridge rectification is used. When the VIN terminal outputs a forward current, the current direction of the circuit is the first current direction. The driving signal VDRIVE1 and the driving signal VDRIVE4 are the seventh driving signals, and the driving signal VDRIVE1 and VDRIVE4 is exactly the same, the drive signal VDRIVE2 and the drive signal VDRIVE3 are the eighth drive signal, and the drive signal VDRIVE2 is exactly the same as VDRIVE3; the preset time can be 200nS, VDRIVE1 and VDRIVE4 turn on 200nS slower than the first drive signal, and at the same time, VDRIVE1 is compared with VDRIVE4. The first drive signal turns off 200nS faster, VDRIVE2 and VDRIVE3 turn on 200nS slower than the second drive signal, while VDRIVE2 and VDRIVE3 turn off 200nS faster than the second drive signal, which not only ensures the safe operation of the rectifiers, but also Improve the efficiency of the whole machine (compared to diode rectification). Among them, if VDRIVE1 and VDRIVE4 are turned on before the first drive signal or turn off slower than the first drive signal, four field effect transistors Q7 and Q8, Q9 and Q10 will be caused They are turned on together, causing output short circuit. The setting of 200nS not only ensures the safety of each field effect tube, but also does not become too large. The conduction time of the field effect tube is guaranteed, which reduces the loss of the field effect tube and improves the efficiency;

When the VO terminal outputs a forward current, the current direction of the circuit is the second current direction. VDRIVE1 and VDRIVE4, VDRIVE2 and VDRIVE3 are used as reverse switching tubes. The first drive signal is 200nS slower than VDRIVE1 and VDRIVE4, and the first drive The signal turns off 200nS faster than VDRIVE1 and VDRIVE4; the second drive signal turns on 200nS slower than VDRIVE2 and VDRIVE3, and the second drive signal turns off 200nS faster than VDRIVE2 and VDRIVE3. Among them, if VDRIVE1 and VDRIVE4 turn off slower than the first drive signal Turning on or turning off before the first drive signal will cause the four FETs Q7 and Q8, Q9 and Q10 to be turned on together, resulting in an output short circuit. The 200nS setting not only ensures the safety of each FET, but also does not cause too much damage. Larger, the conduction time of the field effect tube is guaranteed, the loss of the field effect tube is reduced, and the efficiency is improved.

It can be seen that, because the circuit of the embodiment of the application is in resonance under any input and load conditions, its efficiency is the highest, which is of great significance to the efficiency of the whole machine; on the other hand, because of the first field The switching frequency and duty cycle of the effect tube Q1 and the second field effect tube Q2 are fixed, which is also very beneficial for the electromagnetic compatibility of the whole machine.

In a possible implementation manner, an embodiment of the present application further provides a switching power supply, and the switching power supply includes the pulse width modulation control circuit provided in any of the foregoing application embodiments.

Wherein, the pulse width modulation control circuit in the switching power supply is the same as the pulse width modulation control circuit described in any of the above-mentioned application embodiments, and will not be described here.

In a possible implementation manner, an embodiment of the present application provides a pulse width modulation control device. The pulse width modulation control device includes the pulse width modulation control power supply circuit provided in any of the above application embodiments or the switching power supply provided in the above application embodiments. .

Wherein, the pulse width modulation control circuit in the pulse width modulation control device is the same as the pulse width modulation control circuit described in any of the above application embodiments, and will not be described here.

A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing relevant hardware through a computer program. The program can be stored in a computer readable storage medium. At this time, it may include the procedures of the above-mentioned method embodiments. The aforementioned storage media include: magnetic disks, optical disks, read-only memory (Read-Only Memory, ROM), or random access memory (Random Access Memory, RAM).

In the several embodiments provided in this application, it should be understood that the disclosed device may be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the above-mentioned circuits is only a logical function division, and there may be other divisions in actual implementation, for example, multiple circuits or components can be combined or integrated. To another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or circuits, and may be in electrical or other forms.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Anyone familiar with the technical field can easily think of various equivalents within the technical scope disclosed in this application. Modifications or replacements, these modifications or replacements shall be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

It should be understood that, in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application. The implementation process constitutes any limitation. Although the present application has been described in conjunction with various embodiments, those skilled in the art can understand and implement other changes in the disclosed embodiments during the process of the present application claimed by the embodiments.

Claims

A pulse width modulation control circuit, which is characterized by comprising: a voltage control circuit, a transformer, and a rectifier circuit. The primary coil of the transformer is connected to the voltage control circuit, and the secondary coil of the transformer is connected to the rectifier circuit, wherein:

The voltage control circuit includes a first field effect tube and a second field effect tube, the source of the first field effect tube and the drain of the second field effect tube, and the first coil of the primary coil of the transformer. Terminal connection, the source of the second field effect tube is connected to the second terminal of the primary coil of the transformer;

The gate of the first field effect tube is connected to a first driving signal, and the gate of the second field effect tube is connected to a second driving signal, and the frequency of the first driving signal and the second driving signal are the same And it is a preset fixed frequency, and the duty ratios of the first driving signal and the second driving signal are the same and are the preset fixed duty ratios.
The pulse width modulation control circuit according to claim 1, wherein the voltage control circuit further comprises a third field effect tube and a fourth field effect tube, wherein:

The source of the third field effect transistor is connected to the drain of the fourth field effect transistor and the second end of the primary coil of the transformer, and the drain of the third field effect transistor is connected to the first The drain of the FET is connected, the source of the fourth FET is connected to the source of the second FET, and the source of the first FET is connected to the source of the second FET. The drain is connected to the first end of the primary coil of the transformer;

The grid of the third field effect tube is connected to a third driving signal, and the grid of the fourth field effect tube is connected to a fourth driving signal. The frequencies of the third driving signal and the fourth driving signal are sum The duty cycle is both the preset fixed frequency and the preset fixed duty cycle.
The pulse width modulation control circuit according to claim 1 or 2, wherein the voltage control circuit further comprises a fifth field effect transistor, a sixth field effect transistor, a first capacitor, a second capacitor, a third capacitor, The first inductor and the second inductor, where:

The first end of the first capacitor is connected to the first end of the first inductor, and the second end of the first inductor is connected to the drain of the fifth field effect transistor and the sixth field effect transistor. The drain of the sixth field effect transistor is connected to the first end of the second capacitor and the drain of the first field effect transistor. The source of the first field effect transistor is connected to the The drain of the second field effect transistor is connected to the first end of the second inductor, and the second end of the second inductor is connected to the first end of the primary coil of the transformer. The second end of the third capacitor is connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the source of the second field effect transistor, the second end of the second capacitor, and the first end of the third capacitor. The source of the field effect transistor and the second end of the first capacitor are connected;

The gate of the fifth field effect transistor is connected to a fifth drive signal, and the gate of the sixth field effect transistor is connected to a sixth drive signal; the fifth drive signal is a pulse width modulation signal; the sixth The driving signal is a pulse width modulation signal.
The pulse width modulation control circuit according to claim 3, wherein the rectifier circuit comprises: a seventh field effect tube, an eighth field effect tube, a ninth field effect tube, a tenth field effect tube, and a fourth capacitor ,among them:

The first port of the rectifier circuit is connected to the source of the seventh field effect transistor and the drain of the eighth field effect transistor, and the second port of the rectifier circuit is connected to the source of the ninth field effect transistor. Is connected to the drain of the tenth field effect transistor, the drain of the seventh field effect transistor is connected to the drain of the eighth field effect transistor and the first port of the fourth capacitor, and the The source of the eight field effect transistor is connected to the source of the tenth field effect transistor and the second port of the fourth capacitor;

The grid of the seventh field effect tube and the grid of the tenth field effect tube are connected to a seventh drive signal, and the grid of the eighth field effect tube is connected to the grid of the ninth field effect tube. Enter the eighth drive signal.
The pulse width modulation control circuit of claim 4, wherein the voltage control circuit further comprises a first port, the first port and the first port of the first inductor and the The first port connection;

The rectifier circuit further includes a second port connected to the drain of the seventh field effect transistor, the drain of the ninth field effect transistor, and the first port of the fourth capacitor.
The circuit of claim 5, wherein:

When the first port provides current in the first direction for the voltage control circuit, if the value of the current in the first direction changes, adjust the duty cycle of the fifth drive signal to maintain the rectifier circuit The voltage of the second port is constant;

When the second port provides current in the second direction for the rectifier circuit, if the second voltage changes, the duty cycle of the sixth driving signal is adjusted to maintain the first port of the voltage control circuit The voltage of the current is constant, and the current direction of the current in the second direction is opposite to the current direction of the current in the first direction.
The circuit according to claim 5 or 6, wherein when the first port provides the voltage control circuit with the current in the first direction, the seventh drive signal is guided by the first drive signal The first driving signal is turned off after the preset time interval after the turn-off of the seventh driving signal; and the eighth driving signal is turned off after the second driving signal is turned off. The driving signal is turned on after a predetermined time interval after the driving signal is turned on, and the second driving signal is turned off after the predetermined time interval after the eighth driving signal is turned off.
7. The circuit according to claim 7, wherein when the second port provides the second direction current to the rectifier circuit, the seventh drive signal after the first drive signal is turned off Turn off after a preset time interval, and the first drive signal turns on after the preset time interval after the seventh drive signal turns on; the eighth drive signal turns off after the second drive signal Turn off after a predetermined time interval after turning off, and the second drive signal turns on after the predetermined time interval after the eighth drive signal turns on.
A switching power supply, wherein the switching power supply comprises the pulse width modulation control circuit according to any one of claims 1-8.
A pulse width modulation control device, characterized in that the pulse width modulation control device comprises the pulse width modulation control circuit according to any one of claims 1-8 or the switching power supply according to claim 9.