WO2021030958A1 - 电磁故障注入的检测电路、安全芯片和电子设备 - Google Patents

电磁故障注入的检测电路、安全芯片和电子设备 Download PDF

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Publication number
WO2021030958A1
WO2021030958A1 PCT/CN2019/101081 CN2019101081W WO2021030958A1 WO 2021030958 A1 WO2021030958 A1 WO 2021030958A1 CN 2019101081 W CN2019101081 W CN 2019101081W WO 2021030958 A1 WO2021030958 A1 WO 2021030958A1
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Prior art keywords
mos transistors
latch
detection circuit
signal
shielding layer
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PCT/CN2019/101081
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English (en)
French (fr)
Inventor
薛建锋
杨江
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深圳市汇顶科技股份有限公司
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Priority to CN201980004310.1A priority Critical patent/CN111095004B/zh
Priority to PCT/CN2019/101081 priority patent/WO2021030958A1/zh
Priority to EP19919547.0A priority patent/EP3812946B1/en
Priority to US17/025,823 priority patent/US11181566B2/en
Publication of WO2021030958A1 publication Critical patent/WO2021030958A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/08—Measuring electromagnetic field characteristics
    • G01R29/0807—Measuring electromagnetic field characteristics characterised by the application
    • G01R29/0814—Field measurements related to measuring influence on or from apparatus, components or humans, e.g. in ESD, EMI, EMC, EMP testing, measuring radiation leakage; detecting presence of micro- or radiowave emitters; dosimetry; testing shielding; measurements related to lightning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/001—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing
    • G01R31/002—Measuring interference from external sources to, or emission from, the device under test, e.g. EMC, EMI, EMP or ESD testing where the device under test is an electronic circuit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/004—Countermeasures against attacks on cryptographic mechanisms for fault attacks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers

Definitions

  • the embodiments of the present application relate to the field of electronics, and more specifically, to a detection circuit for electromagnetic fault injection, a security chip, and an electronic device.
  • Security chips can be used to realize functions such as user identification and key data storage. They are widely used in the financial field and are a key target of attackers. By injecting faults, the attacker can make the chip's working status wrong, and then obtain the chip's confidential data.
  • Electromagnetic Fault Inject is a new type of security chip attack method. By placing a magnetic field probe on the chip surface, the attacker can inject electromagnetic radiation into the chip, causing the circuit to produce incorrect timing or abnormal flipping, which in turn makes the system Entering an abnormal working state causes the key information of the chip to leak.
  • the embodiments of the present application provide a detection circuit, a safety chip, and an electronic device for electromagnetic fault injection, which can detect and warn the electromagnetic fault injection in real time, thereby ensuring the robustness and safety of the chip.
  • an electromagnetic fault injection detection circuit including:
  • Shielding layer used to shield interference
  • At least one set of metal oxide semiconductor MOS transistors the source terminals of the at least one set of MOS transistors are connected to the shielding layer;
  • At least one latch the drain terminal of the at least one set of MOS transistors is connected to the input terminal of the at least one latch;
  • a signal output module the input terminal of the signal output module is connected to the output terminal of the at least one latch, and the signal output module is configured to generate and output a target signal based on a voltage change at the output terminal of the at least one latch ,
  • the target signal is used to indicate whether there is electromagnetic fault injection in the shielding layer;
  • the signal output module when part or all of the MOS in the at least one group of MOS transistors are turned on, the signal output module is used to output a first target signal, and the first target signal is used to indicate that electromagnetic fault injection exists in the shielding layer, When the at least one group of MOS transistors are all disconnected, the signal output module is used to output a second target signal, and the second target signal is used to indicate that there is no electromagnetic fault injection in the shielding layer.
  • the at least one set of MOS transistors can detect whether an abnormal voltage is present on the shielding layer, and the latch corresponding to the at least one set of MOS transistors can output a detection signal identifiable by the signal output module 15 for real-time detection. And timely early warning of electromagnetic fault injection to ensure the robustness and safety of the chip.
  • designing an electromagnetic fault injection detection circuit based on the shielding layer can effectively simplify the circuit structure, save circuit area, avoid static power consumption, and reduce circuit cost.
  • the drain terminal of the first group of MOS transistors in the at least one group of MOS transistors is connected to the input terminal of the first latch in the at least one latch, and the first group of MOS transistors
  • the gate terminal of the MOS tube is connected to the ground voltage, and the input terminal of the first latch is connected to the power supply voltage.
  • the detection circuit further includes:
  • a first switch the input terminal of the first latch is connected to the power supply voltage through the first switch.
  • the drain terminal of the second group of MOS transistors in the at least one group of MOS transistors is connected to the input terminal of the second latch of the at least one latch, and the second group of MOS transistors
  • the gate terminal of the MOS tube is connected to the power supply voltage, and the input terminal of the second latch is connected to the ground voltage.
  • the detection circuit further includes:
  • the input terminal of the second latch is connected to the ground voltage through the second switch.
  • the detection circuit further includes:
  • the output terminal of the second latch is connected to the input terminal of the signal output module through the first inverter, and the signal output module is configured to generate a signal based on a voltage change at the output terminal of the first inverter And output the target signal.
  • the shielding layer includes:
  • At least one metal wire At least one metal wire
  • At least one detection node is provided on the at least one metal wire, and the at least one detection node is connected to the input terminal of the at least one latch through the at least one set of MOS transistors.
  • the at least one group of MOS transistors are multiple groups of MOS transistors, and the drain terminals of different groups of MOS transistors in the multiple groups of MOS transistors are connected to the input terminals of different latches.
  • the at least one group of MOS transistors are multiple groups of MOS transistors, and different groups of MOS transistors in the multiple groups of MOS transistors include different types of MOS transistors.
  • each of the at least one latch includes:
  • the input terminal of the second inverter is connected to the output terminal of the third inverter, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the second inverter
  • the input terminal of the inverter or the input terminal of the third inverter is the input terminal of the latch.
  • the signal output module includes a first output terminal and a second output terminal, and the output of the first output terminal is inverted from the output of the second output terminal.
  • the signal output module is a D flip-flop.
  • a security chip including:
  • a transmitter for generating and outputting the first signal
  • the receiver is connected to the transmitter through the shielding layer, and the receiver is configured to receive the first signal output by the transmitter through the shielding layer, and output a second signal based on the first signal signal;
  • a digital processor connected to the transmitter and the receiver respectively, and the digital processor is configured to receive the first signal output by the transmitter and the first signal output by the receiver Two signals, and determining whether the shielding layer is damaged based on the first signal and the second signal;
  • the shielding layer is the shielding layer in the detection circuit.
  • an electronic device including the security chip described in the second aspect.
  • Fig. 1 is a schematic circuit diagram of an electromagnetic fault injection detection circuit according to an embodiment of the present application.
  • Fig. 2 is a schematic circuit diagram of a modified structure of the detection circuit shown in Fig. 1.
  • Fig. 3 is a schematic structural diagram of a signal output module according to an embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of a security chip according to an embodiment of the present application.
  • FIG. 1 is a schematic circuit diagram of an electromagnetic fault injection detection circuit 10 according to an embodiment of the present application.
  • the detection circuit 10 may include a shielding layer 11, at least one set of Metal-Oxide Semiconductor (MOS) tubes, at least one latch, and a signal output module 15.
  • MOS Metal-Oxide Semiconductor
  • the shielding layer 11 is used to shield interference. It can be the shielding layer of an existing security chip, or the shielding layer of any other device or component.
  • the source end of the at least one group of MOS transistors is connected to the at least one lock.
  • the input terminal of the signal output module 15 is connected to the output terminal of the at least one latch, and the signal output module 15 is used to generate voltage changes based on the output terminal of the at least one latch And output a target signal, the target signal is used to indicate whether there is electromagnetic fault injection in the shielding layer 11; wherein, when part or all of the MOS in the at least one group of MOS transistors are turned on, the signal output module 15 is used for Output a first target signal, the first target signal is used to indicate that the shielding layer 11 has electromagnetic fault injection, when the at least one set of MOS transistors are all disconnected, the signal output module 15 is used to output a second target signal The second target signal is used to indicate that there is no electromagnetic fault injection in the shielding layer 11.
  • the signal output module 15 may be configured to output the first target signal when some or all of the MOS transistors in the at least one group of MOS transistors are turned on, and when the at least one group of MOS transistors are all turned off.
  • a second target signal is output, the first target signal is used to indicate that the shielding layer 11 has electromagnetic fault injection, and the second target signal is used to indicate that the shielding layer 11 does not have electromagnetic fault injection.
  • the at least one set of MOS transistors can detect whether an abnormal voltage is present on the shielding layer, and the latch corresponding to the at least one set of MOS transistors can output a detection signal identifiable by the signal output module 15 for real-time detection. And timely early warning of electromagnetic fault injection to ensure the robustness and safety of the chip.
  • designing an electromagnetic fault injection detection circuit based on the shielding layer can effectively simplify the circuit structure, save circuit area, avoid static power consumption, and reduce circuit cost.
  • the drain terminal of the first group of MOS transistors 120 of the at least one group of MOS transistors can be connected to the input terminal of the first latch of the at least one latch, and the The gate terminal of the first group of MOS transistors 120 can be connected to the ground voltage, and the input terminal of the first latch can be connected to the power supply voltage.
  • the first group of MOS transistors 120 can be used to detect whether the shielding layer 11 has an abnormal phenomenon that the voltage value is lower than the ground voltage.
  • the gate of the first NMOS transistor 121 is connected to the ground voltage, and the source of the first NMOS transistor 121 is connected To the shielding layer 11, the drain terminal of the first NMOS transistor 121 is connected to the first latch 13.
  • the shielding layer 11 will generate an induced current, causing the voltage of the shielding layer 11 to change, which in turn causes the voltage range of the shielding layer 11 to exceed VSS to VDD.
  • the first NMOS transistor 121 is turned on, which in turn causes the input of the first latch 13
  • the voltage drop at the input end of the first latch 13 causes the voltage at the output end of the first latch 13 to rise, and the signal output module 15 depends on the output end of the first latch 13
  • the voltage changes, and the output is used to indicate the first target signal to indicate that the shielding layer 11 has electromagnetic fault injection.
  • Fig. 2 is a schematic circuit diagram of a specific implementation of the detection circuit shown in Fig. 1.
  • the detection circuit 10 may further include a first switch 16.
  • the input terminal of the first latch 13 is connected to the power supply voltage VDD through the first switch 16 to ensure that the input terminal of the first latch is in a high voltage state, for example, in the first latch Before an NMOS transistor 121 is turned on, the first switch 16 is turned on to make the voltage at the input end of the first latch 13 equal to the power supply voltage.
  • the drain terminal of the second group of MOS transistors 130 of the at least one group of MOS transistors is connected to the input terminal of the second latch of the at least one latch, and the The gate terminal of the second group of MOS transistors 130 is connected to the power supply voltage, and the input terminal of the second latch is connected to the ground voltage.
  • the second group of MOS transistors 130 can be used to detect whether the shielding layer 11 has an abnormal phenomenon that the voltage value is higher than the power supply voltage.
  • the gate of the first PMOS transistor 122 is connected to the power supply voltage, and the source of the first PMOS transistor 122 is connected To the shielding layer 11, the drain terminal of the first PMOS tube 122 is connected to the second latch 14.
  • the shielding layer 11 will generate an induced current, causing the voltage of the shielding layer 11 to change, which in turn causes the voltage range of the shielding layer 11 to exceed VSS to VDD.
  • the first PMOS transistor 122 is turned on, thereby causing the second latch 14
  • the voltage at the input end of the second latch 14 rises, and the voltage at the input end of the second latch 14 rises, which causes the voltage at the output end of the second latch 14 to fall.
  • the signal output module 15 adjusts according to the second latch 14 The voltage change at the output terminal of, outputs a signal used to indicate the first target to indicate that the shielding layer 11 has electromagnetic fault injection.
  • the detection circuit 10 may further include a second switch 17.
  • the input terminal of the second latch 14 is connected to the ground voltage through the second switch 17 to ensure that the input terminal of the second latch 14 is turned on at the first PMOS transistor 122 Before the first PMOS transistor 122 is turned on, for example, the second switch 17 is turned on to make the voltage at the input terminal of the second latch 14 equal to the ground voltage.
  • the detection circuit 10 may further include a first inverter 18.
  • the output terminal of the second latch 14 is connected to the input terminal of the signal output module 15 through the first inverter 18, and the signal output module 15 is configured to be based on the first inverter
  • the voltage change at the output terminal of 18 generates and outputs the target signal. Therefore, when the signal detection circuit 10 includes the first group of MOS transistors 120 and the second group of MOS transistors 130 at the same time, by detecting the rising edge of the first latch 13 and the first inversion The rising edge of the device 18 generates the target signal, which avoids detecting the rising edge of the first latch 13 and the falling edge of the second latch 14 at the same time, thereby reducing the complexity of the signal output module 15 .
  • the second latch 14 may include a second inverter 181 and a third inverter 182, and the input terminal of the second inverter 181 is connected to the third inverter
  • the output terminal of the second inverter 181 is connected to the input terminal of the third inverter 182, and the drain terminal of the second group of MOS transistors 130 can be connected to the second inverter.
  • the input terminal of the second inverter 181 and the output terminal of the second inverter 181 are connected to the signal output module 15.
  • each group of MOS transistors in the at least one group of MOS transistors may include only one MOS transistor, or may include multiple MOS transistors, which is not specifically limited in the embodiment of the present application.
  • the first group of MOS transistors 120 may only include the first NMOS transistor 121
  • the second group of MOS transistors 130 may only include the first PMOS transistor 122.
  • the first group of MOS transistors 120 may also include a second NMOS transistor 131 and a third NMOS transistor 141
  • the second group of MOS transistors 130 may also include a second PMOS transistor 132 and a third NMOS transistor.
  • Three PMOS tubes 142 are shown.
  • first group of MOS transistors 120 and the second group of MOS transistors 130 may be separately Including other numbers of MOS tubes.
  • the shielding layer 11 may include at least one metal wire; at least one detection node is provided on the at least one metal wire, and the at least one detection node is connected through the at least one set of MOS transistors. To the input terminal of the at least one latch.
  • the first metal wire may be provided with at least one first detection node and/or at least one second detection node, and the at least one set of MOS transistors
  • the first group of MOS transistors 120 is connected to the first latch of the at least one latch through the at least one first detection node, and the second group of MOS transistors 130 of the at least one group of MOS transistors can pass all
  • the at least one second detection node is connected to a second latch of the at least one latch.
  • the drain terminals of all MOS transistors in the same group of MOS transistors in the at least one group of MOS transistors are connected to the input terminals of the same latch.
  • the drain terminals of different groups of MOS transistors in the at least one group of MOS transistors are connected to the input terminals of different latches.
  • the drain terminals of the first group of MOS transistors 120 can be connected to the input terminals of the first latch 13, and the drain terminals of the second group of MOS transistors can be connected to the second latch.
  • a part of the at least one group of MOS transistors is connected to the first first latch 13, and another part of the at least one group of MOS transistors is connected to the second latch. ⁇ 14.
  • the part of the group of MOS transistors may include at least one group of MOS transistors of the same type
  • the other group of MOS transistors may include at least one group of MOS transistors of the same type of MOS transistors.
  • the MOS transistor types of the MOS transistors in the MOS transistors in the partial group and the MOS transistors in the MOS transistors in the other partial group may be the same or different, which is not specifically limited in this application.
  • the at least one group of MOS transistors are multiple groups of MOS transistors, and different groups of MOS transistors in the multiple groups of MOS transistors include different types of MOS transistors.
  • MOS transistors include, but are not limited to, "N-type” MOS transistors (NMOSFET) and “P-type” MOS transistors (PMOSFET).
  • NMOSFET NMOSFET
  • PMOSFET P-type MOS transistors
  • the gate terminal of the "N-type” MOS tube is connected to the high voltage It is usually turned on and turned off when connected to a low level; when the gate terminal of a "P-type” MOS tube (a MOS tube with a PN junction pointing outward or a MOS tube with current flowing in) is connected to a high level, it is turned off, and when connected to a low level, it is turned on.
  • the at least one group of MOS transistors includes multiple MOS transistors of different types.
  • MOS transistors in the at least one group of MOS transistors are connected to the input terminals of different latches.
  • the NMOS transistor in the at least one group of MOS transistors can be connected to the input terminal of the first latch 13
  • the drain terminal of the PMOS transistor in the at least one group of MOS transistors can be connected to all The input terminal of the second latch 14.
  • Fig. 3 is a schematic structural diagram of a signal output module according to an embodiment of the present application.
  • the signal output module 15 may be a D flip-flop.
  • the reset (RESET) terminal B of the D flip-flop is connected to a reset signal W, for example, the reset signal W may be the control signal of the first switch 16 or the control signal of the second switch 17;
  • the D terminal of the D flip-flop is connected to VDD;
  • the detection terminal A of the D flip-flop is connected to the output terminal of the first latch 13 or the output terminal of the first inverter 18 for receiving a detection signal ,
  • the output terminal Q of the D flip-flop outputs a target signal (that is, an ALARM signal).
  • the signal generating circuit 13 may also be other devices, such as a comparator.
  • the signal output module 15 may include a first output terminal and a second output terminal, and the output of the first output terminal is inverted from the output of the second output terminal. That is, the target signal output by the signal output module 15 may be a differential signal.
  • FIG. 4 is a schematic structural diagram of a security chip 20 according to an embodiment of the present application.
  • the security chip 20 may include a transmitter 21, a shielding layer 22, a receiver 23 and a digital processor 24.
  • the shielding layer 22 may be the shielding layer 11 shown in FIG. 1 or FIG. 2, and the transmitter 21 is used to generate and output the first signal; the receiver 23 may be connected to the shielding layer 11 through the shielding layer 11.
  • the transmitter 21, the receiver 23 can be used to receive the first signal output by the transmitter 21 through the shielding layer 11, and output a second signal based on the first signal;
  • the digital processors 24 are respectively connected To the transmitter 21 and the receiver 23, the digital processor 24 can be used to receive the first signal output by the transmitter 21 and the second signal output by the receiver 23, and based on The first signal and the second signal determine whether the shielding layer 11 is damaged (for example, physically damaged).
  • the security chip 20 may include a protected chip body circuit, a shielding layer 22 of the chip body circuit, a circuit for detecting whether the shielding layer 22 is damaged, and a circuit for detecting whether the shielding layer 22 exists.
  • the shielding layer 11 can be used as a circuit for detecting whether the shielding layer 22 is damaged and a device or element in the detecting circuit 10.
  • the present application also provides an electronic device, which may include the security chip 20 shown in FIG. 4.
  • the electronic device may include the security chip described above.
  • portable or mobile computing devices such as smart phones, notebook computers, tablet computers, and gaming devices, as well as other electronic devices such as electronic databases, automobiles, and bank automated teller machines (ATM).
  • ATM bank automated teller machines
  • the embodiments of the present application are not limited thereto.
  • FIGS. 1 to 4 are only examples of this application, and should not be construed as a limitation to this application.
  • the detection circuit 10 may also include a threshold judgment module.
  • the output terminal of the at least one latch is connected to the signal output module 15 through the threshold judgment module, and the threshold judgment module is used to amplify the signal output by the at least one latch and amplify The signal is sent to the signal output module 15.
  • the threshold decision module may include a fourth inverter and a fifth inverter, the output terminal of the at least one latch is connected to one end of the fifth inverter through the fourth inverter, and The other end of the fifth inverter is connected to the signal output module 15.
  • the switching threshold of the fourth inverter may be smaller than the switching threshold of the fifth inverter.
  • the flip threshold of the fourth inverter is 0.3
  • the flip threshold of the fifth inverter is 0.8.
  • the sensitivity of the detection circuit 10 is improved by reducing the flip threshold of the fourth inverter, and By increasing the flip threshold of the fifth inverter, the stability of the detection circuit 10 is ensured.
  • the foregoing 0.3 and 0.8 are only examples, and the present application does not specifically limit the inversion threshold of the fourth inverter and the inversion threshold of the fifth inverter.
  • the threshold judgment module Through the cooperation of the threshold judgment module, the detection accuracy of electromagnetic fault injection can be improved, and the sensitivity of the detection circuit 10 can be further improved.
  • circuits, branches, and modules may be implemented in other ways.
  • the branches described above are illustrative.
  • the division of the modules is only a logical function division, and there may be other divisions in actual implementation.
  • multiple modules can be combined or integrated into one branch. Road, or some features can be ignored or not implemented.
  • the integrated module is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

Abstract

提供了一种电磁故障注入的检测电路、安全芯片和电子设备，电磁故障注入的检测电路包括：屏蔽层，用于屏蔽干扰；至少一组金属氧化物半导体MOS管，所述至少一组MOS管的源端连接至所述屏蔽层；至少一个锁存器，所述至少一组MOS管的漏端连接至所述至少一个锁存器的输入端；信号输出模块，所述信号输出模块的输入端连接至所述至少一个锁存器的输出端。所述检测电路能够实时检测并及时预警电磁故障注入，以保证芯片的鲁棒性与安全性。此外，基于屏蔽层设计电磁故障注入的检测电路，能够达到有效简化电路结构、节省电路面积、避免出现静态功耗以及降低电路成本等目的。

Description

电磁故障注入的检测电路、安全芯片和电子设备 技术领域
本申请实施例涉及电子领域，并且更具体地，涉及电磁故障注入的检测电路、安全芯片和电子设备。
背景技术
安全芯片可以用于实现用户身份识别与关键数据存储等功能，其被广泛应用于金融领域，是攻击者的重点攻击对象。攻击者通过注入故障可以使芯片工作状态发生错误，进而获取芯片机密数据。
电磁故障注入(Electromagnetic Fault Inject,EMFI)是一种新型的安全芯片攻击手段，攻击者通过将磁场探头至于芯片表面，可以在芯片局部注入电磁辐射，导致电路产生错误时序或异常翻转，进而使得系统进入异常工作状态而造成芯片关键信息泄露。
因此，本领域急需一种检测电路，以实时检测并及时预警电磁故障注入，进而保证芯片的鲁棒性与安全性。
发明内容
本申请实施例提供一种电磁故障注入的检测电路、安全芯片和电子设备，能够实时检测并及时预警电磁故障注入，进而保证芯片的鲁棒性与安全性。
第一方面，提供了一种电磁故障注入的检测电路，包括：
屏蔽层，用于屏蔽干扰；
至少一组金属氧化物半导体MOS管，所述至少一组MOS管的源端连接至所述屏蔽层；
至少一个锁存器，所述至少一组MOS管的漏端连接至所述至少一个锁存器的输入端；
信号输出模块，所述信号输出模块的输入端连接至所述至少一个锁存器的输出端，所述信号输出模块用于基于所述至少一个锁存器的输出端的电压变化生成并输出目标信号，所述目标信号用于指示所述屏蔽层是否存在电磁故障注入；
其中，所述至少一组MOS管中的部分或全部MOS导通时，所述信号 输出模块用于输出第一目标信号，所述第一目标信号用于指示所述屏蔽层存在电磁故障注入，所述至少一组MOS管均断开时，所述信号输出模块用于输出第二目标信号，所述第二目标信号用于指示所述屏蔽层不存在电磁故障注入。
通过所述至少一组MOS管能够检测出所述屏蔽层是否出现异常电压，通过所述至少一组MOS管对应的锁存器能够输出所述信号输出模块15可识别的检测信号，进而实时检测并及时预警电磁故障注入，以保证芯片的鲁棒性与安全性。
此外，基于屏蔽层设计电磁故障注入的检测电路，能够达到有效简化电路结构、节省电路面积、避免出现静态功耗以及降低电路成本等目的。
在一些可能的实现方式中，所述至少一组MOS管中的第一组MOS管的漏端连接至所述至少一个锁存器中的第一锁存器的输入端，所述第一组MOS管的栅端连接至地电压，所述第一锁存器的输入端连接至电源电压。
在一些可能的实现方式中，所述检测电路还包括：
第一开关，所述第一锁存器的输入端通过所述第一开关连接至所述电源电压。
在一些可能的实现方式中，所述至少一组MOS管中的第二组MOS管的漏端连接至所述至少一个锁存器中的第二锁存器的输入端，所述第二组MOS管的栅端连接至电源电压，所述第二锁存器的输入端连接至地电压。
在一些可能的实现方式中，所述检测电路还包括：
第二开关；
所述第二锁存器的输入端通过所述第二开关连接至所述地电压。
在一些可能的实现方式中，所述检测电路还包括：
第一反相器；
所述第二锁存器的输出端通过所述第一反相器连接至所述信号输出模块的输入端，所述信号输出模块用于基于所述第一反相器的输出端的电压变化生成并输出所述目标信号。
在一些可能的实现方式中，所述屏蔽层包括：
至少一个金属线；
所述至少一个金属线上设置有至少一个检测节点，所述至少一个检测节点通过所述至少一组MOS管连接至所述至少一个锁存器的输入端。
在一些可能的实现方式中，所述至少一组MOS管为多组MOS管，所述多组MOS管中的不同组MOS管的漏端连接至不同锁存器的输入端。
在一些可能的实现方式中，所述至少一组MOS管为多组MOS管，所述多组MOS管中的不同组MOS管包括不同类型的MOS管。
在一些可能的实现方式中，所述至少一个锁存器中的每个锁存器包括：
第二反相器和第三反相器；
所述第二反相器的输入端连接至所述第三反相器的输出端，所述第二反相器的输出端连接至所述第三反相器的输入端，所述第二反相器的输入端或所述第三反相器的输入端为锁存器的输入端。
在一些可能的实现方式中，所述信号输出模块包括第一输出端和第二输出端，所述第一输出端的输出与所述第二输出端的输出反相。
在一些可能的实现方式中，所述信号输出模块为D触发器。
第二方面，提供了一种安全芯片，包括：
发射器，用于生成并输出第一信号；
屏蔽层；
接收器，所述接收器通过所述屏蔽层连接至所述发射器，所述接收器用于通过所述屏蔽层接收所述发射器输出的第一信号，并基于所述第一信号输出第二信号；
数字处理器，所述数字处理器分别连接至所述发射器和所述接收器，所述数字处理器用于接收所述发射器输出的所述第一信号和所述接收器输出的所述第二信号，并基于所述第一信号和所述第二信号确定所述屏蔽层是否被破坏；
第一方面或第一方面中任一可能的实现方式中所述的检测电路；
其中，所述屏蔽层为所述的检测电路中的屏蔽层。
第三方面，提供了一种电子设备，包括第二方面所述的安全芯片。
附图说明
图1是本申请实施例的电磁故障注入的检测电路的示意性电路图。
图2是图1所示的检测电路的变形结构的示意性电路图。
图3是本申请实施例的信号输出模块的示意性结构图。
图4是本申请实施例的安全芯片的示意性结构图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
图1是本申请实施例的电磁故障注入的检测电路10的示意性电路图。
请参见图1，所述检测电路10可以包括屏蔽层11、至少一组金属氧化物半导体(Metal-Oxide Semiconductor，MOS)管、至少一个锁存器以及信号输出模块15。
屏蔽层11用于屏蔽干扰，其可以是现有的安全芯片的的屏蔽层，也可以是其他任意器件或部件的屏蔽层，所述至少一组MOS管的源端连接至所述至少一个锁存器的输入端；所述信号输出模块15的输入端连接至所述至少一个锁存器的输出端，所述信号输出模块15用于基于所述至少一个锁存器的输出端的电压变化生成并输出目标信号，所述目标信号用于指示所述屏蔽层11是否存在电磁故障注入；其中，所述至少一组MOS管中的部分或全部MOS导通时，所述信号输出模块15用于输出第一目标信号，所述第一目标信号用于指示所述屏蔽层11存在电磁故障注入，所述至少一组MOS管均断开时，所述信号输出模块15用于输出第二目标信号，所述第二目标信号用于指示所述屏蔽层11不存在电磁故障注入。
换言之，所述信号输出模块15可以配置为在所述至少一组MOS管中的部分或全部MOS导通的情况下输出第一目标信号以及在所述至少一组MOS管均断开的情况下输出第二目标信号，所述第一目标信号用于指示所述屏蔽层11存在电磁故障注入，所述第二目标信号用于指示所述屏蔽层11不存在电磁故障注入。
通过所述至少一组MOS管能够检测出所述屏蔽层是否出现异常电压，通过所述至少一组MOS管对应的锁存器能够输出所述信号输出模块15可识别的检测信号，进而实时检测并及时预警电磁故障注入，以保证芯片的鲁棒性与安全性。
此外，基于屏蔽层设计电磁故障注入的检测电路，能够达到有效简化电路结构、节省电路面积、避免出现静态功耗以及降低电路成本等目的。
在本申请的一些实施例中，所述至少一组MOS管中的第一组MOS管120的漏端可连接至所述至少一个锁存器中的第一锁存器的输入端，所述第一组MOS管120的栅端可连接至地电压，所述第一锁存器的输入端可连接 至电源电压。所述第一组MOS管120可用于检测所述屏蔽层11是否出现电压值低于地电压的异常现象。
请继续参见图1，以所述第一组MOS管120包括第一NMOS管121为例，所述第一NMOS管121的栅极连接至地电压，所述第一NMOS管121的源极连接至屏蔽层11，所述第一NMOS管121的漏端连接至第一锁存器13。
假设所述屏蔽层11存在电磁故障注入，所述屏蔽层11会产生感应电流，使得所述屏蔽层11的电压发生变化，进而导致所述屏蔽层11的电压范围超出VSS～VDD，此时，若VSS与所述屏蔽层11的电压的差值大于或等于所述第一NMOS管121的阈值电压，则所述第一NMOS管121导通，进而导致所述第一锁存器13的输入端的电压下降，所述第一锁存器13的输入端的电压下降导致所述第一锁存器13的输出端的电压上升，所述信号输出模块15根据所述第一锁存器13的输出端的电压变化，输出用于指示所述第一目标信号，以指示所述屏蔽层11存在电磁故障注入。
图2是图1所示的检测电路的具体实现方式的示意性电路图。
请参见图2，所述检测电路10还可包括第一开关16。
例如，所述第一锁存器13的输入端通过所述第一开关16连接至所述电源电压VDD，以保证所述第一锁存器的输入端处于高电压状态，例如在所述第一NMOS管121导通前，通过导通所述第一开关16使得所述第一锁存器13的输入端的电压等于电源电压。
在本申请的另一些实施例中，所述至少一组MOS管中的第二组MOS管130的漏端连接至所述至少一个锁存器中的第二锁存器的输入端，所述第二组MOS管130的栅端连接至电源电压，所述第二锁存器的输入端连接至地电压。所述第二组MOS管130可用于检测所述屏蔽层11是否出现电压值高于电源电压的异常现象。
请继续参见图1，以所述第二组MOS管130包括第一PMOS管122为例，所述第一PMOS管122的栅极连接至电源电压，所述第一PMOS管122的源极连接至屏蔽层11，所述第一PMOS管122的漏端连接至第二锁存器14。
假设所述屏蔽层11存在电磁故障注入，所述屏蔽层11会产生感应电流，使得所述屏蔽层11的电压发生变化，进而导致所述屏蔽层11的电压范围超 出VSS～VDD，此时，若所述屏蔽层11的电压与所述VDD的差值大于或等于所述第一PMOS管122的阈值电压，则所述第一PMOS管122导通，进而导致所述第二锁存器14的输入端的电压上升，所述第二锁存器14的输入端的电压上升导致所述第二锁存器14的输出端的电压下降，所述信号输出模块15了根据所述第二锁存器14的输出端的电压变化，输出用于指示所述第一目标信号，以指示所述屏蔽层11存在电磁故障注入。
请继续参见图2，所述检测电路10还可包括第二开关17。
例如，所述第二锁存器14的输入端通过所述第二开关17连接至所述地电压，以保证所述第二锁存器14的输入端在所述第一PMOS管122导通前处于地电压状态，例如在所述第一PMOS管122导通前，通过导通所述第二开关17使得所述所述第二锁存器14的输入端的电压等于地电压。
请继续参见图2，所述检测电路10还可包括第一反相器18。
例如，所述第二锁存器14的输出端通过所述第一反相器18连接至所述信号输出模块15的输入端，所述信号输出模块15用于基于所述第一反相器18的输出端的电压变化生成并输出所述目标信号。由此，所述信号检测电路10同时包括所述第一组MOS管120和所述第二组MOS管130时，通过检测所述第一锁存器13的上升沿和所述第一反相器18的上升沿生成所述目标信号，避免了同时检测所述第一锁存器13上升沿和所述第二锁存器14的下降沿，进而可以降低所述信号输出模块15的复杂度。
请继续参见图2，所述第二锁存器14可包括第二反相器181和第三反相器182，所述第二反相器181的输入端连接至所述第三反相器182的输出端，所述第二反相器181的输出端连接至所述第三反相器182的输入端，所述第二组MOS管130的漏端可以连接至所述第二反相器181的输入端，所述第二反相器181的输出端连接至所述信号输出模块15。
需要说明的是，所述至少一组MOS管中每组MOS管可以仅包括一个MOS管，也可以包括多个MOS管，本申请实施例对此不做具体限定。例如，请继续参见图1，所述第一组MOS管120可以仅第一NMOS管121，所述第二组MOS管130可以仅包括所述第一PMOS管122。又例如，请继续参见图2，所述第一组MOS管120还可以包括第二NMOS管131和第三NMOS管141，所述第二组MOS管130还可以包括第二PMOS管132和第三PMOS管142。当然，图1和图2仅为本申请的示例，不应理解为对本申请的限制， 在其他可替代实施例中，所述第一组MOS管120和所述第二组MOS管130可以分别包括其它数量的MOS管。
在本申请的一些实施例中，所述屏蔽层11可包括至少一个金属线；所述至少一个金属线上设置有至少一个检测节点，所述至少一个检测节点通过所述至少一组MOS管连接至所述至少一个锁存器的输入端。
以所述至少一个金属线中的第一金属线为例，所述第一金属线可以设置有至少一个第一检测节点和/或至少一个第二检测节点，所述至少一组MOS管中的第一组MOS管120通过所述至少一个第一检测节点连接至所述至少一个锁存器中的第一锁存器，所述至少一组MOS管中的第二组MOS管130可通过所述至少一个第二检测节点连接至所述至少一个锁存器中的第二锁存器。
在本申请的一些实施例中，所述至少一组MOS管中同一组MOS管中的所有MOS管的漏端均连接至同一锁存器的输入端。
例如，所述至少一组MOS管中的不同组MOS管的漏端连接至不同的锁存器的输入端。结合图2来说，所述第一组MOS管120的漏端可连接至所述第一锁存器13的输入端，所述第二组MOS管的漏端可连接至所述第二锁存器14的输入端。
又例如，所述至少一组MOS管中的一部分组MOS管连接至所述第一第一锁存器13，所述至少一组MOS管中的另一部分组MOS管连接至所述第二锁存器14。其中，所述一部分组MOS管可包括MOS管类型相同的至少一组MOS管，所述另一部分组MOS管可包括MOS管类型相同的至少一组MOS管。所述一部分组MOS管中的MOS管的MOS管类型和所述另一部分组MOS管中的MOS管的MOS管类型可以相同，也可以不同，本申请对此不做具体限定。
在本申请的一些实施例中，所述至少一组MOS管为多组MOS管，所述多组MOS管中的不同组MOS管包括不同类型的MOS管。
应理解，所述不同类型的MOS管包括但不限于“N型”MOS管(NMOSFET)与“P型”MOS管(PMOSFET)。其中，“N型”MOS管和“P型”MOS管当作开关使用时，“N型”MOS管(衬底PN结指向内的MOS管或电流流出的MOS管)的栅端接高电平时导通，接低电平时关断；“P型”MOS管(PN结指向外的MOS管或电流流入的MOS管)的栅端接高电平时关断， 接低电平时导通。
在本申请的一些实施例中，所述至少一组MOS管包括多个不同类型的MOS管。
例如，所述至少一组MOS管中不同类型的MOS管连接至不同锁存器的输入端。结合图2来说，所述至少一组MOS管中的NMOS管可连接至所述第一锁存器13的输入端，所述至少一组MOS管中的PMOS管的漏端可连接至所述第二锁存器14的输入端。
图3是本申请实施例的信号输出模块的示意性结构图。
请参见图3，所述信号输出模块15可为D触发器。
例如，所述D触发器的重置(RESET)端B连接至重置信号W，例如所述重置信号W可以是与所述第一开关16的控制信号或第二开关17的控制信号；所述D触发器的D端连接至VDD；所述D触发器的检测端A连接至所述第一锁存器13的输出端或第一反相器18的输出端，用于接收检测信号，所述D触发器的输出端Q输出目标信号(即预警(ALARM)信号)。当然，所述信号生成电路13还可以是其他器件，例如比较器。
在本申请的一些实施例中，所述信号输出模块15可包括第一输出端和第二输出端，所述第一输出端的输出与所述第二输出端的输出反相。即所述信号输出模块15输出的目标信号可以是差分信号。
图4是本申请实施例的安全芯片20的示意性结构图。
请参见图4，所述安全芯片20可包括发射器21、屏蔽层22、接收器23以及数字处理器24。
其中，所述屏蔽层22可以是图1或图2所示的屏蔽层11，所述发射器21用于生成并输出第一信号；所述接收器23可通过所述屏蔽层11连接至所述发射器21，所述接收器23可用于通过所述屏蔽层11接收所述发射器21输出的第一信号，并基于所述第一信号输出第二信号；所述数字处理器24分别连接至所述发射器21和所述接收器23，所述数字处理器24可用于接收所述发射器21输出的所述第一信号和所述接收器23输出的所述第二信号，并基于所述第一信号和所述第二信号确定所述屏蔽层11是否被破坏(例如，物理损坏)。
换言之，所述安全芯片20可以包括被保护的芯片主体电路、所述芯片主体电路的屏蔽层22、用于检测所述屏蔽层22是否被破坏的电路以及用于 检测所述屏蔽层22是否存在电磁故障注入的电测电路10。其中，所述屏蔽层11可用作用于检测所述屏蔽层22是否被破坏的电路和所述检测电路10中的器件或元件。
本申请还提供了一种电子设备，其可包括图4所示的安全芯片20。所述电子设备可以包括上文所述的安全芯片。例如，例如，智能手机、笔记本电脑、平板电脑、游戏设备等便携式或移动计算设备，以及电子数据库、汽车、银行自动柜员机(Automated Teller Machine，ATM)等其他电子设备。但本申请实施例对此并不限定。
应理解，图1至图4仅为本申请的示例，不应理解为对本申请的限制。
例如，检测电路10还可以包括阈值判决模块。
例如，所述至少一个锁存器的输出端通过所述阈值判决模块连接至所述信号输出模块15，所述阈值判决模块用于放大所述至少一个锁存器输出的信号，并将放大后的信号发送至所述信号输出模块15。例如所述阈值判决模块可包括第四反相器和第五反相器，所述至少一个锁存器的输出端通过第四反相器连接至所述第五反相器的一端，所述第五反相器的另一端连接至所述信号输出模块15。其中所述第四反相器的翻转阈值可小于所述第五反相器的翻转阈值。例如所述第四反相器的翻转阈值为0.3，所述第五反相器的翻转阈值为0.8，即通过降低所述第四反相器的翻转阈值提升所述检测电路10的灵敏度，并通过增大所述第五反相器的翻转阈值，保证所述检测电路10的稳定性。应理解，上述0.3和0.8仅为示例，本申请对所述第四反相器的翻转阈值和所述第五反相器的翻转阈值不做具体限定。通过所述阈值判决模块的配合，可以提高电磁故障注入的检测精度，进一步提升所述检测电路10的灵敏度。
在本申请所提供的几个实施例中，应该理解到，所揭露的电路、支路和模块，可以通过其它的方式实现。例如，以上所描述的支路是示意性的，例如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到一个支路，或一些特征可以忽略，或不执行。
所述集成的模块如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方 案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以该权利要求的保护范围为准。

Claims (14)

  1. 一种电磁故障注入的检测电路，其特征在于，包括：
    屏蔽层，用于屏蔽干扰；
    至少一组金属氧化物半导体MOS管，所述至少一组MOS管的源端连接至所述屏蔽层；
    至少一个锁存器，所述至少一组MOS管的漏端连接至所述至少一个锁存器的输入端；
    信号输出模块，所述信号输出模块的输入端连接至所述至少一个锁存器的输出端，所述信号输出模块用于基于所述至少一个锁存器的输出端的电压变化生成并输出目标信号，所述目标信号用于指示所述屏蔽层是否存在电磁故障注入；
    其中，所述至少一组MOS管中的部分或全部MOS导通时，所述信号输出模块用于输出第一目标信号，所述第一目标信号用于指示所述屏蔽层存在电磁故障注入，所述至少一组MOS管均断开时，所述信号输出模块用于输出第二目标信号，所述第二目标信号用于指示所述屏蔽层不存在电磁故障注入。
  2. 根据权利要求1所述的检测电路，其特征在于，所述至少一组MOS管中的第一组MOS管的漏端连接至所述至少一个锁存器中的第一锁存器的输入端，所述第一组MOS管的栅端连接至地电压，所述第一锁存器的输入端连接至电源电压。
  3. 根据权利要求2所述的检测电路，其特征在于，所述检测电路还包括：
    第一开关，所述第一锁存器的输入端通过所述第一开关连接至所述电源电压。
  4. 根据权利要求1至3中任一项所述的检测电路，其特征在于，所述至少一组MOS管中的第二组MOS管的漏端连接至所述至少一个锁存器中的第二锁存器的输入端，所述第二组MOS管的栅端连接至电源电压，所述第二锁存器的输入端连接至地电压。
  5. 根据权利要求4所述的检测电路，其特征在于，所述检测电路还包括：
    第二开关；
    所述第二锁存器的输入端通过所述第二开关连接至所述地电压。
  6. 根据权利要求5所述的检测电路，其特征在于，所述检测电路还包括：
    第一反相器；
    所述第二锁存器的输出端通过所述第一反相器连接至所述信号输出模块的输入端，所述信号输出模块用于基于所述第一反相器的输出端的电压变化生成并输出所述目标信号。
  7. 根据权利要求1至6中任一项所述的检测电路，其特征在于，所述屏蔽层包括：
    至少一个金属线；
    所述至少一个金属线上设置有至少一个检测节点，所述至少一个检测节点通过所述至少一组MOS管连接至所述至少一个锁存器的输入端。
  8. 根据权利要求1至7中任一项所述的检测电路，其特征在于，所述至少一组MOS管为多组MOS管，所述多组MOS管中的不同组MOS管的漏端连接至不同锁存器的输入端。
  9. 根据权利要求1至8中任一项所述的检测电路，其特征在于，所述至少一组MOS管为多组MOS管，所述多组MOS管中的不同组MOS管包括不同类型的MOS管。
  10. 根据权利要求1至9中任一项所述的检测电路，其特征在于，所述至少一个锁存器中的每个锁存器包括：
    第二反相器和第三反相器；
    所述第二反相器的输入端连接至所述第三反相器的输出端，所述第二反相器的输出端连接至所述第三反相器的输入端，所述第二反相器的输入端或所述第三反相器的输入端为锁存器的输入端。
  11. 根据权利要求1至10中任一项所述的检测电路，其特征在于，所述信号输出模块包括第一输出端和第二输出端，所述第一输出端的输出与所述第二输出端的输出反相。
  12. 根据权利要求1至11中任一项所述的检测电路，其特征在于，所述信号输出模块为D触发器。
  13. 一种安全芯片，其特征在于，包括：
    发射器，用于生成并输出第一信号；
    屏蔽层；
    接收器，所述接收器通过所述屏蔽层连接至所述发射器，所述接收器用 于通过所述屏蔽层接收所述发射器输出的第一信号，并基于所述第一信号输出第二信号；
    数字处理器，所述数字处理器分别连接至所述发射器和所述接收器，所述数字处理器用于接收所述发射器输出的所述第一信号和所述接收器输出的所述第二信号，并基于所述第一信号和所述第二信号确定所述屏蔽层是否被破坏；
    根据权利要求1至12中任一项所述的检测电路；
    其中，所述屏蔽层为所述的检测电路中的屏蔽层。
  14. 一种电子设备，其特征在于，包括：
    根据权利要求13所述的安全芯片。
PCT/CN2019/101081 2019-08-16 2019-08-16 电磁故障注入的检测电路、安全芯片和电子设备 WO2021030958A1 (zh)

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