WO2021027241A1

WO2021027241A1 - Gan-based radio frequency device having п-shaped gate and manufacturing method therefor

Info

Publication number: WO2021027241A1
Application number: PCT/CN2019/130988
Authority: WO
Inventors: 王洪; 刘晓艺; 周泉斌
Original assignee: 中山市华南理工大学现代产业技术研究院; 华南理工大学
Priority date: 2019-08-13
Filing date: 2019-12-31
Publication date: 2021-02-18
Also published as: CN110600542A

Abstract

A GaN-based radio frequency device having a П-shaped gate and a manufacturing method therefor. The device comprises an AlGaN/GaN heterojunction epitaxial layer (1); the AlGaN/GaN heterojunction epitaxial layer (1) is of a boss structure; the upper portion of the boss is an active region (2); two ends of the upper surface of the active region (2) are respectively connected to a source electrode (3) and a drain electrode (4); a gate dielectric layer (5) is provided in a region, etc., other than a region connected to the active region (2), of the upper surface of the AlGaN/GaN heterojunction epitaxial layer (1); the upper surface of the gate dielectric layer (5) is connected to a П-shaped gate electrode; and the П-shaped gate electrode is positioned between the source electrode (3) and the drain electrode (4). By means of two gate pins (9), having a certain interval and being in direct contact with the AlGaN/GaN heterojunction epitaxial layer (1), of the П-shaped gate, the length of the gate electrode is effectively reduced under the condition of ensuring that the gate resistance is nearly unchanged, and the cut-off frequency is improved.

Description

GaN-based radio frequency device with Π-shaped gate and preparation method thereof

Technical field

The invention relates to a radio frequency device, and more specifically to a GaN-based radio frequency device with a Π-type gate and a preparation method thereof.

Background technique

GaN-based HEMT devices have a wide range of applications in satellite, communications, radar and other fields. GaN belongs to group III nitrides, has excellent breakdown ability, higher electron density and speed, high temperature resistance and radiation resistance, and is suitable for the development of high-frequency, high-temperature and high-power electronic devices. In addition, due to the spontaneous polarization effect and piezoelectric polarization effect of AlGaN/GaN heterojunction at room temperature, there is a high concentration of two-dimensional electron gas at the heterojunction interface, so devices with AlGaN/GaN heterojunction have high electron concentration With high electron mobility, it has broad application prospects in the construction of 5G network infrastructure, anti-missile radar and other fields.

For radio frequency devices, frequency parameters are key parameters that determine the overall performance of radio frequency devices. In order to obtain a larger frequency, the gate electrode section of the device is usually T-shaped. The contact length between the T-type gate electrode and the AlGaN/GaN heterojunction epitaxial layer is small, and a higher cut-off frequency f _T can be obtained, and at the same time. The T-shaped gate electrode has a large-volume gate cap, which increases the cross-sectional area of the gate electrode along the current conduction direction and reduces the parasitic resistance of the gate electrode, thereby increasing the maximum oscillation frequency f _MAX .

In order for the radio frequency device to have a higher cutoff frequency, it is necessary to reduce the length of the gate electrode in direct contact between the device and the barrier layer. Limited by the extreme performance of the lithography equipment and the equipment cost, the lithography method of radio frequency devices usually adopts electron beam lithography. Electron beam lithography refers to the use of electron beams to create patterns on the surface. Since electrons are waves with extremely short wavelengths, compared with other optical lithography processes, electron beam lithography has a higher precision and can reach the nanometer level. Therefore, electron beam lithography can effectively meet the requirements of the gate electrode size in HEMT devices.

In order for the radio frequency device to have a larger maximum oscillation frequency, the volume of the gate cap of the T-shaped gate needs to be increased. Generally, a double-layer or three-layer photoresist is used to strip the gate electrode metal, or a part of the gate dielectric layer is etched as a gate foot, and a gate cap is deposited on the gate dielectric layer to prepare radio frequency devices. In the first solution, because there is only one gate electrode support under the gate cap, it cannot take into account both a smaller gate electrode length and a larger gate cap length; the second solution, although a smaller gate electrode length and a larger gate electrode length can be achieved The length of the gate cap, but introduces etching damage, resulting in device degradation, and the contact area between the gate dielectric layer and the gate cap is too large, which increases the capacitance of the gate source and the gate drain, and reduces the maximum oscillation frequency of the device. Based on the above situation, how to obtain a larger gate cap length while ensuring a smaller gate electrode length without introducing etch damage or gate source and gate drain capacitance to achieve higher frequencies is a GaN-based radio frequency device Problems to be solved.

Summary of the invention

technical problem

The solution to the problem

Technical solutions

The purpose of the present invention is to overcome the defects and limitations of the gate electrode preparation technology of the existing GaN-based HEMT device, and propose a GaN-based radio frequency device with a Π-type gate and a preparation method thereof from the perspective of the shape of the gate electrode and the preparation process. The gate length can be effectively reduced while keeping the gate resistance as constant as possible, and the device frequency can be increased.

The purpose of the present invention is achieved by one of the following technical solutions.

The present invention provides a GaN-based radio frequency device with a Π-type gate, comprising an AlGaN/GaN heterojunction epitaxial layer, the AlGaN/GaN heterojunction epitaxial layer is a boss structure, the upper part of the boss is an active area, and the active area Both ends of the upper surface are connected to the source electrode and the drain electrode. The upper surface of the AlGaN/GaN heterojunction epitaxial layer is connected to the area outside the active area, the sidewall of the active area, and the upper surface of the active area is connected to the source electrode and the drain electrode. The area, the source electrode and the drain electrode are covered with a gate dielectric layer. The gate dielectric layer is provided with an opening on the upper surface of the source electrode and the drain electrode to expose the upper surface of the source electrode and the drain electrode. The upper surface of the gate dielectric layer The surface is connected to the Π-type gate electrode, which is located between the source electrode and the drain electrode. The Π-type gate electrode includes a gate cap and a gate pin. One end of the gate pin is connected to the upper surface of the gate dielectric layer, and the other end is connected to the bottom of the gate cap. The surface is used to support the grid cap, the grid foot includes a first grid foot and a second grid foot, and there is a space between the first grid foot and the second grid foot.

Preferably, the left and right length of the cross section of the grid foot is L _g , 10nm≤L _g ≤300nm; the upper and lower length of the cross section of the grid foot, that is the height is H _g , 0nm＜H _g ≤5L _g ; perpendicular to the cross section of the grid foot The thickness of the grid foot in the direction, that is, the width is W _g , W _g ≥1.2 μm; the distance between the first grid foot and the second grid foot is L _interval , 0nm＜L _interval ≤6L _g ;

The length of the gate cap is L _cap , 2L _g +L _interval ≤L _cap ≤6L _g +2L _interval ; the height of the gate cap is H _cap , 0nm ＜H _cap ≤18L _g +3L _interval ; the width of the gate cap is W _cap , W _cap =W _g .

Preferably, the first gate foot and the source electrode are located on the same side, and the distance between the first gate foot and the source electrode is L _gs , L _gs >(L _cap -L _interval -2L _g )/2; The drain electrode is located on the same side, and the distance between the second gate pin and the drain electrode is L _gd , L _gd >(L _cap -L _interval -2L _g )/2.

Preferably, the source electrode and the drain electrode are Ti/Al/Ni/Au metal layers; the source electrode and the drain electrode are both cuboid, the length of the source electrode and the drain electrode are L _s and L _d , and the heights are H _s and H _{d respectively} , The widths are W _s and W _d , respectively, L _s ＝L _d ≥10nm, H _s ＝H _d ≥10nm, 0nm＜W _s ＝W _d ≤W _g , the distance between source electrode and drain electrode is L _sd , L _sd = 2L _g +L _interval +L _gs +L _gd +L _s +L _d .

Preferably, the AlGaN/GaN heterojunction epitaxial layer is circular, with a diameter of 2-10 inches, and a thickness of 200 μm-1mm;

The length of the active area is L, L≥L _sd , the height is H, 100nm≤H≤1mm, and the width is W, W≥W _g ; the source electrode and the drain electrode are located at both ends of the upper surface of the active area, the source and drain electrodes The bottom surface is completely in contact with the top surface of the active area.

Preferably, the distance between the edge of the lower surface of the source and drain electrode and the edge of the active region parallel to it is not less than 500nm (because the embodiment is 500nm, 1um cannot be used, please verify it).

Preferably, the material of the gate dielectric layer is any one of insulating metal oxide, SiO ₂ and Si ₃ N ₄ , and the thickness of the gate dielectric layer is not less than 1 nm.

The present invention also provides a method for preparing a GaN-based radio frequency device with a Π-type gate as described above, which includes the following steps:

(1) Preparation and cleaning of AlGaN/GaN heterojunction epitaxial layer: soak the AlGaN/GaN heterojunction epitaxial layer in an acid solution to remove the oxide layer on the surface, and then use the organic solution ultrasonic method to remove AlGaN/GaN heterogeneity Organic matter on the surface of the junction epitaxial layer;

(2) Mutual isolation of devices: define the position of the active area with photoresist on the upper surface of the AlGaN/GaN heterojunction epitaxial layer and cover it, and the upper surface of the AlGaN/GaN heterojunction epitaxial layer in the non-active area is covered by photoresist. Plasma bombardment etching, the etching depth is 200nm-600nm;

(3) Strip the source and drain electrodes, annealing to form an ohmic contact: Use photoresist to define the positions and patterns of the source and drain electrodes, so that the positions of the source and drain electrodes are at the two ends of the upper surface of the active area. The area of the source electrode and the non-drain electrode is covered by photoresist, the source electrode and the drain electrode are formed using electron beam evaporation or magnetron sputtering method and stripping process, and finally annealed in a nitrogen atmosphere at a temperature above 800°C to make the source The electrode, the drain electrode and the AlGaN/GaN heterojunction epitaxial layer all form an ohmic contact;

(4) Deposition of the gate dielectric layer: the upper surface of the AlGaN/GaN heterojunction epitaxial layer is connected to the area outside the active area, the sidewalls of the active area, the upper surface of the active area is connected to the area outside the source electrode and the drain electrode, and the source A gate dielectric layer is deposited on the electrode and the drain electrode;

(5) Remove part of the gate dielectric layer on the upper surface of the source electrode and the drain electrode: the area outside the source electrode and the drain electrode is covered and protected by photoresist, remove part of the gate dielectric layer on the upper surface of the source electrode and the drain electrode to expose the source Part of the upper surface of the electrode and the drain electrode;

(6) Preparation of the gate electrode: deposit a double-layer photoresist on the upper surface of the gate dielectric layer and the upper surface of the exposed source and drain electrodes, and make the pattern area of the gate cap on the top photoresist, exposing part of the bottom layer Photoresist, make the pattern area of the gate pin on the exposed part of the bottom photoresist, deposit the gate electrode material layer on the upper surface of the top photoresist, the pattern area of the gate cap and the pattern area of the gate pin, and peel off the top layer photoresist The gate electrode material layer on the upper surface of the resist is removed, and the double-layer photoresist is removed to form a Π-type gate electrode.

Preferably, the method for depositing the gate dielectric layer in step (4) is any one of plasma-enhanced chemical vapor deposition, atomic layer deposition, and magnetron sputtering; wet etching is used in step (5) Or dry etching method to remove part of the gate dielectric layer on the upper surface of the source electrode and drain electrode; in step (6), electron beam lithography is used to make corresponding gate caps and gates on the double-layer photoresist. Foot graphics area.

Preferably, the etching solution used in the wet etching is an acid etching solution, which can etch away insulating oxide, Si ₃ N ₄ or SiO ₂ ; dry etching is an inductively coupled plasma etching process, reactive ion etching Process or any of other ion etching processes.

Preferably, the double-layer photoresist is two immiscible electron beam photoresists. The sensitivity of the bottom photoresist to electron beams is lower than the sensitivity of the top photoresist to electron beams. The thickness is greater than the thickness of the bottom photoresist; in the process of using electron beam lithography, the exposure dose in the gate pattern area is greater than the exposure dose outside the gate pattern area; the gate electrode material layer is more than two metal layers, the bottom The metal of is more than one of nickel or platinum; the topmost metal is more than one of gold or copper; the total thickness of the gate electrode material layer is greater than the thickness of the bottom photoresist and less than the total thickness of the double-layer photoresist .

The beneficial effects of the invention

Beneficial effect

Compared with the prior art, the present invention has the following technical effects and advantages:

(1) The two gate pins of the Π-type gate proposed by the present invention that are in direct contact with the AlGaN/GaN heterojunction epitaxial layer have a certain interval, which effectively reduces the gate electrode's resistance while ensuring that the gate resistance is almost unchanged. Length improves the cut-off frequency.

(2) There is air isolation between the gate cap and the gate dielectric layer of the Π-type gate proposed in the present invention, which reduces the contact area between the gate dielectric layer and the gate electrode metal, and reduces the increase in gate capacitance;

(3) In the preparation method of the Π-type gate electrode proposed in the present invention, a stripping method is adopted, in which only one electron beam lithography is required, no etching is required, and no secondary alignment is required, which not only prevents etching damage, but also simplifies了 Process.

Brief description of the drawings

Description of the drawings

FIG. 1 is a flowchart of a method for manufacturing a GaN-based radio frequency device with a Π-type gate provided in Embodiment 1;

2 to 10 are cross-sectional views of a GaN-based radio frequency device with a Π-type gate during the manufacturing process;

11 is a cross-sectional view of a comparative device (GaN-based radio frequency device with a traditional T-type gate) of a GaN-based radio frequency device with a Π-type gate provided by the embodiment;

FIG. 12 is a graph of current gain versus frequency of a GaN-based radio frequency device with a Π-type gate provided by an embodiment;

FIG. 13 is a graph showing the variation of gate capacitance with frequency of a GaN-based radio frequency device with a Π-type gate provided by an embodiment;

The figure shows: 1-AlGaN/GaN heterojunction epitaxial layer; 2-active area; 3-source electrode; 4-drain electrode; 5-gate dielectric layer; 6-bottom photoresist; 7-top photolithography Glue; 8-grid cap; 9-grid foot; 901-first grid foot; 902-second grid foot.

The drawings of the present invention are only schematic for easier understanding of the present invention, and the specific proportions can be adjusted according to design requirements. The up-down relationship of the relative elements in the graphics described in the text should be understood by those skilled in the art as referring to the relative positions of the components.

Invention embodiment

Embodiments of the invention

The specific implementation of the present invention will be further described below with reference to specific embodiments and drawings, but the implementation of the present invention is not limited to this.

Example

This embodiment provides a GaN-based radio frequency device with a Π-type gate. As shown in FIG. 10, it includes an AlGaN/GaN heterojunction epitaxial layer 1, and the AlGaN/GaN heterojunction epitaxial layer 1 has a boss structure. The upper part is the active area 2. Both ends of the upper surface of the active area 2 are connected to the source electrode 3 and the drain electrode 4 respectively. The upper surface of the AlGaN/GaN heterojunction epitaxial layer 1 is connected to the area outside the active area 2 and the active area 2. The sidewalls of the active region 2 and the upper surface of the active region 2 are connected to the area other than the source electrode 3 and the drain electrode 4. The source electrode 3 and the drain electrode 4 are covered with a gate dielectric layer 5, and the gate dielectric layer 5 is in the source electrode 3 and the drain electrode. The upper surface of the electrode 4 is provided with an opening to expose part of the upper surface of the source electrode 3 and the drain electrode 4. The upper surface of the gate dielectric layer 5 is connected to the Π-type gate electrode, which is located between the source electrode 3 and the drain electrode 4. The Π-type gate electrode includes a gate cap 8 and a gate pin 9. One end of the gate pin 9 is connected to the upper surface of the gate dielectric layer 5, and the other end is connected to the lower surface of the gate cap 8 to support the gate cap 8.

The height of the grid foot is H _g , H _g =300 nm; the grid foot 9 includes a first grid foot 901 and a second grid foot 902, and the lengths of the first grid foot 901 and the second grid foot 902 are both L _g , L _g =100nm, width W _g , W _g =100μm, the distance between the first grid foot 901 and the second grid foot 902 is L _interval , L _interval =300nm; the height of the grid cap 8 is H _cap , H _cap =300nm, the length is L _cap , L _cap =1 μm, the width is W _cap , W _cap ＝100 μm. The first gate foot 901 and the source electrode 3 are located on the same side, and the distance between the first gate foot 901 and the source electrode 3 is L _gs , L _gs =2 μm. The second gate leg 902 and the drain electrode 4 are located on the same side, and the distance between the second gate leg 902 and the drain electrode 4 is L _gd , L _gd = 2 μm.

The source electrode and the drain electrode are Ti/Al/Ni/Au metal layers; the source electrode and the drain electrode are both rectangular parallelepiped, the heights of which are H _s and H _d , H _s = H _d = 620 nm, and the lengths are L _s and L _{d respectively} , L _s =L _d =500nm, the widths are W _s and W _d , W _s =W _d =100 μm, the distance between the source electrode and the drain electrode is L _sd , L _sd =5.5 μm. The lower surfaces of the source electrode and the drain electrode are completely in contact with the upper surface of the active region, and the distance between the edges of the source electrode and the drain electrode and the edge of the active region parallel to them is both 500 nm. The height of the active region is H, H=350nm, the length is L, L=6.5μm, the width is W, W=101μm. The AlGaN/GaN heterojunction epitaxial layer is circular with a diameter of 2 inches and a thickness of 800 μm.

The material of the gate dielectric layer is Si ₃ N ₄ , and the thickness of the gate dielectric layer is 20 nm.

This embodiment also provides a method for preparing the GaN-based radio frequency device with a Π-type gate, as shown in FIG. 1, including the following steps:

(1) Preparation and cleaning of AlGaN/GaN heterojunction epitaxial layer: soak the AlGaN/GaN heterojunction epitaxial layer 1 in a mixed solution with a mass ratio of H ₂ SO ₄ and H ₂ O ₂ of 6:1 for 10 minutes (H ₂ SO ₄ and H ₂ O ₂ are commercially available), remove the oxide layer on the surface of the AlGaN/GaN heterojunction epitaxial layer 1, and then use acetone (commercially available) and isopropanol (commercially available) to ultrasonicate for 10 minutes to remove AlGaN /GaN heterojunction epitaxial layer 1 with organic matter. A schematic diagram of the AlGaN/GaN heterojunction epitaxial layer 1 after step (1) is shown in Figure 2;

(2) Mutual isolation of devices: Use photoresist on the upper surface of the AlGaN/GaN heterojunction epitaxial layer 1 to define the position of the active area 2 and cover it, on the AlGaN/GaN heterojunction epitaxial layer in the non-active area The surface is etched by plasma bombardment, the etching depth is 350nm, and the AlGaN/GaN heterojunction epitaxial layer 1 forms a bump structure, as shown in Figure 3, the specific etching conditions: BCl ₃ flow rate is 10 sccm, Cl ₂ flow rate is 90sccm, RF power is 500W, ICP power is 365W;

(3) Strip the source and drain electrodes, annealing to form an ohmic contact: use photoresist to define the position and pattern of the source electrode 3 and the drain electrode 4 so that the position of the source electrode 3 and the drain electrode 4 is on the upper surface of the active area 3 Both ends of the non-source electrode and non-drain electrode area are covered by photoresist, use electron beam evaporation method to deposit Ti/Al/Ni/Au metal layer, and then use the lift-off process to form the source electrode 3 and the drain electrode 4, and finally Annealing in a nitrogen atmosphere at a temperature of 850°C makes the source electrode 3, the drain electrode 4 and the AlGaN/GaN heterojunction epitaxial layer 1 all form an ohmic contact, as shown in Figure 4;

(4) Deposition of the gate dielectric layer: the upper surface of the AlGaN/GaN heterojunction epitaxial layer 1 is connected to the area outside the active area 2, the sidewalls of the active area 2, and the active area using the plasma-enhanced chemical vapor deposition method 2 The upper surface is connected to the area outside the source electrode 3 and the drain electrode 4, and a gate dielectric layer 5 is deposited on the source electrode 3 and the drain electrode 4. The deposition conditions: NH ₃ flow rate is 25 sccm; content is 5% (volume) SiH ₄ The flow rate of the mixed gas with N ₂ is 900 sccm; the reaction temperature is 300 ℃; the RF power is 50 W, as shown in Figure 5;

(5) Remove part of the gate dielectric layer on the upper surface of the source electrode and the drain electrode: the area outside the source electrode 3 and the drain electrode 4 is covered and protected by photoresist, and the source electrode 3 and the drain electrode 4 are covered by an inductively coupled plasma etching process. Part of the gate dielectric layer 5 on the surface is removed, exposing part of the upper surface of the source electrode 3 and the drain electrode 4, as shown in Figure 6, the etching process conditions are: CHF ₃ flow rate is 50 sccm; O ₂ flow rate is 10 sccm; RF power 60W; ICP power is 600W;

(6) Preparation of the gate electrode: deposit a double-layer photoresist on the upper surface of the gate dielectric layer 5 and the exposed part of the source electrode 3 and the drain electrode 4, and the bottom layer photoresist 6 is made of poly(α-methylbenzene). Ethylene-co-α-methyl chloroacrylate), the thickness is 300nm, the material of the top photoresist 7 is PMMA, the thickness is 800nm, as shown in Figure 7; the developer of the bottom photoresist 6 and the top photoresist 7 All are MIBK:IPA=1:3 (volume ratio), the development rate of the top photoresist 7 is greater than that of the bottom photoresist 6, and the pattern area of the gate cap 8 is made on the top photoresist 7 using electron beam lithography , Expose part of the bottom layer photoresist 6, make the pattern area of the gate foot 9 on the exposed part of the bottom layer photoresist 6, the exposure dose in the pattern area of the gate foot 9 is 4.4C/m ² , the gate cap 8 The exposure dose of the area except the gate pin 9 is 2.4C/m ² , after the photolithography, it is placed in a normal temperature (23°C) developer solution for 60 seconds, and then placed in a normal temperature (23°C) isopropanol solution for 30 seconds. Blow dry with nitrogen, and the longitudinal section of the formed device is shown in Figure 8. On the upper surface of the top layer photoresist 7, the pattern area of the gate cap 8 and the pattern area of the gate foot 9 are sequentially deposited nickel and gold material layers with thicknesses of 100 nm and 500 nm, respectively, as shown in FIG. 9.

The device after depositing the gate electrode material layer was placed in acetone solution, isopropanol solution and deionized water in sequence for 5 minutes, the gate electrode material layer on the upper surface of the top photoresist was stripped, and the double layer photoresist was removed to form a Π Type gate electrode. As shown in Figure 10.

The method for preparing a GaN-based radio frequency device with a Π-type gate proposed in the present invention fully takes advantage of the different dissolution rates of the electron beam photoresist in the same developer and the electron beam lithography process can simultaneously set different exposure doses for different patterns , Effectively reduce the length of the gate electrode. The metal stripping method is used to avoid etching damage. The stripped gate cap is air-isolated from the gate dielectric layer to reduce the gate capacitance. Therefore, GaN-based radio frequency devices with Π-type gates can reach higher frequencies.

The gate metal is also deposited between the first gate pin and the second gate pin, which is a traditional GaN-based radio frequency device with a T-shaped gate. The cross-sectional view is shown in FIG. 11. Silvaco software was used to simulate the current gain and gate capacitance of the embodiment and the GaN-based radio frequency device with a T-shaped gate at different frequencies. The simulation results are shown in Figs. 12 and 13. As shown in Figure 12, the cut-off frequency of a GaN-based radio frequency device with a Π-type gate is 70 GHz, which is nearly 30 GHz higher than that of a GaN-based radio frequency device with a T-type gate. As shown in Figure 13, a GaN-based RF device with a Π-type gate has a capacitance close to 45fF under the DC condition of Vds=2V and Vg=-5.5V, which is about 25% less than a GaN-based RF device with a T-type gate. .

The above-mentioned embodiments are only preferred examples of the present invention and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the content and principles of the present invention, they can do so without departing from the principles and scope of the present invention. In this case, various modifications and changes in form and details are made according to the method of the present invention, but these modifications and changes based on the present invention are still protected by the claims of the present invention.

Claims

A GaN-based radio frequency device with a ∏-shaped gate, which is characterized in that it comprises an AlGaN/GaN heterojunction epitaxial layer, the AlGaN/GaN heterojunction epitaxial layer is a boss structure, the upper part of the boss is an active area, and the active area Both ends of the upper surface are connected to the source electrode and the drain electrode. The upper surface of the AlGaN/GaN heterojunction epitaxial layer is connected to the area outside the active area, the sidewall of the active area, and the upper surface of the active area is connected to the source electrode and the drain electrode. The area, the source electrode and the drain electrode are covered with a gate dielectric layer. The gate dielectric layer is provided with an opening on the upper surface of the source electrode and the drain electrode to expose the upper surface of the source electrode and the drain electrode. The upper surface of the gate dielectric layer The surface is connected to the ∏ gate electrode. The ∏ gate electrode is located between the source electrode and the drain electrode. The ∏ gate electrode includes a gate cap and a gate pin. One end of the gate pin is connected to the upper surface of the gate dielectric layer, and the other end is connected to the bottom of the gate cap. The surface is used to support the grid cap, the grid foot includes a first grid foot and a second grid foot, and there is a space between the first grid foot and the second grid foot.
The GaN-based radio frequency device with a ∏-shaped gate according to claim 1, wherein the left and right length of the cross section of the gate leg is L g , and 10 nm ≤ L g ≤ 300 nm; the upper and lower length of the cross section of the gate leg is the height Is H g , 0nm＜H g ≤5L g ; the thickness of the grid foot perpendicular to the cross-sectional direction of the grid foot is W g , W g ≥1.2μm; the distance between the first grid foot and the second grid foot is L interval ，0nm＜L interval ≤6L g ;

The length of the gate cap is L cap , 2L g +L interval ≤L cap ≤6L g +2L interval ; the height of the gate cap is H cap , 0nm＜H cap ≤18L g +3L interval ; the width of the gate cap is W cap , W cap =W g .
The GaN-based radio frequency device with a ∏-shaped gate according to claim 2, wherein the first gate pin and the source electrode are located on the same side, and the distance between the first gate pin and the source electrode is L gs , L gs > (L cap -L interval -2L g )/2; the second gate foot and the drain electrode are on the same side, the distance between the second gate foot and the drain electrode is L gd , L gd ＞(L cap -L interval -2L g )/2.
The GaN-based radio frequency device with a ∏-shaped gate according to claim 2, wherein the source electrode and the drain electrode are Ti/Al/Ni/Au metal layers; the source electrode and the drain electrode are both rectangular parallelepiped, the source electrode and the drain electrode The length is L s and L d , the height is H s and H d , the width is W s and W d , L s ＝L d ≥10nm, H s ＝H d ≥10nm, 0nm＜W s ＝W d ≤ W g , the distance between the source electrode and the drain electrode is L sd , and L sd = 2L g +L interval +L gs +L gd +L s +L d .
The GaN-based radio frequency device with a ∏-shaped gate according to claim 2, wherein the AlGaN/GaN heterojunction epitaxial layer is circular, with a diameter of 2-10 inches, and a thickness of 200 μm-1mm;

The length of the active area is L, L≥L sd , the height is H, 100nm≤H≤1mm, and the width is W, W≥W g ; the source electrode and the drain electrode are located at both ends of the upper surface of the active area, the source and drain electrodes The bottom surface is completely in contact with the top surface of the active area.
The GaN-based radio frequency device with a ∏-shaped gate according to claim 1, wherein the material of the gate dielectric layer is any one of insulating metal oxide, SiO 2 and Si 3 N 4 , and the thickness of the gate dielectric layer Not less than 1nm.
The method for manufacturing a GaN-based radio frequency device with a ∏-shaped gate according to any one of claims 1 to 6, characterized in that it comprises the following steps:

(1) Preparation and cleaning of AlGaN/GaN heterojunction epitaxial layer: soak the AlGaN/GaN heterojunction epitaxial layer in an acid solution to remove the oxide layer on the surface, and then use the organic solution ultrasonic method to remove AlGaN/GaN heterogeneity Organic matter on the surface of the junction epitaxial layer;

(2) Mutual isolation of devices: define the position of the active area with photoresist on the upper surface of the AlGaN/GaN heterojunction epitaxial layer and cover it, and the upper surface of the AlGaN/GaN heterojunction epitaxial layer in the non-active area is covered by photoresist. Plasma bombardment etching, the etching depth is 200nm-600nm;

(3) Strip the source and drain electrodes, annealing to form an ohmic contact: Use photoresist to define the positions and patterns of the source and drain electrodes, so that the positions of the source and drain electrodes are at the two ends of the upper surface of the active area. The area of the source electrode and the non-drain electrode is covered by photoresist, the source electrode and the drain electrode are formed using electron beam evaporation or magnetron sputtering method and stripping process, and finally annealed in a nitrogen atmosphere at a temperature above 800°C to make the source The electrode, the drain electrode and the AlGaN/GaN heterojunction epitaxial layer all form an ohmic contact;

(4) Deposition of the gate dielectric layer: the upper surface of the AlGaN/GaN heterojunction epitaxial layer is connected to the area outside the active area, the sidewalls of the active area, the upper surface of the active area is connected to the area outside the source electrode and the drain electrode, and the source A gate dielectric layer is deposited on the electrode and the drain electrode;

(5) Remove part of the gate dielectric layer on the upper surface of the source electrode and the drain electrode: the area outside the source electrode and the drain electrode is covered and protected by photoresist, remove part of the gate dielectric layer on the upper surface of the source electrode and the drain electrode to expose the source Part of the upper surface of the electrode and the drain electrode;

(6) Preparation of the gate electrode: deposit a double-layer photoresist on the upper surface of the gate dielectric layer and the upper surface of the exposed source and drain electrodes, and make the pattern area of the gate cap on the top photoresist, exposing part of the bottom layer Photoresist, make the pattern area of the gate pin on the exposed part of the bottom photoresist, deposit the gate electrode material layer on the upper surface of the top photoresist, the pattern area of the gate cap and the pattern area of the gate pin, and peel off the top layer photoresist The gate electrode material layer on the upper surface of the resist is removed and the double-layer photoresist is removed to form a ∏-shaped gate electrode.
The method for preparing a GaN-based radio frequency device with a ∏-shaped gate according to claim 7, wherein the method for depositing the gate dielectric layer in step (4) is plasma-enhanced chemical vapor deposition, atomic layer deposition Any of the magnetron sputtering methods; in step (5), wet etching or dry etching is used to remove part of the gate dielectric layer on the upper surface of the source electrode and the drain electrode; in step (6), The electron beam lithography method makes the corresponding grid cap and grid foot pattern area on the double-layer photoresist.
The method for preparing a GaN-based radio frequency device with a ∏-shaped gate according to claim 8, wherein the etching solution used in the wet etching is an acidic etching solution, which can etch away insulating oxides, Si 3 N 4 Or SiO 2 ; dry etching is any of an inductively coupled plasma etching process, a reactive ion etching process, or other ion etching processes.
The method for preparing a GaN-based radio frequency device with a ∏-shaped gate according to claim 8, wherein the double-layer photoresist is two immiscible electron beam photoresists, and the bottom photoresist is opposite to the electron beam The sensitivity of the top layer photoresist is lower than that of the electron beam, and the thickness of the top layer photoresist is greater than that of the bottom layer; in the process of using electron beam lithography, the exposure dose of the grid foot pattern area is greater than that of the grid foot Exposure dose outside the pattern area; the gate electrode material layer is more than two metal layers, the bottom metal layer is more than one of nickel or platinum; the top metal layer is more than one of gold or copper; The total thickness of the electrode material layer is greater than the thickness of the bottom layer photoresist and less than the total thickness of the double layer photoresist.