CN115881795A - HEMT device - Google Patents

HEMT device Download PDF

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Publication number
CN115881795A
CN115881795A CN202211092714.0A CN202211092714A CN115881795A CN 115881795 A CN115881795 A CN 115881795A CN 202211092714 A CN202211092714 A CN 202211092714A CN 115881795 A CN115881795 A CN 115881795A
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gate
dual
grid
layer
hard mask
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姜涛
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Yiguan Information Technology Shanghai Co ltd
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Yiguan Information Technology Shanghai Co ltd
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Priority to CN202211092714.0A priority Critical patent/CN115881795A/en
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Priority to PCT/CN2023/116685 priority patent/WO2024051635A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to a HEMT device, comprising: the electron source comprises a two-dimensional electron gas structure and at least one pair of dual gates, wherein a two-dimensional electron gas channel is formed in the two-dimensional electron gas structure, and the at least one pair of dual gates are positioned above the two-dimensional electron gas channel; the dual gates are formed by adopting a self-aligned process, each pair of dual gates comprises a first gate and a second gate, and the first gate and the second gate are arranged in mirror symmetry along the central axes of the first gate and the second gate. The HEMT device is provided with at least one pair of dual gates, each pair of dual gates comprises two gates, the redundant design is equivalently added to the gates, when one gate of one pair of dual gates fails, for example, the threshold voltage drifts, the other gate can still work normally, and the reliability of the HEMT device is improved.

Description

HEMT device
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a HEMT device.
Background
GaN High Electron Mobility Transistors (HEMT) devices rely on a characteristic two-dimensional Electron gas 2DEG to operate as a conducting channel and may be used in many electronic devices such as fully controlled power switches, high frequency amplifiers or oscillators. Compared with SiC and Si devices, the GaN device has lower on resistance and smaller charging capacitance. In the absence of a gate signal, a GaN HEMT device has an on-channel in an "normal-on" state, i.e., a D-mode HEMT, and an off-normal-off mode, i.e., an E-mode enhancement mode HEMT, which is a hot spot today. In the future, gaN HEMT devices will also have increasing applications in the industrial control field and the automotive electronics field.
The Normally-on technology is mature and is generally realized by manufacturing a metal gate. While the normal-off state can be implemented by a variety of techniques, such as recessed-gate (recessed-gate) techniques, cascode switching transistors (Cascode cascade) and p-gate structure techniques. The recessed gate technology and the cascode switching transistor affect the stability and performance of the device during operation, and have some problems compared with a real E-mode transistor. The P-gate structure technology is mature, and the normally-off of the HEMT device is realized by adopting a P-type doped gate P-gate; this approach, while presenting some technical challenges and difficulties, has the advantage of greater stability and does not require a zener diode to protect the gate, while the p-gate provides better dynamic on-resistance (RDSon) over temperature.
The mainstream P-gate technology has two types, one is to grow a P-type doped GaN material layer on an AlGaN barrier layer or an undoped GaN cap layer of an HEMT device, etch off part of P-GaN material, only reserve the P-GaN material in a gate region, and then deposit metal on the P-GaN material to form a metal gate electrode, wherein the P-GaN material is called a P-GaN gate. The other method is to etch a concave part on a GaN cap layer and/or an AlGaN barrier layer etched in a grid region, then grow a P-GaN material by a secondary epitaxy method, and finally deposit metal on the P-GaN material to form a grid electrode, wherein the P-GaN material is called as a P-GaN grid.
Since the P-GaN gate has a depletion effect on the 2DEG, the 2DEG under the P-GaN gate in the gate region is in a depletion state when no signal voltage is applied to the gate electrode, and the HEMT device appears to be off. When the grid electrode is applied with high voltage, the 2DEG under the P-GaN grid of the grid region is restored to be conducted, and the HEMT device is shown to be conducted.
The length of the P-GaN gate is the gate length of the device, and the gate length of the HEMT device has influence on various device parameters, such as on-resistance, gate capacitance and the like. The longer the gate, the greater the on-resistance, i.e., the higher the power consumption, while the longer the gate, the greater the gate capacitance, i.e., the lower the characteristic frequency. At present, the manufacture of the mainstream GaN HMET device is based on 4-inch and 6-inch process production lines, a small part of the process production lines can adopt 8-inch process production lines, the line width which can be manufactured by a corresponding photoetching machine is limited, the limit of the 4-inch and 6-inch process production lines is generally 0.5um, and the limit of the 8-inch process production lines is generally 180nm, so that the further reduction of the length of a P-GaN gate is limited.
Meanwhile, the conventional HEMT device only has one grid, and the device cannot work normally when the grid fails under some extreme conditions or the material of a grid covering region has defects. Because the withstand voltage of the HEMT device is mainly determined by the source-drain distance and the grid-drain distance, if a plurality of grids are manufactured, the grid closest to the drain determines the withstand voltage level of the device, and therefore the area of a chip can be increased under the condition of the same withstand voltage.
In summary, the conventional P-gate technology has the problems of long P-GaN gate length, low reliability of a device when a single gate is manufactured, large chip area when a plurality of gates are manufactured, and low reliability.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a HEMT device. The technical problem to be solved by the invention is realized by the following technical scheme:
an embodiment of the present invention provides an HEMT device, including: a two-dimensional electron gas structure and at least one pair of dual gates, wherein,
a two-dimensional electron gas channel is formed in the two-dimensional electron gas structure, and the at least one pair of dual gates are positioned above the two-dimensional electron gas channel;
the dual gates are formed by adopting a self-alignment process, each pair of the dual gates comprises a first gate and a second gate, and the first gate and the second gate are arranged in mirror symmetry along the central axes of the first gate and the second gate.
In one embodiment of the invention, the dual gate is located on a surface of the two-dimensional electron gas structure.
In one embodiment of the invention, the semiconductor device further comprises a gate metal layer wrapping the dual gate and located between the first gate and the second gate.
In one embodiment of the invention, the dual-gate structure further comprises an insulating dielectric layer, wherein the insulating dielectric layer is positioned between the gate metal layer and the dual gate.
In one embodiment of the invention, the dual-gate structure further comprises an insulating dielectric layer, wherein the insulating dielectric layer is located between the gate metal layer and the gate far away from the drain electrode in the dual-gate.
In an embodiment of the present invention, the two-dimensional electron gas structure further includes a gate metal layer and an insulating dielectric layer, the insulating dielectric layer is located on the surface of the two-dimensional electron gas structure, the dual gate penetrates through the insulating dielectric layer, and the gate metal layer is located on the top of the dual gate and on the insulating dielectric layer.
In one embodiment of the invention, the dual gate extends deep into the two-dimensional electron gas structure and has a bottom located above the two-dimensional electron gas channel.
In an embodiment of the invention, the two-dimensional electron gas structure further comprises a gate metal layer, the first gate and the second gate are interconnected, and the gate metal layer is located on the interconnected first gate and second gate and on the two-dimensional electron gas structure.
In one embodiment of the invention, the two-dimensional electron gas structure further comprises an insulating medium layer, wherein the insulating medium layer is positioned between the dual gate and the two-dimensional electron gas structure.
In one embodiment of the invention, the device further comprises a gate metal layer, a buffer insulating dielectric layer and a gate insulating dielectric layer,
the buffer insulating medium layer and the grid insulating medium are stacked between the grid close to the drain electrode in the first grid and the second grid and the two-dimensional electron gas structure and between the first grid and the second grid;
a grid electrode insulating medium layer is arranged between the grid electrode far away from the drain electrode in the first grid electrode and the second grid electrode and the two-dimensional electron gas structure;
the grid metal layer is positioned on the grid insulating medium layer on the first grid and the second grid and positioned on the grid insulating medium layer between the first grid and the second grid.
In an embodiment of the present invention, the device further includes a first gate metal layer and a second gate metal layer, the first gate metal layer is located on the first gate, and the second gate metal layer is located on the second gate.
In one embodiment of the present invention, the materials of the first gate and the second gate each include one or more of a metal, a P-type GaN system material.
In one embodiment of the present invention, the length of the first gate and the second gate is less than 90nm, or the length of the first gate and the second gate is less than 2 times the thickness of the AlGaN barrier layer in the two-dimensional electron gas structure.
Another embodiment of the present invention provides a method for manufacturing an HEMT device, including the steps of:
preparing a first hard mask on the surface of a device, and etching the first hard mask to form a target structure;
preparing a second hard mask on the surfaces of the target structure and the device, and performing self-aligned etching on the second hard mask to form a first grid mask and a second grid mask which are positioned on the side wall of the target structure;
preparing a first grid electrode and a second grid electrode by using the first grid electrode mask and the second grid electrode mask to obtain a dual grid electrode;
wherein the length of the first gate and the length of the second gate are both equal to the thickness of the second hard mask.
Compared with the prior art, the invention has the beneficial effects that:
1. the HEMT device is provided with at least one pair of dual gates, each pair of dual gates comprises two gates, which is equivalent to adding a redundancy design to the gates, when one gate of one pair of dual gates fails, for example, the threshold voltage drifts, the other gate can still work normally, and the reliability of the HEMT device is improved.
2. At least one pair of dual gates in the HEMT device is formed by adopting a self-alignment process, so that the distances between a gate drain and a gate source can be kept unchanged basically, and the area of a chip cannot be increased; meanwhile, a mask pattern with smaller line width can be manufactured by adopting a self-alignment process, so that the limit of the limit capability of a photoetching machine in the manufacturing process of the conventional HEMT device can be eliminated, smaller grid length can be obtained, the high-frequency characteristic of the device can be further improved, the on-resistance of the HEMT device can be reduced, the current on-capability of the HEMT device can be enhanced, and the large-current device can be manufactured.
3. In the HEMT device, the parasitic grid metal layer is arranged between the first grid and the second grid and is connected with the grid metal, and the grid metal layer has an electric field modulation effect, so that the grid closer to the source can be better protected, and the reliability of the grid is further improved.
4. In the HEMT device, the insulating medium layer is arranged between the at least one pair of dual gates and the gate metal layer, so that the gate-source leakage can be greatly reduced, the threshold voltage for opening the channel is improved, and the reliability of the dual gates is further improved.
5. According to the HEMT device, the buffer insulating medium layer and the grid insulating medium are arranged between the grid close to the drain electrode and the two-dimensional electron gas structure, the grid insulating medium is arranged between the grid far away from the drain electrode and the two-dimensional electron gas structure, the thickness of the insulating medium close to the bottom of the grid of the drain electrode is larger than that of the insulating medium far away from the bottom of the grid of the drain electrode, the problem of insulating medium degradation caused by the influence of drain electrode voltage can be better resisted, the grid close to one side of the drain electrode is protected, and the protection similar to the function of a grid field plate is provided for the grid close to one side of the source electrode.
Drawings
Fig. 1 a-1 b are schematic structural diagrams of two HEMT devices according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a third HEMT device according to an embodiment of the present invention;
fig. 3a to fig. 3d are schematic structural diagrams of four HEMT devices according to the embodiment of the present invention;
fig. 4a to fig. 4f are schematic process diagrams of a method for manufacturing a HEMT device according to an embodiment of the present invention;
fig. 5a to fig. 5f are schematic process diagrams of a manufacturing method of a second HEMT device according to the embodiment of the present invention;
fig. 6a to fig. 6e are schematic process diagrams of a method for manufacturing a first enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention;
fig. 7 a-7 f are schematic process diagrams of a method for manufacturing a second enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention;
fig. 8a to 8g are schematic process diagrams of a method for manufacturing a third enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention;
fig. 9a to 9f are schematic diagrams illustrating a manufacturing method and a process of a fourth enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention;
fig. 10a to fig. 10k are schematic process views of a method for manufacturing a third HEMT device according to the embodiment of the present invention;
fig. 11a to fig. 11j are schematic process views of a manufacturing method of a fourth HEMT device according to the embodiment of the present invention;
fig. 12a to 12c are schematic process diagrams of a method for manufacturing a fifth enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention;
fig. 13a to fig. 13c are schematic process diagrams of a method for manufacturing a sixth enhanced HEMT device with a high-reliability gate according to the embodiment of the present invention;
fig. 14a to 14d are schematic process diagrams illustrating a manufacturing method of a seventh enhanced HEMT device for a high-reliability gate according to an embodiment of the present invention;
fig. 15a to fig. 15c are schematic process diagrams of a method for manufacturing an eighth enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention;
fig. 16a to fig. 16h are schematic process diagrams of a method for manufacturing a ninth enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention;
fig. 17a to fig. 17c are schematic process diagrams of a method for manufacturing two pairs of dual gates according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1a to fig. 1b, fig. 1a to fig. 1b are schematic structural views of two HEMT devices according to an embodiment of the present invention.
In this embodiment, the HEMT device may be an enhancement mode HEMT device or a depletion mode HEMT device.
The HEMT device comprises a two-dimensional electron gas structure 1 and at least one pair of dual gates 2. Wherein, a two-dimensional electron gas channel is formed in the two-dimensional electron gas structure 1, and at least one pair of dual gates 2 are positioned above the two-dimensional electron gas channel; the dual gates 2 are formed by a self-aligned process, each pair of dual gates 2 comprises a first gate 21 and a second gate 22, and the first gate 21 and the second gate 22 are arranged in mirror symmetry.
Specifically, the two-dimensional electron gas structure 1 includes, but is not limited to, a structure forming a two-dimensional electron gas channel, for example, the two-dimensional electron gas channel is formed by a channel layer and a barrier layer, and the two-dimensional electron gas structure 1 includes, but is not limited to, the channel layer and the barrier layer. In one specific embodiment, the two-dimensional electron gas structure 1 includes a substrate 11, a buffer layer 12, a channel layer 13, and a barrier layer 14, which are sequentially stacked. In another embodiment, the two-dimensional electron gas structure 1 includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, and a cap layer 15, which are sequentially stacked.
Specifically, the fact that at least one pair of dual gates 2 is located above the two-dimensional electron gas channel includes the following cases: a. at least one pair of dual grid electrodes 2 are positioned on the surface of the two-dimensional electron gas structure 1, and at the moment, the bottoms of the at least one pair of dual grid electrodes 2 are positioned on the surface of the two-dimensional electron gas structure 1; b. at least one pair of dual grid electrodes 2 are positioned in the two-dimensional electron gas structure 1, at the moment, the bottoms of the at least one pair of dual grid electrodes 2 are positioned above the two-dimensional electron gas channel and extend into the two-dimensional electron gas structure 1, and the grid electrodes form a groove grid; c. at least one pair of the dual gate 2 may also have a portion of the dual gate 2 located on the surface of the two-dimensional electron gas structure 1 and another portion of the dual gate 2 located deep into the two-dimensional electron gas structure 1.
Taking the two-dimensional electron gas structure 1 as an example, which includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14 and a cap layer 15 stacked in sequence, the fact that at least one pair of dual gates 2 is located on the surface of the two-dimensional electron gas structure 1 means that at least one pair of dual gates 2 is located on the cap layer 15; the fact that the at least one pair of dual gates 2 are located deep into the two-dimensional electron gas structure 1 means that the bottoms of the at least one pair of dual gates 2 can be deep into the cap layer 15, the barrier layer 14 or the channel layer 13 on the premise that the bottoms of the dual gates are located on the two-dimensional electron gas channel.
Specifically, the dual gates 2 are formed by a self-aligned process, so that the first gate 21 and the second gate 22 in each pair of dual gates have the same profile and height, and the two gate sidewall profiles are mirror-symmetric about the axis perpendicular to the device surface at the middle position of the first gate 21 and the second gate 22, so that the electrical characteristics of the devices can be kept the same, and the structural design of the redundant gate is formed.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a third HEMT device according to an embodiment of the present invention. Specifically, the at least one pair of dual gates 2 may be a pair of dual gates, that is, include 2 gates, or may be a plurality of pairs of dual gates, that is, 4, 6, 8, and the like gates, where the number of gates is an integer multiple of 2. As shown in fig. 3, the number of the dual gates 2 is 2, i.e. 4 gates are included.
Referring to fig. 3a to fig. 3d, fig. 3a to fig. 3d are schematic structural views of four HEMT devices according to the embodiment of the present invention.
In a specific embodiment, the pair of gates in the HEMT device is provided with a gate metal layer 3. When the dual gate 2 is located on the surface of the two-dimensional electron gas structure 1, the gate metal layer 3 wraps the dual gate 2 and is located between the first gate 21 and the second gate 22, see fig. 3a; when the dual gate 2 is deep into the two-dimensional electron gas structure 1 and the bottom thereof is located above the two-dimensional electron gas channel, the first gate 21 and the second gate 22 are interconnected, and the gate metal layer 3 is located on the interconnected first gate 21 and second gate 22 and on the two-dimensional electron gas structure 1, as shown in fig. 3b.
In another embodiment, the first gate metal layer 31 and the second gate metal layer 32 are disposed on the dual gate in the HEMT device, the first gate metal layer 31 is disposed on the first gate 21, and the second gate metal layer 32 is disposed on the second gate 22. Specifically, when the dual gate 2 is located on the surface of the two-dimensional electron gas structure 1, the first gate metal layer 31 wraps the first gate 21, the second gate metal layer 32 wraps the second gate 22, and the first gate metal layer 31 and the second gate metal layer 32 are not interconnected, as shown in fig. 3c; when the dual gate 2 is deep into the two-dimensional electron gas structure 1 and the bottom thereof is located above the two-dimensional electron gas channel, the first gate metal layer 31 is located above the first gate 21, and the second gate metal layer 32 is located above the second gate 21, as shown in fig. 3d.
Specifically, the material of the first gate electrode 21 and the second gate electrode 22 includes one or more of metal and P-type GaN system material, wherein the P-type GaN system material includes P-type GaN, P-type BN and P-type Al x Ga y In 1-x-y N0 is not less than x and not more than 1, y is not less than 0 and not more than 1, x + y is not less than 1. It is understood that the first gate 21 and the second gate 22 in the dual gate 2 may be metal gates, or may be gates of P-type GaN material. Further, when the first gate 21 and the second gate 22 in the dual gate 2 are metal gates, the metal of the metal gates may directly contact the two-dimensional electron gas structure 1, or may be separated from the two-dimensional electron gas structure 1 by a layer of insulating medium.
Specifically, the lengths of the first gate 21 and the second gate 22 are less than 90nm, or the lengths of the first gate 21 and the second gate 22 are less than 2 times the thickness of the AlGaN barrier layer in the two-dimensional electron gas structure 1.
It should be noted that the HEMT device of this embodiment further includes a source S and a drain D, and the structure arrangement and the manufacturing method of the source S and the drain D belong to the prior art, and this embodiment is not described again.
In the HEMT device of this embodiment, at least one pair of dual gates is provided, each pair of dual gates includes two gates, which is equivalent to adding a redundancy design to the gates, and when one gate of one pair of dual gates fails, for example, the threshold voltage drifts, the other gate can still work normally, so that the reliability of the HEMT device is increased.
The present embodiment further provides a method for manufacturing a HEMT device including at least one pair of dual gates, in which the dual gates are formed by a self-aligned process, with reference to fig. 4a to 4f, fig. 5a to 5f, fig. 10a to 10k, and fig. 11a to 11j, the self-aligned process includes the steps of:
s1, preparing a first hard mask 6 on the surface of the device, and etching the first hard mask 6 to form a target structure.
Specifically, the device for preparing the first hard mask 6 may include the two-dimensional electron gas structure 1, and may also include the two-dimensional electron gas structure 1 and the gate material 20 on the surface of the two-dimensional electron gas structure 1. The target structure may be a first hard mask protruding structure formed by etching two ends of the first hard mask 6, or may be a recessed region formed by etching the middle of the first hard mask 6 and located between the first hard masks 6 at two ends.
S2, preparing a second hard mask 7 on the surface of the target structure and the surface of the device, and performing self-aligned etching on the second hard mask 7 to form a first gate mask 71 and a second gate mask 72 which are positioned on the side wall of the target structure.
Specifically, when the target structure is a first hard mask bump structure, the first gate mask 71 and the second gate mask 72 are located on two sidewalls of the first hard mask bump structure; when the target structure is a recess region between the first hard masks 6 at both ends, the first and second gate masks 71 and 72 are located on the sidewalls of the first hard masks 6 at the recess region.
And S3, preparing the first gate 21 and the second gate 22 by using the first gate mask 71 and the second gate mask 72 to obtain the dual gate 2.
Specifically, when the device for preparing the first hard mask 6 includes the two-dimensional electron gas structure 1 and the gate electrode material 20 on the surface of the two-dimensional electron gas structure 1, the gate electrode material layer is etched by using the first gate mask 71 and the second gate mask 72 to form the first gate electrode 21 and the second gate electrode 22, thereby forming the dual gate electrode 2. When the device for preparing the first hard mask 6 includes the two-dimensional electron gas structure, the third hard mask may be used to form a gate etching mask by using the first gate mask 71 and the second gate mask 72, and then the two-dimensional electron gas structure 1 may be etched by using the gate etching mask to form two recess regions, and then a gate material may be deposited in the recess regions to form the first gate 21 and the second gate 22, so as to form the dual gate 2.
Further, the length of the first gate electrode 21 and the length of the second gate electrode 22 are both equal to the thickness of the second hard mask 7.
At least one pair of dual gates in the HEMT device of the embodiment is formed by adopting a self-alignment process, so that the distances between a gate drain and a gate source can be kept basically unchanged, and the area of a chip cannot be increased; meanwhile, a mask pattern with smaller line width can be manufactured by adopting a self-alignment process, so that the limit of the limit capability of a photoetching machine in the manufacturing process of the conventional HEMT device can be eliminated, smaller grid length can be obtained, the high-frequency characteristic of the device can be further improved, the on-resistance of the HEMT device can be reduced, the current on-capability of the HEMT device can be enhanced, and the large-current device can be manufactured.
Example two
Based on the first embodiment, the present embodiment describes a method for manufacturing a HEMT device by taking as an example that the two-dimensional electron gas structure 1 includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, and a cap layer 15, which are sequentially stacked. Specifically, the dual gate 2 can be manufactured by the following two methods.
The first manufacturing method comprises the following steps: referring to fig. 4a to fig. 4f, fig. 4a to fig. 4f are schematic views illustrating a process of a method for manufacturing a HEMT device according to an embodiment of the present invention. The manufacturing method comprises the following steps:
s1, preparing a gate material 20 on a surface of the two-dimensional electron gas structure 1, as shown in fig. 4a, and depositing a first hard mask 6 on the gate material 20, as shown in fig. 4b.
And S2, carrying out photoetching on the first hard mask 6, and removing a part of the first hard mask 6, wherein the removed first hard mask 6 is positioned in the middle of the first hard mask 6, so that a concave region is formed in the middle of the first hard mask 6, as shown in FIG. 4c.
S3, depositing a second hard mask 7 in the recessed region and on the remaining first hard mask 6, as shown in fig. 4d. The position of the dual gate 2 and the length of the dual gate 2 are defined by depositing the second hard mask 7, namely the dual gate 2 is positioned on the side wall of the first hard mask 6 in the concave area, and the thickness of the second hard mask 7 deposited on the side wall of the first hard mask 6 in the concave area is the length of the gate.
S4, etching to remove a portion of the second hard mask 7, then etching to remove the first hard mask 6, leaving the second hard mask 7 on the sidewall of the first hard mask 6 in the recess region, and leaving the second hard mask 7 to form a first gate mask 71 and a second gate mask 72 for a semiconductor material such as P-type GaN, as shown in fig. 4e and 4f.
And S5, etching the gate material 20 by using the first gate mask 71 and the second gate mask 72 formed in the step S4, removing the gate material 20 except the gate etching mask, and forming the first gate 21 and the second gate 22 by remaining the gate material 20 under the gate etching mask.
The second manufacturing method comprises the following steps: referring to fig. 5a to 5f, fig. 5a to 5f are schematic process diagrams of a method for manufacturing a HEMT device according to an embodiment of the present invention. The manufacturing method comprises the following steps:
s1, preparing a gate material 20 on a surface of the two-dimensional electron gas structure 1, as shown in fig. 5a, and depositing a first hard mask 6 on the gate material 20, as shown in fig. 5b.
And S2, carrying out photoetching on the first hard mask 6, and then leaving a part of the first hard mask 6, wherein the left first hard mask 6 is positioned in the middle of the first hard mask 6, so that the gate materials 20 at two ends are exposed, and a first hard mask 6 protrusion is formed, as shown in fig. 5c. Further, the two sides of the protrusion of the first hard mask 6 are left to define the position of the dual gate 2.
S3, depositing a second hard mask 7 on the raised surface of the first hard mask 6 and the exposed gate material 20, as shown in fig. 5d. The thickness of the second hard mask 7 deposited on the raised sidewalls of the first hard mask 6 defines the length of the gate.
S4, removing the gate material 20 and the second hard mask 7 on the first hard mask 6, see fig. 5e, and removing the first hard mask 6, see fig. 5f, leaving the second hard mask 7 portion deposited on both sides of the protrusion of the first hard mask 6, the remaining second hard mask 7 portion forming a first gate mask 71 and a second gate mask 72 for the semiconductor material, such as P-type GaN.
And S5, etching the gate material 20 by using the first gate mask 71 and the second gate mask 72 formed in the step S4, removing the gate material 20 except the gate material covered by the first gate mask 71 and the second gate mask 72, and forming the first gate 21 and the second gate 22 by remaining the gate material 20 covered by the gate etching mask.
In this embodiment, the first hard mask 6 and the second hard mask 7 include Al 2 O 3 、SiO 2 、Si 3 N 4 SiON, i.e. the first hard mask 6, the second hard mask 7 may be a single material or a stack of layers of materials, e.g. Al 2 O 3 、SiO 2 、Si 3 N 4 A single layer of SiON or a stack of multiple materials.
The manufacturing method of this embodiment only describes the manufacturing process of the dual gate, and the manufacturing method of the source S and the drain D belongs to the prior art, and is not described in detail in this embodiment.
In this embodiment, the position of the dual gate between the source and the drain of the HEMT device is determined by the lithography position of the first hard mask, and the gate length of the dual gate is determined by the deposition thickness of the second hard mask. The distance between two paired gates of the dual gate is determined by the photoetching size of the first hard mask and the manufacturing method; the distance between two paired grid electrodes of the dual grid electrode adopting the first manufacturing method is smaller than the photoetching size of the first hard mask; and the distance between the two paired gates of the dual-gate adopting the second manufacturing method is slightly larger than or equal to or slightly smaller than the photoetching size of the first hard mask.
EXAMPLE III
On the basis of the first embodiment and the second embodiment, four HEMT devices with different structures are further prepared in the present embodiment. In this embodiment, the gate material 20 is P-type GaN.
Referring to fig. 6a to fig. 6e, fig. 6a to fig. 6e are schematic diagrams illustrating a manufacturing method and a manufacturing process of a first enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after the P-type GaN dual gate 2 is obtained, photoresist is adopted to coat and expose the region where the P-type GaN dual gate is located, gate metal is deposited, then metal above the photoresist is stripped to form a gate metal layer 3, at the moment, the gate metal layer 3 is in direct contact with the side wall of the P-type GaN material of the P-type GaN dual gate 2, and the top of the P-type GaN material of the P-type GaN dual gate can be in direct contact with the side wall of the P-type GaN dual gate or can be separated by a part of residual hard mask.
Referring to fig. 6e, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2 and a gate metal layer 3, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are sequentially stacked, the dual gate 2 is located on the surface of the cap layer 15, and the gate metal layer 3 wraps the dual gate 2 and is located between the first gate 21 and the second gate 22. It will be appreciated that the gate metal layer 3 is in direct contact with the sidewalls and top of the dual gate 2 and with the cap layer 15 between the first gate 21 and the second gate 22.
In this embodiment, the gate metal layer 3 in the middle of the first gate 21 and the second gate 22 of the dual gate 2 may modulate an electric field below the dual gate, and further protect a gate of the dual gate pair close to the source.
Referring to fig. 7a to fig. 7f, fig. 7a to fig. 7f are schematic diagrams illustrating a manufacturing method and a manufacturing process of a second enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after the P-type GaN dual-gate is obtained, a thin insulating medium layer 4 is deposited on the surface of the device, the insulating medium layer 4 wraps the exposed part of the P-type GaN material of the P-type GaN dual-gate 2 completely, photoresist is coated, photoresist covering the upper part of the P-type GaN dual-gate 2 is removed after exposure and development, metal above the photoresist is stripped after gate metal is deposited, a gate metal layer 3 is formed, the gate metal layer 3 is formed at the moment, the P-type GaN material of the P-type GaN dual-gate is not in direct contact with the gate metal layer, and a layer of insulating medium is arranged between the gate metal layer 3 and the P-type GaN material of the P-type GaN dual-gate.
Referring to fig. 7f, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2, a gate metal layer 3, and an insulating dielectric layer 4, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14, and the cap layer 15 are sequentially stacked, the dual gate 2 is located on the surface of the cap layer 15, the insulating dielectric layer 4 is located between the gate metal layer 3 and the dual gate 2, and the gate metal layer 3 wraps the insulating dielectric layer 4 between the surface of the dual gate 2 and the dual gate 2.
In the enhanced HEMT device, the insulating medium layer 4 is arranged between the grid metal layer 3 and the P-type GaN dual grid 2, and because the length of a single P-type GaN grid is very small, the grid metal layer 3 can exhaust P-type GaN materials when an external voltage signal is connected, induced potential can be generated in the P-type GaN materials, and even positive charges are all caught to the bottom of the P-type GaN grid closest to a channel, so that the purpose of opening the channel is achieved. At this time, because the insulating medium layer 4 is arranged between the gate metal layer 3 and the P-type GaN dual gate 2, the gate leakage current can be reduced, the threshold voltage for opening the channel can be increased, and the reliability of the dual gate can be further increased.
Referring to fig. 8a to 8g, fig. 8a to 8g are schematic diagrams illustrating a manufacturing method and a process of a third enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after the P-type GaN dual-grid 2 is obtained, a thin insulating medium layer 4 is deposited on the surface of the device, the insulating medium layer 4 wraps the exposed part of the P-type GaN material of the P-type GaN dual-grid 2, photoresist is coated, the photoresist covering the upper part of the dual-P-type GaN grid close to one side of the drain electrode is removed after exposure and development, and the exposed insulating medium layer 4 is removed. And coating photoresist again, removing the photoresist covering the P-type GaN dual gate 2 after exposure and development, stripping metal above the photoresist after depositing gate metal to form a gate metal layer 3, wherein the gate metal layer 3 is not directly contacted with the P-type GaN material of the P-type GaN dual gate 2 at the side far away from the drain electrode, and an insulating medium layer 4 is arranged between the gate metal layer 3 and the P-type GaN material.
Referring to fig. 8g, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2, a gate metal layer 3, and an insulating dielectric layer 4, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14, and the cap layer 15 are sequentially stacked, the dual gate 2 is located on the surface of the cap layer 15, the insulating dielectric layer 4 is located between the gate metal layer 3 and a gate far from the drain in the dual gate 2, the insulating dielectric layer 4 is located on the cap layer 15 between the first gate 21 and the second gate 22, the gate metal layer 3 wraps the insulating dielectric layer 4 on the surface of the gate far from the drain in the dual gate 2 and the gate close to the drain, and the gate metal layer 3 is located on the insulating dielectric layer 4 between the first gate 21 and the second gate 22.
In the enhanced HEMT device, at this time, because the insulating layer is arranged between the gate metal layer 3 and the P-type GaN gate far away from the drain electrode, the gate leakage current can be reduced, the threshold voltage for opening a channel can be improved, and meanwhile, no insulating medium layer is arranged between the P-type GaN dual gate close to the drain electrode and the gate metal, the problem of insulating medium degradation caused by the influence of the drain electrode voltage does not exist.
Referring to fig. 9a to 9f, fig. 9a to 9f are schematic diagrams illustrating a manufacturing method and a manufacturing process of a fourth enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after the P-type GaN dual-gate 2 is obtained, an insulating medium layer 4 is deposited, the thickness of the insulating medium layer 4 can cover the whole P-type GaN dual-gate 2, and a part of the insulating medium layer 4 is removed through etching or grinding until the top of the P-type GaN dual-gate 2 is exposed. And then coating photoresist, removing the photoresist covering the P-type GaN dual gate 2 after exposure and development, stripping the metal above the photoresist after depositing gate metal to form a gate metal layer 3, and directly contacting the gate metal layer 3 with the top of the P-type GaN material of the P-type GaN dual gate.
Referring to fig. 9f, the enhanced HEMT device of the high-reliability gate obtained by the manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2, a gate metal layer 3 and an insulating medium layer 4, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are sequentially stacked, the dual gates 2 are located on the surface of the cap layer 15, the insulating medium layer 4 is located on the surface of the two-dimensional electron gas structure 1, the dual gates 2 penetrate through the insulating medium layer 4, and the gate metal layer 3 is located on the tops of the dual gates 2 and the insulating medium layer 4.
In this embodiment, the insulating dielectric layer 4 includes Al 2 O 3 、SiO 2 、Si 3 N 4 SiON, i.e. the insulating dielectric layer 4, may be a single material or a stack of layers of materials, e.g. Al 2 O 3 、SiO 2 、Si 3 N 4 A single layer of SiON or a stack of multiple materials.
The manufacturing method of this embodiment only describes the manufacturing process of the dual gate, and the manufacturing method of the source S and the drain D is a mature process step known in the industry.
In addition, when the HEMT device is a depletion mode HEMT device, after paired dual gates are formed, the gate metal layer 3 may be connected to only one gate of the dual gates 2, and the other gate is in a suspended state; or may be connected to both of the dual gates 2.
In the HEMT device of the embodiment, the parasitic gate metal layer is arranged between the first gate and the second gate, and is connected with the gate metal, so that the gate metal layer has an electric field modulation effect, the gate closer to the source can be better protected, and the reliability of the gate is further improved.
Example four
In addition to the first embodiment, this embodiment describes a method for manufacturing a HEMT device, taking as an example that the two-dimensional electron gas structure 1 includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, and a cap layer 15, which are sequentially stacked. Specifically, the dual gate 2 can be manufactured by the following two methods.
The manufacturing method comprises the following steps: referring to fig. 10a to 10k, fig. 10a to 10k are schematic views illustrating a process of a method for fabricating a third HEMT device according to an embodiment of the present invention. The manufacturing method comprises the following steps:
s1, obtaining a two-dimensional electron gas structure 1, please refer to fig. 10a, and depositing a first hard mask 6 on the two-dimensional electron gas structure 1, please refer to fig. 10b.
And S2, carrying out photoetching on the first hard mask 6, and removing a part of the first hard mask 6, wherein the removed first hard mask 6 is positioned in the middle of the first hard mask 6, so that a concave region is formed in the middle of the first hard mask 6, as shown in FIG. 10c.
S3, depositing a second hard mask 7 in the recessed region and on the remaining first hard mask 6, as shown in fig. 6d. The position of the dual gate 2 and the length of the dual gate 2 are defined by depositing the second hard mask 7, namely the dual gate 2 is positioned on the side wall of the first hard mask 6 in the concave area, and the thickness of the second hard mask 7 deposited on the side wall of the first hard mask 6 in the concave area is the length of the gate.
S4, depositing a third hard mask 8 on the second hard mask 7, removing a portion of the third hard mask 8 and a portion of the second hard mask 7 by a grinding or etching process, exposing the second hard mask 7 on the sidewall of the first hard mask 6 in the recess region, and simultaneously exposing the third hard mask 8 on the second hard mask 7 in the recess region, as shown in fig. 10e.
Alternatively, after etching to remove a portion of the second hard mask 7, the third hard mask 8 is deposited, and a portion of the third hard mask 8 is removed by a grinding or etching process to expose the second hard mask 7 on the sidewalls of the first hard mask 6 in the recessed regions and simultaneously expose the third hard mask 8 between the second hard mask 7 in the recessed regions, as shown in fig. 10f.
Alternatively, after etching to remove a portion of the second hard mask 7 and removing the first hard mask 6, the third hard mask 8 is deposited, and a portion of the third hard mask 8 is removed by a grinding or etching process to expose the second hard mask 7 on the sidewalls of the third hard mask 8 in the recess region and expose the third hard mask 8 between the second hard masks 7, as shown in fig. 10g.
Note that the exposed second hard mask 7 on the side wall of the first hard mask 6 or the third hard mask 8 forms a first gate mask 71 and a second gate mask 72.
S5, removing the second hard mask 7 on the sidewall of the first hard mask 6 in the recess region exposed in step S4, and forming a recess region between the third hard mask 8 and the first hard mask 6, please refer to fig. 10h.
Alternatively, the second hard mask 7 on the sidewall of the first hard mask 6 in the recess region exposed in step S4 is removed to form a recess region between the third hard mask 8 and the first hard mask 6, as shown in fig. 10i.
Alternatively, the second hard mask 7 on the sidewalls of the third hard masks 8 in the recessed regions exposed in step S4 is removed to expose the recessed regions between the third hard masks 8, as shown in fig. 10j.
And S6, taking the hard masks at the two sides of the sunken area in the step S5 as a gate etching mask, continuously etching the cap layer 15 and the barrier layer 14 in the sunken area, and forming the sunken areas in the cap layer 15 and the barrier layer 14 as preparation areas of gates, as shown in FIG. 10k.
And S7, epitaxially growing a P-type GaN material or depositing metal for the second time in the preparation area of the grid obtained in the step S6, and preparing the dual grid 2.
The second manufacturing method comprises the following steps: referring to fig. 11a to 11j, fig. 11a to 11j are schematic process diagrams of a manufacturing method of a fourth HEMT device according to the embodiment of the present invention. The manufacturing method comprises the following steps:
s1, preparing a protection layer 9 on the surface of the two-dimensional electron gas structure 1, as shown in fig. 11a, and depositing a first hard mask 6 on the protection layer 9, as shown in fig. 11b.
And S2, carrying out photoetching on the first hard mask 6, and then leaving a part of the first hard mask 6, wherein the left first hard mask 6 is positioned in the middle of the first hard mask 6, so that the protective layers 9 at two ends are exposed, and a first hard mask 6 protrusion is formed, as shown in fig. 11c. Further, the positions of the dual gates 2 are defined by the two sides of the first hard mask 6 projection.
S3, depositing a second hard mask 7 on the raised surface of the first hard mask 6 and the exposed protective layer 9, as shown in FIG. 11d. The thickness of the second hard mask 7 deposited on the raised sidewalls of the first hard mask 6 defines the length of the gate.
And S4, removing the second hard mask 7 on the protective layer 9, and remaining the second hard mask 7 deposited on the two sides of the projection of the first hard mask 6, as shown in FIG. 11e. A third hard mask 8 is deposited and the remaining portions of the second hard mask 7 deposited on both sides of the protrusion of the first hard mask 6 are exposed by a grinding or etching process, see fig. 11f.
Alternatively, a portion of the second hard mask is removed by etching and the first hard mask is removed, leaving portions of the second hard mask 7 deposited on both sides of the protrusion of the first hard mask 6, as shown in fig. 11g. A third hard mask 8 is deposited and the remaining second hard mask 7 portions are exposed by a grinding or etching process, see fig. 11h.
It should be noted that the second hard mask 7 remaining on the sidewalls of the second hard mask 7 or the third hard mask 8 on both sides of the protrusion of the first hard mask 6 forms a first gate mask 71 and a second gate mask 72.
S6, removing the first hard mask 6 or the second hard mask 7 deposited on both sides of the protrusion of the third hard mask 8, and forming a recess region in the third hard mask 8 and the first hard mask 6, please refer to fig. 11i.
And S7, taking the hard masks at the two sides of the sunken area in the step S5 as a gate etching mask, continuously etching the cap layer 15 and the barrier layer 14 in the sunken area, and forming the sunken areas in the cap layer 15 and the barrier layer 14 as preparation areas of gates, as shown in FIG. 11j.
And S8, epitaxially growing a P-type GaN material or depositing metal for the second time in the preparation area of the grid obtained in the step S6, and preparing the dual grid 2.
In this embodiment, the first hard mask 6, the second hard mask 7, and the third hard mask 8 include a metal material and Al 2 O 3 、SiO 2 、Si 3 N 4 SiON, i.e. the insulating dielectric layer 4 may beSingle material or a stack of layers, e.g. metallic material, al 2 O 3 、SiO 2 、Si 3 N 4 A single layer of SiON or a stack of multiple materials.
The manufacturing method of this embodiment only describes the manufacturing process of the dual gate, and the manufacturing method of the source S and the drain D belongs to the prior art, and is not described in detail in this embodiment.
In this embodiment, the position of the dual gate between the source and the drain of the HEMT device is determined by the lithography position of the first hard mask, and the gate length of the dual gate is determined by the deposition thickness of the second hard mask. The distance between two paired gates of the dual gate is determined by the photoetching size of the first hard mask and the manufacturing method; the distance between two paired grid electrodes of the dual grid electrode adopting the first manufacturing method is smaller than the photoetching size of the first hard mask; and the distance between the two paired gates of the dual-gate adopting the second manufacturing method is slightly larger than or equal to or slightly smaller than the photoetching size of the first hard mask.
EXAMPLE five
On the basis of the first embodiment and the fourth embodiment, five HEMT devices with different structures are further prepared in the present embodiment. In this embodiment, the gate material 20 includes P-type GaN or a metal material or P-type GaN and a metal material.
Referring to fig. 12a to 12c, fig. 12a to 12c are schematic process diagrams of a method for manufacturing a fifth enhanced HEMT device with a high reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after the recessed region where the dual gate 2 is located is obtained, a P-type GaN material is epitaxially grown for the second time, photoresist is coated, the photoresist covering the P-type GaN dual gate 2 is remained after exposure and development, the exposed P-type GaN material is removed by an etching method, and the P-type GaN material in the recessed region of the dual gate 2 and the P-type GaN material above the P-type GaN material are remained. And coating photoresist again, removing the photoresist covering the P-type GaN dual gate 2 after exposure and development, and stripping the metal above the photoresist after depositing the gate metal to obtain a gate metal layer 3.
Referring to fig. 12c, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2 and a gate metal layer 3, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are sequentially stacked, the dual gate 2 extends into the barrier layer 13, the first gate 21 and the second gate 22 are made of P-type GaN and P of the first gate and the second gate are interconnected through P-type GaN, and the gate metal layer 3 is located on the interconnected P-type GaN and the cap layer 15.
Referring to fig. 13a to 13c, fig. 13a to 13c are schematic process diagrams of a method for manufacturing a sixth enhanced HEMT device with a high reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after obtaining the recessed area where the dual gate 2 is located, the recessed area extends into the barrier layer 14, photoresist is coated, the photoresist covering the recessed area of the dual gate 2 is removed after exposure and development, metal above the photoresist is stripped after depositing gate metal, the metal filled in the recessed area where the dual gate is located forms the dual gate 2, and meanwhile, the gate metal layer 3 is formed above the dual gate 2.
Referring to fig. 13c, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2 and a gate metal layer 3, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are sequentially stacked, the dual gates 2 penetrate into the barrier layer 13, the first gate 21 and the second gate 22 are made of metal and are interconnected through metal materials, and the gate metal layer 3 is located on the interconnected metal materials and the cap layer 15. It will be understood that the gate metal layer 3 is located on the first gate 21 and the second gate 22 of the metal material and on the cap layer 15.
Referring to fig. 14a to 14d, fig. 14a to 14d are schematic views illustrating a manufacturing method and a process of a seventh enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: taking the sunken area between the hard masks as the sunken area where the dual gate is located, coating photoresist on the cap layer 15, removing the photoresist covering the sunken area of the dual gate 2 after exposure and development, stripping the metal above the photoresist after depositing the gate metal, forming the dual gate 2 by the metal filled in the sunken area where the dual gate is located, and simultaneously forming the gate metal layer 3 above the dual gate 2.
Referring to fig. 14d, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2, a gate metal layer 3 and a first hard mask 6, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are sequentially stacked, the dual gate 2 is located on the cap layer 15 and penetrates through the first hard mask 6, the first hard mask 6 is located on the cap layer 15, the first gate 21 and the second gate 22 are made of metal and are interconnected through metal materials, and the gate metal layer 3 is located on the interconnected metal materials and on the first hard mask 6. It will be understood that the gate metal layer 3 is located on the first and second gates 21 and 22 of metal material and on the cap layer 15.
Note that the first hard mask 6 in fig. 14d functions in the same manner as the insulating dielectric layer 4 in fig. 9f, and therefore the first hard mask 6 corresponds to the insulating dielectric layer 4.
Referring to fig. 15a to 15c, fig. 15a to 15c are schematic process diagrams of a manufacturing method of an eighth enhanced HEMT device with a high reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after the recessed area where the dual gate 2 is located is obtained, an insulating medium layer 4 is deposited, and the insulating medium layer 4 can cover the inner wall of the recessed area where the whole dual gate is located. And coating photoresist, removing the photoresist covering the concave region of the dual gate 2 after exposure and development, stripping the metal above the photoresist after depositing gate metal, and filling the metal in the concave region where the dual gate 2 is located to form the dual gate 2 and simultaneously form a gate metal layer 3. There is now an insulating dielectric layer 4 between the dual gate metal and the semiconductor layer in the recessed region.
Referring to fig. 15c, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2, a gate metal layer 3 and an insulating dielectric layer 4, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are sequentially stacked, the dual gates 2 penetrate into the barrier layer 13, the insulating dielectric layer 4 is arranged between the dual gates 2 and the barrier layer 13, the first gate 21 and the second gate 22 are interconnected through a metal material, and the gate metal layer 3 is located on the interconnected metal material and on the insulating dielectric layer 4.
Referring to fig. 16a to fig. 16h, fig. 16a to fig. 16h are schematic diagrams illustrating a manufacturing method and a process of a ninth enhanced HEMT device with a high-reliability gate according to an embodiment of the present invention. The manufacturing method comprises the following steps: after the recess region where the dual gate 2 is located is obtained, a buffer insulating dielectric layer 41 is deposited, and the buffer insulating dielectric layer 41 may cover the entire inner wall of the recess region where the dual gate 2 is located. And coating photoresist, exposing and developing, removing the photoresist covering the upper part of the recessed region of the dual gate 2 close to one side of the source electrode, and removing the exposed buffering insulating dielectric layer 41. After the photoresist is removed, a gate insulating dielectric layer 42 is deposited, and the gate insulating dielectric layer 42 can cover the inner wall of the recess region where the entire dual gate 2 is located. And coating photoresist again, removing the photoresist covering the concave region of the dual gate 2 after exposure and development, stripping the metal above the photoresist after depositing gate metal, and forming the dual gate 2 and the gate metal layer 3 by filling the metal in the concave region where the dual gate is located, as shown in fig. 16 f. At this time, an insulating layer is arranged between the metal of the dual gate 2 and the semiconductor layer of the depressed region, and the thickness of the insulating layer between the dual gate 2 and the semiconductor material of the device, which is far away from the source electrode or the side close to the drain electrode, is greater than the thickness of the insulating layer between the dual gate 2 and the semiconductor material of the device, which is far away from the source electrode or the side close to the drain electrode, i.e., the thickness of the buffer insulating dielectric layer 41 plus the thickness of the gate insulating dielectric layer 42, so that the problem of insulating dielectric degradation caused by the influence of the drain voltage can be better resisted, the gate closer to the source electrode or the side far away from the drain electrode is protected by the function similar to a gate field plate, and the threshold voltage of the device is determined by the gate closer to the source electrode or the side far away from the drain electrode.
Referring to fig. 16f, the enhanced HEMT device of the high-reliability gate obtained by the above manufacturing method includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2, a gate metal layer 3, a buffer insulating dielectric layer 41 and a gate insulating dielectric layer 42, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are sequentially stacked, the dual gates 2 penetrate into the barrier layer 13, and the buffer insulating dielectric layer 41 and the gate insulating dielectric layer 42 are stacked between the two-dimensional electron gas structure 1 and between the first gate 21 and the second gate 22, which are close to the drain, of the first gate 21 and the second gate 22 in the dual gates 2; a grid insulating medium layer 42 is arranged between the grid far away from the drain electrode in the first grid 21 and the second grid 22 and the two-dimensional electron gas structure 1; the gate metal layer 3 is located on the gate insulating dielectric layer 42 on the first gate 21 and the second gate 22 and on the gate insulating dielectric layer 42 between the first gate 21 and the second gate 22.
Further, the metal of the dual gate 2 on the side farther from the source or closer to the drain may not be connected to the gate metal as shown in fig. 16g and 16h, but connected to the source metal.
Referring to fig. 16h, the enhanced HEMT device of the high-reliability gate of fig. 16h includes a substrate 11, a buffer layer 12, a channel layer 13, a barrier layer 14, a cap layer 15, a pair of dual gates 2, a first gate metal layer 31, a second gate metal layer 32, a buffer insulating dielectric layer 41 and a gate insulating dielectric layer 42, wherein the substrate 11, the buffer layer 12, the channel layer 13, the barrier layer 14 and the cap layer 15 are stacked in sequence, the dual gates 2 penetrate into the barrier layer 13, and the buffer insulating dielectric layer 41 and the gate insulating dielectric layer 42 are stacked between the gates close to the drain among the first gate 21 and the second gate 22 in the dual gates 2 and the two-dimensional electron gas structure 1, and between the first gate 21 and the second gate 22; a grid insulating medium layer 42 is arranged between the grid far away from the drain electrode in the first grid 21 and the second grid 22 and the two-dimensional electron gas structure 1; the first gate metal layer 3 is positioned on the first gate electrode 21 and on the gate insulating dielectric layer 42, and the second gate metal layer 3 is positioned on the second gate electrode 22 and on the gate insulating dielectric layer 42.
In this embodiment, the insulating dielectric layer 4, the buffer insulating dielectric layer 41, and the gate insulating dielectric layer 42 include Al 2 O 3 、SiO 2 、Si 3 N 4 SiON, i.e. the insulating dielectric layer 4, may be a single material or a stack of layers of materials, e.g. Al 2 O 3 、SiO 2 、Si 3 N 4 A single layer of SiON or a stack of multiple materials.
The manufacturing method of this embodiment only describes the manufacturing process of the dual gate, and the manufacturing method of the source S and the drain D is a mature process step known in the industry.
In the HEMT device of the embodiment, the parasitic gate metal layer is arranged between the first gate and the second gate, and is connected with the gate metal, so that the gate metal layer has an electric field modulation effect, can better protect the gate closer to the source, and further improves the reliability of the gate.
Example six
On the basis of the first, second, and fourth embodiments, the present embodiment provides an HEMT device in which the number of the dual gates 2 is 2 pairs.
Referring to fig. 17a to 17c, fig. 17a to 17c are schematic process diagrams of a method for manufacturing two pairs of dual gates according to an embodiment of the present invention. Specifically, on the basis of obtaining the gate etching masks of the pair of dual gates 2, depositing the third etching mask 8 on the gate etching masks again and performing photoetching to obtain the gate etching masks of the two pairs of dual gates 2, further etching the gate material 20 by using the formed gate etching masks to remove the gate material 20 outside the gate etching masks, and remaining the gate material 20 under the gate etching masks to form 2 pairs of dual gates 2.
Note that the method of manufacturing the pair 2 of dual gates 2 is not limited to the above steps. The manufacturing method of this embodiment only describes the manufacturing process of the dual gate, and the manufacturing method of the source S and the drain D belongs to the prior art, and is not described in detail in this embodiment.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.

Claims (14)

1. A HEMT device, comprising: a two-dimensional electron gas structure (1) and at least one pair of dual grid electrodes (2), wherein,
a two-dimensional electron gas channel is formed in the two-dimensional electron gas structure (1), and the at least one pair of dual gates (2) is positioned above the two-dimensional electron gas channel;
the dual grid (2) is formed by adopting a self-alignment process, each pair of dual grids (2) comprises a first grid (21) and a second grid (22), and the first grid (21) and the second grid (22) are arranged in a mirror symmetry mode along the central axes of the first grid (21) and the second grid (22).
2. The HEMT device of claim 1, wherein said dual gate (2) is located on a surface of said two-dimensional electron gas structure (1).
3. The HEMT device of claim 2, further comprising a gate metal layer (3), the gate metal layer (3) wrapping the dual gate (2) and being located between the first gate (21) and the second gate (22).
4. The HEMT device according to claim 3, further comprising an insulating dielectric layer (4), the insulating dielectric layer (4) being located between the gate metal layer (3) and the dual gate (2).
5. The HEMT device according to claim 3, further comprising an insulating dielectric layer (4), wherein the insulating dielectric layer (4) is located between the gate metal layer (3) and the gate of the dual gate (2) that is far from the drain.
6. The HEMT device of claim 2, further comprising a gate metal layer (3) and an insulating dielectric layer (4), said insulating dielectric layer (4) being located on the surface of said two-dimensional electron gas structure (1) and said dual gate (2) penetrating said insulating dielectric layer (4), said gate metal layer (3) being located on top of said dual gate (2) and on said insulating dielectric layer (4).
7. The HEMT device of claim 1, wherein said dual gate (2) extends deep into said two-dimensional electron gas structure (1) and has its bottom above said two-dimensional electron gas channel.
8. The HEMT device of claim 7, further comprising a gate metal layer (3), wherein said first gate (21) and said second gate (22) are interconnected, and wherein said gate metal layer (3) is located on said interconnected first gate (21) and said second gate (22) and on said two-dimensional electron gas structure (1).
9. The HEMT device of claim 8, further comprising an insulating dielectric layer (4), said insulating dielectric layer (4) being located between said dual gate (2) and said two-dimensional electron gas structure (1).
10. The HEMT device according to claim 7, further comprising a gate metal layer (3), a buffer insulating dielectric layer (41), and a gate insulating dielectric layer (42),
the buffer insulating medium layer (41) and the gate insulating medium (42) are arranged between the grid close to the drain electrode in the first grid (21) and the second grid (22) and the two-dimensional electron gas structure (1) and between the first grid (21) and the second grid (22) in a stacking mode;
the grid insulating medium layer (42) is arranged between the grid far away from the drain electrode in the first grid (21) and the second grid (22) and the two-dimensional electron gas structure (1);
the gate metal layer (3) is located on the gate insulating dielectric layer (42) on the first gate (21) and the second gate (22) and on the gate insulating dielectric layer (42) between the first gate (21) and the second gate (22).
11. The HEMT device of claim 2 or 7, further comprising a first gate metal layer (31) and a second gate metal layer (32), said first gate metal layer (31) being located on said first gate (21) and said second gate metal layer (32) being located on said second gate (22).
12. The HEMT device of claim 1, wherein the materials of said first gate (21) and said second gate (22) each comprise one or more of a metal, a P-type GaN-based material.
13. The HEMT device of claim 1, wherein the length of said first gate (21) and said second gate (22) is less than 90nm, or wherein the length of said first gate (21) and said second gate (22) is less than 2 times the AlGaN barrier thickness in said two-dimensional electron gas structure (1).
14. A preparation method of an HEMT device is characterized by comprising the following steps:
preparing a first hard mask (6) on the surface of a device, and etching the first hard mask (6) to form a target structure;
preparing a second hard mask (7) on the surfaces of the target structure and the device, and performing self-aligned etching on the second hard mask (7) to form a first gate mask (71) and a second gate mask (72) which are positioned on the side wall of the target structure;
preparing a first grid electrode (21) and a second grid electrode (22) by utilizing the first grid electrode mask (71) and the second grid electrode mask (72) to obtain a dual grid electrode (2);
wherein the length of the first gate (21) and the length of the second gate (22) are both equal to the thickness of the second hard mask (7).
CN202211092714.0A 2022-09-07 2022-09-07 HEMT device Pending CN115881795A (en)

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