WO2021027182A1 - 一种服务器电源前后级通讯的方法、设备及可读介质 - Google Patents

一种服务器电源前后级通讯的方法、设备及可读介质 Download PDF

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Publication number
WO2021027182A1
WO2021027182A1 PCT/CN2019/121106 CN2019121106W WO2021027182A1 WO 2021027182 A1 WO2021027182 A1 WO 2021027182A1 CN 2019121106 W CN2019121106 W CN 2019121106W WO 2021027182 A1 WO2021027182 A1 WO 2021027182A1
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serial port
data
update request
data update
interrupt
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PCT/CN2019/121106
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English (en)
French (fr)
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赵燕燕
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苏州浪潮智能科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

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  • the present invention relates to the field of servers, and more specifically, to a method, equipment and readable medium for front and back communication of a server power supply.
  • the server power supply needs to interact with the server's BMC (Baseboard Management Controller, baseboard management controller) through the golden finger board
  • the BMC needs to read the relevant information of the PSU (power supply) or configure certain parameters. This interaction It is carried out through the I2C interface and the Pmbus protocol.
  • the I2C interface is installed in the latter stage of the LLC, which is the power supply.
  • the BMC also needs to interact with part of the data of the previous stage. This requires the help of the LLC. Therefore, the PFC and the LLC are also Need data interaction. Therefore, a convenient, stable and reliable front and back communication method is needed.
  • the purpose of the embodiments of the present invention is to propose a method and device for the communication between the front and rear of the server power supply, which mainly uses the serial port and the adjusted transmission protocol to transmit the data of the front stage to the rear stage more reliably in this way. And feedback to the BMC through the golden finger, which not only increases the data transmission rate, but also improves the reliability of the power supply.
  • one aspect of the embodiments of the present invention provides a method for server power front and rear communication, which includes the following steps: regularly constructing a data update request according to a transmission protocol that deletes address bits; opening the serial port to send interrupts and judging whether there is a pending transmission Data update request; In response to a data update request to be transmitted, the data update request is sent to the previous stage through the serial port sending interrupt and the serial port sending interrupt is closed; the data returned by the previous stage is received through the serial port receiving interrupt.
  • the method further includes: setting the time interval between opening the serial port to send interrupts twice adjacently to be smaller than the time interval between constructing data update requests twice adjacently.
  • constructing the data update request regularly according to the transmission protocol for deleting address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
  • receiving the data returned by the previous stage through the serial port interruption includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interruption to one.
  • it further includes: when it is detected that the receiving flag bit of the serial port receiving interrupt is one, analyzing the received data.
  • a computer device including: at least one processor; and a memory.
  • the memory stores computer instructions that can run on the processor, and the instructions are executed by the processor to implement the following steps: According to the transmission protocol that deletes the address bit, the data update request is constructed regularly; the serial port is opened to send an interrupt, and it is judged whether there is a data update request to be transmitted; in response to the data update request to be transmitted, the data update request is sent to the previous through the serial port sending interrupt Level and close the serial port to send interrupt; receive the data returned by the previous stage through the serial port receive interrupt.
  • the step further includes: setting the time interval between opening the serial port and sending interrupts twice adjacently to be less than the time interval between constructing the data update request twice.
  • constructing the data update request regularly according to the transmission protocol for deleting address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
  • receiving the data returned by the previous stage through the serial port interruption includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interruption to one.
  • a computer-readable storage medium stores a computer program that executes the above method when executed by a processor.
  • the present invention has the following beneficial technical effects: using the serial port and the adjusted transmission protocol, the data of the previous stage can be transmitted to the subsequent stage more reliably in this way and fed back to the BMC through the golden finger, which not only improves the data transmission rate, but also Improve the reliability of the power supply.
  • FIG. 1 is a schematic diagram of an embodiment of a method for back-and-forth communication of a server power supply provided by the present invention
  • FIG. 2 is a flowchart of an embodiment of a method for back-and-forth communication of a server power supply provided by the present invention.
  • Figure 1 shows a schematic diagram of an embodiment of a method for front and back communication of a server power supply provided by the present invention.
  • the embodiment of the present invention includes the following steps:
  • the data update request is constructed regularly according to the transmission protocol of the deleted address bit
  • the Modbus protocol is suitable for data transmission in small systems. Therefore, in this embodiment, the transmission protocol may be the modbus protocol, but this is not a limitation on the transmission protocol. In other embodiments, other transmission protocols may be used.
  • the embodiment of the present invention uses a communication isolation chip to use a serial port on the hardware to connect the front and back stages of the server power supply. According to the Modbus protocol, the latter stage is set to Master (master device), and the previous stage is set to Slave (slave device).
  • the data update request is constructed according to the transmission protocol of the deleted address bit.
  • the master main program builds a data update request according to the transmission protocol.
  • a server power supply has only one front-end part, and there is no need to distinguish the address. Therefore, the transmission protocol is simplified, the slave address in the protocol is removed, and the length of the protocol is shortened. Greatly speed up the data transmission rate, thereby speeding up the data update rate.
  • the data update request also includes the data request of the input voltage of the PFC front stage and the bus voltage.
  • the Master can be set to poll the required data regularly, and the data update request can also be set at the same time.
  • the serial port transmission interrupt can be set to be opened every predetermined time.
  • the method further includes: setting the time interval between two consecutive opening of the serial port to send interrupts to be smaller than the time interval between two consecutive construction of data update requests.
  • regularly constructing a data update request according to a transmission protocol that deletes address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
  • an unsigned char sending buffer with a length of 128 can be defined, and the data update request can be written into the sending buffer.
  • receiving the data returned by the previous stage through the serial port receiving interrupt includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interrupt to one.
  • the serial port receiving interrupt is always in the open mode. When receiving the data returned by the Slave, it enters the serial port receiving interrupt to store the data in the receiving buffer. You can define an unsigned char receiving buffer with a length of 128. When the received data length is equal to a predetermined value, for example, the predetermined value in this embodiment is 7 (the length of the returned data is fixed to 7 bytes according to the transmission protocol), Set the received data flag to 1, which means that the data has been received.
  • the method further includes: when it is detected that the receiving flag bit of the serial port receiving interrupt is one, analyzing the received data. After the LLC main program detects that the serial port receive interrupt receive data flag bit is 1, the received data is processed, and finally the data to be updated is obtained.
  • Slave's serial port receive interrupt is always on. You can define an unsigned char type receive buffer with a length of 32. After receiving the data, put the data into the receive buffer, and receive the serial port when one frame of data is received. The interrupted data receiving flag bit is 1; the main program detects that the data receiving flag bit in the serial port receiving interrupt is 1 and processes the data in the receiving buffer according to the protocol; fills the processed content with the corresponding data in the return frame Or assign a value to the corresponding variable; fill the return frame data into the send buffer of the Slave, you can define an unsigned char type send buffer with a length of 32, fill the return frame data into it, and set the send flag position to 1. Open the serial port to send interrupt and start data transmission. In this way, the interaction of the front and back level data is realized.
  • FIG. 2 shows a flowchart of an embodiment of a method for front and back communication of a server power supply provided by the present invention.
  • FIG. 2 shows a flowchart of an embodiment of a method for front and back communication of a server power supply provided by the present invention.
  • box 101 starting from box 101, then proceeding to box 102, constructing a data update request according to the transmission protocol that deletes the address bit; then proceeding to box 103, opening the serial port to send interrupt; then proceeding to box 104 to determine whether there is a waiting
  • the transmitted data update request then proceed to block 105, send the data update request to the previous stage through the serial port sending interrupt; then proceed to block 106, receive the data returned by the previous stage through the serial port receiving interrupt, and then proceed to the end of block 107.
  • the second aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory, the memory stores computer instructions that can run on the processor, and the instructions are executed by the processor to The following steps are implemented: S1, the data update request is constructed regularly according to the transmission protocol of the deleted address bit; S2, the serial port is opened to send an interrupt and judge whether there is a data update request to be transmitted; S3, in response to the data update request to be transmitted, through the serial port The sending interrupt sends the data update request to the previous stage and closes the serial port sending interrupt; and S4, receiving the data returned by the previous stage through the serial port receiving interrupt.
  • the method further includes: setting the time interval between opening the serial port to send interrupts twice adjacently to be smaller than the time interval between constructing data update requests twice adjacently.
  • constructing the data update request regularly according to the transmission protocol for deleting address bits includes: setting a sending buffer, and writing the data update request to be sent into the sending buffer.
  • receiving the data returned by the previous stage through the serial port interruption includes: determining whether the data length is equal to a predetermined value; and in response to the data length being equal to the predetermined value, setting the receiving flag of the serial port receiving interruption to one.
  • it further includes: when it is detected that the receiving flag bit of the serial port receiving interrupt is one, analyzing the received data.
  • the present invention also provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program that executes the above method when executed by a processor.
  • the program for the method of server power front and back communication can be stored in a computer.
  • the readable storage medium when the program is executed, it may include the procedures of the above-mentioned method embodiments.
  • the storage medium of the program can be a magnetic disk, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc.
  • the foregoing computer program embodiment can achieve the same or similar effects as any of the foregoing corresponding method embodiments.
  • the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, and the computer program may be stored in a computer-readable storage medium.
  • the computer program executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.
  • the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.
  • non-volatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory Memory.
  • Volatile memory can include random access memory (RAM), which can act as external cache memory.
  • RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM).
  • DRAM synchronous RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDR SDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM Synchronous link DRAM
  • DRRAM direct Rambus RAM
  • the storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA Field Programmable Gate Array
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP, and/or any other such configuration.
  • the steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two.
  • the software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium.
  • the storage medium may be integrated with the processor.
  • the processor and the storage medium may reside in the ASIC.
  • the ASIC can reside in the user terminal.
  • the processor and the storage medium may reside as discrete components in the user terminal.
  • functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium.
  • Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another.
  • a storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used for carrying or storing instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
  • coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source
  • coaxial cable Cable, fiber optic cable, twisted pair, DSL or wireless technologies such as infrared, radio, and microwave are all included in the definition of media.
  • magnetic disks and optical disks include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVD), floppy disks, and Blu-ray disks. Disks generally reproduce data magnetically, while optical disks use lasers to optically reproduce data .
  • the combination of the above content should also be included in the scope of computer-readable media.
  • the program can be stored in a computer-readable storage medium.
  • the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

一种服务器电源前后级通讯的方法，包括以下步骤：根据删除地址位的传输协议定时构建数据更新请求；打开串口发送中断并判断是否存在待传输的数据更新请求；响应于存在待传输的数据更新请求，通过串口发送中断将数据更新请求发送到前级并关闭串口发送中断；通过串口接收中断接收前级返回的数据。本发明还公开了一种计算机设备和可读存储介质。本发明提出的服务器电源前后级通讯的方法及装置有效解决服务器电源前后级的通讯问题，将前级的数据通过此方式更可靠的传输到后级并通过金手指反馈给BMC，提高电源的可靠性。

Description

一种服务器电源前后级通讯的方法、设备及可读介质
本申请要求于2019年8月9日提交中国专利局、申请号为201910735663.0、发明名称为“一种服务器电源前后级通讯的方法、设备及可读介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及服务器领域，更具体地，特别是指一种服务器电源前后级通讯的方法、设备及可读介质。
背景技术
伴随科学技术进步及经济发展，现代的电源技术向着更高效率和更高的功率密度发展，近年来随着LLC(谐振变换技术)的成熟和稳定，已经开始应用到电源中并取得很好的效果。LLC谐振变换器因为能实现主开关管的零电压开通、副边整流二极管的零电流关断的软开关技术，实现高效率的能量转换，并且降低开关损耗，正在受到广泛的应用和研究。而服务器电源为了提高效率大部分使用的是LLC技术，除此之外为了符合国标要求，对于大功率的器件必须进行功率因数校正，减少对电网的损害，因此必须包含功率矫正电路，从成本，操作性等方面综合考虑选择BOOST升压电路进行功率因数校正(PFC)，因此PFC与LLC构成了服务器电源的前级与后级。
由于服务器电源需要与服务器的BMC(Baseboard Management Controller，基板管理控制器)通过金手指板进行数据的交互，BMC需要读取PSU(供电电源)的相关信息或者对某些参数进行配置，这种交互是通过I2C接口和Pmbus协议进行的，此I2C接口是安装在LLC也就是电源的后级，BMC也需要与前级的部分数据进行交互，这就需要借助于LLC，因此PFC与LLC之间也需要数据的交互。因此需要一种便捷稳定且可靠的前后级通讯方式。
发明内容
有鉴于此，本发明实施例的目的在于提出一种服务器电源前后级通讯的方法及装置，主要是采用串口和调整后的传输协议，将前级的数据通过此方式更可靠的传输到后级并通过金手指反馈给BMC，不仅提高了数据的传输速率，更提高了电源的可靠性。
基于上述目的，本发明实施例的一方面提供了一种服务器电源前后级通讯的方法，包括如下步骤：根据删除地址位的传输协议定时构建数据更新请求；打开串口发送中断并判断是否存在待传输的数据更新请求；响应于存在待传输的数据更新请求，通过串口发送中断将数据更新请求发送到前级并关闭串口发送中断；通过串口接收中断接收前级返回的数据。
在一些实施方式中，还包括：设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。
在一些实施方式中，根据删除地址位的传输协议定时构建数据更新请求包括：设定发送缓冲区，将待发送的数据更新请求写入发送缓冲区。
在一些实施方式中，通过串口接收中断接收前级返回的数据包括：判断数据长度是否等于预定数值；以及响应于数据长度等于预定数值，将串口接收中断的接收标志位置一。
在一些实施方式中，还包括：检测到串口接收中断的接收标志位为一时，对接收到的数据进行解析。
本发明实施例的另一方面，还提供了一种计算机设备，包括：至少一个处理器；以及存储器，存储器存储有可在处理器上运行的计算机指令，指令由处理器执行以实现如下步骤：根据删除地址位的传输协议定时构建数据更新请求；打开串口发送中断，并判断是否存在待传输的数据更新请求；响应于存在待传输的数据更新请求，通过串口发送中断将数据更新请求发送到前级并关闭串口发送中断；通过串口接收中断接收前级返回的数据。
在一些实施方式中，步骤还包括：设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。
在一些实施方式中，根据删除地址位的传输协议定时构建数据更新请求包括：设定发送缓冲区，将待发送的数据更新请求写入发送缓冲区。
在一些实施方式中，通过串口接收中断接收前级返回的数据包括：判断数据长度是否等于预定数值；以及响应于数据长度等于预定数值，将串口接收中断的接收标志位置一。
本发明实施例的再一方面，还提供了一种计算机可读存储介质，计算机可读存储介质存储有被处理器执行时执行如上方法的计算机程序。
本发明具有以下有益技术效果：采用采用串口和调整后的传输协议，将前级的数据通过此方式更可靠的传输到后级并通过金手指反馈给BMC，不仅提高了数据的传输速率，更提高了电源的可靠性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的实施例。
图1为本发明提供的服务器电源前后级通讯的方法的实施例的示意图；
图2为本发明提供的服务器电源前后级通讯的方法的实施例的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明实施例进一步详细说明。
需要说明的是，本发明实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”“第二”仅为了表述的方便，不应理解为对本发明实施例的限定，后续实施例对此不再一一说明。
基于上述目的，本发明实施例的第一个方面，提出了一种服务器电源前后级通讯的方法的实施例。图1示出的是本发明提供的服务器电源前后 级通讯的方法的实施例的示意图。如图1所示，本发明实施例包括如下步骤：
S1、根据删除地址位的传输协议定时构建数据更新请求；
S2、打开串口发送中断并判断是否存在待传输的数据更新请求；
S3、响应于存在待传输的数据更新请求，通过串口发送中断将数据更新请求发送到前级并关闭串口发送中断；以及
S4、通过串口接收中断接收前级返回的数据。
Modbus协议适用于小型系统中的数据传输，因此，在本实施例中，传输协议可以是modbus协议，但这并不是对传输协议的限制，在其他的实施例中，可以采用其他传输协议。本发明实施例在硬件上采用通信隔离芯片使用串口的形式对服务器电源的前后级进行连接。根据Modbus规约，将后级设置为Master(主设备)，将前级设置为Slave(从设备)。
根据删除地址位的传输协议构建数据更新请求。Master主程序根据传输协议组建数据更新请求，鉴于应用的具体情景，一个服务器电源只有一个前级部分，不需要区分地址，因此简化传输协议，将协议中的Slave地址去掉，缩短协议长度，从而可以大大加快数据的传输速率，进而加快数据更新的速率。数据更新请求中还包括：PFC前级的输入电压、母线电压的数据请求。
在本实施例中可以设置Master定时进行所需数据的轮询，也可以同时设置数据更新请求。
打开串口发送中断，并判断是否存在待传输的数据更新请求。在本实施例中可以设置串口发送中断每隔预定时间打开。在某些实施例中，方法还包括：设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。在某些实施例中，根据删除地址位的传输协议定时构建数据更新请求包括：设定发送缓冲区，将待发送的数据更新请求写入所述发送缓冲区。在本实施例中，可以定义一个unsigned char型的长度为128的发送缓冲区，将数据更新请求写入发送缓冲区之中。打开串口发送中断后当发送缓冲区有数据时就进入中断进行字节数据发送，发送完成后即发送缓冲区中无数据后将串口发送中断关闭。
在某些实施例中，通过串口接收中断接收所述前级返回的数据包括：判断数据长度是否等于预定数值；以及响应于数据长度等于预定数值，将串口接收中断的接收标志位置一。串口接收中断一直处于打开模式，当接收到Slave返回的数据时进入串口接收中断将数据存入接收缓冲区。可以定义一个unsigned char型的长度为128的接收缓冲区，当接收的数据长度等于预定数值，例如本实施例中的预定数值为7(根据传输协议返回数据长度固定为7个字节)时，将接收数据标志位置1，代表数据接收完毕。
在某些实施例中，方法还包括：检测到所述串口接收中断的接收标志位为一时，对接收到的数据进行解析。LLC主程序中检测到串口接收中断接收数据标志位为1后将接收到的数据进行数据处理，最终得到要更新的数据。
对于PFC级的Slave部分步骤如下：
Slave的串口接收中断一直处于开启状态，可以定义一个unsigned char型的长度为32的接收缓冲区，接收到数据后将数据放入接收缓冲区中，当接收到一帧的数据长后将串口接收中断的数据接收标志位置1；主程序检测到串口接收中断中的数据接收标志位为1后将接收缓冲区中的数据根据协议进行处理；将处理后的内容在返回帧中填入相应的数据或者对对应的变量赋值；将返回帧数据填入到Slave的发送缓冲区中，可以定义一个unsigned char型的长度为32的发送缓冲区，返回帧数据填入其中，并将发送标志位置1，打开串口发送中断，开始进行数据发送。这样就实现了前后级数据的交互。
图2示出的是本发明提供的服务器电源前后级通讯的方法的实施例的流程图。如图2所示，从框101开始，接着前进到框102，根据删除地址位的传输协议构建数据更新请求；接着前进到框103，打开串口发送中断；接着前进到框104，判断是否存在待传输的数据更新请求；接着前进到框105，通过串口发送中断将数据更新请求发送到前级；接着前进到框106，通过串口接收中断接收前级返回的数据，然后前进到框107结束。
需要特别指出的是，上述服务器电源前后级通讯的方法的各个实施例中的各个步骤均可以相互交叉、替换、增加、删减，因此，这些合理的排 列组合变换之于服务器电源前后级通讯的方法也应当属于本发明的保护范围，并且不应将本发明的保护范围局限在实施例之上。
基于上述目的，本发明实施例的第二个方面，提出了一种计算机设备，包括：至少一个处理器；以及存储器，存储器存储有可在处理器上运行的计算机指令，指令由处理器执行以实现如下步骤：S1、根据删除地址位的传输协议定时构建数据更新请求；S2、打开串口发送中断并判断是否存在待传输的数据更新请求；S3、响应于存在待传输的数据更新请求，通过串口发送中断将数据更新请求发送到前级并关闭串口发送中断；以及S4、通过串口接收中断接收前级返回的数据。
在一些实施方式中，还包括：设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。
在一些实施方式中，根据删除地址位的传输协议定时构建数据更新请求包括：设定发送缓冲区，将待发送的数据更新请求写入发送缓冲区。
在一些实施方式中，通过串口接收中断接收前级返回的数据包括：判断数据长度是否等于预定数值；以及响应于数据长度等于预定数值，将串口接收中断的接收标志位置一。
在一些实施方式中，还包括：检测到串口接收中断的接收标志位为一时，对接收到的数据进行解析。
本发明还提供了一种计算机可读存储介质，计算机可读存储介质存储有被处理器执行时执行如上方法的计算机程序。
最后需要说明的是，本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，可以通过计算机程序来指令相关硬件来完成，服务器电源前后级通讯的方法的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，程序的存储介质可为磁碟、光盘、只读存储记忆体(ROM)或随机存储记忆体(RAM)等。上述计算机程序的实施例，可以达到与之对应的前述任意方法实施例相同或者相类似的效果。
此外，根据本发明实施例公开的方法还可以被实现为由处理器执行的计算机程序，该计算机程序可以存储在计算机可读存储介质中。在该计算 机程序被处理器执行时，执行本发明实施例公开的方法中限定的上述功能。
此外，上述方法步骤以及系统单元也可以利用控制器以及用于存储使得控制器实现上述步骤或单元功能的计算机程序的计算机可读存储介质实现。
此外，应该明白的是，本文的计算机可读存储介质(例如，存储器)可以是易失性存储器或非易失性存储器，或者可以包括易失性存储器和非易失性存储器两者。作为例子而非限制性的，非易失性存储器可以包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦写可编程ROM(EEPROM)或快闪存储器。易失性存储器可以包括随机存取存储器(RAM)，该RAM可以充当外部高速缓存存储器。作为例子而非限制性的，RAM可以以多种形式获得，比如同步RAM(DRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据速率SDRAM(DDR SDRAM)、增强SDRAM(ESDRAM)、同步链路DRAM(SLDRAM)、以及直接Rambus RAM(DRRAM)。所公开的方面的存储设备意在包括但不限于这些和其它合适类型的存储器。
本领域技术人员还将明白的是，结合这里的公开所描述的各种示例性逻辑块、模块、电路和算法步骤可以被实现为电子硬件、计算机软件或两者的组合。为了清楚地说明硬件和软件的这种可互换性，已经就各种示意性组件、方块、模块、电路和步骤的功能对其进行了一般性的描述。这种功能是被实现为软件还是被实现为硬件取决于具体应用以及施加给整个系统的设计约束。本领域技术人员可以针对每种具体应用以各种方式来实现的功能，但是这种实现决定不应被解释为导致脱离本发明实施例公开的范围。
结合这里的公开所描述的各种示例性逻辑块、模块和电路可以利用被设计成用于执行这里功能的下列部件来实现或执行：通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或其它可编程逻辑器件、分立门或晶体管逻辑、分立的硬件组件或者这些部件的任何组合。通用处理器可以是微处理器，但是可替换地，处理器可以是任何传统处理器、控制器、微控制器或状态机。处理器也可以被实现 为计算设备的组合，例如，DSP和微处理器的组合、多个微处理器、一个或多个微处理器结合DSP和/或任何其它这种配置。
结合这里的公开所描述的方法或算法的步骤可以直接包含在硬件中、由处理器执行的软件模块中或这两者的组合中。软件模块可以驻留在RAM存储器、快闪存储器、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动盘、CD-ROM、或本领域已知的任何其它形式的存储介质中。示例性的存储介质被耦合到处理器，使得处理器能够从该存储介质中读取信息或向该存储介质写入信息。在一个替换方案中，存储介质可以与处理器集成在一起。处理器和存储介质可以驻留在ASIC中。ASIC可以驻留在用户终端中。在一个替换方案中，处理器和存储介质可以作为分立组件驻留在用户终端中。
在一个或多个示例性设计中，功能可以在硬件、软件、固件或其任意组合中实现。如果在软件中实现，则可以将功能作为一个或多个指令或代码存储在计算机可读介质上或通过计算机可读介质来传送。计算机可读介质包括计算机存储介质和通信介质，该通信介质包括有助于将计算机程序从一个位置传送到另一个位置的任何介质。存储介质可以是能够被通用或专用计算机访问的任何可用介质。作为例子而非限制性的，该计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其它光盘存储设备、磁盘存储设备或其它磁性存储设备，或者是可以用于携带或存储形式为指令或数据结构的所需程序代码并且能够被通用或专用计算机或者通用或专用处理器访问的任何其它介质。此外，任何连接都可以适当地称为计算机可读介质。例如，如果使用同轴线缆、光纤线缆、双绞线、数字用户线路(DSL)或诸如红外线、无线电和微波的无线技术来从网站、服务器或其它远程源发送软件，则上述同轴线缆、光纤线缆、双绞线、DSL或诸如红外线、无线电和微波的无线技术均包括在介质的定义。如这里所使用的，磁盘和光盘包括压缩盘(CD)、激光盘、光盘、数字多功能盘(DVD)、软盘、蓝光盘，其中磁盘通常磁性地再现数据，而光盘利用激光光学地再现数据。上述内容的组合也应当包括在计算机可读介质的范围内。
以上是本发明公开的示例性实施例，但是应当注意，在不背离权利要 求限定的本发明实施例公开的范围的前提下，可以进行多种改变和修改。根据这里描述的公开实施例的方法权利要求的功能、步骤和/或动作不需以任何特定顺序执行。此外，尽管本发明实施例公开的元素可以以个体形式描述或要求，但除非明确限制为单数，也可以理解为多个。
应当理解的是，在本文中使用的，除非上下文清楚地支持例外情况，单数形式“一个”旨在也包括复数形式。还应当理解的是，在本文中使用的“和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
上述本发明实施例公开实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
所属领域的普通技术人员应当理解：以上任何实施例的讨论仅为示例性的，并非旨在暗示本发明实施例公开的范围(包括权利要求)被限于这些例子；在本发明实施例的思路下，以上实施例或者不同实施例中的技术特征之间也可以进行组合，并存在如上的本发明实施例的不同方面的许多其它变化，为了简明它们没有在细节中提供。因此，凡在本发明实施例的精神和原则之内，所做的任何省略、修改、等同替换、改进等，均应包含在本发明实施例的保护范围之内。

Claims (10)

  1. 一种服务器电源前后级通讯的方法，其特征在于，包括：
    根据删除地址位的传输协议定时构建数据更新请求；
    打开串口发送中断并判断是否存在待传输的数据更新请求；
    响应于存在待传输的数据更新请求，通过所述串口发送中断将所述数据更新请求发送到前级并关闭所述串口发送中断；
    通过串口接收中断接收所述前级返回的数据。
  2. 根据权利要求1所述的方法，其特征在于，还包括：
    设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。
  3. 根据权利要求1所述的方法，其特征在于，所述根据删除地址位的传输协议定时构建数据更新请求包括：
    设定发送缓冲区，将待发送的数据更新请求写入所述发送缓冲区。
  4. 根据权利要求1所述的方法，其特征在于，所述通过串口接收中断接收所述前级返回的数据包括：
    判断数据长度是否等于预定数值；以及
    响应于数据长度等于预定数值，将串口接收中断的接收标志位置一。
  5. 根据权利要求4所述的方法，其特征在于，还包括：
    检测到所述串口接收中断的接收标志位为一时，对接收到的数据进行解析。
  6. 一种计算机设备，其特征在于，包括：
    至少一个处理器；以及
    存储器，所述存储器存储有可在所述处理器上运行的计算机指令，所述指令由所述处理器执行时实现如下步骤：
    根据删除地址位的传输协议定时构建数据更新请求；
    打开串口发送中断并判断是否存在待传输的数据更新请求；
    响应于存在待传输的数据更新请求，通过所述串口发送中断将所述数据更新请求发送到前级并关闭所述串口发送中断；
    通过串口接收中断接收所述前级返回的数据。
  7. 根据权利要求6所述的计算机设备，其特征在于，步骤还包括：
    设定相邻两次打开串口发送中断的时间间隔小于相邻两次构建数据更新请求的时间间隔。
  8. 根据权利要求6所述的计算机设备，其特征在于，所述根据删除地址位的传输协议定时构建数据更新请求包括：
    设定发送缓冲区，将待发送的数据更新请求写入所述发送缓冲区。
  9. 根据权利要求6所述的计算机设备，其特征在于，所述通过串口接收中断接收所述前级返回的数据包括：
    判断数据长度是否等于预定数值；以及
    响应于数据长度等于预定数值，将串口接收中断的接收标志位置一。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时执行权利要求1-5任意一项所述的方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113094305A (zh) * 2021-04-02 2021-07-09 北京黑蚁兄弟科技有限公司 一种异步通信处理方法、装置和存储介质

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111007423B (zh) * 2019-12-22 2022-04-22 苏州浪潮智能科技有限公司 一种服务器电源前后级的通讯测试治具
CN111352889B (zh) * 2020-02-29 2021-10-19 苏州浪潮智能科技有限公司 一种基于mctp协议的设备管理方法、设备、装置和介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101136735A (zh) * 2006-09-12 2008-03-05 中兴通讯股份有限公司 使用通用异步收发报机的半双工串口通信系统及通信方法
CN102937944A (zh) * 2012-10-16 2013-02-20 北京交控科技有限公司 一种基于Arcnet串口服务器
CN106155960A (zh) * 2016-06-29 2016-11-23 广州慧睿思通信息科技有限公司 基于gpio握手和edma的uart串口通信方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101291331A (zh) * 2007-04-19 2008-10-22 华硕电脑股份有限公司 无线通信系统改善重排序功能的方法及其相关装置
CN102014027B (zh) * 2010-12-13 2013-01-16 东南大学 一种基于goose报文帧聚合技术的断路器在线监测装置
CN102360204A (zh) * 2011-08-04 2012-02-22 南京航空航天大学 基于FlexRay的分布式飞行控制计算机通信系统及控制方法
CN106533621B (zh) * 2016-11-15 2019-07-19 合肥工业大学智能制造技术研究院 基于简化的modbus协议的永磁同步电机实时监控的通讯方法
CN106533874B (zh) * 2016-11-22 2019-05-21 北京金自天正智能控制股份有限公司 一种基于Modbus RTU协议的永磁同步电机数据通信系统及方法
CN107134839A (zh) * 2017-05-11 2017-09-05 山东鲁能智能技术有限公司 一种基于全数字控制的高功率密度充电模块及方法
CN107465576A (zh) * 2017-08-23 2017-12-12 江苏舾普泰克自动化科技有限公司 一种基于Modbus协议的多主机通讯系统及方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101136735A (zh) * 2006-09-12 2008-03-05 中兴通讯股份有限公司 使用通用异步收发报机的半双工串口通信系统及通信方法
CN102937944A (zh) * 2012-10-16 2013-02-20 北京交控科技有限公司 一种基于Arcnet串口服务器
CN106155960A (zh) * 2016-06-29 2016-11-23 广州慧睿思通信息科技有限公司 基于gpio握手和edma的uart串口通信方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113094305A (zh) * 2021-04-02 2021-07-09 北京黑蚁兄弟科技有限公司 一种异步通信处理方法、装置和存储介质
CN113094305B (zh) * 2021-04-02 2024-03-26 北京黑蚁兄弟科技有限公司 一种异步通信处理方法、装置和存储介质

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