WO2021026914A1 - 毛刺信号检测电路、安全芯片和电子设备 - Google Patents

毛刺信号检测电路、安全芯片和电子设备 Download PDF

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Publication number
WO2021026914A1
WO2021026914A1 PCT/CN2019/100864 CN2019100864W WO2021026914A1 WO 2021026914 A1 WO2021026914 A1 WO 2021026914A1 CN 2019100864 W CN2019100864 W CN 2019100864W WO 2021026914 A1 WO2021026914 A1 WO 2021026914A1
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Prior art keywords
mos
voltage
mos transistors
mos transistor
detection circuit
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PCT/CN2019/100864
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English (en)
French (fr)
Inventor
薛建锋
杨江
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2019/100864 priority Critical patent/WO2021026914A1/zh
Priority to EP19919549.6A priority patent/EP3805767B1/en
Priority to CN201980001599.1A priority patent/CN112673263B/zh
Priority to US17/025,788 priority patent/US11187731B2/en
Publication of WO2021026914A1 publication Critical patent/WO2021026914A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2513—Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging

Definitions

  • the embodiments of the present application relate to the field of electronics, and more specifically, to glitch signal detection circuits, security chips, and electronic devices.
  • Security chips can be used to realize functions such as user identification and key data storage. They are widely used in the financial field and are a key target of attackers.
  • Attackers can use fault attacks (such as power glitch attacks) to make the chip work in an abnormal state, resulting in chip misbehavior; at this time, the attacker can easily obtain the confidential data in the security chip by using fault analysis technology .
  • the glitch on the power supply voltage or ground voltage
  • an alarm signal can be given in time, thereby increasing the robustness and safety of the chip system.
  • the existing glitch signal detection circuit can only realize a simple glitch signal detection function, and cannot detect a glitch signal with a fixed amplitude, and its applicability is low. In addition, the existing glitch signal detection circuit cannot adjust the detection range of the glitch signal, and its sensitivity is low.
  • the embodiments of the present application provide a glitch signal detection circuit, a security chip, and an electronic device, which can improve the applicability and sensitivity of the glitch signal detection circuit.
  • a glitch signal detection circuit including:
  • Voltage sampling module used to obtain and output the sampling voltage of the power supply voltage
  • the detection unit array includes a plurality of metal oxide semiconductor MOS transistors with different threshold voltages, the first ends of the plurality of MOS transistors are connected to the sampling voltage, and the second ends of the plurality of MOS transistors are connected to the power supply voltage;
  • a switch array including a plurality of switches corresponding to the plurality of MOS tubes
  • a signal generating circuit, the drain terminals of the plurality of MOS transistors are respectively connected to the signal generating circuit through the plurality of switches;
  • the signal generation circuit is configured to perform according to the voltage of the output terminal of the target switch
  • the change in value generates and outputs a target signal, which is used to indicate whether a glitch signal appears in the power supply voltage or the ground voltage.
  • the glitch signal detection circuit can detect the power supply voltage on the basis of different threshold voltages through the detection unit array and the switch array. Whether a glitch signal appears and whether a glitch signal appears on the ground voltage. That is, by selecting different MOS tubes, the glitch signal of a specific amplitude can be detected, thereby improving the applicability and sensitivity of the glitch signal detection circuit.
  • the MOS transistors with different threshold voltages in the detection unit array share the sampling voltage output by the voltage sampling module, which can reduce device overhead and chip area, thereby reducing costs; moreover, the glitch signal detection circuit is also compatible with digital The (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) process can enhance the portability of the glitch signal detection circuit.
  • CMOS complementary Metal-Oxide-Semiconductor Transistor
  • the glitch signal detection circuit can not only detect glitches on the power supply voltage or ground voltage, but also has the advantages of strong applicability, high sensitivity, low cost, and strong portability.
  • the multiple MOS transistors include:
  • the first end of the first MOS transistor is the gate end of the first MOS transistor, and the second end of the first MOS transistor is the source end of the first MOS transistor.
  • the switch array includes:
  • the source terminals of the plurality of second MOS transistors are respectively connected to the drain terminals of the plurality of first MOS transistors, and the drain terminals of the plurality of second MOS transistors are connected to the signal generating circuit;
  • the gate terminal of the target MOS tube among the plurality of second MOS tubes is used to receive the ground voltage
  • the gate terminals of the MOS transistors other than the target MOS transistor among the plurality of second MOS transistors are used to receive the power supply voltage.
  • the multiple MOS transistors include:
  • the first end of the third MOS transistor is the source end of the third MOS transistor, and the second end of the third MOS transistor is the gate end of the third MOS transistor.
  • the switch array includes:
  • the source terminals of the plurality of fourth MOS transistors are respectively connected to the drain terminals of the plurality of third MOS transistors, and the drain terminals of the plurality of fourth MOS transistors are connected to the signal generating circuit;
  • the gate terminal of the target MOS tube among the plurality of fourth MOS tubes is used to receive the ground voltage
  • the gate terminals of the MOS transistors other than the target MOS transistor among the plurality of fourth MOS transistors are used to receive the power supply voltage or the sampling voltage.
  • the switch array further includes:
  • the source terminals of the plurality of fifth MOS transistors are used to receive the power supply voltage, and the drain terminals of the plurality of fifth MOS transistors are respectively connected to the source terminals of the plurality of fourth MOS transistors;
  • the gate terminal of the target MOS transistor among the plurality of fifth MOS transistors is used to receive the power supply voltage
  • the gate terminals of the MOS transistors other than the target MOS transistor among the plurality of fifth MOS transistors are used to receive the ground voltage.
  • the voltage sampling module includes:
  • the first capacitor and the sixth MOS tube are connected to The first capacitor and the sixth MOS tube.
  • the gate terminal of the sixth MOS transistor is connected to the ground voltage through the first capacitor, and the source terminal of the sixth MOS transistor is connected to the ground voltage.
  • the voltage sampling module further includes:
  • the seventh MOS tube, the eighth MOS tube and the first inverter are connected to the seventh MOS tube, the eighth MOS tube and the first inverter;
  • the gate terminal of the sixth MOS transistor is connected to the power supply voltage through the seventh MOS transistor, and the drain terminal of the sixth MOS transistor is connected to the ground voltage through the eighth MOS transistor.
  • the drain terminal of the MOS tube is connected to the gate terminal of the sixth MOS tube through the first inverter.
  • the voltage sampling module includes:
  • One end of the resistor is connected to the power supply voltage, and the other end of the resistor is connected to the ground voltage through the second capacitor.
  • the signal generating circuit is a D flip-flop.
  • a security chip including the glitch signal detection circuit described in the first aspect and any possible implementation of the first aspect.
  • an electronic device including:
  • the security chip and a processor, wherein the processor is configured to receive a target signal sent by the security chip, and the target signal is used to indicate whether a glitch signal occurs in a power supply voltage or a ground voltage.
  • Fig. 1 is a schematic structural diagram of a glitch signal detection circuit in an embodiment of the present application.
  • Fig. 2 is another schematic structural diagram of the glitch signal detection circuit shown in Fig. 1.
  • FIG. 3 is a schematic circuit diagram of a positive direction burr detection array in the burr signal detection circuit shown in FIG. 1.
  • FIG. 4 is a schematic circuit diagram of a negative direction burr detection array in the burr signal detection circuit shown in FIG. 1.
  • FIG. 5 is a schematic circuit diagram of a switch array in the glitch signal detection circuit of an embodiment of the present application.
  • 6 and 7 are schematic circuit diagrams of the voltage sampling module in the glitch signal detection circuit of the embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a signal generation circuit in a glitch signal detection circuit in an embodiment of the present application.
  • a power glitch attack quickly changes the power supply voltage (or ground voltage) input to the chip, which affects certain circuit units of the chip; then causes one or more circuit units to enter an error state, causing the chip's processor to jump The wrong operation is performed or based on the error state; and the hidden security information in the chip is exposed.
  • the glitch signal may be a regular or irregular pulse signal or spike signal in the input waveform of the circuit.
  • the voltage value when a positive glitch signal appears on the power supply voltage is equal to the voltage value when no glitch signal appears on the power supply voltage plus the voltage value of the glitch signal.
  • the voltage value when a negative and positive glitch signal appears on the power supply voltage is equal to the voltage value when there is no glitch signal on the power supply voltage minus the voltage value of the glitch signal.
  • a glitch signal in the positive direction and a glitch signal in the negative direction can also appear on the ground voltage.
  • the unstable power supply voltage it can also be considered as the voltage after a glitch signal is superimposed on the stable power supply voltage.
  • the unstable ground voltage it can also be considered as the voltage after a glitch signal is superimposed on the stable ground voltage.
  • FIG. 1 is a schematic structural diagram of a glitch signal detection circuit 10 according to an embodiment of the present application.
  • the glitch signal detection circuit 10 may include a voltage sampling module 15, a detection unit array 11, a switch array 12 and a signal generation circuit 13.
  • the voltage sampling module 15 is used to obtain and output the sampling voltage of the power supply voltage.
  • the detection unit array 11 may include a plurality of Metal-Oxide Semiconductor (MOS) tubes with different threshold voltages.
  • the plurality of MOS tubes have different threshold voltages, and the first ends of the plurality of MOS tubes Connected to the sampling voltage, and the second ends of the plurality of MOS transistors are connected to the power supply voltage.
  • MOS Metal-Oxide Semiconductor
  • the switch array 12 may include a plurality of switches corresponding to the plurality of MOS transistors, and the plurality of switches may be used to turn on or disconnect the plurality of MOS transistors in the detection unit array 11 and the signal generating circuit 13 For example, the path between the MOS transistor with a specific threshold voltage in the detection unit array 11 and the signal generation circuit 13 is turned on, and the other MOS transistors in the detection unit array and the signal generation circuit 13 are disconnected.
  • the signal generation circuit 13 can receive the detection signal transmitted by the drain terminal of the MOS tube with a specific threshold voltage.
  • the signal generating circuit 13 may be used to receive the detection signal output from the drain terminals of the plurality of MOS transistors, and generate a target signal based on the detection signal. That is, the drain terminals of the plurality of MOS transistors can be connected to the signal generating circuit 13 respectively through the plurality of switches; for example, the drain terminals of the plurality of MOS transistors are respectively connected to one end of the plurality of switches, the The other ends of the switches are respectively connected to the input ends of the signal generating circuit.
  • the signal generating circuit 13 is configured to perform according to the voltage value of the output terminal of the target switch The change of, generates and outputs a target signal, which is used to indicate whether a glitch signal appears in the power supply voltage or the ground voltage.
  • the glitch signal detection circuit 10 can detect the signals based on different threshold voltages through the detection unit array 11 and the switch array 12 Whether a glitch signal appears on the power supply voltage and whether a glitch signal appears on the ground voltage. That is, MOS transistors with different threshold voltages can detect glitch signals of a specific amplitude, thereby improving the applicability and sensitivity of the glitch signal detection circuit 10.
  • the MOS transistors with different threshold voltages in the detection unit array 11 share the sampling voltage output by the voltage sampling module 15, which can reduce device overhead and chip area, thereby reducing costs; moreover, the glitch signal detection circuit 10 also Compatible with digital (Complementary Metal-Oxide-Semiconductor Transistor, CMOS) process, which can enhance the portability of the glitch signal detection circuit.
  • CMOS Complementary Metal-Oxide-Semiconductor Transistor
  • the glitch signal detection circuit 10 can not only detect glitches on the power supply voltage or the ground voltage, but also has the advantages of strong applicability, high sensitivity, low cost, and strong portability.
  • FIG. 2 is another schematic structural diagram of the glitch signal detection circuit 10 shown in FIG. 1.
  • the detection unit array 11 may include a positive direction burr detection array 14 and/or a negative direction burr detection array 16, wherein the voltage sampling module 15 is used to obtain the sampling voltage, and the sampling The voltage is output to the positive direction burr detection array 14 and the negative direction burr detection array 16 respectively.
  • the positive-direction burr detection array 14 and the negative-direction burr detection array 16 share the sampling voltage output by the voltage sampling module 15, so as to reduce device overhead and chip area, thereby reducing costs.
  • the positive direction burr detection array 14 may include a plurality of first MOS tubes; the gate terminal of each first MOS tube of the plurality of first MOS tubes is connected to the sampler The source terminal of each first MOS transistor of the plurality of first MOS transistors is connected to the power supply voltage. That is, the first ends of the multiple MOS transistors mentioned above include the gate ends of the multiple first MOS transistors, and the second ends of the multiple MOS transistors include the source ends of the multiple first MOS transistors. . In other words, the first terminal of the first MOS tube is the gate terminal of the first MOS tube, and the second terminal of the first MOS tube is the source terminal of the first MOS tube.
  • FIG. 3 is a schematic circuit diagram of the positive burr detection array 14 shown in FIG. 2.
  • the positive direction burr detection array 14 may include a first PMOS tube 141, a second PMOS tube 142 and a third PMOS tube 143.
  • the sampling voltage VDD_C is respectively connected to the gate terminal of the first PMOS tube 141, the gate terminal of the second PMOS tube 142, and the gate terminal of the third PMOS tube 143; the power supply voltage VDD is respectively connected to the first PMOS tube 141 The source terminal of the second PMOS transistor 142 and the source terminal of the third PMOS transistor 143.
  • the switch array 12 is respectively connected to the drain terminal P1 of the first PMOS tube 141, the drain terminal P2 of the second PMOS tube 142 and the drain terminal P3 of the third PMOS tube 143.
  • the switch corresponding to the first PMOS transistor 141, the switch corresponding to the second PMOS transistor 142, and the switch corresponding to the third PMOS transistor 143 in the switch array 12 can be turned on or off to control the signal generating circuit 13 to receive A detection signal output from the drain terminal of a MOS tube with a specific threshold voltage.
  • the switch corresponding to the first PMOS tube 141 can be turned on, and the switch corresponding to the second PMOS tube 142 and the switch corresponding to the third PMOS tube 143 can be turned off, so that the signal generating circuit 13 receives the drain of the first PMOS tube 141.
  • the target signal is generated based on the detection signal P1 output from the drain terminal P1 of the first PMOS tube 141 (ie, the change in the drain terminal voltage of the first PMOS tube 141).
  • the power supply voltage VDD when the power supply voltage VDD is attacked by a glitch in the positive direction, that is, when a glitch signal in the positive direction appears on the power supply voltage VDD, the power supply voltage VDD is greater than the sampling voltage VDD_C; the difference between the power supply voltage VDD and the sampling voltage VDD_C When the difference is greater than the threshold voltage of the first PMOS tube 141, the first PMOS tube 141 is turned on, the drain voltage of the first PMOS tube 141 rises, and the signal generating circuit 13 can pass through the first PMOS tube The change of the drain terminal voltage of 141 generates the target signal.
  • the local voltage is attacked by a glitch in the negative direction, that is, when a glitch signal in the negative direction appears on the local voltage, due to the capacitive coupling effect of the capacitor in the voltage sampling module 15, the gate terminal voltage of the first PMOS tube 141 (that is, the sampling When the voltage VDD_C) drops, the source voltage VDD remains unchanged, and the difference between the power supply voltage VDD and the sampling voltage VDD_C is greater than the threshold voltage of the first PMOS transistor 141, the first PMOS transistor 141 is turned on, and the first PMOS transistor The drain terminal voltage of 141 rises, and the signal generating circuit 13 can generate the target signal through the change of the drain terminal voltage of the first PMOS transistor 141.
  • the negative direction burr detection array 16 may include a plurality of third MOS tubes; the source end of each third MOS tube of the plurality of third MOS tubes is connected to the sampler
  • the gate terminal of each third MOS transistor of the plurality of third MOS transistors is connected to the power supply voltage. That is, the first ends of the multiple MOS transistors mentioned above include the source ends of the multiple third MOS transistors, and the second ends of the multiple MOS transistors include the gate ends of the multiple third MOS transistors. .
  • the first end of the third MOS transistor is the source end of the third MOS transistor, and the second end of the third MOS transistor is the gate end of the third MOS transistor.
  • FIG. 4 is a schematic circuit diagram of the negative direction burr detection array 16 shown in FIG. 2.
  • the negative direction burr detection array 16 may include a first NMOS tube 161, a second NMOS tube 162 and a third NMOS tube 163.
  • the power supply voltage VDD is respectively connected to the gate terminal of the first NMOS tube 161, the gate terminal of the second NMOS tube 162, and the gate terminal of the third NMOS tube 163; the sampling voltage VDD_C is respectively connected to the first NMOS tube 161 The source terminal of the second NMOS transistor 162 and the source terminal of the third NMOS transistor 163.
  • the switch array 12 is respectively connected to the drain terminal N1 of the first NMOS tube 161, the drain terminal N2 of the second NMOS tube 162, and the drain terminal N3 of the third NMOS tube 163.
  • the switch corresponding to the first NMOS tube 161, the switch corresponding to the second NMOS tube 162, and the switch corresponding to the third NMOS tube 163 in the switch array 12 can be turned on or off to control the signal generating circuit to receive a specific Threshold voltage detection signal output from the drain terminal of the MOS tube.
  • the switch corresponding to the first NMOS tube 161 can be turned on, and the switch corresponding to the second NMOS tube 162 and the switch corresponding to the third NMOS tube 163 can be turned off, so that the signal generating circuit 13 receives the drain of the first NMOS tube 161.
  • the target signal is generated based on the detection signal N1 output from the drain terminal N1 of the first NMOS transistor 161 (that is, the change in the drain terminal voltage of the first NMOS transistor 161).
  • the sampling voltage VDD_C is greater than the power supply voltage VDD; the sampling voltage VDD_C is compared with the power supply voltage
  • the difference of VDD is greater than the threshold voltage of the first NMOS transistor 161
  • the first NMOS transistor 161 is turned on, the drain voltage of the first NMOS transistor 161 rises, and the signal generating circuit 13 can pass through the first NMOS transistor 161.
  • the change of the drain terminal voltage of the NMOS transistor 161 generates the target signal.
  • the local voltage is attacked by a glitch in the positive direction, that is, when a glitch signal in the positive direction appears on the local voltage, through the capacitive coupling effect of the capacitor in the voltage sampling module 15, the source terminal voltage of the first NMOS tube 161 (that is, the sampling When the voltage VDD_C) rises, the gate terminal voltage VDD remains unchanged, and the difference between the sampling voltage VDD_C and the power supply voltage VDD is greater than the threshold voltage of the first NMOS transistor 161, the first NMOS transistor 161 is turned on, and the first NMOS transistor The drain terminal voltage of 161 rises, the signal generation circuit 13 can generate the target signal through the change in the drain terminal voltage of the MOS transistors in the negative direction burr detection array 16, and the signal generation circuit 13 can pass the first The change of the drain terminal voltage of an NMOS transistor 161 generates the target signal.
  • the switch array 12 may include multiple second MOS transistors; the multiple second MOS transistors are MOS transistors corresponding to the MOS transistors in the forward burr detection array 14, and The path between the drain terminal of the MOS transistor in the positive direction burr detection array 14 and the signal generating circuit 13 is turned on or off.
  • the source terminals of the plurality of second MOS transistors may be respectively connected to the drain terminals of the plurality of first MOS transistors in the positive burr detection array 14, and each of the plurality of second MOS transistors
  • the drain terminals of the two MOS transistors can be connected to the signal generating circuit 13;
  • the gate terminals of the target MOS transistors among the plurality of second MOS transistors can be used to receive the first control signal (for example, the ground voltage);
  • the gate terminals of the second MOS transistors other than the target MOS transistor can be used to receive a second control signal (for example, the power supply voltage VDD).
  • FIG. 5 is a schematic circuit diagram of the switch array shown in FIG. 2.
  • the switch array 12 may include a MOS tube 12-p1 corresponding to the first PMOS tube 141, a MOS tube 12-p2 corresponding to the second PMOS tube 142, and the third PMOS tube
  • the tube 143 corresponds to the MOS tube 12-p3.
  • the source terminal of the MOS tube 12-p1 is connected to the drain terminal of the first PMOS tube 141, and the gate terminal of the MOS tube 12-p1 is used to receive the control signal Sel-p1 If the MOS tube 12-p1 is not a target MOS tube (that is, the glitch signal detection circuit does not detect the glitch signal through the first PMOS tube 141), the gate terminal of the MOS tube 12-p1 is used to receive power Voltage VDD to disconnect the MOS transistor 12-p1. If the MOS transistor 12-p1 is a target MOS transistor, the gate terminal of the MOS transistor 12-p1 is used to receive the ground voltage to turn on the MOS Tube 12-p1.
  • the source terminal voltage of the MOS tube 12-p1 is the power supply voltage VDD. If the gate terminal of the MOS tube 12-p1 is connected to the power supply voltage VDD, the MOS tube 12-p1 is disconnected, that is, the drain terminal of the first PMOS tube 141 and the signal generating circuit 13 are in a disconnected state, The glitch signal detection circuit 10 does not detect glitch signals through the first PMOS tube 141; if the gate terminal of the MOS tube 12-p1 is connected to the ground voltage, the MOS tube 12-p1 is turned on, that is, the The drain terminal of a PMOS transistor 141 is in a conductive state with the signal generating circuit 13, and the glitch signal detection circuit 10 detects the glitch signal through the first PMOS transistor 141.
  • the switch array 12 may further include a plurality of fourth MOS tubes; the plurality of fourth MOS tubes are MOS tubes corresponding to the MOS tubes in the negative direction burr detection array 16, and It is used to control the drain terminal of the MOS tube in the negative direction burr detection array 16 to be turned on or off from the signal generating circuit 13.
  • the source terminals of the plurality of fourth MOS transistors may be respectively connected to the drain terminals of the plurality of third MOS transistors in the negative direction burr detection array 16, each of the plurality of fourth MOS transistors
  • the drain terminal of the four MOS transistors can be connected to the signal generating circuit 13; the gate terminal of the target MOS transistor among the plurality of fourth MOS transistors can be used to receive a third control signal (for example, the ground voltage);
  • the gate terminals of the MOS transistors other than the target MOS transistor among the fourth MOS transistors can be used to receive a fourth control signal (for example, the power supply voltage VDD or the sampling voltage VDD-C).
  • the switch array 12 may include MOS tubes 12-n11 corresponding to the first NMOS tube 161, MOS tubes 12-n12 corresponding to the second NMOS tube 162, and MOS tubes corresponding to the third NMOS tube 163. 12-n1n.
  • the source terminal of the MOS tube 12-n11 is connected to the drain terminal of the first PMOS tube 161, and the gate terminal of the MOS tube 12-n11 is used to receive the control signal Sel-n1 If the MOS transistor 12-n11 is not the target MOS transistor (that is, the glitch signal detection circuit does not detect the glitch signal through the first NMOS transistor 161), the control signal Sel-n1 is used to control the MOS transistor 12-n11 is turned off. If the MOS transistor 12-n11 is a target MOS transistor, the control signal Sel-n1 is used to control the MOS transistor 12-n11 to turn on.
  • the source terminal voltage of the MOS tube 12-n11 is the sampling voltage VDD-C; if the MOS tube 12- The gate terminal of n11 is connected to the sampling voltage VDD-C, the MOS transistors 12-n11 are disconnected, that is, the drain terminal of the first NMOS transistor 161 is in a disconnected state from the path of the signal generating circuit 13, and the glitch The signal detection circuit 10 does not detect a glitch signal through the first NMOS transistor 161; if the gate terminal of the MOS transistor 12-n11 is connected to the ground voltage, the MOS transistor 12-n11 is turned on, that is, the first NMOS transistor The path between the drain terminal of 161 and the signal generating circuit 13 is in a conductive state, and the glitch signal detection circuit 10 detects the glitch signal through the first NMOS transistor 161.
  • the gate terminal of the MOS transistor 12-n11 can also be connected to the power supply voltage VDD.
  • the PMOS tube when VSG-VTH>0, the PMOS tube is turned on; when VSG-VTH ⁇ 0, the PMOS tube is turned off. Therefore, for the switch responsible for turning off the MOS transistor path in the positive direction glitch detection array 14, the source terminal voltage is VDD and the gate terminal voltage is also VDD, and the path can be guaranteed to be closed; and for the switch responsible for turning off the negative direction glitch detection array 16
  • the source terminal voltage is the sampling voltage VDD_C
  • the gate terminal voltage is VDD, the switch cannot be completely turned off, and the path can still be turned on.
  • the switch array may further include a plurality of fifth MOS transistors, which are used to ensure that the non-target MOS transistors of the plurality of fourth MOS transistors are in an off state.
  • each fifth MOS transistor of the plurality of fifth MOS transistors may be used to receive the power supply voltage
  • the drain terminal of the plurality of fifth MOS transistors may be respectively connected to the plurality of fourth MOS transistors.
  • the source terminal of the MOS tube; the gate terminal of the target MOS tube among the plurality of fifth MOS tubes can be used to receive the power supply voltage; the gate terminal of the MOS tube except the target MOS tube among the plurality of fifth MOS tubes
  • the terminal can be used to receive the ground voltage.
  • the plurality of fifth MOS tubes may include MOS tubes 12-n21 corresponding to MOS tubes 12-n11, MOS tubes 12-n22 corresponding to MOS tubes 12-n12, and MOS tubes 12-n1n corresponding to The MOS tube 12-n2n.
  • the source terminal of the MOS transistor 12-n21 is connected to the power supply voltage VDD, and the gate terminal of the MOS transistor 12-n21 is used to receive the control signal Sel-n1.
  • the tube 12-n21 is not the target MOS tube (that is, the glitch signal detection circuit does not detect the glitch signal through the first NMOS tube 161), then the control signal Sel-n1 is used to control the MOS tube 12-n21 to turn on , And then control the MOS transistor 12-n11 to turn off through the power supply voltage VDD output from the drain terminal. If the MOS transistor 12-n21 is the target MOS transistor, the control signal Sel-n1 is used to control the MOS transistor 12-n21. Turn off, and then turn on the MOS transistor 12-n11 through the drain terminal voltage of the first NMOS transistor 161.
  • the source terminal voltage of the MOS tube 12-n11 is the sampling voltage VDD-C; if the MOS tube 12- The gate terminal of n11 is connected to the power supply voltage VDD and the gate terminal of the MOS transistor 12-n21 is connected to the ground voltage, the MOS transistor 12-n11 is disconnected, that is, the drain terminal of the first NMOS transistor 161 is connected to The path of the signal generating circuit 13 is in an open state, and the glitch signal detection circuit 10 does not detect the glitch signal through the first NMOS tube 161; if the gate terminal of the MOS tube 12-n11 is connected to the ground voltage and the The gate terminal of the MOS transistor 12-n21 is connected to the power supply voltage, the MOS transistor 12-n11 is turned on, that is, the drain terminal of the first NMOS transistor 161 and the path of the signal generating circuit 13 are in a conductive state, so The glitch signal detection circuit 10 can detect glitch
  • FIG. 6 and 7 are schematic circuit diagrams of the voltage sampling module shown in FIG. 1.
  • the voltage sampling module 15 may include a first capacitor 154 and a sixth MOS transistor 153.
  • the gate terminal of the sixth MOS transistor 153 is connected to the ground voltage through the first capacitor 154, and the source terminal of the sixth MOS transistor 153 is connected to the ground voltage; the power supply voltage and the ground voltage
  • the voltage at the drain terminal of the sixth MOS tube 153 is the ground voltage
  • the voltage at the gate terminal of the sixth MOS tube 153 is the sampling voltage sampled by the first capacitor 154 .
  • the voltage of the drain of the sixth MOS transistor 153 is reset to prevent the drain terminal of the sixth MOS transistor 153 from being in a high impedance floating state. Therefore, when no glitch signal appears on the power supply voltage VDD and no glitch signal appears on the ground voltage, the voltage value of the drain terminal of the sixth MOS transistor 153 is the ground voltage, and the sixth MOS The voltage value of the gate terminal of the tube 153 is the power supply voltage VDD sampled by the first capacitor 154, that is, the sample voltage VDD-C.
  • the voltage sampling module 15 may further include a seventh MOS transistor 156, an eighth MOS transistor 155 and a first inverter 157.
  • the gate terminal of the sixth MOS tube 153 is connected to the power supply voltage VDD through the seventh MOS tube 156, and the drain terminal of the sixth MOS tube 153 is connected to the power supply voltage VDD through the eighth MOS tube 155. Ground voltage, the drain terminal of the sixth MOS transistor 153 is connected to the gate terminal of the sixth MOS transistor 153 through the first inverter 157.
  • control signal used to control the seventh MOS transistor 156 and the control signal used to control the eighth MOS transistor 155 may be a set of reverse signals.
  • the gate terminal of the eighth MOS transistor 155 is used to receive the first signal R
  • the gate terminal of the seventh MOS transistor 156 is used to receive the reverse signal R_b of the first signal R.
  • the seventh MOS transistor 156 and the eighth MOS transistor 155 are both turned on, that is, the power supply voltage charges the first capacitor 154 through the seventh MOS transistor 156 , So that the first voltage of the gate terminal N of the sixth MOS transistor 153 is "1", and the drain terminal M of the sixth MOS transistor 153 is connected to the ground through the eighth MOS transistor 155, so that the sixth The second voltage of the drain terminal M of the MOS transistor 153 is "0".
  • the seventh MOS transistor 156 and the eighth MOS transistor 155 are both disconnected, so that the first voltage of the gate terminal N of the sixth MOS transistor 153 is maintained at "1".
  • the second voltage of the drain terminal M of the sixth MOS transistor 153 is maintained at "0".
  • the gate terminal N of the sixth MOS transistor 153 can be pulled up to VDD, and the drain terminal M of the sixth MOS transistor 153 can be pulled down to GND. .
  • the first inverter 157 By controlling the first inverter 157, it is possible to ensure that the voltage of the drain terminal of the sixth MOS transistor 153 is at “0”, thereby ensuring the performance of the glitch signal detection circuit 10. Even if the voltage of the drain terminal of the sixth MOS transistor 153 increases, the first inverter 157 can ensure that the voltage of the drain terminal of the sixth MOS transistor 153 is restored to "0". In addition, through the first inverter 157, the leakage of the first capacitor 154 can also be avoided, thereby ensuring that the voltage value of the capacitor remains at the power supply voltage. Therefore, the glitch signal detection circuit can detect in real time whether the power supply voltage or the ground voltage is attacked by a glitch.
  • the sixth MOS transistor 153, the MOS transistor in the detection unit array 11, and the first inverter 157 can be used to form a latch.
  • the seventh MOS transistor 156 and the eighth MOS transistor 155 are enabling circuits for the latch.
  • the sixth MOS tube 153, the MOS tube in the detection unit array 11, the first inverter 157, the seventh MOS tube 156, and the eighth MOS tube 155 may form a band Controllable latch.
  • the voltage sampling module formed by the capacitor and the MOS tube can not only realize the sampling of the power supply voltage, but also can form a latch with the MOS tube in the detection unit array 11, which can directly use the existing latch to prepare the burr of this application
  • the signal detection circuit further improves the applicability.
  • the voltage sampling module 15 may include a resistor 151 and a second capacitor 152; one end of the resistor 151 is connected to the power supply voltage, and the other end of the resistor 151 passes through the second capacitor 152 is connected to the ground voltage.
  • FIG. 8 is a schematic structural diagram of the signal generating circuit 13 according to an embodiment of the present application.
  • the signal generating circuit 13 may be a D flip-flop.
  • the reset (RESET) terminal B of the D flip-flop is connected to the reset signal W, for example, the reset signal W may be the above-mentioned first signal R; the D terminal of the D flip-flop is connected to VDD; The detection terminal A of the D flip-flop is connected to the output terminal of the switch array 12 for receiving a detection signal, and the output terminal Q of the D flip-flop outputs a target signal (that is, an ALARM signal).
  • the signal generating circuit 13 may also be other devices, such as a comparator.
  • the target signal may also be a differential signal.
  • MOS tube may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • NMOSFET N-type MOS tube
  • PMOSFET P-type MOS tube
  • the gate terminal of the "N-type” MOS tube (the MOS tube with the substrate PN junction pointing inward or the MOS tube with current flowing out) is connected to the high voltage It is usually turned on and turned off when connected to a low level; when the gate terminal of a "P-type” MOS tube (a MOS tube with a PN junction pointing outward or a MOS tube through which current flows) is turned off when it is connected to a high level, it is turned on when connected to a low level.
  • FIGS. 1 to 8 are only examples of the present application, and should not be construed as limiting the present application.
  • the glitch signal detection circuit 10 may also include a threshold judgment module.
  • the output terminal of the switch array 12 is connected to the signal generation circuit 13 through the threshold judgment module, and the threshold judgment module is used to amplify the signal output by the switch array 12 and send the amplified signal to The signal generating circuit 13.
  • the threshold judgment module may include a second inverter and a third inverter, the output terminal of the switch array 12 is connected to one end of the third inverter through the second inverter, and the third inverter The other end of the inverter is connected to the signal generating circuit 13.
  • the switching threshold of the second inverter may be smaller than the switching threshold of the third inverter.
  • the flip threshold of the second inverter is 0.3
  • the flip threshold of the third inverter is 0.8
  • the sensitivity of the glitch signal detection circuit 10 is improved by reducing the flip threshold of the second inverter
  • the flip threshold of the third inverter is 0.8
  • the foregoing 0.3 and 0.8 are only examples, and this application does not specifically limit the switching threshold of the second inverter and the switching threshold of the third inverter.
  • the threshold judgment module With the cooperation of the threshold judgment module, glitch signals of lower amplitude can be detected, which further improves the sensitivity of the glitch signal detection circuit 10.
  • the number of MOS transistors in the switch array 12 and the detection unit array 11 in the drawings is only an example, and should not be construed as a limitation of the application. Those skilled in the art can set up multiple MOS transistors according to actual needs.
  • the present application also provides a security chip, which may include the glitch signal detection circuit described above.
  • the security chip may be a fingerprint sensor chip or a processor chip or the like.
  • the application also provides an electronic device, which may include the security chip described above.
  • portable or mobile computing devices such as smart phones, notebook computers, tablet computers, and gaming devices, as well as other electronic devices such as electronic databases, automobiles, and bank automated teller machines (ATM).
  • ATM bank automated teller machines
  • the embodiments of the present application are not limited thereto.
  • circuits, branches, and modules may be implemented in other ways.
  • the branches described above are illustrative.
  • the division of the modules is only a logical function division, and there may be other divisions in actual implementation.
  • multiple modules can be combined or integrated into one branch. Road, or some features can be ignored or not implemented.
  • the integrated module is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

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Abstract

提供了一种毛刺信号检测电路、安全芯片和电子设备，所述毛刺信号检测电路包括：电压采样模块，用于获取并输出电源电压的采样电压；检测单元阵列，包括阈值电压不同的多个金属氧化物半导体MOS管，所述多个MOS管的第一端连接至所述采样电压，所述多个MOS管的第二端连接至电源电压；开关阵列，包括所述多个MOS管对应的多个开关；信号生成电路，所述多个MOS管的漏端分别通过所述多个开关连接至所述信号生成电路。所述毛刺信号检测电路不仅能够检测电源电压或地电压上的毛刺，并且，所述毛刺信号检测电路具有可应用性强、灵敏度高、成本低以及可移植性强等优点。

Description

毛刺信号检测电路、安全芯片和电子设备 技术领域
本申请实施例涉及电子领域，并且更具体地，涉及毛刺信号检测电路、安全芯片和电子设备。
背景技术
安全芯片可以用于实现用户身份识别与关键数据存储等功能，其被广泛应用于金融领域，是攻击者的重点攻击对象。
攻击者可以通过故障攻击(如毛刺(power glitch)攻击)，使芯片工作在非正常状态下，从而导致芯片发生错误行为；此时，攻击者可以利用故障分析技术轻易获取安全芯片中的机密数据。通常情况下，可以通过毛刺信号检测电路检测电源电压(或地电压)上的毛刺，并及时给出报警信号，从而增加芯片系统的鲁棒性和安全性。
但是，现有的毛刺信号检测电路仅能够实现简单的毛刺信号检测功能，并不能针对固定幅值的毛刺信号检测，其可应用性低。此外，现有的毛刺信号检测电路不能调整毛刺信号的检测范围，其灵敏度较低。
发明内容
本申请实施例提供一种毛刺信号检测电路、安全芯片和电子设备，能够提高毛刺信号检测电路的可应用性和灵敏度。
第一方面，提供了一种毛刺信号检测电路，包括：
电压采样模块，用于获取并输出电源电压的采样电压；
检测单元阵列，包括阈值电压不同的多个金属氧化物半导体MOS管，所述多个MOS管的第一端连接至所述采样电压，所述多个MOS管的第二端连接至电源电压；
开关阵列，包括所述多个MOS管对应的多个开关；
信号生成电路，所述多个MOS管的漏端分别通过所述多个开关连接至所述信号生成电路；
其中，导通所述多个开关中的目标开关，并断开所述多个开关中除所述目标开关之外的开关时，所述信号生成电路用于根据所述目标开关的输出端 的电压值的变化生成并输出目标信号，所述目标信号用于指示电源电压或地电压是否出现毛刺信号。
由于所述检测单元阵列包括的多个MOS管具有不同的阈值电压，因此，所述毛刺信号检测电路可以通过所述检测单元阵列和所述开关阵列，基于不同的阈值电压检测所述电源电压上是否出现毛刺信号以及所述地电压上是否出现毛刺信号。即通过选择不同的MOS管可对特定幅度的毛刺信号进行检测，进而提高毛刺信号检测电路的可应用性和灵敏度。
此外，所述检测单元阵列中的具有不同阈值电压的MOS管通过共用所述电压采样模块输出的采样电压，能够减少器件开销和芯片面积，进而降低成本；而且，毛刺信号检测电路还可以兼容数字(Complementary Metal-Oxide-Semiconductor Transistor，CMOS)工艺，能够增强毛刺信号检测电路的可移植性。
综上所述，毛刺信号检测电路不仅能够检测电源电压或地电压上的毛刺，并且所述毛刺信号检测电路具有可应用性强、灵敏度高、成本低以及可移植性强等优点。
在一些可能的实现方式中，所述多个MOS管包括：
多个第一MOS管；
所述第一MOS管的第一端为所述第一MOS管的栅端，所述第一MOS管的第二端为所述第一MOS管的源端。
在一些可能的实现方式中，所述开关阵列包括：
多个第二MOS管；
所述多个第二MOS管的源端分别连接至所述多个第一MOS管的漏端，所述多个第二MOS管的漏端连接至所述信号生成电路；
所述多个第二MOS管中的目标MOS管的栅端用于接收所述地电压；
所述多个第二MOS管中除目标MOS管之外的MOS管的栅端用于接收所述电源电压。
在一些可能的实现方式中，所述多个MOS管包括：
多个第三MOS管；
所述第三MOS管的第一端为所述第三MOS管的源端，所述第三MOS管的第二端为所述第三MOS管的栅端。
在一些可能的实现方式中，所述开关阵列包括：
多个第四MOS管；
所述多个第四MOS管的源端分别连接至所述多个第三MOS管的漏端，所述多个第四MOS管的漏端连接至所述信号生成电路；
所述多个第四MOS管中的目标MOS管的栅端用于接收所述地电压；
所述多个第四MOS管中除目标MOS管之外的MOS管的栅端用于接收所述电源电压或所述采样电压。
在一些可能的实现方式中，所述开关阵列还包括：
多个第五MOS管；
所述多个第五MOS管的源端用于接收所述电源电压，所述多个第五MOS管的漏端分别连接至所述多个第四MOS管的源端；
所述多个第五MOS管中的目标MOS管的栅端用于接收所述电源电压；
所述多个第五MOS管中除目标MOS管之外的MOS管的栅端用于接收所述地电压。
在一些可能的实现方式中，所述电压采样模块包括：
第一电容器和第六MOS管；
所述第六MOS管的栅端通过所述第一电容器连接至所述地电压，所述第六MOS管的源端连接至所述地电压。
在一些可能的实现方式中，所述电压采样模块还包括：
第七MOS管、第八MOS管以及第一反相器；
所述第六MOS管的栅端通过所述第七MOS管连接至所述电源电压，所述第六MOS管的漏端通过所述第八MOS管连接至所述地电压，所述第六MOS管的漏端通过所述第一反相器连接至所述第六MOS管的栅端。
在一些可能的实现方式中，所述电压采样模块包括：
电阻器和第二电容器；
所述电阻器的一端连接至所述电源电压，所述电阻器的另一端通过所述第二电容器连接至所述地电压。
在一些可能的实现方式中，所述信号生成电路为D触发器。
第二方面，提供了一种安全芯片，包括第一方面以及第一方面中任一可能的实现方式中所述的毛刺信号检测电路。
第三方面，提供了一种电子设备，包括：
第二方面所述的安全芯片，以及处理器，所述处理器用于接收所述安全 芯片发送的目标信号，所述目标信号用于指示电源电压或地电压是否出现毛刺信号。
附图说明
图1是本申请实施例的毛刺信号检测电路的示意性结构图。
图2是图1所示的毛刺信号检测电路的另一示意性结构图。
图3是图1所示的毛刺信号检测电路中的正方向毛刺检测阵列的示意性电路图。
图4是图1所示的毛刺信号检测电路中的负方向毛刺检测阵列的示意性电路图。
图5是本申请实施例的毛刺信号检测电路中的开关阵列的示意性电路图。
图6和图7是本申请实施例的毛刺信号检测电路中的电压采样模块的示意性电路图。
图8是本申请实施例的毛刺信号检测电路中的信号生成电路的示意性结构图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
电源毛刺(power glitch)攻击通过快速改变输入到芯片的电源电压(或地电压)，使得芯片的某些电路单元受到影响；继而引起一个或者多个电路单元进入错误状态，使得芯片的处理器跳过或者根据错误状态实施错误操作；进而暴露了芯片内隐藏的安全信息。
其中，毛刺信号可以是电路的输入波形中包括有规律或没有规律的脉冲信号或尖峰信号。例如，电源电压上出现正方向的毛刺信号时的电压值等于所述电源电压上未出现毛刺信号时的电压值加所述毛刺信号的电压值。又例如，电源电压上出现负正方向的毛刺信号时的电压值等于所述电源电压上未出现毛刺信号时的电压值减去所述毛刺信号的电压值。
类似地，地电压上也可以出现正方向的毛刺信号和负方向的毛刺信号。
针对不稳定的电源电压，其也可以认为是稳定的电源电压上叠加有一个毛刺信号后的电压。针对不稳定的地电压，其也可以认为是在稳定的地电压 上叠加一个毛刺信号后的电压。
图1是本申请实施例的毛刺信号检测电路10的示意性结构图。
请参见图1，所述毛刺信号检测电路10可以包括电压采样模块15、检测单元阵列11、开关阵列12以及信号生成电路13。
电压采样模块15用于获取并输出电源电压的采样电压。
检测单元阵列11可包括阈值电压不同的多个金属氧化物半导体(Metal-Oxide Semiconductor，MOS)管，例如所述多个MOS管分别具有不同的阈值电压，所述多个MOS管的第一端连接至所述采样电压，所述多个MOS管的第二端连接至电源电压。
开关阵列12可包括所述多个MOS管对应的多个开关，所述多个开关可用于导通或断开所述检测单元阵列11中的多个MOS管与所述信号生成电路13之间的通路，例如，导通检测单元阵列11中具有特定阈值电压的MOS管与所述信号生成电路13之间的通路，并断开所述检测单元阵列中其他MOS管和所述信号生成电路13之间的通路，以使得所述信号生成电路13能够接收到具有特定阈值电压的MOS管的漏端传输的检测信号。
信号生成电路13可用于接收所述多个MOS管的漏端输出的检测信号，并基于检测信号生成目标信号。即所述多个MOS管的漏端可分别通过所述多个开关连接至所述信号生成电路13；例如所述多个MOS管的漏端分别连接至所述多个开关的一端，所述多个开关的另一端分别连接至所述信号生成电路的输入端。
导通所述开关阵列12中的目标开关，并断开所述开关阵列12中除所述目标开关之外的开关时，所述信号生成电路13用于根据所述目标开关的输出端的电压值的变化生成并输出目标信号，所述目标信号用于指示所述电源电压或地电压是否出现毛刺信号。
由于所述检测单元阵列11包括的多个MOS管具有不同的阈值电压，因此，所述毛刺信号检测电路10可以通过所述检测单元阵列11和所述开关阵列12，基于不同的阈值电压检测所述电源电压上是否出现毛刺信号以及所述地电压上是否出现毛刺信号。即通过具有不同的阈值电压的MOS管，可对特定幅度的毛刺信号进行检测，进而提高毛刺信号检测电路10的可应用性和灵敏度。
此外，所述检测单元阵列11中的具有不同阈值电压的MOS管通过共用 所述电压采样模块15输出的采样电压，能够减少器件开销和芯片面积，进而降低成本；而且，毛刺信号检测电路10还可以兼容数字(Complementary Metal-Oxide-Semiconductor Transistor，CMOS)工艺，能够增强毛刺信号检测电路的可移植性。
综上所述，毛刺信号检测电路10不仅能够检测电源电压或地电压上的毛刺，并且所述毛刺信号检测电路具有可应用性强、灵敏度高、成本低以及可移植性强等优点。
图2是图1所示的毛刺信号检测电路10的另一示意性结构图。
请参见图2，所述检测单元阵列11可包括正方向毛刺检测阵列14和/或负方向毛刺检测阵列16，其中，所述电压采样模块15用于获取所述采样电压，并将所述采样电压分别输出至正方向毛刺检测阵列14和负方向毛刺检测阵列16。换句话说，正方向毛刺检测阵列14和负方向毛刺检测阵列16通过共用所述电压采样模块15输出的采样电压，能够减少器件开销和芯片面积，进而降低成本。
在本申请的一些实施例中，所述正方向毛刺检测阵列14可包括多个第一MOS管；所述多个第一MOS管中的每个第一MOS管的栅端连接至所述采样电压，所述多个第一MOS管中的每个第一MOS管的源端连接至电源电压。即上文涉及的所述多个MOS管的第一端包括所述多个第一MOS管的栅端，所述多个MOS管的第二端包括所述多个第一MOS管的源端。或者说，所述第一MOS管的第一端为所述第一MOS管的栅端，所述第一MOS管的第二端为所述第一MOS管的源端。
图3是图2所示的正方向毛刺检测阵列14的示意性电路图。
请参见图3，所述正方向毛刺检测阵列14可包括第一PMOS管141、第二PMOS管142和第三PMOS管143。
其中，所述采样电压VDD_C分别连接至第一PMOS管141的栅端、第二PMOS管142的栅端和第三PMOS管143的栅端；所述电源电压VDD分别连接至第一PMOS管141的源端、第二PMOS管142的源端和第三PMOS管143的源端。所述开关阵列12分别连接至所述第一PMOS管141的漏端P1、所述第二PMOS管142的漏端P2以及所述第三PMOS管143的漏端P3。
进一步地，可通过导通或断开开关阵列12中的第一PMOS管141对应 的开关、第二PMOS管142对应的开关和第三PMOS管143对应的开关，来控制信号生成电路13接收具有特定阈值电压的MOS管的漏端输出的检测信号。例如，可导通第一PMOS管141对应的开关，并断开第二PMOS管142对应的开关和第三PMOS管143对应的开关，以便所述信号生成电路13接收第一PMOS管141的漏端输出的检测信号P1，并基于第一PMOS管141的漏端P1输出的检测信号(即第一PMOS管141的漏端电压的变化)生成目标信号。
以第一PMOS管141为例，当电源电压VDD受到正方向的毛刺攻击，即当电源电压VDD上出现正方向的毛刺信号时，电源电压VDD大于采样电压VDD_C；电源电压VDD与采样电压VDD_C的差值大于第一PMOS管141的阈值电压时，所述第一PMOS管141导通，所述第一PMOS管141的漏端电压上升，所述信号生成电路13可通过所述第一PMOS管141的漏端电压的变化生成所述目标信号。当地电压受到负方向的毛刺攻击，即当地电压上出现负方向的毛刺信号时，由于电压采样模块15中的电容器的电容耦合效应，所述第一PMOS管141的栅端电压(即所述采样电压VDD_C)下降，源端电压VDD保持不变，电源电压VDD与采样电压VDD_C的差值大于第一PMOS管141的阈值电压时，所述第一PMOS管141导通，所述第一PMOS管141的漏端电压上升，所述信号生成电路13可通过所述第一PMOS管141的漏端电压的变化生成所述目标信号。
在本申请的一些实施例中，所述负方向毛刺检测阵列16可包括多个第三MOS管；所述多个第三MOS管中的每个第三MOS管的源端连接至所述采样电压，所述多个第三MOS管中的每个第三MOS管的栅端连接至电源电压。即上文涉及的所述多个MOS管的第一端包括所述多个第三MOS管的源端，所述多个MOS管的第二端包括所述多个第三MOS管的栅端。或者说，所述第三MOS管的第一端为所述第三MOS管的源端，所述第三MOS管的第二端为所述第三MOS管的栅端。
图4是图2所示的负方向毛刺检测阵列16的示意性电路图。
请参见图4，所述负方向毛刺检测阵列16可包括第一NMOS管161、第二NMOS管162和第三NMOS管163。
其中，所述电源电压VDD分别连接至第一NMOS管161的栅端、第二NMOS管162的栅端和第三NMOS管163的栅端；所述采样电压VDD_C 分别连接至第一NMOS管161的源端、第二NMOS管162的源端和第三NMOS管163的源端。所述开关阵列12分别连接至所述第一NMOS管161的漏端N1、所述第二NMOS管162的漏端N2以及所述第三NMOS管163的漏端N3。
此时，可通过导通或断开开关阵列12中的第一NMOS管161对应的开关、第二NMOS管162对应的开关和第三NMOS管163对应的开关，来控制信号生成电路接收具有特定阈值电压的MOS管的漏端输出的检测信号。例如，可导通第一NMOS管161对应的开关，并断开第二NMOS管162对应的开关和第三NMOS管163对应的开关，以便所述信号生成电路13接收第一NMOS管161的漏端输出的检测信号N1，并基于第一NMOS管161的漏端N1输出的检测信号(即第一NMOS管161的漏端电压的变化)生成目标信号。
以所述第一NMOS管161为例，当电源电压VDD受到负方向的毛刺攻击，即当电源电压VDD上出现负方向的毛刺信号时，采样电压VDD_C大于电源电压VDD；采样电压VDD_C与电源电压VDD的差值大于第一NMOS管161的阈值电压时，所述第一NMOS管161导通，所述第一NMOS管161的漏端电压上升，所述信号生成电路13可通过所述第一NMOS管161的漏端电压的变化生成所述目标信号。当地电压受到正方向的毛刺攻击，即当地电压上出现正方向的毛刺信号时，通过电压采样模块15中的电容器的电容耦合效应，所述第一NMOS管161的源端电压(即所述采样电压VDD_C)上升，栅端电压VDD保持不变，采样电压VDD_C与电源电压VDD的差值大于第一NMOS管161的阈值电压时，所述第一NMOS管161导通，所述第一NMOS管161的漏端电压上升，所述信号生成电路13可通过所述负方向毛刺检测阵列16中的MOS管的漏端电压的变化生成所述目标信号，所述信号生成电路13可通过所述第一NMOS管161的漏端电压的变化生成所述目标信号。
在本申请的一些实施例中，所述开关阵列12可包括多个第二MOS管；所述多个第二MOS管为所述正方向毛刺检测阵列14中的MOS管对应的MOS管，用于导通或断开所述正方向毛刺检测阵列14中的MOS管的漏端与所述信号生成电路13之间的通路。
例如，所述多个第二MOS管的源端可分别连接至所述正方向毛刺检测 阵列14中的多个第一MOS管的漏端，所述多个第二MOS管中的每个第二MOS管的漏端可连接至所述信号生成电路13；所述多个第二MOS管中的目标MOS管的栅端可用于接收第一控制信号(例如所述地电压)；所述多个第二MOS管中除目标MOS管之外的MOS管的栅端可用于接收第二控制信号(例如所述电源电压VDD)。
图5是图2所示的开关阵列的示意性电路图。
请参见图5，作为示例，所述开关阵列12可包括所述第一PMOS管141对应的MOS管12-p1、所述第二PMOS管142对应的MOS管12-p2以及所述第三PMOS管143对应的MOS管12-p3。
以MOS管12-p1为例，所述MOS管12-p1的源端连接至所述第一PMOS管141的漏端，所述MOS管12-p1的栅端用于接收控制信号Sel-p1，若所述MOS管12-p1不是目标MOS管(即所述毛刺信号检测电路不通过所述第一PMOS管141检测毛刺信号)，则所述MOS管12-p1的栅端用于接收电源电压VDD，以断开所述MOS管12-p1，若所述MOS管12-p1是目标MOS管，则所述MOS管12-p1的栅端用于接收地电压，以导通所述MOS管12-p1。
假设电源电压VDD出现有正方向的毛刺信号或地电压上出现有负方向的毛刺信号，所述MOS管12-p1的源端电压为电源电压VDD。若所述MOS管12-p1的栅端连接至电源电压VDD，所述MOS管12-p1断开，即所述第一PMOS管141的漏端与所述信号生成电路13处于断开状态，所述毛刺信号检测电路10不通过所述第一PMOS管141检测毛刺信号；若所述MOS管12-p1的栅端连接至地电压，所述MOS管12-p1导通，即所述第一PMOS管141的漏端与所述信号生成电路13处于导通状态，所述毛刺信号检测电路10通过所述第一PMOS管141检测毛刺信号。
在本申请的一些实施例中，所述开关阵列12还可包括多个第四MOS管；所述多个第四MOS管为所述负方向毛刺检测阵列16中的MOS管对应的MOS管，用于控制所述负方向毛刺检测阵列16中的MOS管的漏端与所述信号生成电路13导通或断开。
例如，所述多个第四MOS管的源端可分别连接至所述负方向毛刺检测阵列16中的多个第三MOS管的漏端，所述多个第四MOS管中的每个第四MOS管的漏端可连接至所述信号生成电路13；所述多个第四MOS管中的目标MOS管的栅端可用于接收第三控制信号(例如所述地电压)；所述多个 第四MOS管中除目标MOS管之外的MOS管的栅端可用于接收第四控制信号(例如所述电源电压VDD或采样电压VDD-C)。
例如，请继续参见图5，所述开关阵列12可包括第一NMOS管161对应的MOS管12-n11、第二NMOS管162对应的MOS管12-n12和第三NMOS管163对应的MOS管12-n1n。
以MOS管12-n11为例，所述MOS管12-n11的源端连接至所述第一PMOS管161的漏端，所述MOS管12-n11的栅端用于接收控制信号Sel-n1，若所述MOS管12-n11不是目标MOS管(即所述毛刺信号检测电路不通过所述第一NMOS管161检测毛刺信号)，则所述控制信号Sel-n1用于控制所述MOS管12-n11断开，若所述MOS管12-n11是目标MOS管，则所述控制信号Sel-n1用于控制所述MOS管12-n11导通。
假设电源电压VDD上出现有负方向的毛刺信号或地电压上出现有正方向的毛刺信号，即所述MOS管12-n11的源端电压为采样电压VDD-C；若所述MOS管12-n11的栅端连接至采样电压VDD-C，所述MOS管12-n11断开，即所述第一NMOS管161的漏端与所述信号生成电路13的通路处于断开状态，所述毛刺信号检测电路10不通过所述第一NMOS管161检测毛刺信号；若所述MOS管12-n11的栅端连接至地电压，所述MOS管12-n11导通，即所述第一NMOS管161的漏端与所述信号生成电路13的通路处于导通状态，所述毛刺信号检测电路10通过所述第一NMOS管161检测毛刺信号。
当然，所述MOS管12-n11的栅端也可以连接至电源电压VDD。
需要说明的是，对于PMOS管而言，当VSG-VTH>0，PMOS管导通；当VSG-VTH<0时，PMOS管关断。因此，对于负责关断正方向毛刺检测阵列14中MOS管通路的开关而言，源端电压为VDD，栅端电压也为VDD，通路可以保证关闭；而对于负责关断负方向毛刺检测阵列16中MOS管的通路的开关而言，源端电压为采样电压VDD_C,栅端电压为VDD，开关无法完全关断，通路仍能导通。
在本申请的一些实施例中，所述开关阵列还可包括多个第五MOS管，用于保证上述多个第四MOS管中的非目标MOS管处于断开状态。
例如，所述多个第五MOS管中的每个第五MOS管的源端可用于接收所述电源电压，所述多个第五MOS管的漏端可分别连接至所述多个第四 MOS管的源端；所述多个第五MOS管中的目标MOS管的栅端可用于接收所述电源电压；所述多个第五MOS管中除目标MOS管之外的MOS管的栅端可用于接收所述地电压。
例如，请继续参见图5，所述多个第五MOS管可包括MOS管12-n11对应的MOS管12-n21、MOS管12-n12对应的MOS管12-n22和MOS管12-n1n对应的MOS管12-n2n。
以MOS管12-n21为例，所述MOS管12-n21的源端连接至所述电源电压VDD，所述MOS管12-n21的栅端用于接收控制信号Sel-n1，若所述MOS管12-n21不是目标MOS管(即所述毛刺信号检测电路不通过所述第一NMOS管161检测毛刺信号)，则所述控制信号Sel-n1用于控制所述MOS管12-n21导通，进而通过漏端输出的电源电压VDD控制MOS管12-n11断开，若所述MOS管12-n21是目标MOS管，则所述控制信号Sel-n1用于控制所述MOS管12-n21断开，进而通过所述第一NMOS管161的漏端电压导通MOS管12-n11。
假设电源电压VDD上出现有负方向的毛刺信号或地电压上出现有正方向的毛刺信号，即所述MOS管12-n11的源端电压为采样电压VDD-C；若所述MOS管12-n11的栅端连接至所述电源电压VDD且所述MOS管12-n21的栅端连接至地电压，则所述MOS管12-n11断开，即所述第一NMOS管161的漏端与所述信号生成电路13的通路处于断开状态，所述毛刺信号检测电路10不通过所述第一NMOS管161检测毛刺信号；若所述MOS管12-n11的栅端连接至地电压且所述MOS管12-n21的栅端连接至电源电压，所述MOS管12-n11导通，即所述第一NMOS管161的漏端与所述信号生成电路13的通路处于导通状态，所述毛刺信号检测电路10可通过所述第一NMOS管161检测毛刺信号。
图6和图7是图1所示的电压采样模块的示意性电路图。
请参见图6，所述电压采样模块15可包括第一电容器154和第六MOS管153。
其中，所述第六MOS管153的栅端通过所述第一电容器154连接至地电压，所述第六MOS管153的源端连接至地电压；所述电源电压上和所述地电压上均未出现毛刺信号时，所述第六MOS管153的漏端的电压值为所述地电压，所述第六MOS管153的栅端的电压值为所述第一电容器154采 样的所述采样电压。所述第六MOS管153的栅端通过连接至所述电容器154，可以获取所述电容器154采样的不受毛刺信号影响的电源电压，通过将所述第六MOS管153连接至地电压，可以对所述第六MOS管153的漏极的电压进行重置，避免所述第六MOS管153漏端处于高阻悬空状态。由此，可以使得所述电源电压VDD上未出现毛刺信号且所述地电压上未出现毛刺信号时，所述第六MOS管153的漏端的电压值为所述地电压，所述第六MOS管153的栅端的电压值为通过所述第一电容器154采样的电源电压VDD，即采样电压VDD-C。
请继续参见图6，所述电压采样模块15还可包括第七MOS管156、第八MOS管155以及第一反相器157。
其中，所述第六MOS管153的栅端通过所述第七MOS管156连接至所述电源电压VDD，所述第六MOS管153的漏端通过所述第八MOS管155连接至所述地电压，所述第六MOS管153的漏端通过所述第一反相器157连接至所述第六MOS管153的栅端。
进一步地，用于控制所述第七MOS管156的控制信号和用于控制第八MOS管155的控制信号可以是一组反向信号。例如，所述第八MOS管155的栅端用于接收第一信号R，所述第七MOS管156的栅端用于接收第一信号R的反向信号R_b。
例如，所述第一信号R为高电平时，所述第七MOS管156和第八MOS管155均导通，即电源电压通过所述第七MOS管156对所述第一电容器154进行充电，使得所述第六MOS管153的栅端N的第一电压为“1”，且所述第六MOS管153的漏端M通过第八MOS管155连接至地，以使得所述第六MOS管153的漏端M的第二电压为“0”。然后，所述第一信号R为低电平时，所述第七MOS管156和第八MOS管155均断开，使得所述第六MOS管153的栅端N的第一电压维持在“1”，所述第六MOS管153的漏端M的第二电压维持在“0”。
即通过第七MOS管156和第八MOS管155能够使得所述第六MOS管153的栅端N被拉高至VDD，并使得所述第六MOS管153的漏端M被拉低至GND。
通过控制所述第一反相器157，可以保证所述第六MOS管153的漏端的电压处于“0”，进而保证所述毛刺信号检测电路10的性能。即使所述第六 MOS管153的漏端的电压升高，第一反相器157也可以保证所述第六MOS管153的漏端的电压恢复至“0”。此外，通过所述第一反相器157，也可以避免所述第一电容器154出现漏电，进而保证所述电容器的电压值保持在电源电压。由此，所述毛刺信号检测电路可以实时检测所述电源电压或地电压是否收到毛刺攻击。
此外，所述第六MOS管153、所述检测单元阵列11中的MOS管以及所述第一反相器157可用于形成锁存器。第七MOS管156和第八MOS管155为所述锁存器的使能电路。或者说，所述第六MOS管153、所述检测单元阵列11中的MOS管、所述第一反相器157、所述第七MOS管156以及所述第八MOS管155可形成带使能控制的锁存器。
通过电容器和MOS管形成电压采样模块，不仅能够实现对电源电压的采样，还能够与检测单元阵列11中的MOS管形成锁存器，即可直接利用现有的锁存器制备本申请的毛刺信号检测电路，进一步提高了可应用性。
请参见图7，所述电压采样模块15可包括电阻器151和第二电容器152；所述电阻器151的一端连接至所述电源电压，所述电阻器151的另一端通过所述第二电容器152连接至所述地电压。
图8是本申请实施例的信号生成电路13的示意性结构图。
请参见图8，所述信号生成电路13可以为D触发器。
例如，所述D触发器的重置(RESET)端B连接至重置信号W，例如所述重置信号W可以是上述第一信号R；所述D触发器的D端连接至VDD；所述D触发器的检测端A连接至所述开关阵列12的输出端，用于接收检测信号，所述D触发器的输出端Q输出目标信号(即预警(ALARM)信号)。当然，所述信号生成电路13还可以是其他器件，例如比较器。可选地，所述目标信号也可以是差分信号。
应理解，上文的MOS管可以是金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)。例如“N型”MOS管(NMOSFET)与“P型”MOS管(PMOSFET)。其中，“N型”MOS管和“P型”MOS管当作开关使用时，“N型”MOS管(衬底PN结指向内的MOS管或电流流出的MOS管)的栅端接高电平时导通，接低电平时关断；“P型”MOS管(PN结指向外的MOS管或电流流入的MOS管)的栅端接高电平时关断，接低电平时导通。
还应理解，图1至图8仅为本申请的示例，不应理解为对本申请的限制。
例如，毛刺信号检测电路10还可以包括阈值判决模块。
例如，所述开关阵列12的输出端通过所述阈值判决模块连接至所述信号生成电路13，所述阈值判决模块用于放大所述开关阵列12输出的信号，并将放大后的信号发送至所述信号生成电路13。例如所述阈值判决模块可包括第二反相器和第三反相器，所述开关阵列12的输出端通过第二反相器连接至所述第三反相器的一端，所述第三反相器的另一端连接至所述信号生成电路13。其中所述第二反相器的翻转阈值可小于所述第三反相器的翻转阈值。例如所述第二反相器的翻转阈值为0.3，所述第三反相器的翻转阈值为0.8，即通过降低所述第二反相器的翻转阈值提升所述毛刺信号检测电路10的灵敏度，并通过增大所述第三反相器的翻转阈值，保证所述毛刺信号检测电路10的稳定性。应理解，上述0.3和0.8仅为示例，本申请对所述第二反相器的翻转阈值和所述第三反相器的翻转阈值不做具体限定。通过所述阈值判决模块的配合，可以检测更低幅度的毛刺信号，进一步提升所述毛刺信号检测电路10的灵敏度。
又例如，附图中的开关阵列12和检测单元阵列11中的MOS管的数量仅为示例，不应理解为对本申请的限制。本领域技术人员可以根据实际需求设置多个MOS管。
本申请还提供了一种安全芯片，所述安全芯片可以包括上文所述的毛刺信号检测电路。例如，所述安全芯片可以是指纹传感器芯片或者处理器芯片等等。本申请还提供了一种电子设备，所述电子设备可以包括上文所述的安全芯片。例如，例如，智能手机、笔记本电脑、平板电脑、游戏设备等便携式或移动计算设备，以及电子数据库、汽车、银行自动柜员机(Automated Teller Machine，ATM)等其他电子设备。但本申请实施例对此并不限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及电路，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的电路、支路和模块，可以通过其它的方式实现。例如，以上所描述的支路是示意性的，例 如，该模块的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个模块可以结合或者可以集成到一个支路，或一些特征可以忽略，或不执行。
所述集成的模块如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以该权利要求的保护范围为准。

Claims (12)

  1. 一种毛刺信号检测电路，其特征在于，包括：
    电压采样模块，用于获取并输出电源电压的采样电压；
    检测单元阵列，包括多个金属氧化物半导体MOS管，所述多个MOS管的第一端连接至所述采样电压，所述多个MOS管的第二端连接至电源电压，其中，所述多个MOS管分别具有不同的阈值电压；
    开关阵列，包括所述多个MOS管对应的多个开关；
    信号生成电路，所述多个MOS管的漏端分别通过所述多个开关连接至所述信号生成电路；
    其中，导通所述多个开关中的目标开关，并断开所述多个开关中除所述目标开关之外的开关时，所述信号生成电路用于根据所述目标开关的输出端的电压值的变化生成并输出目标信号，所述目标信号用于指示电源电压或地电压是否出现毛刺信号。
  2. 根据权利要求1所述的毛刺信号检测电路，其特征在于，所述多个MOS管包括：
    多个第一MOS管；
    所述第一MOS管的第一端为所述第一MOS管的栅端，所述第一MOS管的第二端为所述第一MOS管的源端。
  3. 根据权利要求2所述的毛刺信号检测电路，其特征在于，所述开关阵列包括：
    多个第二MOS管；
    所述多个第二MOS管的源端分别连接至所述多个第一MOS管的漏端，所述多个第二MOS管的漏端连接至所述信号生成电路；
    所述多个第二MOS管中的目标MOS管的栅端用于接收所述地电压；
    所述多个第二MOS管中除目标MOS管之外的MOS管的栅端用于接收所述电源电压。
  4. 根据权利要求1至3中任一项所述的毛刺信号检测电路，其特征在于，所述多个MOS管包括：
    多个第三MOS管；
    所述第三MOS管的第一端为所述第三MOS管的源端，所述第三MOS 管的第二端为所述第三MOS管的栅端。
  5. 根据权利要求4所述的毛刺信号检测电路，其特征在于，所述开关阵列包括：
    多个第四MOS管；
    所述多个第四MOS管的源端分别连接至所述多个第三MOS管的漏端，所述多个第四MOS管的漏端连接至所述信号生成电路；
    所述多个第四MOS管中的目标MOS管的栅端用于接收所述地电压；
    所述多个第四MOS管中除目标MOS管之外的MOS管的栅端用于接收所述电源电压或所述采样电压。
  6. 根据权利要求5所述的毛刺信号检测电路，其特征在于，所述开关阵列还包括：
    多个第五MOS管；
    所述多个第五MOS管的源端用于接收所述电源电压，所述多个第五MOS管的漏端分别连接至所述多个第四MOS管的源端；
    所述多个第五MOS管中的目标MOS管的栅端用于接收所述电源电压；
    所述多个第五MOS管中除目标MOS管之外的MOS管的栅端用于接收所述地电压。
  7. 根据权利要求1至6中任一项所述的毛刺信号检测电路，其特征在于，所述电压采样模块包括：
    第一电容器和第六MOS管；
    所述第六MOS管的栅端通过所述第一电容器连接至所述地电压，所述第六MOS管的源端连接至所述地电压。
  8. 根据权利要求7所述的毛刺信号检测电路，其特征在于，所述电压采样模块还包括：
    第七MOS管、第八MOS管以及第一反相器；
    所述第六MOS管的栅端通过所述第七MOS管连接至所述电源电压，所述第六MOS管的漏端通过所述第八MOS管连接至所述地电压，所述第六MOS管的漏端通过所述第一反相器连接至所述第六MOS管的栅端。
  9. 根据权利要求1至5中任一项所述的毛刺信号检测电路，其特征在于，所述电压采样模块包括：
    电阻器和第二电容器；
    所述电阻器的一端连接至所述电源电压，所述电阻器的另一端通过所述第二电容器连接至所述地电压。
  10. 根据权利要求1至9中任一项所述的毛刺信号检测电路，其特征在于，所述信号生成电路为D触发器。
  11. 一种安全芯片，其特征在于，包括：
    权利要求1至10中任一项所述的毛刺信号检测电路。
  12. 一种电子设备，其特征在于，包括：
    权利要求11所述的安全芯片；和
    处理器，所述处理器用于接收所述安全芯片发送的目标信号，所述目标信号用于指示电源电压或地电压是否出现毛刺信号。
PCT/CN2019/100864 2019-08-15 2019-08-15 毛刺信号检测电路、安全芯片和电子设备 WO2021026914A1 (zh)

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