WO2021017862A1 - 一种保护电路及装置 - Google Patents

一种保护电路及装置 Download PDF

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Publication number
WO2021017862A1
WO2021017862A1 PCT/CN2020/102387 CN2020102387W WO2021017862A1 WO 2021017862 A1 WO2021017862 A1 WO 2021017862A1 CN 2020102387 W CN2020102387 W CN 2020102387W WO 2021017862 A1 WO2021017862 A1 WO 2021017862A1
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Prior art keywords
control signal
protection
switch module
circuit
triode
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PCT/CN2020/102387
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English (en)
French (fr)
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卢驭龙
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卢驭龙
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Publication of WO2021017862A1 publication Critical patent/WO2021017862A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit

Definitions

  • This application relates to the field of electronic technology, in particular to a protection circuit and device.
  • the output characteristic of the bridge circuit is that the two control signals must be turned on in turn, and there is an interval of tens of nanoseconds (commonly known as dead time) in the middle. If affected by the interference signal, the two control signals simultaneously generate high levels. , The upper and lower arms of the same phase input high level at the same time to cause a short circuit, which will cause a short circuit of the driven power device (usually a MOS tube or an IGBT tube) and damage the power device.
  • the driven power device usually a MOS tube or an IGBT tube
  • One of the objectives of the embodiments of the present application is to provide a protection circuit, which aims to solve the problem that the power device being driven is short-circuited and damaged when the two control signals in the traditional technical solution generate high levels at the same time. .
  • a protection circuit which is connected between a drive circuit and a bridge circuit, and the protection circuit includes:
  • a logic operation module for generating a protection signal according to the first control signal of the first level and the second control signal of the third level output by the drive circuit;
  • the driving circuit is also used to stop working according to the disconnection of the enable signal
  • the bridge circuit is used to stop working according to the disconnection of the first control signal and the second control signal.
  • the logic operation module includes an AND gate chip, a first resistor, and a first diode;
  • the first input terminal of the AND chip is the first control signal input terminal of the logic operation module
  • the second input terminal of the AND chip is the second control signal input terminal of the logic operation module.
  • the output terminal of the AND chip is the protection signal output terminal of the logic operation module
  • the output terminal of the AND chip is connected to the anode of the first diode
  • the cathode of the first diode is connected to the first diode.
  • a switch module, the second switch module, and the third switch module, the power terminal of the AND chip is connected to a power supply, and the power terminal of the AND chip is connected to the first and the second through the first resistor The anode of the pole tube.
  • the first switch module includes a first triode, a second diode, and a first capacitor
  • the base of the first triode is the protection signal input end of the first switch module
  • the collector of the first triode is the enable signal input end of the first switch module
  • the first The emitter of the triode is grounded
  • the cathode of the second diode is connected to the base of the first triode
  • the anode of the second diode is grounded through the first capacitor.
  • the second switch module includes a second triode
  • the base of the second triode is the protection signal input terminal of the second switch module, and the collector of the second triode is the first control signal input terminal of the second switch module.
  • the emitter of the triode is grounded.
  • the third switch module includes a third triode
  • the base of the third triode is the protection signal input end of the third switch module
  • the collector of the third triode is the second control signal input end of the third switch module
  • the first The emitter of the triode is grounded.
  • it further includes:
  • a sampling module connected to the bridge circuit for generating a sampling voltage according to the input voltage of the bridge circuit
  • the driving circuit is also used to generate the first control signal and the second control signal according to the sampling voltage.
  • the sampling module includes: a second resistor, a third resistor, a second capacitor, and a third capacitor;
  • the second resistor and the third resistor are connected in series between the input voltage input terminal of the sampling module and ground, and the common connection end of the second resistor and the third resistor is the sampling voltage of the sampling module At the output end, the common connection end of the second resistor and the third resistor is grounded through the second capacitor, and the third capacitor is connected between the input voltage input end of the sampling module and the ground.
  • a protection device which is connected between the drive circuit and the bridge circuit.
  • the protection device includes: the above-mentioned protection circuit.
  • the beneficial effect of the protection circuit is that the logic operation module performs logical operations on the first control signal and the second control signal output by the driving circuit, and generates the protection signal according to the first control signal and the second control signal.
  • the first switch module is controlled by the protection signal to turn off the enable signal of the drive circuit to stop the drive circuit
  • the second switch module is controlled by the protection signal
  • the third switch module respectively turn off the first control signal and the second control signal to stop the bridge circuit from working, and prevent the power devices of the bridge circuit from being short-circuited when the first control signal and the second control signal are both at high level. The power device was burned out.
  • FIG. 1 is a schematic diagram of a module structure of a protection circuit provided by an embodiment of the application
  • Fig. 2 is an example circuit schematic diagram of a logic operation module in the protection circuit shown in Fig. 1;
  • Fig. 3 is a schematic circuit diagram of an example of a first switch module in the protection circuit shown in Fig. 1;
  • FIG. 4 is a schematic circuit diagram of an example of a second switch module and a third switch module in the protection circuit shown in FIG. 1;
  • Fig. 5 is a schematic circuit diagram of an example of the sampling module in the protection circuit shown in Fig. 1.
  • FIG. 1 is a schematic diagram of the module structure of a protection circuit 1 provided by an embodiment of the application. As shown in FIG. 1, the protection circuit 1 provided in the present application is connected between the driving circuit 2 and the bridge circuit 3.
  • the protection circuit 1 It includes: a logic operation module 10, a first switch module 20, a second switch module 30, and a third switch module 40.
  • the logic operation module 10 is connected to the drive circuit 2 and is used to generate the protection signal P1 according to the first control signal CT1 of the first level and the second control signal CT2 of the third level output by the drive circuit 2;
  • the first switch module 20 is connected to the logic operation module 10, and is used to turn off the enable signal EN according to the protection signal P1;
  • the driving circuit 2 is also used to stop working according to the disconnection of the enable signal EN;
  • the second switch module 30 is connected to the logic operation module 10, Used to turn off the first control signal CT1 according to the protection signal P1;
  • the third switch module 40 is connected to the logic operation module 10 and used to turn off the first control signal CT1 according to the protection signal P1;
  • the bridge circuit is used to turn off the first control signal CT1 according to the first control signal The disconnection of CT1 and the second control signal CT2 stops working.
  • the first control signal CT1 may be at the first level or the second level
  • the second control signal CT2 may be at the third level or the fourth level
  • the first level and the third level may be at a high level
  • the second level and the fourth level are low levels.
  • the logic operation module 10 performs a logic operation on the first control signal CT1 and the second control signal CT2 output by the driving circuit 2, and according to the first control signal CT1 of the first level and the third level
  • the second control signal CT2 generates the protection signal P1, for example, when the first level and the third level are high, the protection signal P1 (high level) is generated, and the first switch module 20 is controlled to turn off the drive through the protection signal P1
  • the enable signal EN of the circuit 2 stops the driving circuit 2, and at the same time, the second switch module 30 and the third switch module 40 are controlled by the protection signal P1 to turn off the first control signal CT1 and the second control signal CT2, respectively, so that the bridge
  • the circuit 3 stops working to prevent the power device of the bridge circuit 3 from being short-circuited when the first control signal CT1 and the second control signal CT2 are both at a high level, causing the power device to be burned.
  • the logic operation module 10 includes an AND gate chip U1, a first resistor R1, and a first diode D1; the first input terminal of the AND gate chip U1 is the logic operation module 10 The first control signal CT1 input terminal, the second input terminal of the AND chip U1 is the second control signal CT2 input terminal of the logic operation module 10, and the output terminal of the AND chip U1 is the protection signal P1 output terminal of the logic operation module 10.
  • the output terminal of the AND chip U1 is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to the first switch module 20, the second switch module 30 and the third switch module 40, and the power supply of the AND chip U1
  • the terminal is connected to the power supply, and the power terminal of the AND chip U1 is connected to the anode of the first diode D1 through the first resistor R1.
  • the first control signal CT1 and the second control signal CT2 are both pulse width modulated signals. When the bridge circuit 3 is in normal operation, the first control signal CT1 and the second control signal CT2 have high-level pulse widths.
  • the modulation signal and the low-level pulse width modulation signal control the power devices in the bridge circuit 3 to alternately conduct, that is, under normal circumstances, one of the first control signal CT1 and the second control signal CT2 at the same time Is a high level signal and the other is a low level signal.
  • the logic operation module 10 stops generating the protection signal P1, and the first switch module 20, the second switch module 30, and the third switch module 40 respectively turn on the first control signal CT1 and the second control signal CT2.
  • the logic operation module 10 generates the protection signal P1 and the first switch module 20 turns off the enable signal EN of the drive circuit 2 to enable the drive Circuit 2 stops working.
  • the first switch module 20 includes a first transistor Q1, a second diode D2, and a first capacitor C1; the base of the first transistor Q1 is a first switch The input terminal of the protection signal P1 of the module 20, the collector of the first transistor Q1 is connected to the input terminal of the enable signal EN of the first switch module 20, the emitter of the first transistor Q1 is grounded, and the second diode D2 The cathode of is connected to the base of the first transistor Q1, and the anode of the second diode D2 is grounded through the first capacitor C1.
  • the second switch module 30 includes a second transistor Q2; the base of the second transistor Q2 is the input terminal of the protection signal P1 of the second switch module 30, The collector of the transistor Q2 is the input terminal of the first control signal CT1 of the second switch module 30, and the emitter of the second transistor Q2 is grounded.
  • the third switch module 40 includes a third triode Q3; the base of the third triode Q3 is the input terminal of the protection signal P1 of the third switch module 40, and the collector of the third triode Q3 It is the input terminal of the second control signal CT2 of the third switch module 40, and the emitter of the third transistor Q3 is grounded.
  • the protection circuit 1 further includes: a sampling module connected to the bridge circuit 3 for generating a sampling voltage according to the input voltage of the bridge circuit 3; The sampling voltage generates a first control signal CT1 and a second control signal CT2.
  • the sampling module includes: a second resistor R2, a third resistor R3, a second capacitor C2, and a third capacitor C3; the second resistor R2 and the third resistor R3 are connected in series with the sampling module Between the input voltage input end of the second resistor R2 and the third resistor R3 and the ground, the common connection end of the second resistor R2 and the third resistor R3 is the sampling voltage output end of the sampling module, and the common connection end of the second resistor R2 and the third resistor R3 passes through the second capacitor C2 Ground, the third capacitor C3 is connected between the input voltage input terminal of the sampling module and the ground.
  • the enable signal EN is at a high level, and the drive circuit 2 works normally.
  • a high-level first control signal CT1 and a low-level second control signal CT2 are generated.
  • the AND gate The chip U1 performs an AND logic operation on the high-level first control signal CT1 and the low-level second control signal CT2 to stop generating the protection signal P1.
  • the base of the first transistor Q1 is at a low level, and the first triode The tube Q1 is turned off, and the enable terminal of the drive circuit 2 receives the high-level enable signal EN, and keeps generating the high-level first control signal CT1 and the low-level second control signal CT2.
  • the second triode The base of the tube Q2 is extremely low, the second transistor Q2 is turned off, the first control terminal of the bridge circuit 3 is connected to the first control signal CT1 of high level, and the base of the third transistor Q3 is extremely low.
  • the third transistor Q3 is turned off, the second control terminal of the bridge circuit 3 is connected to the low-level second control signal CT2, and the bridge circuit 3 outputs the required voltage during normal operation.
  • the drive circuit 2 In the second half of the cycle, the drive circuit 2 generates a low-level first control signal CT1 and a high-level second control signal CT2.
  • the AND chip U1 responds to the low-level first control signal CT1 and high-level
  • the second control signal CT2 performs the AND logic operation to stop generating the protection signal P1, the base of the first transistor Q1 is low, the first transistor Q1 is turned off, and the enable terminal of the drive circuit 2 receives the high level
  • the enable signal EN keeps generating the low-level first control signal CT1 and the high-level second control signal CT2.
  • the base of the second triode Q2 is extremely low, and the second triode Q2 is off Off
  • the first control terminal of the bridge circuit 3 is connected to the low-level first control signal CT1
  • the base of the third transistor Q3 is at a low level
  • the third transistor Q3 is turned off
  • the bridge circuit 3 The second control terminal is connected to the high-level second control signal CT2, and the bridge circuit 3 normally works and outputs the required voltage.
  • the AND chip U1 calculates the first control signal CT1 and the second control signal CT2 to a high level, that is, the AND chip U1 generates a protection signal P1 (high level), at this time, the base of the first transistor Q1 is at high level, the first transistor Q1 is turned on, and the enable terminal of the driving circuit 2 is grounded through the first transistor Q1 and turned off With the enable signal EN, the enable terminal of the drive circuit 2 is low, and the drive circuit 2 stops outputting the first control signal CT1 and the second control signal CT2.
  • the base of the second transistor Q2 is high, the second transistor Q2 is turned on, the first control terminal of the bridge circuit 3 is grounded through the second transistor Q2, and the first control signal CT1 is turned off.
  • the base of the third transistor Q3 is high, the third transistor Q3 is turned on, the second control terminal of the bridge circuit 3 is grounded through the third transistor Q3, and the second control signal CT2 is turned off. All power devices in the circuit 3 are turned off, and the bridge circuit 3 stops working, so as to prevent the power devices of the bridge circuit 3 from being short-circuited when the first control signal CT1 and the second control signal CT2 are both high at the same time. burn.

Abstract

一种保护电路(1)及装置。保护电路(1)连接于驱动电路(2)和桥式电路(3)之间，保护电路(1)包括：逻辑运算模块(10)、第一开关模块(20)、第二开关模块(30)以及第三开关模块(40)。逻辑运算模块(10)与驱动电路(2)连接，用于根据驱动电路(2)输出的第一控制信号(CT1)和第二控制信号(CT2)生成保护信号(P1)；第一开关模块(20)与逻辑运算模块(10)连接，用于根据保护信号(P1)关断使能信号(EN)；驱动电路(2)还用于根据使能信号(EN)的断开停止工作；第二开关模块(30)与逻辑运算模块(10)连接，用于根据保护信号(P1)关断第一控制信号(CT1)；第三开关模块(40)与逻辑运算模块(10)连接，用于根据保护信号(P1)关断第二控制信号(CT2)。

Description

一种保护电路及装置
本申请要求于2019年07月26日在中国专利局提交的、申请号为201921196521.3、发明名称为“一种保护电路及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种保护电路及装置。
 背景技术
桥式电路的输出特点为两路控制信号必须是轮流导通，中间还有几十纳秒的间隔时间（俗称死区时间），如果受干扰信号的影响，两路控制信号同时产生高电平时，同一相上下两个桥臂同时输入高电平造成短路，则会造成被驱动的功率器件（通常是MOS管或IGBT管）产生短路，损坏功率器件。
因此，传统的技术方案中存在两路控制信号同时产生高电平时，造成被驱动的功率器件产生短路，损坏功率器件的问题。
 技术问题
本申请实施例的目的之一在于：提供一种保护电路，旨在解决传统的技术方案中存在的两路控制信号同时产生高电平时，造成被驱动的功率器件产生短路，损坏功率器件的问题。
 技术解决方案
为解决上述技术问题，本申请实施例采用的技术方案是：
第一方面，提供了一种保护电路，连接于驱动电路和桥式电路之间，所述保护电路包括：
与所述驱动电路连接，用于根据所述驱动电路输出的第一电平的第一控制信号和第三电平的第二控制信号生成保护信号的逻辑运算模块；
与所述逻辑运算模块连接，用于根据所述保护信号关断使能信号的第一开关模块；
所述驱动电路还用于根据所述使能信号的断开停止工作；
与所述逻辑运算模块连接，用于根据所述保护信号关断所述第一控制信号的第二开关模块；
与所述逻辑运算模块连接，用于根据所述保护信号关断所述第一控制信号的第三开关模块；
所述桥式电路用于根据所述第一控制信号和所述第二控制信号的断开停止工作。
在其中一个实施例中，所述逻辑运算模块包括与门芯片、第一电阻以及第一二极管；
所述与门芯片的第一输入端为所述逻辑运算模块的第一控制信号输入端，所述与门芯片的第二输入端为所述逻辑运算模块的第二控制信号输入端，所述与门芯片的输出端为所述逻辑运算模块的保护信号输出端，所述与门芯片的输出端连接所述第一二极管的正极，所述第一二极管的负极连接所述第一开关模块、所述第二开关模块以及所述第三开关模块，所述与门芯片的电源端连接供电电源，所述与门芯片的电源端通过所述第一电阻连接所述第一二极管的正极。
在其中一个实施例中，所述第一开关模块包括第一三极管、第二二极管以及第一电容；
所述第一三极管的基极为所述第一开关模块的保护信号输入端，所述第一三极管的集电极为所述第一开关模块的使能信号输入端，所述第一三极管的发射极接地，所述第二二极管的负极连接所述第一三极管的基极，所述第二二极管的正极通过所述第一电容接地。
在其中一个实施例中，所述第二开关模块包括第二三极管；
所述第二三极管的基极为所述第二开关模块的保护信号输入端，所述第二三极管的集电极为所述第二开关模块的第一控制信号输入端，所述第二三极管的发射极接地。
在其中一个实施例中，所述第三开关模块包括第三三极管；
所述第三三极管的基极为所述第三开关模块的保护信号输入端，所述第三三极管的集电极为所述第三开关模块的第二控制信号输入端，所述第三三极管的发射极接地。
在其中一个实施例中，还包括：
与所述桥式电路连接，用于根据所述桥式电路的输入电压生成采样电压的采样模块；
所述驱动电路还用于根据所述采样电压生成所述第一控制信号和所述第二控制信号。
在其中一个实施例中，所述采样模块包括：第二电阻、第三电阻、第二电容以及第三电容；
所述第二电阻和所述第三电阻串联于所述采样模块的输入电压输入端和地之间，所述第二电阻和所述第三电阻的公共连接端为所述采样模块的采样电压输出端，所述第二电阻和所述第三电阻的公共连接端通过所述第二电容接地，所述第三电容连接于所述采样模块的输入电压输入端和地之间。
第二方面，提供了一种保护装置，连接于驱动电路和桥式电路之间，所述保护装置包括：上述的保护电路。
 有益效果
本申请实施例提供的保护电路的有益效果在于：通过逻辑运算模块对驱动电路输出的第一控制信号和第二控制信号进行逻辑运算，当并根据第一控制信号和第二控制信号生成保护信号，当第一控制信号和第二控制信号同时为高电平时，通过保护信号控制第一开关模块关断驱动电路的使能信号，使驱动电路停止工作，同时，通过保护信号控制第二开关模块和第三开关模块分别关断第一控制信号和第二控制信号，使桥式电路停止工作，防止第一控制信号和第二控制信号同时为高电平时，桥式电路的功率器件短路，导致功率器件被烧毁。
 附图说明
图1为本申请实施例提供的保护电路的模块结构示意图；
图2为图1所示的保护电路中逻辑运算模块的示例电路原理图；
图3为图1所示的保护电路中第一开关模块的示例电路原理图；
图4为图1所示的保护电路中第二开关模块和第三开关模块的示例电路原理图；
图5为图1所示的保护电路中采样模块的示例电路原理图。
 本发明的实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。同时，在本申请的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在此本申请说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本申请。如在本申请说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当进一步理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
为了说明本申请上述的技术方案，下面通过具体实施例来进行说明。
图1为本申请实施例提供的一种保护电路1的模块结构示意图，如图1所示，本申请提供的保护电路1，连接于驱动电路2和桥式电路3之间，该保护电路1包括：逻辑运算模块10、第一开关模块20、第二开关模块30以及第三开关模块40。其中，逻辑运算模块10与驱动电路2连接，用于根据驱动电路2输出的第一电平的第一控制信号CT1和第三电平的第二控制信号CT2生成保护信号P1；第一开关模块20与逻辑运算模块10连接，用于根据保护信号P1关断使能信号EN；驱动电路2还用于根据使能信号EN的断开停止工作；第二开关模块30与逻辑运算模块10连接，用于根据保护信号P1关断第一控制信号CT1；第三开关模块40与逻辑运算模块10连接，用于根据保护信号P1关断第一控制信号CT1；桥式电路用于根据第一控制信号CT1和第二控制信号CT2的断开停止工作。其中，第一控制信号CT1可以为第一电平或第二电平，第二控制信号CT2可以为第三电平或第四电平，第一电平和第三电平可以为高电平，第二电平和第四电平为低电平。
在本实施例中，通过逻辑运算模块10对驱动电路2输出的第一控制信号CT1和第二控制信号CT2进行逻辑运算，当并根据第一电平的第一控制信号CT1和第三电平的第二控制信号CT2生成保护信号P1，例如，当第一电平和第三电平为高电平时，生成保护信号P1（高电平），通过保护信号P1控制第一开关模块20关断驱动电路2的使能信号EN，使驱动电路2停止工作，同时，通过保护信号P1控制第二开关模块30和第三开关模块40分别关断第一控制信号CT1和第二控制信号CT2，使桥式电路3停止工作，防止第一控制信号CT1和第二控制信号CT2同时为高电平时，桥式电路3的功率器件短路，导致功率器件被烧毁。
如图2所示，在其中一个实施例中，逻辑运算模块10包括与门芯片U1、第一电阻R1以及第一二极管D1；与门芯片U1的第一输入端为逻辑运算模块10的第一控制信号CT1输入端，与门芯片U1的第二输入端为逻辑运算模块10的第二控制信号CT2输入端，与门芯片U1的输出端为逻辑运算模块10的保护信号P1输出端，与门芯片U1的输出端连接第一二极管D1的正极，第一二极管D1的负极连接第一开关模块20、第二开关模块30以及第三开关模块40，与门芯片U1的电源端连接供电电源，与门芯片U1的电源端通过第一电阻R1连接第一二极管D1的正极。具体来说，第一控制信号CT1和第二控制信号CT2均为脉冲宽度调制信号，桥式电路3在正常工作时，第一控制信号CT1和第二控制信号CT2分别为高电平的脉冲宽度调制信号和低电平的脉冲宽度调制信号，控制桥式电路3中的功率器件交替导通，即在正常情况下，在同一时刻的第一控制信号CT1和第二控制信号CT2中，其中一个为高电平信号，另一个为低电平信号，此时逻辑运算模块10停止生成保护信号P1，第一开关模块20、第二开关模块30以及第三开关模块40分别导通第一控制信号CT1和第二控制信号CT2。当由于故障导致第一控制信号CT1和第二控制信号CT2同时为高电平时，此时逻辑运算模块10生成保护信号P1，第一开关模块20关断驱动电路2的使能信号EN，使驱动电路2停止工作。
如图3所示，在其中一个实施例中，第一开关模块20包括第一三极管Q1、第二二极管D2以及第一电容C1；第一三极管Q1的基极为第一开关模块20的保护信号P1输入端，第一三极管Q1的集电极连接为第一开关模块20的使能信号EN输入端，第一三极管Q1的发射极接地，第二二极管D2的负极连接第一三极管Q1的基极，第二二极管D2的正极通过第一电容C1接地。
如图4所示，在其中一个实施例中，第二开关模块30包括第二三极管Q2；第二三极管Q2的基极为第二开关模块30的保护信号P1输入端，第二三极管Q2的集电极为第二开关模块30的第一控制信号CT1输入端，第二三极管Q2的发射极接地。
在其中一个实施例中，第三开关模块40包括第三三极管Q3；第三三极管Q3的基极为第三开关模块40的保护信号P1输入端，第三三极管Q3的集电极为第三开关模块40的第二控制信号CT2输入端，第三三极管Q3的发射极接地。
如图4所示，在其中一个实施例中，保护电路1还包括：与桥式电路3连接，用于根据桥式电路3的输入电压生成采样电压的采样模块；驱动电路2还用于根据采样电压生成第一控制信号CT1和第二控制信号CT2。
如图5所示，在其中一个实施例中，采样模块包括：第二电阻R2、第三电阻R3、第二电容C2以及第三电容C3；第二电阻R2和第三电阻R3串联于采样模块的输入电压输入端和地之间，第二电阻R2和第三电阻R3的公共连接端为采样模块的采样电压输出端，第二电阻R2和第三电阻R3的公共连接端通过第二电容C2接地，第三电容C3连接于所述采样模块的输入电压输入端和地之间。
以下结合工作原理对图2至图4进行进一步说明。
正常工作模式下，使能信号EN为高电平，驱动电路2正常工作，在前半周期时，生成高电平的第一控制信号CT1和低电平的第二控制信号CT2，此时与门芯片U1对高电平的第一控制信号CT1和低电平的第二控制信号CT2进行与逻辑运算，停止生成保护信号P1，第一三极管Q1的基极为低电平，第一三极管Q1关断，驱动电路2的使能端接收高电平的使能信号EN，保持生成高电平的第一控制信号CT1和低电平的第二控制信号CT2，同时，第二三极管Q2的基极为低电平，第二三极管Q2关断，桥式电路3的第一控制端接入高电平的第一控制信号CT1，第三三极管Q3的基极为低电平，第三三极管Q3关断，桥式电路3的第二控制端接入低电平的第二控制信号CT2，桥式电路3正常工作输出所需的电压。
在后半周期时，驱动电路2生成低电平的第一控制信号CT1和高电平的第二控制信号CT2，此时与门芯片U1对低电平的第一控制信号CT1和高电平的第二控制信号CT2进行与逻辑运算，停止生成保护信号P1，第一三极管Q1的基极为低电平，第一三极管Q1关断，驱动电路2的使能端接收高电平的使能信号EN，保持生成低电平的第一控制信号CT1和高电平的第二控制信号CT2，同时，第二三极管Q2的基极为低电平，第二三极管Q2关断，桥式电路3的第一控制端接入低电平的第一控制信号CT1，第三三极管Q3的基极为低电平，第三三极管Q3关断，桥式电路3的第二控制端接入高电平的第二控制信号CT2，桥式电路3正常工作输出所需的电压。
当第一控制信号CT1和第二控制信号CT2均为高电平时，与门芯片U1对第一控制信号CT1和第二控制信号CT2的运算结果为高电平，即与门芯片U1生成保护信号P1（高电平），此时，第一三极管Q1的基极为高电平，第一三极管Q1导通，驱动电路2的使能端通过第一三极管Q1接地，关断使能信号EN，驱动电路2的使能端为低电平，驱动电路2停止输出第一控制信号CT1和第二控制信号CT2。同时，第二三极管Q2的基极为高电平，第二三极管Q2导通，桥式电路3的第一控制端通过第二三极管Q2接地，关断第一控制信号CT1，第三三极管Q3的基极为高电平，第三三极管Q3导通，桥式电路3的第二控制端通过第三三极管Q3接地，关断第二控制信号CT2，桥式电路3中的所有功率器件均关断，桥式电路3停止工作，从而防止第一控制信号CT1和第二控制信号CT2同时为高电平时，桥式电路3的功率器件短路，导致功率器件被烧毁。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (8)

  1. 一种保护电路，连接于驱动电路和桥式电路之间，其特征在于，所述保护电路包括：
    与所述驱动电路连接，用于根据所述驱动电路输出的第一电平的第一控制信号和第三电平的第二控制信号生成保护信号的逻辑运算模块；
    与所述逻辑运算模块连接，用于根据所述保护信号关断使能信号的第一开关模块；
    所述驱动电路还用于根据所述使能信号的断开停止工作；
    与所述逻辑运算模块连接，用于根据所述保护信号关断所述第一控制信号的第二开关模块；
    与所述逻辑运算模块连接，用于根据所述保护信号关断所述第一控制信号的第三开关模块；
    所述桥式电路用于根据所述第一控制信号和所述第二控制信号的断开停止工作。
  2. 如权利要求1所述的保护电路，其特征在于，所述逻辑运算模块包括与门芯片、第一电阻以及第一二极管；
    所述与门芯片的第一输入端为所述逻辑运算模块的第一控制信号输入端，所述与门芯片的第二输入端为所述逻辑运算模块的第二控制信号输入端，所述与门芯片的输出端为所述逻辑运算模块的保护信号输出端，所述与门芯片的输出端连接所述第一二极管的正极，所述第一二极管的负极连接所述第一开关模块、所述第二开关模块以及所述第三开关模块，所述与门芯片的电源端连接供电电源，所述与门芯片的电源端通过所述第一电阻连接所述第一二极管的正极。
  3. 如权利要求1所述的保护电路，其特征在于，所述第一开关模块包括第一三极管、第二二极管以及第一电容；
    所述第一三极管的基极为所述第一开关模块的保护信号输入端，所述第一三极管的集电极为所述第一开关模块的使能信号输入端，所述第一三极管的发射极接地，所述第二二极管的负极连接所述第一三极管的基极，所述第二二极管的正极通过所述第一电容接地。
  4. 如权利要求1所述的保护电路，其特征在于，所述第二开关模块包括第二三极管；
    所述第二三极管的基极为所述第二开关模块的保护信号输入端，所述第二三极管的集电极为所述第二开关模块的第一控制信号输入端，所述第二三极管的发射极接地。
  5. 如权利要求1所述的保护电路，其特征在于，所述第三开关模块包括第三三极管；
    所述第三三极管的基极为所述第三开关模块的保护信号输入端，所述第三三极管的集电极为所述第三开关模块的第二控制信号输入端，所述第三三极管的发射极接地。
  6. 如权利要求1所述的保护电路，其特征在于，还包括：
    与所述桥式电路连接，用于根据所述桥式电路的输入电压生成采样电压的采样模块；
    所述驱动电路还用于根据所述采样电压生成所述第一控制信号和所述第二控制信号。
  7. 如权利要求6所述的保护电路，其特征在于，所述采样模块包括：第二电阻、第三电阻、第二电容以及第三电容；
    所述第二电阻和所述第三电阻串联于所述采样模块的输入电压输入端和地之间，所述第二电阻和所述第三电阻的公共连接端为所述采样模块的采样电压输出端，所述第二电阻和所述第三电阻的公共连接端通过所述第二电容接地，所述第三电容连接于所述采样模块的输入电压输入端和地之间。
  8. 一种保护装置，连接于驱动电路和桥式电路之间，其特征在于，所述保护装置包括：如权利要求1至7任一项所述的保护电路。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004056982A (ja) * 2002-07-24 2004-02-19 Seiko Epson Corp 電源回路
US20040052096A1 (en) * 2002-09-16 2004-03-18 Sodick America Corporation Pulse width modulation controller and method
CN102892245A (zh) * 2011-07-18 2013-01-23 台达电子企业管理（上海）有限公司 放电灯系统及其控制方法
CN105048783A (zh) * 2015-08-14 2015-11-11 中国商用飞机有限责任公司北京民用飞机技术研究中心 一种基于窄脉冲解调的自储能igbt驱动电路
CN208094438U (zh) * 2018-04-24 2018-11-13 无锡市艾克特电气股份有限公司 一种igbt桥臂防直通保护电路
CN210578247U (zh) * 2019-07-26 2020-05-19 深圳驭龙电焰科技有限公司 一种保护电路及装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004056982A (ja) * 2002-07-24 2004-02-19 Seiko Epson Corp 電源回路
US20040052096A1 (en) * 2002-09-16 2004-03-18 Sodick America Corporation Pulse width modulation controller and method
CN102892245A (zh) * 2011-07-18 2013-01-23 台达电子企业管理（上海）有限公司 放电灯系统及其控制方法
CN105048783A (zh) * 2015-08-14 2015-11-11 中国商用飞机有限责任公司北京民用飞机技术研究中心 一种基于窄脉冲解调的自储能igbt驱动电路
CN208094438U (zh) * 2018-04-24 2018-11-13 无锡市艾克特电气股份有限公司 一种igbt桥臂防直通保护电路
CN210578247U (zh) * 2019-07-26 2020-05-19 深圳驭龙电焰科技有限公司 一种保护电路及装置

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