WO2016165451A1 - 一种采用隔离变压器栅驱动的移相全桥变换器的故障保护方法 - Google Patents

一种采用隔离变压器栅驱动的移相全桥变换器的故障保护方法 Download PDF

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WO2016165451A1
WO2016165451A1 PCT/CN2016/072689 CN2016072689W WO2016165451A1 WO 2016165451 A1 WO2016165451 A1 WO 2016165451A1 CN 2016072689 W CN2016072689 W CN 2016072689W WO 2016165451 A1 WO2016165451 A1 WO 2016165451A1
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gate drive
output
circuit
gate
microprocessor
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PCT/CN2016/072689
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English (en)
French (fr)
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钱钦松
卢致鹏
张太之
徐申
孙伟峰
陆生礼
时龙兴
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东南大学
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Publication of WO2016165451A1 publication Critical patent/WO2016165451A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers

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  • the invention relates to a fault protection method for a phase-shifted full-bridge converter driven by an isolation transformer gate, which can be applied to high-power applications, improves the service life of the switch tube and increases the reliability of the converter.
  • the object of the present invention is to provide a novel fault protection method for the existing problems of fault-protected phase-shifted full-bridge converters using an isolation transformer gate drive.
  • phase-shifted full-bridge converter circuit includes a main lead and lag two bridge arms, the main transformer T r, the output of the filter circuit, Load and output voltage sampling circuit, output current sampling circuit and cement resistor, the leading bridge arm includes an upper switch tube Q 3 and a lower switch tube Q 1 , and the delay bridge arm includes an upper switch tube Q 4 and a lower switch tube Q 2 ;
  • the GPIO is connected to the input relay control circuit through its internal general-purpose input/output interface.
  • the microprocessor is connected to the output voltage sampling circuit, the output current sampling circuit and the gate drive supply voltage sampling circuit through its internal analog-digital conversion module ADC.
  • the sampling circuit is connected in series between the output positive pole and ground, and the output current sampling circuit is connected in series between the load and the ground.
  • Between the gate drive supply voltage sampling circuit is connected in series between VDD and ground; the microprocessor generates the gate drive signals of the four switch tubes through its internal advanced timers TIMER1 and TIMER2, and the TIMER1 is programmed to generate two channels that are always complementary.
  • the gate drive signals respectively drive Q 2 and Q 4 through respective gate drive circuits, and TIMER2 generates two channels of gate drive signals that are always complementary, respectively, and drives Q 1 and Q 3 through respective gate drive circuits;
  • the structure of the four gate drive circuits is the same, and the output thereof through their respective driving gate drive circuit equipped with a transformer and one end of the DC blocking capacitor connected to the gate four switch Q 1 -Q 4, the four source switch Q 1 -Q 4 are each respectively connected to the gate drive transformer The other end;
  • the input relay is connected in parallel with the cement resistor; when the power is turned on, the input relay is disconnected, and the cement resistor is connected in the main circuit of the converter to reduce the inrush current when the converter is turned on;
  • the output of the device is controlled by the input relay control circuit to open the relay.
  • the cement resistor is short-circuited by the input relay and is no longer connected to the main circuit to prevent cement resistance. Continue to consume energy while the converter is operating normally;
  • the utility model is characterized in that: the output voltage, the output current and the gate drive supply voltage data of the phase-shifted full-bridge converter are read in real time, and the read three kinds of data are respectively compared with respective setting values, and the setting value is converted according to the bridge type.
  • the actual working environment in order to ensure the stable and reliable operation of the converter, manually set and write the upper limit value of the output voltage of the microprocessor, the upper limit of the output current and the upper and lower limits of the gate drive supply voltage, as long as the above three kinds of data If any of them exceeds the range of their settings, the protection is triggered and the protection is implemented in the following four steps:
  • Step 1 the power input is cut off, the microprocessor outputs a low level through the GPIO interface, the input relay is disconnected through the input relay control circuit, and the originally shorted cement resistor is reconnected back to the main circuit for subsequent steps.
  • the use of this cement resistor instead of the switch tube takes over the power of a short straight through;
  • Step 2 outputting an empty duty ratio, the microprocessor adjusts the phase shift between the two gate drive signals generated by TIMER2 and the two gate drive signals generated by TIMER1, so that the two bridge arms are diagonally opposite each other. Only the switching tubes Q 1 and Q 4 , Q 2 and Q 3 are turned on at the same time for zero, that is, the output empty duty ratio ensures that the energy is transmitted to the output immediately after the protection is triggered, so as to prevent the fault in the circuit from further expanding. ;
  • Step 3 output a minimum duty ratio.
  • the microprocessor adjusts the phase shift between the two gate drive signals generated by TIMER2 and the two gate drive signals generated by TIMER1, so that two The two switching tubes Q 1 and Q 4 of the bridge arms are diagonally opposite each other, and the time when Q 2 and Q 3 are simultaneously turned on is the minimum value, that is, the minimum duty ratio is output to release 25% to 35% of the bus capacitance.
  • the energy in C in further reduces the power that the switch tube needs to withstand shortly after its drive signal is turned off;
  • Step 4 closing the gate drive signal, which is completed by the microprocessor and the cement resistor to completely disconnect the input and the output; the microprocessor simultaneously sets all the four gate drive signals to zero, at this time due to the gate In the presence of DC blocking capacitors, there is a short-lived voltage value equal to half of VDD between the gate and source of all switching transistors.
  • the upper and lower tubes Q 1 and Q 3 , Q 2 and Q 4 of the same bridge arm are briefly turned on, but due to In step 1, the cement resistor has been connected, and the equivalent resistance of the switch tube when conducting is very small. At this time, all the input power and the energy in the bus capacitor C in will be added to the cement resistor, and the cement resistor will be These power and energy are consumed in the form of thermal energy. After the voltage drop between the gate and the source of the switch is zero, the switch is completely closed, the input and output are completely disconnected, and the protection action is completed.
  • Figure 1 is a flow chart of the implementation of the present invention
  • FIG. 2 is a circuit schematic diagram of the protection of the present invention
  • Figure 3 is a waveform diagram of a prototype oscilloscope using a conventional protection method
  • FIG. 4 is a waveform diagram of a prototype oscilloscope using the protection method of the present invention.
  • FIG. 2 is a schematic diagram of a basic circuit of a well-known phase-shifted full-bridge converter driven by an isolation transformer, including a phase-shifted full-bridge converter main circuit (including a front bridge arm composed of Q 1 and Q 3 , Q 2 and Q 4 ) Lagging bridge arm, main transformer Tr, output filter circuit, load and output voltage sampling circuit, output current sampling circuit and cement resistor), input relay control circuit (including input relay), microprocessor, gate drive circuit (illustration Taking the gate drive circuit of Q 2 as an example, the following also takes the gate drive circuit of Q2 as an example, which includes two transistors Q 5 and Q 6 , a gate drive transformer Tr1 , a resistor R 1 , a DC blocking capacitor C 1 , C 2 .
  • Q 1 , Q 3 , Q 4 gate drive circuit and gate drive circuit are connected to the respective switch tubes in the same manner as Q 2 , and all four switch tubes are N-channel enhancement type MOS transistors) Drive the supply voltage sampling circuit (including voltage dividing resistors R 5 , R 6 ).
  • the microprocessor is connected to the input relay control circuit through its internal GPIO (General Purpose Input Output) interface, and through its internal ADC (Analog to Digital Conversion) module and output voltage sampling circuit, output current sampling circuit and gate drive supply voltage sampling circuit Connected, and connected to the gate drive circuit of the four switches through its internal advanced timers TIMER1 and TIMER2.
  • the input relay in the input relay control circuit is connected in parallel with the cement resistance in the main circuit of the phase-shifted full-bridge converter.
  • the cement resistor is originally connected in the main circuit of the converter to reduce the inrush current when the converter is turned on. After the converter is turned on, the microprocessor needs to control the input relay to open. After that, the cement resistor is short-circuited by the input relay and is no longer connected to the main circuit. The purpose is to prevent the cement resistor from continuing to consume energy when the converter is working normally.
  • the gate drive circuits of the four switch tubes are directly connected in series to the respective switch tubes.
  • the output voltage sampling circuit is connected in series between the output positive pole and the ground, the output current sampling circuit is connected in series between the load and the ground, and the gate drive supply voltage sampling circuit is connected in series between VDD and ground.
  • the specific connection manner of the gate driving circuit and the switching transistor is exemplified by the gate driving circuit of Q 2 : the gate of the switching transistor is connected to one end of the gate driving transformer Tr1 through the DC blocking capacitor C 2 , and the source of the switching transistor is The other end of the gate drive transformer T r1 is connected.
  • the push-pull amplifier circuit composed of Q 5 and Q 6 in the drive circuit functions to amplify the drive current.
  • the role of R 1 is to further control the magnitude of the drive current.
  • C 1 , C 2 and T r1 are to provide electrical isolation and to provide gate isolation.
  • the amplitude of the driving supply voltage VDD is constant and is transmitted between the gate sources of the switching transistor Q 2 .
  • Q 5 When the gate driving signal is high, Q 5 is turned on, the switch voltage between the gate sources of the VDD Q 2, Q 2 open switch; when the gate drive signal is low, Q 6 is turned on, the switching transistor Q the voltage between the gate and source is 0, the switch Q 2 is turned off, the supply voltage so that the gate driver can monitor the reaction efficiently switch between the normal voltage of the gate source Q 2.
  • the gate drive signals of the four switches Q 1 -Q 4 are generated by two advanced timers TIMER1 and TIMER2 inside the microprocessor.
  • the TIMER1 is programmed to generate two complementary gate drive signals to drive Q 2 and Q respectively. 4 , TIMER2 generates two complementary gate drive signals to drive Q 1 and Q 3 respectively .
  • the phase of the two gate drive signals generated by TIMER1 remains unchanged.
  • the microprocessor adjusts the phase shift between the two gate drive signals generated by TIMER2 and the two gate drive signals generated by TIMER1.
  • the time during which the two switching tubes (Q 1 and Q 4 , Q 2 and Q 3 ) are diagonally turned on is controlled, and then the duty ratio of the phase-shifted full-bridge converter is controlled.
  • the gate blocking capacitor C 2 Due to the presence of the gate blocking capacitor C 2 in the gate driving circuit, after the microprocessor sends a signal to turn off the switching transistor, the voltage on the capacitor C 2 cannot be immediately reduced to zero, which causes the same bridge arm to switch up and down.
  • the short-term simultaneous conduction of the tubes (Q 1 and Q 3 , Q 2 and Q 4 ) (referred to as “straight-through”), while the upper and lower tubes of the straight-through are equivalent to a resistor with a small resistance directly connected between the input power source and the ground. Will generate a lot of current.
  • the traditional phase-shifted full-bridge converter fault protection method for directly closing the switch tube will cause the switch tube to withstand huge power and shorten its service life in a short straight-through state. It is in order to solve this problem that the fault protection method of the present invention has been proposed.
  • the fault protection method of the present invention reads the output voltage, the output current and the gate drive supply voltage data of the phase-shifted full-bridge converter in real time, and respectively reads the above three kinds of data and their respective setting values.
  • the setting value is artificially set and written to the output voltage upper limit value of the microprocessor, the output current upper limit value and the gate drive supply voltage according to the actual working environment of the bridge converter to ensure stable and reliable operation of the converter.
  • the lower limit value is triggered as long as any one of the above three types of data exceeds the set value range (the output voltage data enters the ADC module of the microprocessor through the output voltage sampling circuit, and the output current data also enters through the output current sampling circuit.
  • the ADC module of the microprocessor, the gate drive supply voltage data is also input into the ADC module of the microprocessor through the gate drive supply voltage sampling circuit.
  • the ADC module can simultaneously receive and complete the conversion of the above three kinds of data from analog to digital, and
  • the microprocessor sequentially reads the above three kinds of data that have been converted into digital quantities from the ADC module for subsequent processing.
  • the protection is implemented step by step in the following four steps:
  • Step 1 Turn off the power input and turn off the input relay.
  • the relay is first turned off by the microprocessor via its internal relay control signal from the GPIO interface for generating the relay control signal (when the GPIO port output is low, the input relay is off).
  • the purpose of turning off the input relay is to reconnect the originally short-circuited cement resistor back to the main circuit, so that in the subsequent steps, the cement resistor can be skillfully used instead of the switch tube to take power for a short straight-through.
  • Step 2 Output an empty duty cycle.
  • the microprocessor needs to adjust the phase shift between the two gate drive signals generated by TIMER2 and the two gate drive signals generated by TIMER1, so that diagonally diagonal The time when the two switches are turned on at the same time is zero, that is, the output duty cycle is output. This step is done entirely by the microprocessor in order to stop the transfer of energy to the output immediately after the protection is triggered, in case the fault in the circuit is further amplified.
  • step 3 the minimum duty cycle is output, and the input relay is completely turned off after maintaining the empty duty cycle for 15ms to 25ms. Then, the microprocessor adjusts the phase shift between the two gate drive signals generated by TIMER2 and the two gate drive signals generated by TIMER1, so that the time when the diagonally opposite switches are simultaneously turned on is the minimum value, that is, The minimum duty cycle is output. This step is also done independently by the microprocessor in order to release the energy in the 25% to 35% bus capacitance Cin, further reducing the power that the switch requires to withstand shortly after its drive signal is turned off.
  • step 4 the gate drive signal is turned off. This step is done by the microprocessor and the cement resistor in order to completely disconnect the input and output.
  • the microprocessor simultaneously sets all four gate drive signals to zero.
  • the upper and lower tubes of the bridge arm (Q 1 and Q 3 , Q 2 and Q 4 ) are briefly through, but since the cement resistor has been connected in step 1, and the equivalent resistance of the switch tube during conduction is very small, at this time All of the input power and the energy in the bus capacitance C in will be applied to the cement resistor, and these power and energy are consumed as thermal energy by the cement resistor.
  • the voltage waveforms of the gate drive power supply voltage, the relay control signal, and the voltage across the cement resistor are respectively shown.
  • time is the abscissa and the voltage value is the ordinate.
  • the positions of X4, X2 and X1 on the left side indicate the coordinate origin of the gate drive power supply voltage, the relay control signal and the voltage across the cement resistor. It can be seen from the circled part in the figure that, in the case where the invention is not used, after the gate drive signal is set to zero by the microprocessor, the voltage across the cement resistor is still zero, indicating that the input power is still not disconnected at this time. The cement resistance is still short-circuited. At this time, all power and energy will be added to the straight-through switch tube, which greatly shortens the service life of the switch tube.
  • the voltage waveforms of the gate drive power supply voltage, the relay control signal, and the voltage across the cement resistor are respectively shown.
  • time is the abscissa and the voltage value is the ordinate.
  • the positions of X4, X2 and X1 on the left side indicate the coordinate origin of the gate drive power supply voltage, the relay control signal and the voltage across the cement resistor.

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Abstract

一种采用隔离变压器栅驱动的移相全桥变换器故障保护方法，实时读取移相全桥变换器的输出电压、输出电流和栅驱动供电电压数据，并将读取的上述三种数据分别与各自的整定值比较，整定值即根据桥式变换器实际工作环境，为保证变换器稳定可靠运行而人为设定并写入微处理器的输出电压上限值、输出电流上限值和栅驱动供电电压上、下限值，只要上述三种数据中的任何一种超出其整定值范围，就触发保护，分四步实施保护：(1)切断电源输入，(2)输出空占空比，(3)输出最小占空比，(4)关闭栅驱动信号，保护动作完成。该故障保护方法响应速度快，能够有效延长开关管的使用寿命，提高桥式变换器的可靠性和稳定性。

Description

一种采用隔离变压器栅驱动的移相全桥变换器的故障保护方法 技术领域
本发明涉及一种采用隔离变压器栅驱动的移相全桥变换器的故障保护方法，可适用于大功率的应用场合，提高开关管使用寿命的同时又增加了变换器的可靠性。
背景技术
近年来，大功率开关变换器的需求越来越强烈，而拥有更高输出功率的桥式变换器常常被应用于大功率的应用场合。更高的输出功率一方面缩短了充电时间，另一方面，也对变换器的可靠性提出了更高的要求。例如，对于任何桥式变换器，在长期的使用过程当中都有可能发生故障，如输出出现开路或者短路的情况。在故障发生之后，如何立刻进行保护动作以避免系统进一步损坏是一个必须要考虑的问题。
一般来说，故障之后的保护需要断开输入与输出之间的连接，其中，最好的方法就是关闭开关管。对于采用隔离变压器的栅驱动而言，由于栅极隔直电容的电压不能立刻降为零，同一桥臂上下两只开关管会出现短暂直通，传统的直接关闭开关管的故障保护方法缺乏对这个问题的考虑，若依旧采用此种方法，会大大缩短开关管的使用寿命。
发明内容
本发明的目的是针对现有采用隔离变压器栅驱动的移相全桥变换器在故障保护时存在的问题，提供一种新型的故障保护方法。
本发明为实现上述目的，采用如下技术方案：一种采用隔离变压器栅驱动的移相全桥变换器的故障保护方法，隔离变压器栅驱动的移相全桥变换器包括移相全桥变换器主电路、输入继电器及其控制电路、微处理器、栅驱动电路以及栅驱动供电电压采样电路，移相全桥变换器主电路包括超前和滞后两个桥臂、主变压器Tr、输出滤波电路、负载以及输出电压采样电路、输出电流采样电路和水泥电阻，超前桥臂包括上开关管Q3和下开关管Q1，滞后桥臂包括上开关管Q4和下开关管Q2；微处理器通过其内部的通用输入输出接口GPIO与输入继电器控制电路连接，微处理器通过其内部的模拟数字转换模块ADC分别与输出电压采样电路、输出电流采样电路和栅驱动供电电压采样电路连接，输出电压采样电路串联在输出正极和地之间，输出电流采样电路串联在负载和地之间，栅驱动供电电压采样电路串联在VDD和地之间；微处理器通过其内部的高级定时器TIMER1和TIMER2产生四个开关管的栅驱动信号，通过编程使TIMER1产生两路始终互补的栅驱动信号分别通过各自栅驱动电路驱动Q2和Q4，TIMER2产生两路始终互补的栅驱动信号分别通过各自栅驱动电路驱动Q1和Q3；四个栅驱动电路的结构相同，其输出分别通过各自驱动电路内设的栅驱动变压器的一端和隔直电容连接到四个开关管Q1-Q4的栅极，四个开关管Q1-Q4的源极分别连接各自栅驱动变压器的另一端；输入继电器与水泥电阻并联； 开机时，输入继电器断开，水泥电阻接入在变换器的主回路中，用于减小变换器开机时的浪涌电流；开机完成之后，微处理器输出通过输入继电器控制电路控制输入继电器开启，水泥电阻被输入继电器短路，不再接入主回路，以防止水泥电阻在变换器正常工作时继续消耗能量；
其特征在于：实时读取移相全桥变换器的输出电压、输出电流和栅驱动供电电压数据，并将读取的上述三种数据分别与各自的整定值比较，整定值即根据桥式变换器实际工作环境，为保证变换器稳定可靠运行而人为设定并写入微处理器的输出电压上限值、输出电流上限值和栅驱动供电电压上、下限值，只要上述三种数据中的任何一种超出其整定值范围，就触发保护，按以下四个步骤实施保护：
步骤1，切断电源输入，由微处理器通过GPIO接口输出低电平，通过输入继电器控制电路将输入继电器断开，将原本被短路的水泥电阻又重新接回到主回路中，以便在后续步骤中利用这个水泥电阻代替开关管承担短暂直通时的功率；
步骤2，输出空占空比，由微处理器调整TIMER2产生的两路栅驱动信号相对TIMER1产生的两路栅驱动信号之间的相移，使两个桥臂中互为斜对角的两只开关管Q1与Q4，Q2与Q3同时导通的时间为零，即输出空占空比，保证在保护被触发之后立即停止向输出传递能量，以防电路中的故障进一步扩大；
步骤3，输出最小占空比，在维持空占空比15ms至25ms之后，由微处理器调整TIMER2产生的两路栅驱动信号相对TIMER1产生的两路栅驱动信号之间的相移，使两个桥臂中互为斜对角的两只开关管Q1与Q4，Q2与Q3同时导通的时间为最小值，即输出最小占空比，以释放25％至35％母线电容Cin当中的能量，进一步减小开关管在其驱动信号关闭之后所需短暂承受的功率；
步骤4，关闭栅驱动信号，由微处理器和水泥电阻共同完成，以彻底断开输入与输出之间的连接；由微处理器同时将所有四路栅驱动信号置零，此时由于栅极隔直电容的存在，所有开关管的栅源之间都短暂存在着幅值等于VDD一半的电压值，同一桥臂的上下两管Q1和Q3、Q2和Q4短暂直通，但由于在步骤1中水泥电阻已经接入，且导通时的开关管等效电阻非常小，此时的全部输入功率和母线电容Cin中的能量都将加在水泥电阻上，并由水泥电阻将这些功率和能量以热能的形式消耗，待开关管栅源之间的电压降为零之后，开关管彻底关闭，输入和输出就彻底断开，保护动作完成。
本发明具有如下优点及显着效果：
1)无需增加任何硬件电路，成本低；
2)所有保护动作只需在控制方式上做相应处理即可，实现简单；
3)通过输出空占空比的方式迅速断开输入与输出的连接，响应速度快；
4)适用于各种类型的保护，如输出电压过压保护、输出电流过流保护和栅驱动过压、欠压保护等各类保护，应用方便；
5)有效延长开关管的使用寿命，提高桥式变换器的可靠性和稳定性。
附图说明
图1是本发明实现流程图；
图2是本发明保护的电路原理图；
图3是采用传统保护方法的样机实测示波器波形图；
图4是采用本发明保护方法的样机实测示波器波形图。
具体实施方式
下面结合附图对发明的技术方案进行详细说明。
图2是公知的采用隔离变压器栅驱动的移相全桥变换器的基本电路原理图，包括移相全桥变换器主电路(含Q1和Q3构成的超前桥臂、Q2和Q4构成的滞后桥臂，主变压器Tr、输出滤波电路、负载以及输出电压采样电路、输出电流采样电路和水泥电阻)、输入继电器控制电路(含输入继电器)、微处理器、栅驱动电路(图示中以Q2的栅驱动电路为例，以下也以Q2的栅驱动电路为例说明，其包括两只三极管Q5和Q6、栅驱动变压器Tr1、电阻R1、隔直电容C1、C2。Q1、Q3、Q4的栅驱动电路以及栅驱动电路与各自开关管的连接方式与Q2的都一样，而且四只开关管都是N沟道增强型MOS管)、栅驱动供电电压采样电路(包括分压电阻R5、R6)。微处理器通过其内部的GPIO(通用输入输出)接口与输入继电器控制电路连接，并通过其内部的ADC(模拟数字转换)模块与输出电压采样电路、输出电流采样电路和栅驱动供电电压采样电路连接，再通过其内部的高级定时器TIMER1和TIMER2与四只开关管的栅驱动电路连接。输入继电器控制电路中的输入继电器与移相全桥变换器主电路中的水泥电阻并联，水泥电阻原本接入在变换器的主回路当中，用于减小变换器开机时的浪涌电流，在变换器开机完成之后，需由微处理器控制输入继电器开启，此后水泥电阻就被输入继电器短路而不再接入主回路，目的是为了防止水泥电阻在变换器正常工作时继续消耗能量。四只开关管的栅驱动电路分别直接串联至各自所驱动的开关管。输出电压采样电路串联在输出正极和地之间，输出电流采样电路串联在负载和地之间，栅驱动供电电压采样电路串联在VDD和地之间。另外，栅驱动电路与开关管的具体连接方式以Q2的栅驱动电路为例：开关管的栅极经过隔直电容C2与栅驱动变压器Tr1的一端相连，开关管的源极则与栅驱动变压器Tr1的另一端相连。驱动电路中Q5和Q6组成的推挽放大电路的作用在于放大驱动电流，R1的作用在于进一步控制驱动电流的大小，C1、C2和Tr1的作用在于提供电气隔离并将栅驱动供电电压VDD幅值不变的传递到开关管Q2的栅源之间。当栅驱动信号为高电平时，Q5导通，开关管Q2栅源之间的电压为VDD，开关管Q2开通；当栅驱动信号为低电平时，Q6导通，开关管Q2栅源之间的电压为0，开关管Q2关断，故监测栅驱动供电电压可以有效反应开关管Q2栅源之间电压 的是否正常。
四只开关管Q1-Q4的栅驱动信号由微处理器内部的两个高级定时器TIMER1和TIMER2产生，通过编程使其中的TIMER1产生两路始终互补的栅驱动信号分别驱动Q2和Q4，TIMER2再产生两路始终互补的栅驱动信号分别驱动Q1和Q3。系统工作时，由TIMER1产生的两路栅驱动信号的相位保持不变，微处理器通过调整由TIMER2产生的两路栅驱动信号相对由TIMER1产生的两路栅驱动信号之间的相移，来控制斜对角的两只开关管(Q1和Q4、Q2和Q3)同时导通的时间，继而控制移相全桥变换器的占空比。
由于栅驱动电路中栅极隔直电容C2的存在，在微处理器发出关闭开关管的信号之后，电容C2上的电压不能立刻降为零，这就会造成同一桥臂上下两只开关管(Q1和Q3、Q2和Q4)的短暂同时导通(称为“直通”)，而直通的上下两管相当于阻值很小的电阻直接接在输入电源和地之间，将产生很大的电流。传统的直接关闭开关管的移相全桥变换器故障保护方法会造成开关管在短暂直通时承受巨大功率，缩短其使用寿命。正是为了解决这个问题，才提出了本发明的故障保护方法。
如图1所示，本发明的故障保护方法：实时读取移相全桥变换器的输出电压、输出电流和栅驱动供电电压数据，并将读取的上述三种数据分别与各自的整定值比较，整定值即根据桥式变换器实际工作环境，为保证变换器稳定可靠运行而人为设定并写入微处理器的输出电压上限值、输出电流上限值和栅驱动供电电压上、下限值，只要上述三种数据中的任何一种超出其整定值范围，就触发保护(输出电压数据经输出电压采样电路进入微处理器的ADC模块，输出电流数据经输出电流采样电路也进入微处理器的ADC模块，栅驱动供电电压数据经栅驱动供电电压采样电路同样进入微处理器的ADC模块。ADC模块可同时接收并完成上述三种数据从模拟量到数字量的转换，并由微处理器实时将已经转换成数字量的上述三种数据同时从ADC模块中读取进来，以便后续处理)。
按以下四个步骤分步式实施保护：
步骤1，切断电源输入，关闭输入继电器。在保护被触发之后，首先由微处理器通过其内部的用于产生继电器控制信号的GPIO接口发出的继电器控制信号(当该GPIO口输出为低电平时，输入继电器关闭)将输入继电器关闭。如图2所示，关闭输入继电器的目的在于将原本被短路的水泥电阻又重新接回到主回路中，以便在后续步骤中可以巧妙利用这个水泥电阻代替开关管承担短暂直通时的功率。
步骤2，输出空占空比。在关闭输入继电器的继电器控制信号发出之后，紧接着，需要由微处理器调整由TIMER2产生的两路栅驱动信号相对由TIMER1产生的两路栅驱动信号之间的相移，使得斜对角的两只开关管同时导通的时间为零，即输出空占空比。此步骤完全由微处理器完成，目的是为了在保护被触发之后立即停止向输出传递能量，以防电路中的故障进一步扩大。
步骤3，输出最小占空比，在维持空占空比15ms至25ms之后，输入继电器已经完 全关闭。再由微处理器调整由TIMER2产生的两路栅驱动信号相对由TIMER1产生的两路栅驱动信号之间的相移，使得斜对角的两只开关管同时导通的时间为最小值，即输出最小占空比。此步骤同样由微处理器独立完成，目的是为了释放25％至35％母线电容Cin当中的能量，进一步减小开关管在其驱动信号关闭之后所需短暂承受的功率。
步骤4，关闭栅驱动信号。此步骤由微处理器和水泥电阻共同完成，目的是为了彻底断开输入与输出之间的连接。由微处理器同时将所有四路栅驱动信号置零，此时由于栅极隔直电容C2的存在，所有开关管的栅源之间都短暂存在着幅值等于VDD一半的电压值，同一桥臂的上下两管(Q1和Q3、Q2和Q4)短暂直通，但由于在步骤1中水泥电阻已经接入，且导通时的开关管等效电阻非常小，故此时的全部输入功率和母线电容Cin中的能量都将加在水泥电阻上，并由水泥电阻将这些功率和能量以热能的形式消耗。待开关管栅源之间的电压降为零之后，开关管彻底关闭，输入和输出就彻底断开，保护动作完成。
如图3所示，分别为栅驱动供电电压、继电器控制信号和水泥电阻两端电压的电压波形图。图中以时间为横坐标，电压值为纵坐标，左侧X4、X2和X1所在的位置分别表示栅驱动供电电压、继电器控制信号和水泥电阻两端电压的坐标原点。从图中画圈的部分可以看出，在没有采用本发明的情况下，由微处理器将栅驱动信号置零后，水泥电阻两端电压仍然是零，说明此时输入电源仍未断开，水泥电阻也依然被短路，此时全部功率和能量都将加在直通的开关管上，大大缩短了开关管的使用寿命。
如图4所示，分别为栅驱动供电电压、继电器控制信号和水泥电阻两端电压的电压波形图。图中以时间为横坐标，电压值为纵坐标，左侧X4、X2和X1所在的位置分别表示栅驱动供电电压、继电器控制信号和水泥电阻两端电压的坐标原点。从图中画圈的部分可以看出，在采用本发明之后，由微处理器将栅驱动信号置零后，水泥电阻两端电压已经升为输入电压，说明此时输入电源已经断开，水泥电阻也已经接入主回路，此时全部功率和能量都将加在水泥电阻上，开关管不受影响。

Claims (1)

  1. 一种采用隔离变压器栅驱动的移相全桥变换器的故障保护方法，隔离变压器栅驱动的移相全桥变换器包括移相全桥变换器主电路、输入继电器及其控制电路、微处理器、栅驱动电路以及栅驱动供电电压采样电路，移相全桥变换器主电路包括超前和滞后两个桥臂、主变压器Tr、输出滤波电路、负载以及输出电压采样电路、输出电流采样电路和水泥电阻，超前桥臂包括上开关管Q3和下开关管Q1，滞后桥臂包括上开关管Q4和下开关管Q2；微处理器通过其内部的通用输入输出接口GPIO与输入继电器控制电路连接，微处理器通过其内部的模拟数字转换模块ADC分别与输出电压采样电路、输出电流采样电路和栅驱动供电电压采样电路连接，输出电压采样电路串联在输出正极和地之间，输出电流采样电路串联在负载和地之间，栅驱动供电电压采样电路串联在VDD和地之间；微处理器通过其内部的高级定时器TIMER1和TIMER2产生四个开关管的栅驱动信号，通过编程使TIMER1产生两路始终互补的栅驱动信号分别通过各自栅驱动电路驱动Q2和Q4，TIMER2产生两路始终互补的栅驱动信号分别通过各自栅驱动电路驱动Q1和Q3；四个栅驱动电路的结构相同，其输出分别通过各自驱动电路内设的栅驱动变压器的一端和隔直电容连接到四个开关管Q1-Q4的栅极，四个开关管Q1-Q4的源极分别连接各自栅驱动变压器的另一端；输入继电器与水泥电阻并联；开机时，输入继电器断开，水泥电阻接入在变换器的主回路中，用于减小变换器开机时的浪涌电流；开机完成之后，微处理器输出通过输入继电器控制电路控制输入继电器开启，水泥电阻被输入继电器短路，不再接入主回路，以防止水泥电阻在变换器正常工作时继续消耗能量；
    其特征在于：实时读取移相全桥变换器的输出电压、输出电流和栅驱动供电电压数据，并将读取的上述三种数据分别与各自的整定值比较，整定值即根据桥式变换器实际工作环境，为保证变换器稳定可靠运行而人为设定并写入微处理器的输出电压上限值、输出电流上限值和栅驱动供电电压上、下限值，只要上述三种数据中的任何一种超出其整定值范围，就触发保护，按以下四个步骤实施保护：
    步骤1，切断电源输入，由微处理器通过GPIO接口输出低电平，通过输入继电器控制电路将输入继电器断开，将原本被短路的水泥电阻又重新接回到主回路中，以便在后续步骤中利用这个水泥电阻代替开关管承担短暂直通时的功率；
    步骤2，输出空占空比，由微处理器调整TIMER2产生的两路栅驱动信号相对TIMER1产生的两路栅驱动信号之间的相移，使两个桥臂中互为斜对角的两只开关管Q1与Q4，Q2与Q3同时导通的时间为零，即输出空占空比，保证在保护被触发之后立即停止向输出传递能量，以防电路中的故障进一步扩大；
    步骤3，输出最小占空比，在维持空占空比15ms至25ms之后，由微处理器调整TIMER2产生的两路栅驱动信号相对TIMER1产生的两路栅驱动信号之间的相移，使两个桥臂中互为斜对角的两只开关管Q1与Q4，Q2与Q3同时导通的时间为最小值，即输出最 小占空比，以释放25％至35％母线电容Cin当中的能量，进一步减小开关管在其驱动信号关闭之后所需短暂承受的功率；
    步骤4，关闭栅驱动信号，由微处理器和水泥电阻共同完成，以彻底断开输入与输出之间的连接；由微处理器同时将所有四路栅驱动信号置零，此时由于栅极隔直电容的存在，所有开关管的栅源之间都短暂存在着幅值等于VDD一半的电压值，同一桥臂的上下两管Q1和Q3、Q2和Q4短暂直通，但由于在步骤1中水泥电阻已经接入，且导通时的开关管等效电阻非常小，此时的全部输入功率和母线电容Cin中的能量都将加在水泥电阻上，并由水泥电阻将这些功率和能量以热能的形式消耗，待开关管栅源之间的电压降为零之后，开关管彻底关闭，输入和输出就彻底断开，保护动作完成。
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