WO2021016893A1

WO2021016893A1 - Dwt computing device, method, image processing device, and movable platform

Info

Publication number: WO2021016893A1
Application number: PCT/CN2019/098457
Authority: WO
Inventors: 任子木; 吴莹颖; 张健华
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2019-07-30
Filing date: 2019-07-30
Publication date: 2021-02-04
Also published as: CN111684484A

Abstract

A DWT computing device, a method, an image processing device, and a movable platform. The DWT computing device comprises: a column circuit, a permuter circuit, and a row circuit; the column circuit is configured to receive preset data blocks to be processed, perform DWT computing on said data blocks in columns to generate intermediate data blocks, and output the intermediate data blocks to the permuter circuit in columns; the permuter circuit is configured to output the intermediate data blocks input in columns into the row circuit in rows; the row circuit is configured to perform DWT computing on the intermediate data blocks input in rows to obtain the computing result. According to the DWT computing device, the method, the image processing device, and the movable platform provided in the present application, DWT computing can be efficiently realized, and high real-time performance and low power consumption can be realized.

Description

DWT computing device, method, image processing device and movable platform

Copyright statement

The content disclosed in this patent document contains copyrighted material. The copyright belongs to the copyright owner. The copyright owner does not object to anyone copying the patent document or the patent disclosure in the official records and archives of the Patent and Trademark Office.

Technical field

This application relates to the field of image processing, and in particular to a discrete wavelet transform operation device, method, image processing device and movable platform.

Background technique

Discrete Wavelet Transform (DWT) has good localized analysis performance in time and frequency domain. It has the function of "mathematical microscope" focusing. It has been applied to many signal processing fields, especially in the field of image compression. Many still image compression schemes based on wavelet transform.

In the prior art, a commonly used way to implement DWT is: in a general-purpose processor, multiple instructions are used to implement each step of the DWT operation. This kind of implementation has slow calculation speed and low real-time performance.

For example, in the field of image processing, DWT97 is usually used to achieve lossy compression, and DWT53 is used to achieve lossless compression. DWT97 contains a large number of multiplication and addition operations, DWT53 contains a large number of addition operations. If you call the addition and multiplication instructions in a general-purpose processor, you need to call many times. The scheduling of instructions is performed at the software level, because the software is very real-time. Low, which greatly increases the execution time of the DWT operation, so the real-time performance of this implementation is very low; in addition, this implementation requires multiple reads and writes of the on-chip cache, and the power consumption of reading and writing the on-chip cache is high, so this The power consumption of the implementation is also large.

Summary of the invention

This application provides a DWT computing device, method, image processing device, and movable platform, which can efficiently implement DWT computing, with high real-time performance and low power consumption.

In a first aspect, a DWT operation device is provided, including: a column circuit, an interleaver circuit, and a row circuit. The column circuit is used to: receive a preset data block to be processed, and perform column-based processing on the data block to be processed. DWT operation generates intermediate data blocks, and outputs the intermediate data blocks to the interleaver circuit in columns; the interleaver circuit is used to: output the intermediate data blocks input in columns to the row in rows In the circuit; the row circuit is used to perform a DWT operation on the intermediate data block input by row to obtain the operation result.

In a second aspect, a method for processing data in a DWT operation device is provided, wherein the DWT operation device includes a column circuit, an interleaver circuit, and a row circuit, and the method includes: obtaining a preset waiting Process data blocks; perform DWT operations on the to-be-processed data blocks by the column circuit to generate intermediate data blocks, and output the intermediate data blocks to the interleaver circuit in columns; pass the interleaver circuit The intermediate data blocks input in columns are output to the row circuit in rows; and the intermediate data blocks input in rows are subjected to a DWT operation through the row circuit to obtain an operation result.

In a third aspect, an image processing device is provided, including: a processing device and a DWT computing device in the first aspect or any possible implementation of the first aspect. The DWT operation device is used to perform DWT operation on the data block to be processed to generate wavelet coefficients, and transmit the wavelet coefficients to the processing device; the processing device is used to perform one of the following on the wavelet coefficients Or multiple processing: noise reduction processing, DWT inverse operation, quantization processing and entropy coding processing.

In a fourth aspect, a movable platform is provided, including: a body; a power system, which is provided in the body, and is used to provide power to the movable platform; an image acquisition device, which is used to collect images; and the second aspect The image processing device in is used to process the image.

In a fifth aspect, a camera is provided, including: a housing; a lens assembly arranged inside the housing; a sensor module arranged inside the housing and at the rear end of the lens assembly for sensing passing through The light of the lens assembly generates an electric signal; and the image processing device in the second aspect is used to process the electric signal.

Description of the drawings

Fig. 1 is a schematic block diagram of a DWT computing device according to an embodiment of the present application.

Fig. 2 is a schematic diagram of an application scenario of a DWT computing device according to an embodiment of the present application.

Fig. 3 is a schematic diagram of a reading sequence of image data in an embodiment of the present application.

FIG. 4 is another schematic diagram of the image data reading sequence of the embodiment of the present application.

FIG. 5 is a schematic diagram of the structure of the Column circuit in the DWT computing device of the embodiment of the present application.

FIG. 6 is a schematic diagram of the operation process of DWT53 in an embodiment of the present application.

Fig. 7 is a schematic diagram of the operation process of DWT97 in an embodiment of the present application.

FIG. 8 is a schematic diagram of image data read by the Permuter circuit in the DWT computing device of the embodiment of the present application.

FIG. 9 is a schematic diagram of the Row circuit of the DWT computing device according to an embodiment of the present application.

Fig. 10 is a schematic block diagram of an image processing device according to an embodiment of the present application.

Fig. 11 is a schematic block diagram of a movable platform according to an embodiment of the present application.

Fig. 12 is a schematic block diagram of a camera according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of this application. The terms used in the description of the application herein are only for the purpose of describing specific embodiments, and are not intended to limit the application.

The embodiment of the present application proposes a DWT computing device 100. As shown in FIG. 1, the DWT computing device 100 is a hardware structure, which mainly includes three circuits, namely a column circuit 110 and an interleaver (Permuter). Circuit 120 and Row circuit 130. Specifically, for a preset data block to be processed, for example, the DWT computing device 100 may receive the data block to be processed; the Column circuit 110 is used to perform DWT operations on the data block to be processed in columns to generate intermediate data blocks, and The intermediate data block is output to the Permuter circuit 120 in columns, that is, the input data block to be processed is subjected to DWT column transformation and then output to the Permuter circuit 120; the Permuter circuit 120 is used to input the intermediate data block in columns Read by row and output to Row circuit 130; The Row circuit 130 is used to perform DWT operation on the intermediate data block input by row to obtain the operation result, that is, perform DWT row transformation on the intermediate data block input by row Then output by line to complete the DWT calculation process.

The DWT computing device 100 will be described in detail below in conjunction with specific embodiments and FIGS. 2 to 9.

It should be understood that the DWT computing device 100 may be used to process data. For example, the embodiment of the present application takes the processing of image data as an example for description. Fig. 2 shows a schematic diagram of an application scenario of a DWT computing device in an embodiment of the present application. As shown in FIG. 2, the image data is input to the DWT computing device 100, and the image data is the data block to be processed. For example, image data can be input to the DWT computing device 100 through a data reading circuit, where the data reading circuit can be expressed as a raw_fetch circuit.

Optionally, the DWT computing device 100 may or may not include the raw_fetch circuit. For example, as shown in FIG. 2, the embodiment of the present application takes the raw_fetch circuit not belonging to the DWT computing device 100 as an example for description, but the embodiment of the present application is not limited to this.

Specifically, the external raw_fetch circuit is responsible for reading image data from the double data rate (Double Data Rate, DDR) circuit. For example, the raw_fetch circuit can read the image data from the DDR circuit through the Advanced eXtensible Interface (AXI). The image data is read and output to the Column circuit 110 in the DWT computing device 100 for processing, that is, the output of the raw_fetch circuit is the same as the input of the Column circuit 110. Specifically, the DWT computing device 100 may perform multi-stage processing, that is, perform multiple repeated processing. For example, as shown in Figure 2, take the 3-level processing as an example, that is, the input data is processed three times repeatedly. Among them, the 1-level processing is to process the original data, and the output processing result is used as the input data of the 2-level processing, and The input result of level 2 is then used as input data for level 3 processing. For any level of processing, for example, any level of processing in the 1/2/3 level in Figure 2, the output data sequence of the raw_fetch circuit can be as shown in Figure 3.

It should be understood that processing a 256*256 image data is taken as an example for description. First, divide the 256*256 image into 16 64*64 blocks. For example, FIG. 3 shows the first 4 64*64 blocks, that is, the 4 large blocks in FIG. 3. As shown in Figure 3, for these 4 64*64 blocks, the raw_fetch circuit will output sequentially from left to right, and then output the 4 64*64 blocks below the 4 64*64. And so on.

For each 64*64 block in the 4 64*64 blocks in Figure 3, each 64*64 block can be divided into 64 8*8 blocks, that is, 4 blocks in Figure 3 The small blocks in each big block in the big block are shown, and each small block represents an 8*8 block. For each 64*64 block, the reading order of the raw_fetch circuit is shown by the arrow in Figure 3. That is, when the raw_fetch circuit reads each 64*64 block, it follows from left to right, and then from top to bottom. Read each 8*8 block in sequence.

Further, for each 8*8 small block, the reading sequence of the raw_fetch circuit can be read in a column-first-line manner as shown in FIG. 4. Specifically, FIG. 4 shows a schematic diagram of any 8*8 block in any 64*64 large block and an 8*8 block directly below and adjacent to it. As shown in Figure 4, when the raw_fetch circuit reads each 8*8 block, it first reads the first column of the 8*8, and then reads the next column to the right until the 8*8 is read. After the small block, read the next 8*8 small block on the right side adjacent to the 8*8 small block, and so on.

The raw_fetch circuit inputs image data to the DWT computing device 100 in the above sequence. Specifically, the raw_fetch circuit can input image data to the Column circuit 110 in the DWT computing device 100 as a data block to be processed, so that the Column circuit 110 can proceed further. deal with. The DWT operation device 100 of the embodiment of the present application mainly includes three circuits: Column circuit 110, Permuter circuit 120, and Row circuit 130. These three parts are described in detail below.

The first is the Column circuit 110. The Column circuit 110 can be used to generate an intermediate data block after performing DWT operations on the data block to be processed input by column, and output the intermediate data block to the Permuter circuit 120 by column, or it can be said that the Column circuit 110 Used to complete the dwt column transformation.

Specifically, the structure of the Column circuit 110 may be as shown in FIG. 5. Specifically, the Column circuit 110 can be used to perform DWT53 operations and/or DWT97 operations. For example, the Column circuit 110 may include a DWT53 unit (ie, "dwt_53" in Figure 2) and a DWT97 unit (ie, "dwt_97" in Figure 2), where the dwt_53 unit can be used in lossless mode, and the dwt_97 unit can be used in Loss mode.

Optionally, the Column circuit 110 may also include an address calculation unit (ie, "col_pst" in FIG. 2), through which the col_pst unit selects to output the input data block to be processed to the DWT53 unit, so as to use the DWT53 operation process for processing; and / Or, choose to output the input data block to be processed to the DWT97 unit to use the DWT97 operation process for processing.

It should be understood that, for the to-be-processed data block input to the Column circuit 110, the input to-be-processed data block may refer to the data read and input in columns by the raw_fetch circuit. Specifically, as shown in Fig. 4, for ease of description, a coordinate system with row number and column number as the axis is established. Therefore, for two 8*8 small blocks adjacent to each other as shown in FIG. 4, each pixel can be expressed in the form of coordinates.

For example, for the first pixel in the upper left corner of the first 8*8 block in Figure 4, its coordinates can be expressed as (1,1), which represents the pixel in the first row and first column, and the pixel below it The coordinate of the point is (2,1), which represents the pixel point in the second row and first column, and so on. For the second 8*8 small block, the coordinates of the first pixel in the upper left corner are (9,1), which means it is the pixel in the ninth row and the first column, which is the 8*8 The coordinates of the small block are further calculated on the basis of the previous 8*8 small block, and so on.

According to the above representation, for the pixels shown in FIG. 3, the coordinate system can also be established. As shown in Figure 3, the four 64*64 blocks can be based on the first pixel in the upper left corner of the first 64*64 block, and the coordinates of other pixels can be calculated in turn; corresponding to Figure 4, this figure is shown The first 8*8 small block in the upper left corner of the first 64*64 block in 3 and the adjacent 8*8 small block directly below it.

It should be understood that, as shown in FIG. 4, the raw_fetch circuit reads the data of a column of pixels in each cycle. Specifically, the DWT53 unit of the embodiment of the present application is used to perform DWT53 operations on the input data, where the DWT53 operation process may be as shown in FIG. 6, where there are 9 p0 to p8 on the leftmost side in FIG. The pixel is the input image column data. In other words, each cycle inputs 9 pixels of data, where the 9 pixels of data can refer to any column of 8 pixels and one compensated pixel. For example, as shown in Figure 4, input 8 pixels in the first column and a pixel directly below it, a total of 9 pixels, which is shown by the diagonal square in Figure 4, as the input data in the calculation process of the DWT53, namely Corresponding to a total of 9 pixels from p0 to p8.

As shown in FIG. 6, for the image data of 9 pixels input by any cycle, after 4 stages (stg1 to stg4) pipeline calculation, 4 low-frequency data L0-L3 and 4 high-frequency data H0-H3 are obtained. Among them, as shown in Figure 6, during the operation of DWT53, the plus sign indicates that the adder performs addition; the minus sign indicates that the subtractor performs subtraction; rd indicates that the lower data is discarded; the "2" of the adder before rd refers to this The addition operation corresponding to the adder is the input result +2, which is specified by the J2K standard.

In addition, for the calculation process of the DWT53 of the image data of 9 pixels input by any cycle, there is an intermediate result h3, for example, the intermediate result h3 is marked with an asterisk as shown in FIG. 6. The intermediate result h3 needs to be used in the subsequent calculation process. For example, the intermediate result h3 obtained corresponding to the current input data can be used in the DWT53 calculation process of a column of data directly below the current input data, such as the intermediate result h3 can be used as the substitution data at the dotted minus sign as shown in Figure 6. Wherein, if the currently input data is performing the calculation process as shown in FIG. 6 and there is no corresponding intermediate result h3 obtained from the previous data, the data substituted at the minus sign of the dotted line can be the preset value.

For example, as shown in Figure 4, assuming that the data currently input to the DWT53 operation process is the first column of 8 pixels and one compensation pixel, then after the calculation process shown in Figure 6, there is no other input data before it. Therefore, the data substituted at the dotted minus sign of the first column of data may be a preset value set in advance. In addition, in the calculation process shown in FIG. 6, the intermediate result h3 marked with an asterisk can be obtained, which is denoted as h31 here for the convenience of distinction. After that, when the data input in the DWT53 operation process is the first column of the second 8*8 block as shown in Figure 4, that is, the pixel in the column where the pixel with the coordinate (9, 1) is located (I.e. the coordinates are (9,1) to (16,1)) and a compensation pixel below it. When the set of input data is in the calculation process shown in Figure 6, the dashed minus sign in Figure 6 is substituted The value is the aforementioned intermediate result h31, and the intermediate result marked with a new asterisk is further obtained, which can be expressed as h32, for example. By analogy, according to the above process, multiple intermediate results h3 can be obtained during the operation of the DWT53.

According to the output data sequence of the raw_fetch circuit, the DWT53 operation process is used to sequentially process the input data of each cycle, which will not be repeated here.

Similarly, the DWT97 unit is used to perform DWT97 operations on the input data, where the DWT53 operation process can be as shown in Figure 7. In the figure, p0～p10 are the input image column data, where the 11 pixels can refer to any A column of 8 pixels and 3 compensated pixels. For example, as shown in Figure 4, for the 8 pixels in the fourth column of the input, and the three pixels directly below, a total of 11 pixels, that is, as shown by the cross-line square in Figure 4, are used as input in the calculation process of the DWT97 The data corresponds to a total of 11 pixels from p0 to p10.

As shown in FIG. 7, for the image data of 11 pixels input by any cycle, after 12 stages (stg1 to stg12) pipeline calculation, 4 low-frequency data L0~L3 and 4 high-frequency data H0~H3 are obtained. Among them, in the DWT97 operation process, the plus sign corresponds to the adder for addition; the minus sign indicates that the subtractor performs subtraction; the multiplication sign indicates that the multiplier performs multiplication; the α, β, γ, and δ before the multiplication sign indicate each The coefficient multiplied by the multiplier, for example, the specific value of the coefficient may be specified by the J2K standard.

In addition, there are intermediate results h3 and a3 for the DWT97 calculation process of the image data of 11 pixels input by any cycle. For example, the intermediate results marked with an asterisk as shown in Figure 6 can be called a3 respectively (corresponding to Figure 7 The asterisk on the right) and h3 (corresponding to the asterisk on the left in Figure 7). The intermediate results a3 and h3 also need to be used in subsequent calculation processes. For example, the intermediate results a3 and h3 obtained corresponding to the current input data can be used in the DWT53 calculation process of the adjacent column of data directly below the current input data. For example, the intermediate results a3 and h3 can be divided into half as the substitution data at the dotted line plus sign and dotted line minus sign as shown in FIG. 7. Among them, if the currently input data is in the calculation process shown in Figure 7, there is no corresponding intermediate results a3 and h3 obtained from the previous data, the data substituted at the dotted plus sign and dotted minus sign can be Is the default value.

For example, as shown in Figure 4, assuming that the data currently input to the DWT97 operation process is the 8 pixels in the fourth column and the three compensation pixels below, then in the calculation process shown in Figure 7, the There is no other input data. Therefore, the data substituted at the dotted plus sign and dotted minus sign of the fourth column of data can be preset values set in advance. In addition, in the calculation process as shown in Figure 7, the intermediate results a3 and h3 marked with asterisks can be obtained. For the convenience of distinction, they are represented as a31 and h31 respectively here. After that, when the data input in the DWT97 operation process is the fourth column of the second 8*8 block as shown in Figure 4, that is, the pixel in the column where the pixel with the coordinate (9, 4) is located (I.e. the coordinates are (9,4) to (16,4)) and the 3 compensation pixels below it. When this group of input data is in the calculation process shown in Figure 7, the dotted line minus sign in Figure 7 is substituted The value of is the above calculation result h31, and the value substituted in the dotted plus sign in FIG. 7 is the above calculation result a31, and the new calculation result marked with an asterisk is further obtained, which can be expressed as a32 and h32, for example.

It should be understood that for the above calculation process of DWT53 and DWT97, since the calculation process of the image data of each cycle needs to use part of the intermediate data of the corresponding upper data, the Column circuit 110 may also include a storage unit. Each storage unit may be a memory, for example, including random access memory (Random Access Memory, RAM) to save the intermediate results h3 that need to be saved during the operation of DWT53 and the intermediate results a3 and a3 that need to be saved during the operation of DWT97. h3. For example, the Column circuit 110 may include two groups of storage units, which are referred to herein as the first storage unit group col8_ram and the second storage unit group col64_ram, respectively, for storing the calculation results marked with an asterisk in the foregoing process. Wherein, the first storage unit group and the second storage unit group may respectively include one or more storage units.

Specifically, as shown in FIG. 5, the Column circuit 110 can be configured to include 4 memories, of which 2 memories are used to store the operation process of DWT53 and h3 in the operation process of DWT97, for example, as shown in FIG. 5 col8_ram_h and col64_ram_h; the other two memories are used to store a3 during the operation of DWT97, for example, col8_ram_a and col64_ram_a in Figure 5. Correspondingly, the first storage unit group col8_ram includes two storage units, namely col8_ram_h and col8_ram_a; the second storage unit group col64_ram includes two storage units, respectively, col64_ram_h and col64_ram_a.

It should be understood that, according to the above content, the calculation results marked with asterisks as shown in FIGS. 6 and 7 correspond to the calculation process for a column of input data directly below the currently input column of data. Then, suppose that for the image data with 256*256 pixels, as shown in Figure 3, for each 64*64 block, after calculating 8 8*8* small blocks in a row of the 64*64 block , Will go back and continue to calculate each 8*8 block in the next line, then you need to use the calculation result marked with the asterisk of each 8*8 block in the previous line until the 64*64 block is input. The Column circuit 110 can store the a3/h3 data generated in the calculation of 97/53 rows of 64*8 blocks through the set first storage unit group col8_ram, where a3 and h3 can be stored separately, and the first storage unit group includes The first storage unit and the second storage unit are used to store a3 and h3, respectively. For example, the first storage unit is used to store the first intermediate result h3 output after the DWT53 operation or the DWT97 operation of the first column of data, and the first intermediate result h3 is used for the DWT5 3 operation of the second column of data Process or the DWT97 calculation process, the first column of data here refers to any column of data, not necessarily the first column in position; the second storage unit is used to store the first column of data after the DWT97 operation The second intermediate result a3 is output, and the second intermediate result a3 is used in the DWT53 operation process of the second column of data. The first column of data is located directly above the second column of data and is the same as the second column of data. A column of adjacent data.

That is, col8_ram_h is set to store 64 h3 per row in Column circuit 110, and col8_ram_a is set to store 64 a3 per row. As shown in Figure 3, assuming that the first 64*64 block is calculated, then the second 64*64 block to the right will continue to be calculated, but the 64 a3 in the last row of the first 64*64 block The result of sum h3 is used when calculating the 64*64 block (not shown in FIG. 3) directly below the first 64*64 block. By analogy, after the calculation of the 4 64*64 blocks shown in Figure 3 is completed, 64*4 a3 and h3 values will be obtained. These values can be passed through the second storage unit group col64_ram set in the Column circuit 110 Save it. Similarly, a3 and h3 are stored separately, that is, col64_ram_h is set to store 64*4 h3 for each entire row in Column circuit 110, and col64_ram_a is set to store 64*4 a3 for each entire row.

Optionally, store the h3 of the DWT53 operation process and the h3 of the DWT97 operation process in the same ram. In this way, memory and power consumption can be saved, which is conducive to circuit miniaturization.

In addition, when DWT53 mode is selected, col8_ram_a and col64_ram_a can be disabled to save power consumption.

The Permute circuit (also called a row-column conversion circuit) 120 is described below. The Permuter circuit 120 is used for buffering the intermediate data blocks input in columns and outputting them to the Row circuit 130 according to rows, or it can be said that the Permuter circuit 120 is used for transposing the input intermediate data blocks and outputting them to Row circuit 130.

Specifically, the input data of the Permuter circuit 120 is the output data of the Column circuit 110. The Permuter circuit 120 stores the result of the column operation output by the Column circuit 110 in the register file, and then outputs the data in rows to the register file in the order of FIG. 8 Row circuit 130 for row operations.

For example, taking the calculation process of DWT97 as an example, the Permuter circuit 120 stores the input data in columns. As shown in Figure 8, when 11 columns of data are input, the input of the first 8*8 block is completed. , And when the next 8*8 small block is input, the Permuter circuit 120 can start to read and output the data to the Row circuit 130; at the same time, the Permuter circuit 120 is still storing the next 8* In the small block of 8, the input and output of the Permuter circuit 120 can be performed at the same time, and, except for the first clock cycle, the Permuter circuit 120 needs to wait for the Permuter circuit 120 to store 11 columns (that is, 11 columns represented by pmt0 as shown in FIG. After completing 8 columns of input, you can start reading in rows.

As shown in Figure 8, for the first 8*8 small block, in the order from top to bottom, Permuter circuit 120 sequentially outputs 11 pixels in each row, including 3 compensation pixels. For example, the output is as shown in Figure 8. The ellipse on the left shown includes 11 pixels, where tmp0 represents the compensated part. When the output of 8 rows of data is completed, that is, the output of the first 8*8 small block is completed, and the output of the second 8*8 small block on the right is continued, and 11 pixels are output in a row at a time. It includes 3 compensation pixels, for example, 11 pixels of the ellipse on the right as shown in FIG. 8 are output, where tmp1 represents the compensated part. By analogy, each 8*8 small block of image data is output in turn.

For another example, for the calculation process of DWT53, the difference from the output of DWT97 above is that the output data each time is 9 pixels, including 1 compensation pixel, that is, the calculation process of DWT53 and the compensation pixel of the foregoing DWT97 calculation process The number is different, resulting in different output data each time, but the output method and direction are the same. For the sake of brevity, I will not repeat it here.

It should be understood that the Permuter circuit 120 outputs each row in each 8*8 small block in the above-mentioned top-to-bottom manner; and for the four 64*64 blocks shown in FIG. 3, if each 8*8 block is The block of *8 is a unit, and the sequence of reading each unit by the Permuter circuit 120 is the same as that of FIG. 3, that is, from left to right, and then from top to bottom, which will not be repeated here.

The Row circuit 130 is described below. The Row circuit 130 is used to perform DWT row operations on the data input in rows and then output them in rows to complete the DWT calculation process of the DWT operation device 100, or it can be said that the Row circuit 130 is used to complete dwt row conversion.

Specifically, the calculation process of the Row circuit 130 and the Column circuit 110 are basically the same. The difference is that the data input in the Row circuit 130 is row data. For brevity, it will not be repeated here.

In addition, in terms of the use of ram resources, similar to the Column circuit 110, the Row circuit 130 also includes storage units. Each storage unit can be used to store the intermediate results h3 that need to be saved during the operation of DWT53 and the need for the operation of DWT97. Save the intermediate results a3 and h3. For example, the Row circuit 130 may include two groups of storage units, which are referred to herein as the third storage unit group col8_ram and the fourth storage unit group col64_ram, respectively, for storing intermediate calculation results marked with an asterisk during the operation. Wherein, the third storage unit group and the fourth storage unit group may respectively include one or more storage units.

Specifically, similar to the Column circuit 110, the Row circuit 130 can also be provided with four storage units as shown in FIG. 5, two memories are used to store the operation process of DWT53 and h3 in the operation process of DWT97, for example, set As shown in Figure 5, col8_ram_h and col64_ram_h; the other two memories are used to store a3 in the operation of DWT97, for example, set col8_ram_a and col64_ram_a in Figure 5. That is, the third storage unit group col8_ram includes two storage units, respectively, the third storage unit col8_ram_h and the fourth storage unit col8_ram_a; the fourth storage unit group col64_ram includes two storage units, respectively, col64_ram_h and col64_ram_a.

Among them, the third storage unit col8_ram_h is used to store the first intermediate result h3 output by the first row of data after the DWT53 operation or the DWT97 operation, and the first intermediate result h3 is used for the DWT5 of the second row of data. In the calculation process or the DWT97 calculation process, the first row of data here refers to any row of data, not necessarily the first row in position; the fourth storage unit col8_ram_a is used to store the first row of data after passing through the DWT97 The second intermediate result a3 output after the operation. The second intermediate result a3 is used in the DWT53 operation process of the second row of data. The first row of data is located to the left of the second row of data and is the same as the second row of data. Adjacent row of data.

Because in the calculation process of Row circuit 130, when processing the next 8*8 small block, it will use the currently processed 8*8 small block corresponding to the obtained and stored asterisk a3/h3 instead of Column The circuit 110 has the same operation process, it needs to wait for at least one row of 8*64 pixels to be completed before using it. Therefore, in Row circuit 130, the size of col8_ram (including col8_ram_h and col8_ram_a) can be set to 8*32bit (here it is assumed that each h3 or a3 occupies 32bit), instead of 64*32bit in Column circuit 110; the same, The size of row64_ram in Row circuit 130 can be set to 64*32bit instead of 256*32bit in Column circuit 110.

In addition, for the DWT97 operation process, the Row circuit 130 may also include a scaler, which is used to enlarge or reduce the DWT97 result. After the row conversion of the Row circuit 130 in the DWT97 process is completed, the output result {LL, HL, LH, HH} needs to be scaled once; while the DWT53 process does not need it. Therefore, a scaler can be added to the Row circuit 130.

Specifically, as shown in Figure 9, the output result of DWT97 requires 3-stage pipeline processing. Among them, in the first stage of pipeline (stg1 as shown in Figure 9), for the results output by DWT97 in rows, different coefficients (coeff) are determined by the scaler. For example, according to the size of the results output by DWT97 in rows, you can Correspondingly multiplied by the coefficient {k ² ,1}, or can also be multiplied by the coefficient {1,1/k ² }. For example, the selector on the left as shown in FIG. 9 can be used to select different coefficients for output according to different input data. Specifically, any data in the data block to be processed may be output as high-frequency data H or low-frequency data L after the operation of DWT97 in Column circuit 110. This data will subsequently pass through DWT97 in Row circuit 130. After the operation, the data may be output as any of the following four types: HH, HL, LH, LL. Therefore, for the four possible data types {HH, HL, LH, LL} input to the scaler, HL and LH are multiplied by the coefficient 1, HH is multiplied by the coefficient k ² , and LL is multiplied by the coefficient 1/k ² . Different coefficients are multiplied with the results output by DWT97 in rows.

Then in the second stage of pipeline (stg2 as shown in Figure 9), the result of the previous stage of pipeline is rounded and/or overflowed (clip) processing. The clip processing refers to if the data range exceeds the output The maximum or minimum value of the data is replaced by the corresponding maximum or minimum value.

Then in the third stage of pipeline (stg3 as shown in Figure 9), the selector according to the encoding mode, for example, the hardware can use a 1-bit signal to distinguish whether the encoding is lossy or lossless, so as to select the output data, which is the final Calculation results.

The difference with the DWT97 process is that in the DWT53 process, only one stage of pipeline processing is passed, that is, through sgt3 as shown in Figure 9, after the selector selects the encoding mode, the output data is the final calculation result.

Therefore, the DWT computing device provided in the embodiments of the present application is a hardware structure that can efficiently implement DWT operations, with high real-time performance and low power consumption. For example, in the above-mentioned embodiments of the present application, the processing speed can reach 8 pixels/cycle, which greatly The execution time and power consumption of the DWT operation are reduced; and the DWT operation device supports the switch between DWT97 and DWT53, with high flexibility, complete reuse of RAM resources in the two modes, and low resource consumption.

The embodiments of the present invention can be implemented by SoC FPGA.

Optionally, an embodiment of the present application also proposes an image processing device. Specifically, FIG. 10 shows a schematic block diagram of an image processing apparatus 200 according to an embodiment of the present application. As shown in FIG. 10, the image processing device 200 includes a DWT computing device 210 and a processing device 220.

Specifically, the DWT computing device may be the DWT computing device of the embodiment of the present application, for example, it may include the DWT computing device 100 of the embodiment of the present application. The DWT operation device 210 is used to perform DWT operation on the data block to be processed to generate wavelet coefficients, and transmit the wavelet coefficients to the processing device 220; the processing device 220 is used to perform at least one of the following processing on the wavelet coefficients: Noise reduction processing, DWT inverse operation, quantization processing and entropy coding processing.

For example, the image processing device 200 may be used to denoise signals based on DWT transformation. Specifically, firstly, wavelet transformation is performed on the noisy signal, that is, the wavelet transformation is performed by the DWT operation device 210 to generate wavelet coefficients; secondly, the wavelet coefficients obtained by the transformation are processed to remove the noise contained therein, that is, through The processing device 220 performs noise reduction processing. The noise reduction processing may be to perform noise reduction processing on the wavelet coefficients to remove the noise contained therein; finally, perform wavelet inverse transformation on the processed wavelet coefficients to obtain a denoised signal, That is, the DWT inverse operation is performed by the processing device 220, and the DWT inverse operation is to perform the DWT inverse transformation on the wavelet coefficients after the noise reduction processing, and output the de-sanded signal.

For another example, the image processing device 200 may also be used in the processing process of an encoder. The quantization processing of the processing device 220 may include: quantizing the wavelet coefficients according to a preset quantization step size, and sending the quantized wavelet coefficients to the entropy encoding device; the entropy encoding processing of the processing device 220 may Including: encoding the wavelet coefficient after the quantization process according to a preset encoding rule.

Optionally, the embodiment of the present application also proposes a movable platform. Specifically, FIG. 11 shows a schematic block diagram of a movable platform 300 according to an embodiment of the present application. As shown in FIG. 11, the movable platform 300 includes: a body 310; a power system 320, which is provided in the body 310, and is used to provide power for the movable platform 300; an image acquisition device 330, which is used to collect images; The processing device 340 is used to process the image. The image processing device 340 may be the image processing device in the embodiment of the application, for example, the image processing device 340 may be the image processing device 200 in the embodiment of the application. The image processing device 340 may include the DWT computing device in the embodiment of the present application, for example, may include the DWT computing device 100 in the embodiment of the present application.

The movable platform 300 in the embodiment of the present invention can refer to any movable device that can be moved in any suitable environment, for example, in the air (for example, a fixed-wing aircraft, a rotary-wing aircraft, or a fixed-wing aircraft or a rotary-wing aircraft without fixed wings or Aircraft without rotors), water (for example, ships or submarines), on land (for example, cars or trains), space (for example, space planes, satellites or probes), and any combination of the above various environments. The movable device may be an airplane, such as a drone (Unmanned Aerial Vehicle, referred to as "UAV" for short).

The body 310 may also be referred to as a body. The body may include a center frame and one or more arms connected to the center frame, and the one or more arms extend radially from the center frame. The tripod is connected to the fuselage to support the UAV during landing.

The power system 320 may include an electronic governor (referred to as an ESC for short), one or more propellers, and one or more motors corresponding to the one or more propellers, where the motors are connected between the electronic governor and the propellers, The motor and the propeller are arranged on the corresponding arm; the electronic governor is used to receive the driving signal generated by the flight controller, and provide a driving current to the motor according to the driving signal to control the speed of the motor. The motor is used to drive the propeller to rotate to provide power for the flight of the UAV, which enables the UAV to achieve one or more degrees of freedom of movement. It should be understood that the motor may be a DC motor or an AC motor. In addition, the motor can be a brushless motor or a brush motor.

The image acquisition device 330 includes a photographing device (for example, a camera, a video camera, etc.) or a visual sensor (for example, a monocular camera or a dual/multi-view camera, etc.).

Optionally, an embodiment of the present application also proposes a camera. Specifically, FIG. 12 shows a schematic block diagram of a camera 400 according to an embodiment of the present application. As shown in FIG. 12, the camera 400 includes: a housing 410; a lens assembly 420 arranged inside the housing 410; a sensor module 430 arranged inside the housing 410 and at the rear end of the lens assembly 420 for sensing passing The light of the lens assembly 420 generates an electric signal; and an image processing device 440 for processing the electric signal.

Wherein, the image processing device 440 may be an image processing device in an embodiment of the application, for example, the image processing device 440 may be an image processing device 200 in an embodiment of the application. The image processing device 440 may include the DWT computing device in the embodiment of the present application, for example, may include the DWT computing device 100 in the embodiment of the present application.

It should be understood that each circuit in the device of each embodiment of the present application may also include a memory and processor-based part, where each memory is used to store instructions for executing the method of each embodiment of the present application, and the processor executes The foregoing instructions enable the corresponding part to execute part of the methods in the embodiments of the present application.

It should be understood that the processor mentioned in the embodiments of this application may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), and application-specific integrated circuits ( Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.

It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. The volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache. By way of exemplary but not restrictive description, many forms of RAM are available, such as static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (Synchlink DRAM, SLDRAM) ) And Direct Rambus RAM (DR RAM).

It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated in the processor.

It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

The embodiments of the present application also provide a computer-readable storage medium on which instructions are stored, and when the instructions are run on a computer, the computer executes the methods of the foregoing method embodiments.

An embodiment of the present application also provides a computing device, which includes the computer-readable storage medium described above.

The embodiments of the present application can be applied to aircraft, especially in the field of drones.

It should be understood that the division of circuits, sub-circuits, and sub-units in each embodiment of the present application is only illustrative. A person of ordinary skill in the art may be aware that the circuits, sub-circuits, and sub-units of the examples described in the embodiments disclosed herein can be further divided or combined.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website, computer, server, or data center through a cable (such as Coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) to transmit to another website, computer, server, or data center. A computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrated with one or more available media. Available media can be magnetic media (for example, floppy disks, hard drives, tapes), optical media (for example, high-density digital video discs (Digital Video Disc, DVD)), or semiconductor media (for example, solid state disks (Solid State Disk, SSD)) )Wait.

It should be understood that each embodiment of the present application is described by taking a total bit width of 16 bits as an example, and each embodiment of the present application may be applicable to other bit widths.

It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment" or "in an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner.

It should be understood that, in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application. The implementation process constitutes any limitation.

It should be understood that in the embodiments of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean that B is determined only according to A, and B can also be determined according to A and/or other information.

It should be understood that the term "and/or" in this article is only an association relationship describing the associated objects, indicating that there can be three types of relationships, for example, A and/or B can mean: A alone exists, and both A and B exist. , There are three cases of B alone. In addition, the character "/" in this text generally indicates that the associated objects before and after are in an "or" relationship.

A person of ordinary skill in the art may be aware that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

A DWT arithmetic device, characterized in that it comprises a column circuit (110), an interleaver circuit (120) and a row circuit (130),

The column circuit (110) is configured to: receive preset data blocks to be processed, perform DWT operations on the data blocks to be processed in columns to generate intermediate data blocks, and output the intermediate data blocks to the interleaver in columns In the device circuit (120);

The interleaver circuit (120) is used to: output the intermediate data block input in columns to the row circuit (130) in rows;

The row circuit (130) is used for performing DWT operation on the intermediate data block input by row to obtain an operation result.
The DWT operation device according to claim 1, wherein the DWT operation includes DWT53 operation and/or DWT97 operation.
The DWT operation device according to claim 2, wherein the column circuit (110) includes a first DWT53 unit and a first DWT97 unit, and the row circuit (120) includes a second DWT53 unit and a second DWT97 unit ,

The first DWT53 unit is used to: perform the DWT53 operation on the to-be-processed data block input by column;

The first DWT97 unit is used to: perform the DWT97 operation on the to-be-processed data block input by column;

The second DWT53 unit is used to: perform the DWT53 operation on the intermediate data block input by line;

The second DWT97 unit is used for: performing the DWT97 operation on the intermediate data block input by line.
The DWT computing device according to claim 3, wherein the column circuit (110) comprises:

A first address calculation unit, configured to output the to-be-processed data block input by column to the first DWT53 unit and/or the first DWT97 unit;

The row circuit (120) includes:

The second address calculation unit is configured to output the intermediate data block input in rows to the second DWT53 unit and/or the second DWT97 unit.
The DWT computing device according to any one of claims 2 to 4, wherein the column circuit (110) comprises at least one storage unit, and the at least one storage unit is used to store the input first column data At least one intermediate result output after the DWT53 operation and/or the DWT97 operation, and the at least one intermediate result is used for the DWT53 operation and/or the second column of data corresponding to the first column of data In the DWT97 operation process, the first column of data is any column of data in the input data block to be processed.
The DWT computing device according to claim 5, wherein the at least one storage unit comprises a first storage unit and a second storage unit,

The first storage unit is used to store the first intermediate result output after the DWT53 operation or the DWT97 operation of the first column data, and the first intermediate result is used for the second column data The DWT53 operation process or the DWT97 operation process;

The second storage unit is used to store a second intermediate result output after the DWT97 operation of the first column of data, and the second intermediate result is used in the DWT53 operation process of the second column of data The first column of data is a column of data located directly above the second column of data and adjacent to the second column of data.
The DWT computing device according to any one of claims 2 to 4, wherein the row circuit (130) comprises at least one storage unit, and the at least one storage unit is used to store the first row of input data At least one intermediate result output after the DWT53 operation and/or the DWT97 operation, the at least one intermediate result is used for the DWT53 operation and/or the second row of data corresponding to the first row of data In the DWT97 operation process, the first row of data is any row of data in the input intermediate data block.
The DWT computing device according to claim 7, wherein the at least one storage unit includes a third storage unit and a fourth storage unit,

The third storage unit is used to store a third intermediate result output after the DWT53 operation or the DWT97 operation of the first row of data, and the third intermediate result is used for the second row of data The DWT5 3 operation process or the DWT97 operation process;

The fourth storage unit is configured to store a fourth intermediate result output after the DWT97 operation of the first row of data, and the fourth intermediate result is used in the DWT53 operation process of the second row of data The first row of data is a row of data located to the left of the second row of data and adjacent to the second row of data.
The DWT computing device according to any one of claims 2 to 8, wherein the row circuit (130) further comprises:

The scaler is used to enlarge or reduce the output result of the DWT97 operation in the row circuit (130).
A method for processing data in a DWT computing device, wherein the DWT computing device includes a column circuit, an interleaver circuit, and a row circuit, and the method includes:

Obtain preset data blocks to be processed;

Performing a DWT operation on the to-be-processed data block by column by the column circuit to generate an intermediate data block, and output the intermediate data block to the interleaver circuit by column;

Output the intermediate data blocks input in columns to the row circuit in rows by the interleaver circuit;

DWT operation is performed on the intermediate data block input by row through the row circuit to obtain the operation result.
The method according to claim 10, wherein the DWT operation comprises DWT53 operation and/or DWT97 operation.
The method according to claim 11, wherein the column circuit includes a first DWT53 unit and a first DWT97 unit, and the row circuit includes a second DWT53 unit and a second DWT97 unit,

The performing DWT operation on the data block to be processed by the column circuit to generate the intermediate data block by column includes:

Through the first DWT53 unit, perform the DWT53 operation on the to-be-processed data block input by column to generate the intermediate data block, or,

Using the first DWT97 unit to perform the DWT97 operation on the to-be-processed data block input by column to generate the intermediate data block;

The performing DWT operation on the intermediate data block input by row by the row circuit includes:

Perform the DWT53 operation on the intermediate data block input by row through the second DWT53 unit, or,

Through the second DWT97 unit, the DWT97 operation is performed on the intermediate data block input by line.
The method according to claim 12, wherein the column circuit further comprises a first address calculation unit, and the row circuit further comprises a second address calculation unit,

The method also includes:

Output the to-be-processed data block input by column to the first DWT53 unit and/or the first DWT97 unit through the first address calculation unit;

Through the second address calculation unit, the intermediate data blocks input in rows are output to the second DWT53 unit and/or the second DWT97 unit.
The method according to any one of claims 11 to 13, wherein the column circuit includes at least one memory cell,

The DWT operation in the column circuit includes:

The at least one storage unit stores at least one intermediate result of the input first column of data after the DWT53 operation and/or the DWT97 operation, and the at least one intermediate result is used to compare with the first column For the DWT53 operation and/or the DWT97 operation process of the second column of data corresponding to the data, the first column of data is any column of data in the input data block to be processed.
The method according to claim 14, wherein the at least one storage unit comprises a first storage unit and a second storage unit,

Said storing at least one intermediate result outputted after the DWT53 operation and/or the DWT97 operation of the input first column of data through the at least one storage unit includes:

The first storage unit stores the first intermediate result of the first column of data output after the DWT53 operation or the DWT97 operation, and the first intermediate result is used for all of the second column of data The DWT5 3 operation process or the DWT97 operation process;

Through the second storage unit, the second intermediate result output after the DWT97 operation of the first column of data is stored, and the second intermediate result is used in the DWT53 operation process of the second column of data, The first column of data is a column of data located directly above the second column of data and adjacent to the second column of data.
The method according to any one of claims 11 to 13, wherein the row circuit includes at least one storage unit,

The DWT operation in the row circuit includes:

The at least one storage unit stores at least one intermediate result of the input first row of data after the DWT53 operation and/or the DWT97 operation, and the at least one intermediate result is used to compare with the first row The DWT53 operation and/or the DWT97 operation process of the second row of data corresponding to the data, the first row of data is any row of data in the input intermediate data block.
The method according to claim 16, wherein the at least one storage unit includes a third storage unit and a fourth storage unit,

Said storing at least one intermediate result outputted after the DWT53 operation and/or the DWT97 operation of the first row of input data by the at least one storage unit includes:

Through the third storage unit, the third intermediate result of the first row of data output after the DWT53 operation or the DWT97 operation is stored, and the third intermediate result is used for all of the second row of data. The DWT53 operation process or the DWT97 operation process;

The fourth storage unit stores the fourth intermediate result output after the DWT97 operation of the first row of data, and the fourth intermediate result is used in the DWT53 operation process of the second row of data, The first row of data is a row of data located to the left of the second row of data and adjacent to the second row of data.
The method according to any one of claims 11 to 17, wherein the row circuit further comprises: a scaler;

The method also includes:

Through the scaler, the output result of the DWT97 operation in the row circuit is enlarged or reduced, and then output by row.
An image processing device, characterized by comprising: a processing device and the DWT computing device according to any one of claims 1 to 9;

The DWT operation device is configured to perform DWT operation on the data block to be processed to generate wavelet coefficients, and transmit the wavelet coefficients to the processing device;

The processing device is configured to perform one or more of the following processing on the wavelet coefficients:

Noise reduction processing, DWT inverse operation, quantization processing and entropy coding processing.
A movable platform, characterized in that it comprises:

Body

The power system is arranged in the body and used to provide power for the movable platform;

An image capture device for capturing images; and

The image processing device according to claim 19, which is used to process the image.
A camera, characterized in that it comprises:

shell;

The lens assembly is arranged inside the housing;

A sensor module, arranged inside the housing and at the rear end of the lens assembly, for sensing light passing through the lens assembly and generating electrical signals; and

The image processing device according to claim 19, configured to process the electrical signal.