WO2021016893A1 - Dwt computing device, method, image processing device, and movable platform - Google Patents
Dwt computing device, method, image processing device, and movable platform Download PDFInfo
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- WO2021016893A1 WO2021016893A1 PCT/CN2019/098457 CN2019098457W WO2021016893A1 WO 2021016893 A1 WO2021016893 A1 WO 2021016893A1 CN 2019098457 W CN2019098457 W CN 2019098457W WO 2021016893 A1 WO2021016893 A1 WO 2021016893A1
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- a camera including: a housing; a lens assembly arranged inside the housing; a sensor module arranged inside the housing and at the rear end of the lens assembly for sensing passing through The light of the lens assembly generates an electric signal; and the image processing device in the second aspect is used to process the electric signal.
- FIG. 4 is another schematic diagram of the image data reading sequence of the embodiment of the present application.
- FIG. 6 is a schematic diagram of the operation process of DWT53 in an embodiment of the present application.
- Fig. 10 is a schematic block diagram of an image processing device according to an embodiment of the present application.
- the DWT computing device 100 may or may not include the raw_fetch circuit.
- the embodiment of the present application takes the raw_fetch circuit not belonging to the DWT computing device 100 as an example for description, but the embodiment of the present application is not limited to this.
- intermediate results h3 and a3 for the DWT97 calculation process of the image data of 11 pixels input by any cycle.
- the intermediate results marked with an asterisk as shown in Figure 6 can be called a3 respectively (corresponding to Figure 7 The asterisk on the right) and h3 (corresponding to the asterisk on the left in Figure 7).
- the intermediate results a3 and h3 also need to be used in subsequent calculation processes.
- the intermediate results a3 and h3 obtained corresponding to the current input data can be used in the DWT53 calculation process of the adjacent column of data directly below the current input data.
- the Column circuit 110 can be configured to include 4 memories, of which 2 memories are used to store the operation process of DWT53 and h3 in the operation process of DWT97, for example, as shown in FIG. 5 col8_ram_h and col64_ram_h; the other two memories are used to store a3 during the operation of DWT97, for example, col8_ram_a and col64_ram_a in Figure 5.
- the first storage unit group col8_ram includes two storage units, namely col8_ram_h and col8_ram_a; the second storage unit group col64_ram includes two storage units, respectively, col64_ram_h and col64_ram_a.
- col8_ram_h is set to store 64 h3 per row in Column circuit 110
- col8_ram_a is set to store 64 a3 per row.
- the first 64*64 block is calculated, then the second 64*64 block to the right will continue to be calculated, but the 64 a3 in the last row of the first 64*64 block
- the result of sum h3 is used when calculating the 64*64 block (not shown in FIG. 3) directly below the first 64*64 block.
- 64*4 a3 and h3 values will be obtained. These values can be passed through the second storage unit group col64_ram set in the Column circuit 110 Save it.
- the Permuter circuit 120 stores the input data in columns. As shown in Figure 8, when 11 columns of data are input, the input of the first 8*8 block is completed. , And when the next 8*8 small block is input, the Permuter circuit 120 can start to read and output the data to the Row circuit 130; at the same time, the Permuter circuit 120 is still storing the next 8* In the small block of 8, the input and output of the Permuter circuit 120 can be performed at the same time, and, except for the first clock cycle, the Permuter circuit 120 needs to wait for the Permuter circuit 120 to store 11 columns (that is, 11 columns represented by pmt0 as shown in FIG. After completing 8 columns of input, you can start reading in rows.
- the difference with the DWT97 process is that in the DWT53 process, only one stage of pipeline processing is passed, that is, through sgt3 as shown in Figure 9, after the selector selects the encoding mode, the output data is the final calculation result.
- the noise reduction processing may be to perform noise reduction processing on the wavelet coefficients to remove the noise contained therein; finally, perform wavelet inverse transformation on the processed wavelet coefficients to obtain a denoised signal, That is, the DWT inverse operation is performed by the processing device 220, and the DWT inverse operation is to perform the DWT inverse transformation on the wavelet coefficients after the noise reduction processing, and output the de-sanded signal.
- the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
- the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
- the volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache.
- the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component
- the memory storage module
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Abstract
A DWT computing device, a method, an image processing device, and a movable platform. The DWT computing device comprises: a column circuit, a permuter circuit, and a row circuit; the column circuit is configured to receive preset data blocks to be processed, perform DWT computing on said data blocks in columns to generate intermediate data blocks, and output the intermediate data blocks to the permuter circuit in columns; the permuter circuit is configured to output the intermediate data blocks input in columns into the row circuit in rows; the row circuit is configured to perform DWT computing on the intermediate data blocks input in rows to obtain the computing result. According to the DWT computing device, the method, the image processing device, and the movable platform provided in the present application, DWT computing can be efficiently realized, and high real-time performance and low power consumption can be realized.
Description
版权申明Copyright statement
本专利文件披露的内容包含受版权保护的材料。该版权为版权所有人所有。版权所有人不反对任何人复制专利与商标局的官方记录和档案中所存在的该专利文件或者该专利披露。The content disclosed in this patent document contains copyrighted material. The copyright belongs to the copyright owner. The copyright owner does not object to anyone copying the patent document or the patent disclosure in the official records and archives of the Patent and Trademark Office.
本申请涉及图像处理领域,尤其涉及一种离散小波变换运算装置、方法、图像处理装置和可移动平台。This application relates to the field of image processing, and in particular to a discrete wavelet transform operation device, method, image processing device and movable platform.
离散小波变换(Discrete Wavelet Transform,DWT)具有良好的时频域局部化分析性能,它具有“数学显微镜”聚焦的功能,现已应用于多个信号处理的领域,尤其在图像压缩领域,出现了很多基于小波变换的静止图像压缩方案。Discrete Wavelet Transform (DWT) has good localized analysis performance in time and frequency domain. It has the function of "mathematical microscope" focusing. It has been applied to many signal processing fields, especially in the field of image compression. Many still image compression schemes based on wavelet transform.
现有技术中,常用的实现DWT的方式是:在通用处理器中,用多条指令实现DWT的各步运算。这种实现方式运算速度慢,实时性低。In the prior art, a commonly used way to implement DWT is: in a general-purpose processor, multiple instructions are used to implement each step of the DWT operation. This kind of implementation has slow calculation speed and low real-time performance.
例如,在图像处理领域,通常用DWT97来实现有损压缩,用DWT53来实现无损压缩。DWT97包含大量的乘法和加法运算,DWT53包含大量的加法运算,如果调用通用处理器中的加法和乘法指令,需要调用很多次,指令的调度是在软件层面进行的,由于软件的处理实时性很低,这大大增加了DWT运算执行的时间,所以这种实现方式的实时性很低;另外这种实现方式需要读写多次片上缓存,而读写片上缓存的功耗很大,所以这种实现方式的功耗也很大。For example, in the field of image processing, DWT97 is usually used to achieve lossy compression, and DWT53 is used to achieve lossless compression. DWT97 contains a large number of multiplication and addition operations, DWT53 contains a large number of addition operations. If you call the addition and multiplication instructions in a general-purpose processor, you need to call many times. The scheduling of instructions is performed at the software level, because the software is very real-time. Low, which greatly increases the execution time of the DWT operation, so the real-time performance of this implementation is very low; in addition, this implementation requires multiple reads and writes of the on-chip cache, and the power consumption of reading and writing the on-chip cache is high, so this The power consumption of the implementation is also large.
发明内容Summary of the invention
本申请提供了一种DWT运算装置、方法、图像处理装置和可移动平台,能够高效实现DWT运算,实时性高,功耗低。This application provides a DWT computing device, method, image processing device, and movable platform, which can efficiently implement DWT computing, with high real-time performance and low power consumption.
第一方面,提供了一种DWT运算装置,包括:列电路、交织器电路和 行电路,所述列电路用于:接收预设的待处理数据块,对所述待处理数据块按列进行DWT运算生成中间数据块,并将所述中间数据块按列输出至所述交织器电路中;所述交织器电路用于:对按列输入的所述中间数据块按行输出至所述行电路中;所述行电路用于:将按行输入的所述中间数据块进行DWT运算,以获得运算结果。In a first aspect, a DWT operation device is provided, including: a column circuit, an interleaver circuit, and a row circuit. The column circuit is used to: receive a preset data block to be processed, and perform column-based processing on the data block to be processed. DWT operation generates intermediate data blocks, and outputs the intermediate data blocks to the interleaver circuit in columns; the interleaver circuit is used to: output the intermediate data blocks input in columns to the row in rows In the circuit; the row circuit is used to perform a DWT operation on the intermediate data block input by row to obtain the operation result.
第二方面,提供了一种用于DWT运算装置中处理数据的方法,其特征在于,所述DWT运算装置包括:列电路、交织器电路和行电路,所述方法包括:获取预设的待处理数据块;通过所述列电路对所述待处理数据块按列进行DWT运算生成中间数据块,并将所述中间数据块按列输出至所述交织器电路中;通过所述交织器电路对按列输入的所述中间数据块按行输出至所述行电路中;通过所述行电路将按行输入的所述中间数据块进行DWT运算,以获得运算结果。In a second aspect, a method for processing data in a DWT operation device is provided, wherein the DWT operation device includes a column circuit, an interleaver circuit, and a row circuit, and the method includes: obtaining a preset waiting Process data blocks; perform DWT operations on the to-be-processed data blocks by the column circuit to generate intermediate data blocks, and output the intermediate data blocks to the interleaver circuit in columns; pass the interleaver circuit The intermediate data blocks input in columns are output to the row circuit in rows; and the intermediate data blocks input in rows are subjected to a DWT operation through the row circuit to obtain an operation result.
第三方面,提供了一种图像处理装置,包括:处理装置以及第一方面或第一方面的任意可能的实现方式中的DWT运算装置。所述DWT运算装置用于对所述待处理数据块进行DWT运算后生成小波系数,并将所述小波系数传输至所述处理装置;所述处理装置用于对所述小波系数进行以下一种或多种处理:降噪处理,DWT逆运算,量化处理和熵编码处理。In a third aspect, an image processing device is provided, including: a processing device and a DWT computing device in the first aspect or any possible implementation of the first aspect. The DWT operation device is used to perform DWT operation on the data block to be processed to generate wavelet coefficients, and transmit the wavelet coefficients to the processing device; the processing device is used to perform one of the following on the wavelet coefficients Or multiple processing: noise reduction processing, DWT inverse operation, quantization processing and entropy coding processing.
第四方面,提供了一种可移动平台,包括:机体;动力系统,设于所述机体内,用于为所述可移动平台提供动力;图像采集装置,用于采集图像;以及第二方面中的图像处理装置,用于对所述图像进行处理。In a fourth aspect, a movable platform is provided, including: a body; a power system, which is provided in the body, and is used to provide power to the movable platform; an image acquisition device, which is used to collect images; and the second aspect The image processing device in is used to process the image.
第五方面,提供了一种相机,包括:外壳;镜头组件,设于所述外壳内部;传感器模块,设于所述外壳内部并设于所述镜头组件的后端,用于感知通过所述镜头组件的光并生成电信号;以及第二方面中的图像处理装置,用于对所述电信号进行处理。In a fifth aspect, a camera is provided, including: a housing; a lens assembly arranged inside the housing; a sensor module arranged inside the housing and at the rear end of the lens assembly for sensing passing through The light of the lens assembly generates an electric signal; and the image processing device in the second aspect is used to process the electric signal.
图1是本申请实施例的DWT运算装置的示意性框图。Fig. 1 is a schematic block diagram of a DWT computing device according to an embodiment of the present application.
图2是本申请实施例的DWT运算装置的应用场景的示意图。Fig. 2 is a schematic diagram of an application scenario of a DWT computing device according to an embodiment of the present application.
图3是本申请实施例的图像数据的读取顺序的示意图。Fig. 3 is a schematic diagram of a reading sequence of image data in an embodiment of the present application.
图4是本申请实施例的图像数据的读取顺序的另一个示意图。FIG. 4 is another schematic diagram of the image data reading sequence of the embodiment of the present application.
图5是本申请实施例的DWT运算装置中Column电路的结构的示意图。FIG. 5 is a schematic diagram of the structure of the Column circuit in the DWT computing device of the embodiment of the present application.
图6是本申请实施例的DWT53的运算过程的示意图。FIG. 6 is a schematic diagram of the operation process of DWT53 in an embodiment of the present application.
图7是本申请实施例的DWT97的运算过程的示意图。Fig. 7 is a schematic diagram of the operation process of DWT97 in an embodiment of the present application.
图8是本申请实施例的DWT运算装置中Permuter电路读取图像数据的示意图。FIG. 8 is a schematic diagram of image data read by the Permuter circuit in the DWT computing device of the embodiment of the present application.
图9是本申请实施例的DWT运算装置的Row电路的示意图。FIG. 9 is a schematic diagram of the Row circuit of the DWT computing device according to an embodiment of the present application.
图10是本申请实施例的图像处理装置的示意性框图。Fig. 10 is a schematic block diagram of an image processing device according to an embodiment of the present application.
图11是本申请实施例的可移动平台的示意性框图。Fig. 11 is a schematic block diagram of a movable platform according to an embodiment of the present application.
图12是本申请实施例的相机的示意性框图。Fig. 12 is a schematic block diagram of a camera according to an embodiment of the present application.
下面将结合附图,对本申请实施例中的技术方案进行描述。The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings.
除非另有定义,本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请。Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of this application. The terms used in the description of the application herein are only for the purpose of describing specific embodiments, and are not intended to limit the application.
本申请实施例提出了一种DWT运算装置100,如图1所示,该DWT运算装置100为一个硬件结构,其主要包括三个电路,分别为列(Column)电路110、交织器(Permuter)电路120以及行(Row)电路130。具体地,对于预设的待处理数据块,例如,该DWT运算装置100可以接收该待处理数据块;该Column电路110用于对该待处理数据块按列进行DWT运算生成中间数据块,并将该中间数据块按列输出至该Permuter电路120中,也就是将输入的待处理数据块进行DWT列变换后输出至Permuter电路120中;该Permuter电路120用于将按列输入的中间数据块按行读取并输出至Row电路130中;该Row电路130用于将按行输入的该中间数据块进行DWT运算,以获得运算结果,也就是将按行输入的中间数据块进行DWT行变换后按行输出,以完成DWT的计算过程。The embodiment of the present application proposes a DWT computing device 100. As shown in FIG. 1, the DWT computing device 100 is a hardware structure, which mainly includes three circuits, namely a column circuit 110 and an interleaver (Permuter). Circuit 120 and Row circuit 130. Specifically, for a preset data block to be processed, for example, the DWT computing device 100 may receive the data block to be processed; the Column circuit 110 is used to perform DWT operations on the data block to be processed in columns to generate intermediate data blocks, and The intermediate data block is output to the Permuter circuit 120 in columns, that is, the input data block to be processed is subjected to DWT column transformation and then output to the Permuter circuit 120; the Permuter circuit 120 is used to input the intermediate data block in columns Read by row and output to Row circuit 130; The Row circuit 130 is used to perform DWT operation on the intermediate data block input by row to obtain the operation result, that is, perform DWT row transformation on the intermediate data block input by row Then output by line to complete the DWT calculation process.
下面将结合具体实施例以及图2至图9对该DWT运算装置100进行详细描述。The DWT computing device 100 will be described in detail below in conjunction with specific embodiments and FIGS. 2 to 9.
应理解,该DWT运算装置100可以用于处理数据,例如本申请实施例以用于图像数据的处理为例进行说明。图2示出了本申请实施例的DWT运算装置的应用场景的示意图。如图2所示,向DWT运算装置100输入图像数据,该图像数据即为待处理数据块。例如,可以通过数据读取电路向该 DWT运算装置100输入图像数据,其中,该数据读取电路可以表示为raw_fetch电路。It should be understood that the DWT computing device 100 may be used to process data. For example, the embodiment of the present application takes the processing of image data as an example for description. Fig. 2 shows a schematic diagram of an application scenario of a DWT computing device in an embodiment of the present application. As shown in FIG. 2, the image data is input to the DWT computing device 100, and the image data is the data block to be processed. For example, image data can be input to the DWT computing device 100 through a data reading circuit, where the data reading circuit can be expressed as a raw_fetch circuit.
可选地,该DWT运算装置100可以包括或者不包括该raw_fetch电路。例如,如图2所示,本申请实施例以该raw_fetch电路不属于该DWT运算装置100为例进行说明,但本申请实施例并不限于此。Optionally, the DWT computing device 100 may or may not include the raw_fetch circuit. For example, as shown in FIG. 2, the embodiment of the present application takes the raw_fetch circuit not belonging to the DWT computing device 100 as an example for description, but the embodiment of the present application is not limited to this.
具体地,由该外部的raw_fetch电路负责从双数据速率(Double Data Rate,DDR)电路中读取图像数据,例如,该raw_fetch电路可以通过高级可扩展接口(Advanced eXtensible Interface,AXI)从DDR电路中读取图像数据,并输出至DWT运算装置100中的Column电路110进行处理,也就是说raw_fetch电路的输出与Column电路110的输入是相同的。具体地,该DWT运算装置100可以进行多级处理,也就是进行多次反复处理。例如,如图2所示,以3级处理为例,也就是对输入数据进行三次反复处理,其中,1级处理是对原始数据进行处理,输出的处理结果作为2级处理的输入数据,而2级输入结果再作为3级处理的输入数据。对于任意一级处理,例如,图2中1/2/3级中任意一级处理,raw_fetch电路输出数据顺序可以如图3所示。Specifically, the external raw_fetch circuit is responsible for reading image data from the double data rate (Double Data Rate, DDR) circuit. For example, the raw_fetch circuit can read the image data from the DDR circuit through the Advanced eXtensible Interface (AXI). The image data is read and output to the Column circuit 110 in the DWT computing device 100 for processing, that is, the output of the raw_fetch circuit is the same as the input of the Column circuit 110. Specifically, the DWT computing device 100 may perform multi-stage processing, that is, perform multiple repeated processing. For example, as shown in Figure 2, take the 3-level processing as an example, that is, the input data is processed three times repeatedly. Among them, the 1-level processing is to process the original data, and the output processing result is used as the input data of the 2-level processing, and The input result of level 2 is then used as input data for level 3 processing. For any level of processing, for example, any level of processing in the 1/2/3 level in Figure 2, the output data sequence of the raw_fetch circuit can be as shown in Figure 3.
应理解,这里以处理一个256*256的图像数据为例进行说明。首先将该256*256的图像分为16个64*64的块,例如,图3示出了其中的前4个64*64的块,即图3中的4个大块。如图3所示,对于这4个64*64的块,raw_fetch电路会按照从左到右的顺序依次输出,之后再输出位于该4个64*64下方的再4个64*64的块,依次类推。It should be understood that processing a 256*256 image data is taken as an example for description. First, divide the 256*256 image into 16 64*64 blocks. For example, FIG. 3 shows the first 4 64*64 blocks, that is, the 4 large blocks in FIG. 3. As shown in Figure 3, for these 4 64*64 blocks, the raw_fetch circuit will output sequentially from left to right, and then output the 4 64*64 blocks below the 4 64*64. And so on.
而对于图3中4个64*64的块中每个64*64的块而言,可以再将每个64*64的块分为64个8*8的块,即如图3中4个大块中每个大块中的小块所示,每个小块都表示一个8*8的块。对于每个64*64的块,raw_fetch电路的读取顺序为图3中箭头所示,即raw_fetch电路在读取每个64*64的大块时,按照从左至右,再从上之下的顺序,依次读取每个8*8的小块。For each 64*64 block in the 4 64*64 blocks in Figure 3, each 64*64 block can be divided into 64 8*8 blocks, that is, 4 blocks in Figure 3 The small blocks in each big block in the big block are shown, and each small block represents an 8*8 block. For each 64*64 block, the reading order of the raw_fetch circuit is shown by the arrow in Figure 3. That is, when the raw_fetch circuit reads each 64*64 block, it follows from left to right, and then from top to bottom. Read each 8*8 block in sequence.
进一步的,对于每个8*8的小块而言,raw_fetch电路的读取顺序则可以如图4所示,采用先列后行的方式读取。具体地,图4示出了任意一个64*64的大块中任意一个8*8的块和位于其正下方且与其相邻的8*8的块的示意图。如图4所示,raw_fetch电路在读取每个8*8的小块时,先读取该8*8的第一列,然后依次向右读取下一列,直至读取完该8*8的小块后,再读取与该8*8的小块相邻的右侧的下一个8*8的小块,依次类推。Further, for each 8*8 small block, the reading sequence of the raw_fetch circuit can be read in a column-first-line manner as shown in FIG. 4. Specifically, FIG. 4 shows a schematic diagram of any 8*8 block in any 64*64 large block and an 8*8 block directly below and adjacent to it. As shown in Figure 4, when the raw_fetch circuit reads each 8*8 block, it first reads the first column of the 8*8, and then reads the next column to the right until the 8*8 is read. After the small block, read the next 8*8 small block on the right side adjacent to the 8*8 small block, and so on.
raw_fetch电路按照上述顺序向DWT运算装置100中输入图像数据,具体地,该raw_fetch电路可以向该DWT运算装置100中的Column电路110输入图像数据作为待处理数据块,以便于该Column电路110进行进一步处理。本申请实施例的DWT运算装置100主要包括3个电路:Column电路110、Permuter电路120以及Row电路130,下面对这三部分进行详细介绍。The raw_fetch circuit inputs image data to the DWT computing device 100 in the above sequence. Specifically, the raw_fetch circuit can input image data to the Column circuit 110 in the DWT computing device 100 as a data block to be processed, so that the Column circuit 110 can proceed further. deal with. The DWT operation device 100 of the embodiment of the present application mainly includes three circuits: Column circuit 110, Permuter circuit 120, and Row circuit 130. These three parts are described in detail below.
首先是Column电路110。该Column电路110可以用于将按列输入的该待处理数据块进行DWT运算后生成中间数据块,并将该中间数据块按列输出至Permuter电路120中,或者也可以说,该Column电路110用于完成dwt列变换。The first is the Column circuit 110. The Column circuit 110 can be used to generate an intermediate data block after performing DWT operations on the data block to be processed input by column, and output the intermediate data block to the Permuter circuit 120 by column, or it can be said that the Column circuit 110 Used to complete the dwt column transformation.
具体地,该Column电路110的结构可以如图5所示。具体地,该Column电路110可以用于进行DWT53运算和/或DWT97运算。例如,该Column电路110可以包括DWT53单元(即图2中的“dwt_53”)和DWT97单元(即图2中的“dwt_97”),其中,dwt_53单元可以用于无损模式,dwt_97单元可以用于有损模式。Specifically, the structure of the Column circuit 110 may be as shown in FIG. 5. Specifically, the Column circuit 110 can be used to perform DWT53 operations and/or DWT97 operations. For example, the Column circuit 110 may include a DWT53 unit (ie, "dwt_53" in Figure 2) and a DWT97 unit (ie, "dwt_97" in Figure 2), where the dwt_53 unit can be used in lossless mode, and the dwt_97 unit can be used in Loss mode.
可选的,Column电路110还可以包括地址计算单元(即图2中的“col_pst”),通过该col_pst单元选择将输入的待处理数据块输出至DWT53单元,以采用DWT53运算过程进行处理;和/或,选择将输入的待处理数据块输出至DWT97单元,以采用DWT97运算过程进行处理。Optionally, the Column circuit 110 may also include an address calculation unit (ie, "col_pst" in FIG. 2), through which the col_pst unit selects to output the input data block to be processed to the DWT53 unit, so as to use the DWT53 operation process for processing; and / Or, choose to output the input data block to be processed to the DWT97 unit to use the DWT97 operation process for processing.
应理解,对于输入Column电路110的待处理数据块,该输入的待处理数据块可以指上述raw_fetch电路按列读取并输入的数据。具体地,如图4所示,为了便于描述,建立一个以行号和列号为轴的坐标系。因此,对于如图4所示的上下相邻的两个8*8的小块,每个像素点都可以用坐标的形式表示。It should be understood that, for the to-be-processed data block input to the Column circuit 110, the input to-be-processed data block may refer to the data read and input in columns by the raw_fetch circuit. Specifically, as shown in Fig. 4, for ease of description, a coordinate system with row number and column number as the axis is established. Therefore, for two 8*8 small blocks adjacent to each other as shown in FIG. 4, each pixel can be expressed in the form of coordinates.
例如,对于图4中第一个8*8的小块中的左上角第一个像素,其坐标可以表示为(1,1),表示第一行第一列的像素点,其下方的像素点的坐标为(2,1),表示第二行第一列的像素点,依次类推。而对于第二个8*8的小块,其左上角的第一个像素点的的坐标为(9,1),表示其为第九行第一列的像素点,也就是该8*8的小块的坐标是在上一个8*8的小块的基础上进一步计算,依次类推。For example, for the first pixel in the upper left corner of the first 8*8 block in Figure 4, its coordinates can be expressed as (1,1), which represents the pixel in the first row and first column, and the pixel below it The coordinate of the point is (2,1), which represents the pixel point in the second row and first column, and so on. For the second 8*8 small block, the coordinates of the first pixel in the upper left corner are (9,1), which means it is the pixel in the ninth row and the first column, which is the 8*8 The coordinates of the small block are further calculated on the basis of the previous 8*8 small block, and so on.
按照上述表示方式,对于图3所示的像素点,同样可以建立该坐标系。如图3所示,该4个64*64的块可以以第一个64*64的块左上角的第一个像 素点为基准,依次推算其他像素点的坐标;对应图4即表示该图3中第一64*64的块的左上角第一个8*8的小块和其正下方相邻的一个8*8的小块。According to the above representation, for the pixels shown in FIG. 3, the coordinate system can also be established. As shown in Figure 3, the four 64*64 blocks can be based on the first pixel in the upper left corner of the first 64*64 block, and the coordinates of other pixels can be calculated in turn; corresponding to Figure 4, this figure is shown The first 8*8 small block in the upper left corner of the first 64*64 block in 3 and the adjacent 8*8 small block directly below it.
应理解,如图4所示,raw_fetch电路会在每个周期(cycle)内读取一列像素的数据。具体地,本申请实施例的DWT53单元用于对输入的数据进行DWT53运算,其中,该DWT53运算过程可以如图6所示,其中,该图6中的最左侧的p0~p8共9个像素是输入的图像列数据。也就是说,每个cycle输入的是9个像素的数据,其中,该9个像素的数据可以指任意一列8个像素和一个补偿的像素。例如,如图4所示,输入第一列8个像素和其正下方的一个像素,共9个像素,即图4中斜线方块所示,作为该DWT53的运算过程中的输入数据,即对应p0~p8共9个像素。It should be understood that, as shown in FIG. 4, the raw_fetch circuit reads the data of a column of pixels in each cycle. Specifically, the DWT53 unit of the embodiment of the present application is used to perform DWT53 operations on the input data, where the DWT53 operation process may be as shown in FIG. 6, where there are 9 p0 to p8 on the leftmost side in FIG. The pixel is the input image column data. In other words, each cycle inputs 9 pixels of data, where the 9 pixels of data can refer to any column of 8 pixels and one compensated pixel. For example, as shown in Figure 4, input 8 pixels in the first column and a pixel directly below it, a total of 9 pixels, which is shown by the diagonal square in Figure 4, as the input data in the calculation process of the DWT53, namely Corresponding to a total of 9 pixels from p0 to p8.
如图6所示,对于任意一个cycle输入的9个像素的图像数据,经过4级(stg1至stg4)流水线计算后,得到4个低频数据L0~L3,以及4个高频数据H0~H3。其中,如图6所示,在DWT53运算过程中,加号表示加法器进行加法运算;减号表示减法器进行减法运算;rd表示舍弃低位数据;rd前面的加法器的“2”是指这个加法器对应的加法运算是将输入结果+2,这是J2K标准规定的。As shown in FIG. 6, for the image data of 9 pixels input by any cycle, after 4 stages (stg1 to stg4) pipeline calculation, 4 low-frequency data L0-L3 and 4 high-frequency data H0-H3 are obtained. Among them, as shown in Figure 6, during the operation of DWT53, the plus sign indicates that the adder performs addition; the minus sign indicates that the subtractor performs subtraction; rd indicates that the lower data is discarded; the "2" of the adder before rd refers to this The addition operation corresponding to the adder is the input result +2, which is specified by the J2K standard.
另外,对于任意一个cycle输入的9个像素的图像数据的DWT53的运算过程,存在中间结果h3,例如如图6所示的星号标注的即为中间结果h3。该中间结果h3需要供后续的运算过程使用,例如,对于当前输入数据对应获得的中间结果h3,可以用于位于该当前输入数据正下方且相邻的一列数据的DWT53运算过程,例如该中间结果h3可以作为如图6所示的虚线减号处的代入数据。其中,若当前输入的数据在进行如图6所示的运算过程时,其不存在与之对应的根据之前的数据获得中间结果h3时,该虚线减号处代入的数据可以为预设值。In addition, for the calculation process of the DWT53 of the image data of 9 pixels input by any cycle, there is an intermediate result h3, for example, the intermediate result h3 is marked with an asterisk as shown in FIG. 6. The intermediate result h3 needs to be used in the subsequent calculation process. For example, the intermediate result h3 obtained corresponding to the current input data can be used in the DWT53 calculation process of a column of data directly below the current input data, such as the intermediate result h3 can be used as the substitution data at the dotted minus sign as shown in Figure 6. Wherein, if the currently input data is performing the calculation process as shown in FIG. 6 and there is no corresponding intermediate result h3 obtained from the previous data, the data substituted at the minus sign of the dotted line can be the preset value.
例如,如图4所示,假设当前输入该DWT53运算过程中的数据为第一列8个像素与一个补偿像素,那么经过如图6所示的计算过程,由于在其之前没有其他输入数据,因此,该第一列数据的虚线减号处代入的数据可以为预先设置的预设值。另外,在如图6所示的计算过程中,可以获得星号标注的中间结果h3,为了便于区别,这里表示为h31。之后,在输入该DWT53运算过程中的数据为如图4所示的第二个8*8的小块的第一列时,也就是坐标为(9,1)的像素点所在的一列的像素(即坐标为(9,1)至(16,1))以及 其下方的一个补偿像素,该组输入数据在进行如图6所示的计算过程时,图6中虚线减号处的代入的数值为上述中间结果h31,并且进一步获得新的星号标注的中间结果,例如可以表示为h32。依次类推,按照上述过程,在该DWT53的运算过程中可以获得多个中间结果h3。For example, as shown in Figure 4, assuming that the data currently input to the DWT53 operation process is the first column of 8 pixels and one compensation pixel, then after the calculation process shown in Figure 6, there is no other input data before it. Therefore, the data substituted at the dotted minus sign of the first column of data may be a preset value set in advance. In addition, in the calculation process shown in FIG. 6, the intermediate result h3 marked with an asterisk can be obtained, which is denoted as h31 here for the convenience of distinction. After that, when the data input in the DWT53 operation process is the first column of the second 8*8 block as shown in Figure 4, that is, the pixel in the column where the pixel with the coordinate (9, 1) is located (I.e. the coordinates are (9,1) to (16,1)) and a compensation pixel below it. When the set of input data is in the calculation process shown in Figure 6, the dashed minus sign in Figure 6 is substituted The value is the aforementioned intermediate result h31, and the intermediate result marked with a new asterisk is further obtained, which can be expressed as h32, for example. By analogy, according to the above process, multiple intermediate results h3 can be obtained during the operation of the DWT53.
按照上述raw_fetch电路输出数据的顺序,采用该DWT53的运算过程依次处理每个cycle的输入数据,在此不再赘述。According to the output data sequence of the raw_fetch circuit, the DWT53 operation process is used to sequentially process the input data of each cycle, which will not be repeated here.
类似的,DWT97单元用于对输入的数据进行DWT97运算,其中,该DWT53运算过程可以如图7所示,图中p0~p10是输入的图像列数据,其中,该11个像素点可以指任意一列8个像素和3个补偿的像素。例如,如图4所示,对于输入第4列的8个像素,与其正下方的三个像素,共11个像素,即图4中交叉线方块所示,作为该DWT97的运算过程中的输入数据,即对应p0~p10共11个像素。Similarly, the DWT97 unit is used to perform DWT97 operations on the input data, where the DWT53 operation process can be as shown in Figure 7. In the figure, p0~p10 are the input image column data, where the 11 pixels can refer to any A column of 8 pixels and 3 compensated pixels. For example, as shown in Figure 4, for the 8 pixels in the fourth column of the input, and the three pixels directly below, a total of 11 pixels, that is, as shown by the cross-line square in Figure 4, are used as input in the calculation process of the DWT97 The data corresponds to a total of 11 pixels from p0 to p10.
如图7所示,对于任意一个cycle输入的11个像素的图像数据,经过12级(stg1至stg12)流水线计算后,得到4个低频数据L0~L3,以及4个高频数据H0~H3。其中,在DWT97运算过程中,加号对应表示加法器进行加法运算;减号表示减法器进行减法运算;乘号表示乘法器进行乘法运算;乘号前面的α、β、γ以及δ表示每个乘法器乘的系数,例如,该系数的具体取值可以为J2K标准规定的。As shown in FIG. 7, for the image data of 11 pixels input by any cycle, after 12 stages (stg1 to stg12) pipeline calculation, 4 low-frequency data L0~L3 and 4 high-frequency data H0~H3 are obtained. Among them, in the DWT97 operation process, the plus sign corresponds to the adder for addition; the minus sign indicates that the subtractor performs subtraction; the multiplication sign indicates that the multiplier performs multiplication; the α, β, γ, and δ before the multiplication sign indicate each The coefficient multiplied by the multiplier, for example, the specific value of the coefficient may be specified by the J2K standard.
另外,对于任意一个cycle输入的11个像素的图像数据的DWT97的运算过程,存在中间结果h3和a3,例如如图6所示的星号标注的中间结果可以分别称为a3(对应图7中的右边星号)和h3(对应图7中左边星号)。该中间结果a3和h3也需要供后续运算过程使用,例如,对于当前输入数据对应获得的中间结果a3和h3,可以用于位于该当前输入数据正下方且相邻的一列数据的DWT53运算过程,例如该中间结果a3和h3可以分半作为如图7所示的虚线加号和虚线减号处的代入数据。其中,若当前输入的数据在进行如图7所示的运算过程时,不存在与之对应的根据之前的数据获得中间结果a3和h3时,该虚线加号和虚线减号处代入的数据可以为预设值。In addition, there are intermediate results h3 and a3 for the DWT97 calculation process of the image data of 11 pixels input by any cycle. For example, the intermediate results marked with an asterisk as shown in Figure 6 can be called a3 respectively (corresponding to Figure 7 The asterisk on the right) and h3 (corresponding to the asterisk on the left in Figure 7). The intermediate results a3 and h3 also need to be used in subsequent calculation processes. For example, the intermediate results a3 and h3 obtained corresponding to the current input data can be used in the DWT53 calculation process of the adjacent column of data directly below the current input data. For example, the intermediate results a3 and h3 can be divided into half as the substitution data at the dotted line plus sign and dotted line minus sign as shown in FIG. 7. Among them, if the currently input data is in the calculation process shown in Figure 7, there is no corresponding intermediate results a3 and h3 obtained from the previous data, the data substituted at the dotted plus sign and dotted minus sign can be Is the default value.
例如,如图4所示,假设当前输入该DWT97运算过程中的数据为第四列8个像素与下方的三个补偿像素,那么在进行如图7所示的计算过程中,由于在其之上没有其他输入数据,因此,该第四列数据的虚线加号和虚线减号处代入的数据可以为预先设置的预设值。另外,在如图7所示的计算过程 中,可以获得星号标注的中间结果a3和h3,为了便于区别,这里分别表示为a31和h31。之后,在输入该DWT97运算过程中的数据为如图4所示的第二个8*8的小块的第四列时,也就是坐标为(9,4)的像素点所在的一列的像素(即坐标为(9,4)至(16,4))以及其下方的3个补偿像素,该组输入数据在进行如图7所示的计算过程时,图7中虚线减号处的代入的数值为上述计算结果h31,图7中虚线加号处的代入的数值为上述计算结果a31,并且进一步获得新的星号标注的计算结果,例如可以分别表示为a32和h32。For example, as shown in Figure 4, assuming that the data currently input to the DWT97 operation process is the 8 pixels in the fourth column and the three compensation pixels below, then in the calculation process shown in Figure 7, the There is no other input data. Therefore, the data substituted at the dotted plus sign and dotted minus sign of the fourth column of data can be preset values set in advance. In addition, in the calculation process as shown in Figure 7, the intermediate results a3 and h3 marked with asterisks can be obtained. For the convenience of distinction, they are represented as a31 and h31 respectively here. After that, when the data input in the DWT97 operation process is the fourth column of the second 8*8 block as shown in Figure 4, that is, the pixel in the column where the pixel with the coordinate (9, 4) is located (I.e. the coordinates are (9,4) to (16,4)) and the 3 compensation pixels below it. When this group of input data is in the calculation process shown in Figure 7, the dotted line minus sign in Figure 7 is substituted The value of is the above calculation result h31, and the value substituted in the dotted plus sign in FIG. 7 is the above calculation result a31, and the new calculation result marked with an asterisk is further obtained, which can be expressed as a32 and h32, for example.
应理解,对于上述DWT53和DWT97计算过程,由于每个cycle的图像数据的计算过程中,需要使用与其对应的上方数据的部分中间数据,因此,在该Column电路110中还可以包括存储单元,每个存储单元可以为存储器,例如,包括随机存取存储器(Random Access Memory,RAM),以用于保存DWT53的运算过程中需要保存的中间结果h3以及DWT97的运算过程中需要保存的中间结果a3和h3。例如,该Column电路110中可以包括两组存储单元,这里分别称为第一存储单元组col8_ram和第二存储单元组col64_ram,以用于存储上述过程中星号标注的计算结果。其中,第一存储单元组和第二存储单元组分别可以包括一个或者多个存储单元。It should be understood that for the above calculation process of DWT53 and DWT97, since the calculation process of the image data of each cycle needs to use part of the intermediate data of the corresponding upper data, the Column circuit 110 may also include a storage unit. Each storage unit may be a memory, for example, including random access memory (Random Access Memory, RAM) to save the intermediate results h3 that need to be saved during the operation of DWT53 and the intermediate results a3 and a3 that need to be saved during the operation of DWT97. h3. For example, the Column circuit 110 may include two groups of storage units, which are referred to herein as the first storage unit group col8_ram and the second storage unit group col64_ram, respectively, for storing the calculation results marked with an asterisk in the foregoing process. Wherein, the first storage unit group and the second storage unit group may respectively include one or more storage units.
具体地,如图5所示,该Column电路110中可以设置为包括4个存储器,其中,2个存储器用于存储DWT53的运算过程和DWT97的运算过程中的h3,例如,如图5中的col8_ram_h和col64_ram_h;另外2个存储器用于存储DWT97的运算过程中的a3,例如,如图5中的col8_ram_a和col64_ram_a。对应的,即第一存储单元组col8_ram包括两个存储单元,分别为col8_ram_h和col8_ram_a;第二存储单元组col64_ram包括两个存储单元,分别为col64_ram_h和col64_ram_a。Specifically, as shown in FIG. 5, the Column circuit 110 can be configured to include 4 memories, of which 2 memories are used to store the operation process of DWT53 and h3 in the operation process of DWT97, for example, as shown in FIG. 5 col8_ram_h and col64_ram_h; the other two memories are used to store a3 during the operation of DWT97, for example, col8_ram_a and col64_ram_a in Figure 5. Correspondingly, the first storage unit group col8_ram includes two storage units, namely col8_ram_h and col8_ram_a; the second storage unit group col64_ram includes two storage units, respectively, col64_ram_h and col64_ram_a.
应理解,按照上述内容,如图6和图7所示的星号标注的计算结果,对应用于当前输入的列数据的正下方的一列输入数据的计算过程。那么,假设对于具有256*256个像素点的图像数据,如图3所示,对于每个64*64的块,每计算完该64*64的块的一行的8个8*8*小块,会折回继续计算下一行的各个8*8的小块,那么此时需要使用上一行的各个8*8的小块的星号标注的计算结果,直至输入完该64*64块。该Column电路110可以通过设置的第一存储单元组col8_ram分别存储97/53的一行64*8块计算中产生的a3/h3数据,其中,a3和h3可以分开存储,该第一存储单元组包括第一存储单元和 第二存储单元,分别用于存储a3和h3。例如,第一存储单元用于:存储第一列数据在经过该DWT53运算或者该DWT97运算后输出的第一中间结果h3,该第一中间结果h3用于该第二列数据的该DWT5 3运算过程或者该DWT97运算过程,这里的第一列数据指的是任意一列数据,并非一定是位置上的第一列;该第二存储单元用于:存储该第一列数据在经过该DWT97运算后输出的第二中间结果a3,该第二中间结果a3用于该第二列数据的该DWT53运算过程,该第一列数据为位于该第二列数据的正上方且与该第二列数据相邻的一列数据。It should be understood that, according to the above content, the calculation results marked with asterisks as shown in FIGS. 6 and 7 correspond to the calculation process for a column of input data directly below the currently input column of data. Then, suppose that for the image data with 256*256 pixels, as shown in Figure 3, for each 64*64 block, after calculating 8 8*8* small blocks in a row of the 64*64 block , Will go back and continue to calculate each 8*8 block in the next line, then you need to use the calculation result marked with the asterisk of each 8*8 block in the previous line until the 64*64 block is input. The Column circuit 110 can store the a3/h3 data generated in the calculation of 97/53 rows of 64*8 blocks through the set first storage unit group col8_ram, where a3 and h3 can be stored separately, and the first storage unit group includes The first storage unit and the second storage unit are used to store a3 and h3, respectively. For example, the first storage unit is used to store the first intermediate result h3 output after the DWT53 operation or the DWT97 operation of the first column of data, and the first intermediate result h3 is used for the DWT5 3 operation of the second column of data Process or the DWT97 calculation process, the first column of data here refers to any column of data, not necessarily the first column in position; the second storage unit is used to store the first column of data after the DWT97 operation The second intermediate result a3 is output, and the second intermediate result a3 is used in the DWT53 operation process of the second column of data. The first column of data is located directly above the second column of data and is the same as the second column of data. A column of adjacent data.
即Column电路110中设置col8_ram_h存储每行64个h3,以及设置col8_ram_a存储每行64个a3。如图3所示,假设计算完第一个64*64的块,那么会继续计算其右边的第二个64*64的块,但是第一个64*64的块的最后一行的64个a3和h3的结果是在计算该第一个64*64的块的正下方的64*64的块(图3中未示出)时使用。以此类推,那么如图3所示的4个64*64的块均计算完成后,会得到64*4个a3和h3值,这些值可以通过Column电路110中设置的第二存储单元组col64_ram进行保存。同样的,a3和h3分开存储,即Column电路110中设置col64_ram_h存储每一整行64*4个h3,以及设置col64_ram_a存储每一整行64*4个a3。That is, col8_ram_h is set to store 64 h3 per row in Column circuit 110, and col8_ram_a is set to store 64 a3 per row. As shown in Figure 3, assuming that the first 64*64 block is calculated, then the second 64*64 block to the right will continue to be calculated, but the 64 a3 in the last row of the first 64*64 block The result of sum h3 is used when calculating the 64*64 block (not shown in FIG. 3) directly below the first 64*64 block. By analogy, after the calculation of the 4 64*64 blocks shown in Figure 3 is completed, 64*4 a3 and h3 values will be obtained. These values can be passed through the second storage unit group col64_ram set in the Column circuit 110 Save it. Similarly, a3 and h3 are stored separately, that is, col64_ram_h is set to store 64*4 h3 for each entire row in Column circuit 110, and col64_ram_a is set to store 64*4 a3 for each entire row.
可选的,将DWT53运算过程的h3和DWT97运算过程的h3存储在相同的ram中,这样,可以节省存储器和功耗,利于电路小型化。Optionally, store the h3 of the DWT53 operation process and the h3 of the DWT97 operation process in the same ram. In this way, memory and power consumption can be saved, which is conducive to circuit miniaturization.
另外,当选择DWT53模式时,可以不使能col8_ram_a和col64_ram_a,以此节省功耗。In addition, when DWT53 mode is selected, col8_ram_a and col64_ram_a can be disabled to save power consumption.
下面描述Permute电路(也可称为行列转换电路)120。该Permuter电路120用于将按列输入的中间数据块进行缓存后按行输出至Row电路130中,或者也可以说,该Permuter电路120用于将输入的中间数据块进行转置处理后输出至Row电路130中。The Permute circuit (also called a row-column conversion circuit) 120 is described below. The Permuter circuit 120 is used for buffering the intermediate data blocks input in columns and outputting them to the Row circuit 130 according to rows, or it can be said that the Permuter circuit 120 is used for transposing the input intermediate data blocks and outputting them to Row circuit 130.
具体地,Permuter电路120的输入数据即为Column电路110的输出数据,Permuter电路120将Column电路110输出的列运算的结果存在寄存器堆中,再按照图8的顺序将数据按行输出到用于行运算的Row电路130。Specifically, the input data of the Permuter circuit 120 is the output data of the Column circuit 110. The Permuter circuit 120 stores the result of the column operation output by the Column circuit 110 in the register file, and then outputs the data in rows to the register file in the order of FIG. 8 Row circuit 130 for row operations.
例如,以DWT97的运算过程为例,Permuter电路120将按列输入的数据进行存储,如图8所示,当输入了11列数据之后,也就是完成第一个8*8的小块的输入,以及下一个8*8的小块的部分输入时,Permuter电路120则 可以开始按行读取并输出该数据至Row电路130;与此同时,该Permuter电路120的依然在存储下一个8*8的小块,Permuter电路120的输入和输出可以同时进行,并且,除了第一个时钟周期需要等该Permuter电路120存储11列(即如图8所示的pmt0表示的11列)以外,之后每完成8列输入,即可以开始按行读取。For example, taking the calculation process of DWT97 as an example, the Permuter circuit 120 stores the input data in columns. As shown in Figure 8, when 11 columns of data are input, the input of the first 8*8 block is completed. , And when the next 8*8 small block is input, the Permuter circuit 120 can start to read and output the data to the Row circuit 130; at the same time, the Permuter circuit 120 is still storing the next 8* In the small block of 8, the input and output of the Permuter circuit 120 can be performed at the same time, and, except for the first clock cycle, the Permuter circuit 120 needs to wait for the Permuter circuit 120 to store 11 columns (that is, 11 columns represented by pmt0 as shown in FIG. After completing 8 columns of input, you can start reading in rows.
如图8所示,对于第一个8*8的小块,按照从上之下的顺序,Permuter电路120依次输出每一行11个像素,其中包括3个补偿像素,例如,输出如图8所示的左边的椭圆形包括的11个像素,其中,tmp0表示补偿的部分。当完成8行数据的输出之后,也就是完成第一个8*8的小块的输出,继续执行其右边的第二个8*8的小块的输出,同样每次输出一行11个像素,其中包括3个补偿像素,例如,输出如图8所示的右边的椭圆形的11像素,其中,tmp1表示补偿的部分。依次类推,依次输出每个8*8的小块的图像数据。As shown in Figure 8, for the first 8*8 small block, in the order from top to bottom, Permuter circuit 120 sequentially outputs 11 pixels in each row, including 3 compensation pixels. For example, the output is as shown in Figure 8. The ellipse on the left shown includes 11 pixels, where tmp0 represents the compensated part. When the output of 8 rows of data is completed, that is, the output of the first 8*8 small block is completed, and the output of the second 8*8 small block on the right is continued, and 11 pixels are output in a row at a time. It includes 3 compensation pixels, for example, 11 pixels of the ellipse on the right as shown in FIG. 8 are output, where tmp1 represents the compensated part. By analogy, each 8*8 small block of image data is output in turn.
再例如,对于DWT53的运算过程,与上述DWT97的输出不同的地方在于,每次输出的数据为9个像素,其中包括1个补偿像素,也就是DWT53的运算过程与上述DWT97运算过程的补偿像素个数不同,导致每次输出的数据不同,但是输出的方式和方向相同,为了简洁,在此不再赘述。For another example, for the calculation process of DWT53, the difference from the output of DWT97 above is that the output data each time is 9 pixels, including 1 compensation pixel, that is, the calculation process of DWT53 and the compensation pixel of the foregoing DWT97 calculation process The number is different, resulting in different output data each time, but the output method and direction are the same. For the sake of brevity, I will not repeat it here.
应理解,该Permuter电路120在每个8*8的小块内部按照上述从上到下的方式输出每一行;而对于如图3所示的4个64*64的块,若以每个8*8的块为一个单元,则Permuter电路120读取每个单元的顺序与图3相同,即从左至右,再从上至下,在此不再赘述。It should be understood that the Permuter circuit 120 outputs each row in each 8*8 small block in the above-mentioned top-to-bottom manner; and for the four 64*64 blocks shown in FIG. 3, if each 8*8 block is The block of *8 is a unit, and the sequence of reading each unit by the Permuter circuit 120 is the same as that of FIG. 3, that is, from left to right, and then from top to bottom, which will not be repeated here.
下面描述Row电路130。该Row电路130用于将按行输入的数据进行DWT行运算后按行输出,以完成该DWT运算装置100的DWT的计算过程,或者也可以说,该Row电路130用于完成dwt行变换。The Row circuit 130 is described below. The Row circuit 130 is used to perform DWT row operations on the data input in rows and then output them in rows to complete the DWT calculation process of the DWT operation device 100, or it can be said that the Row circuit 130 is used to complete dwt row conversion.
具体地,Row电路130与Column电路110的计算过程基本一致,差别在于Row电路130中输入的数据为行数据,为了简洁,在此不再赘述。Specifically, the calculation process of the Row circuit 130 and the Column circuit 110 are basically the same. The difference is that the data input in the Row circuit 130 is row data. For brevity, it will not be repeated here.
另外,在ram资源使用方面,与Column电路110类似,该Row电路130中也包括存储单元,每个存储单元可以用于保存DWT53的运算过程中需要保存的中间结果h3以及DWT97的运算过程中需要保存的中间结果a3和h3。例如,该Row电路130中可以包括两组存储单元,这里分别称为第三存储单元组col8_ram和第四存储单元组col64_ram,以用于存储运算过程 中星号标注的中间计算结果。其中,第三存储单元组和第四存储单元组分别可以包括一个或者多个存储单元。In addition, in terms of the use of ram resources, similar to the Column circuit 110, the Row circuit 130 also includes storage units. Each storage unit can be used to store the intermediate results h3 that need to be saved during the operation of DWT53 and the need for the operation of DWT97. Save the intermediate results a3 and h3. For example, the Row circuit 130 may include two groups of storage units, which are referred to herein as the third storage unit group col8_ram and the fourth storage unit group col64_ram, respectively, for storing intermediate calculation results marked with an asterisk during the operation. Wherein, the third storage unit group and the fourth storage unit group may respectively include one or more storage units.
具体地,与Column电路110类似,该Row电路130中也可以设置如图5所示的四个存储单元,2个存储器用于存储DWT53的运算过程和DWT97的运算过程中的h3,例如,设置如图5中的col8_ram_h和col64_ram_h;另外2个存储器用于存储DWT97的运算过程中的a3,例如,设置如图5中的col8_ram_a和col64_ram_a。即第三存储单元组col8_ram包括两个存储单元,分别为第三存储单元col8_ram_h和第四存储单元col8_ram_a;第四存储单元组col64_ram包括两个存储单元,分别为col64_ram_h和col64_ram_a。Specifically, similar to the Column circuit 110, the Row circuit 130 can also be provided with four storage units as shown in FIG. 5, two memories are used to store the operation process of DWT53 and h3 in the operation process of DWT97, for example, set As shown in Figure 5, col8_ram_h and col64_ram_h; the other two memories are used to store a3 in the operation of DWT97, for example, set col8_ram_a and col64_ram_a in Figure 5. That is, the third storage unit group col8_ram includes two storage units, respectively, the third storage unit col8_ram_h and the fourth storage unit col8_ram_a; the fourth storage unit group col64_ram includes two storage units, respectively, col64_ram_h and col64_ram_a.
其中,第三存储单元col8_ram_h用于:存储第一行数据在经过该DWT53运算或者该DWT97运算后输出的第一中间结果h3,该第一中间结果h3用于该第二行数据的该DWT5 3运算过程或者该DWT97运算过程,这里的第一行数据指的是任意一行数据,并非一定是位置上的第一行;该第四存储单元col8_ram_a用于:存储该第一行数据在经过该DWT97运算后输出的第二中间结果a3,该第二中间结果a3用于该第二行数据的该DWT53运算过程,该第一行数据为位于该第二行数据的左边且与该第二行数据相邻的一行数据。Among them, the third storage unit col8_ram_h is used to store the first intermediate result h3 output by the first row of data after the DWT53 operation or the DWT97 operation, and the first intermediate result h3 is used for the DWT5 of the second row of data. In the calculation process or the DWT97 calculation process, the first row of data here refers to any row of data, not necessarily the first row in position; the fourth storage unit col8_ram_a is used to store the first row of data after passing through the DWT97 The second intermediate result a3 output after the operation. The second intermediate result a3 is used in the DWT53 operation process of the second row of data. The first row of data is located to the left of the second row of data and is the same as the second row of data. Adjacent row of data.
由于Row电路130的运算过程中,在处理下一个8*8的小块时,就会使用当前处理的8*8的小块对应获得并存储的星号标注的a3/h3,而不是如Column电路110运算过程一样,需要等待最少完成一行8*64个像素之后才使用。因此,在Row电路130中,可以将col8_ram(包括col8_ram_h和col8_ram_a)的大小设置为8*32bit(这里假设每个h3或者a3占用32bit),而不是Column电路110中的64*32bit;同样的,对于Row电路130中的row64_ram的大小,可以设置为64*32bit,而不是Column电路110中的256*32bit。Because in the calculation process of Row circuit 130, when processing the next 8*8 small block, it will use the currently processed 8*8 small block corresponding to the obtained and stored asterisk a3/h3 instead of Column The circuit 110 has the same operation process, it needs to wait for at least one row of 8*64 pixels to be completed before using it. Therefore, in Row circuit 130, the size of col8_ram (including col8_ram_h and col8_ram_a) can be set to 8*32bit (here it is assumed that each h3 or a3 occupies 32bit), instead of 64*32bit in Column circuit 110; the same, The size of row64_ram in Row circuit 130 can be set to 64*32bit instead of 256*32bit in Column circuit 110.
另外,针对DWT97运算过程,Row电路130还可以包括定标器scaler,用于对DWT97结果进行放大或者缩小处理。DWT97过程中Row电路130的行变换完成后,需对输出结果{LL,HL,LH,HH}做一次scale操作;而DWT53过程不需要。因此,可以将scaler加到Row电路130中。In addition, for the DWT97 operation process, the Row circuit 130 may also include a scaler, which is used to enlarge or reduce the DWT97 result. After the row conversion of the Row circuit 130 in the DWT97 process is completed, the output result {LL, HL, LH, HH} needs to be scaled once; while the DWT53 process does not need it. Therefore, a scaler can be added to the Row circuit 130.
具体地,如图9所示,DWT97的输出结果需要进行3级流水处理。其中,第一级流水(如图9所示的stg1)中,对于DWT97按行输出的结果, 通过scaler确定乘以不同的系数(coeff),例如,根据DWT97按行输出的结果的大小,可以对应乘以系数{k
2,1},或者也可以乘以系数{1,1/k
2}。例如,可以通过如图9所示的左边的选择器,根据输入数据的不同,选择出不同的系数输出。具体地,待处理数据块中任意一个数据经过Column电路110中DWT97的运算后,可能输出为高频数据H,或者,也可能输出为低频数据L;后续该数据在经过Row电路130中DWT97的运算后,则该数据可能输出为以下四种类型中任意一种:HH,HL,LH,LL。因此,对于输入scaler的{HH,HL,LH,LL}这四种可能的数据类型,HL和LH乘以系数1,HH乘以系数k
2,LL乘以系数1/k
2。不同的系数(coefficient)与DWT97按行输出的结果相乘。
Specifically, as shown in Figure 9, the output result of DWT97 requires 3-stage pipeline processing. Among them, in the first stage of pipeline (stg1 as shown in Figure 9), for the results output by DWT97 in rows, different coefficients (coeff) are determined by the scaler. For example, according to the size of the results output by DWT97 in rows, you can Correspondingly multiplied by the coefficient {k 2 ,1}, or can also be multiplied by the coefficient {1,1/k 2 }. For example, the selector on the left as shown in FIG. 9 can be used to select different coefficients for output according to different input data. Specifically, any data in the data block to be processed may be output as high-frequency data H or low-frequency data L after the operation of DWT97 in Column circuit 110. This data will subsequently pass through DWT97 in Row circuit 130. After the operation, the data may be output as any of the following four types: HH, HL, LH, LL. Therefore, for the four possible data types {HH, HL, LH, LL} input to the scaler, HL and LH are multiplied by the coefficient 1, HH is multiplied by the coefficient k 2 , and LL is multiplied by the coefficient 1/k 2 . Different coefficients are multiplied with the results output by DWT97 in rows.
之后在第二级流水(如图9所示的stg2)中,上一级流水的结果再进行四舍五入(round)操作和/或溢出(clip)处理,其中,clip处理是指如果数据范围超出输出数据的最大或最小值,用对应的最大值或者最小值代替。Then in the second stage of pipeline (stg2 as shown in Figure 9), the result of the previous stage of pipeline is rounded and/or overflowed (clip) processing. The clip processing refers to if the data range exceeds the output The maximum or minimum value of the data is replaced by the corresponding maximum or minimum value.
之后在第三级流水(如图9所示的stg3)中,选择器根据编码模式,例如硬件中可以通过1bit的信号来区分编码是有损还是无损,从而选择输出的数据,即为最终的计算结果。Then in the third stage of pipeline (stg3 as shown in Figure 9), the selector according to the encoding mode, for example, the hardware can use a 1-bit signal to distinguish whether the encoding is lossy or lossless, so as to select the output data, which is the final Calculation results.
与DWT97过程不同的是,在DWT53过程中,仅经过1级流水处理,即经过如图9所示的sgt3,经过选择器根据编码模式的选择,输出数据,即为最终的计算结果。The difference with the DWT97 process is that in the DWT53 process, only one stage of pipeline processing is passed, that is, through sgt3 as shown in Figure 9, after the selector selects the encoding mode, the output data is the final calculation result.
因此,本申请实施例提供的DWT运算装置为能够高效实现DWT运算的硬件结构,实时性高,功耗低,例如,在本申请上述实施例中,其处理速度可以达到8pixel/cycle,这样大大降低了DWT运算的执行时间和功耗;并且该DWT运算装置支持DWT97和DWT53的切换,灵活性高,两种模式的RAM资源完全复用,资源消耗少。Therefore, the DWT computing device provided in the embodiments of the present application is a hardware structure that can efficiently implement DWT operations, with high real-time performance and low power consumption. For example, in the above-mentioned embodiments of the present application, the processing speed can reach 8 pixels/cycle, which greatly The execution time and power consumption of the DWT operation are reduced; and the DWT operation device supports the switch between DWT97 and DWT53, with high flexibility, complete reuse of RAM resources in the two modes, and low resource consumption.
本发明实施例可通过SoC FPGA实现。The embodiments of the present invention can be implemented by SoC FPGA.
可选的,本申请实施例还提出了一种图像处理装置。具体地,图10示出了本申请实施例的图像处理装置200的示意性框图。如图10所示,该图像处理装置200包括DWT运算装置210和处理装置220。Optionally, an embodiment of the present application also proposes an image processing device. Specifically, FIG. 10 shows a schematic block diagram of an image processing apparatus 200 according to an embodiment of the present application. As shown in FIG. 10, the image processing device 200 includes a DWT computing device 210 and a processing device 220.
具体地,该DWT运算装置可以为本申请实施例的DWT运算装置,例如,可以包括本申请实施例的DWT运算装置100。该DWT运算装置210用于对该待处理数据块进行DWT运算后生成小波系数,并将该小波系数传 输至该处理装置220;该处理装置220用于对该小波系数进行以下至少一种处理:降噪处理,DWT逆运算,量化处理和熵编码处理。Specifically, the DWT computing device may be the DWT computing device of the embodiment of the present application, for example, it may include the DWT computing device 100 of the embodiment of the present application. The DWT operation device 210 is used to perform DWT operation on the data block to be processed to generate wavelet coefficients, and transmit the wavelet coefficients to the processing device 220; the processing device 220 is used to perform at least one of the following processing on the wavelet coefficients: Noise reduction processing, DWT inverse operation, quantization processing and entropy coding processing.
例如,该图像处理装置200可以用于基于DWT变换对信号进行去噪。具体地,首先对含噪声的信号进行小波变换,即通过DWT运算装置210进行小波变换,以生成小波系数;其次,对变换得到的小波系数进行某种处理,以去除其中包含的噪声,即通过处理装置220进行降噪处理,该降噪处理可以为对该小波系数进行降噪处理,以去除其中包含的噪声;最后,对处理后的小波系数进行小波逆变换,得到去噪后的信号,即通过处理装置220进行DWT逆运算,该DWT逆运算为对降噪处理后的小波系数进行DWT逆变换,输出去燥后的信号。For example, the image processing device 200 may be used to denoise signals based on DWT transformation. Specifically, firstly, wavelet transformation is performed on the noisy signal, that is, the wavelet transformation is performed by the DWT operation device 210 to generate wavelet coefficients; secondly, the wavelet coefficients obtained by the transformation are processed to remove the noise contained therein, that is, through The processing device 220 performs noise reduction processing. The noise reduction processing may be to perform noise reduction processing on the wavelet coefficients to remove the noise contained therein; finally, perform wavelet inverse transformation on the processed wavelet coefficients to obtain a denoised signal, That is, the DWT inverse operation is performed by the processing device 220, and the DWT inverse operation is to perform the DWT inverse transformation on the wavelet coefficients after the noise reduction processing, and output the de-sanded signal.
再例如,该图像处理装置200还可以用于编码器的处理过程。其中,处理装置220的量化处理可以包括:对按照预设的量化步长对小波系数进行量化处理,并将量化处理后的小波系数发送至该熵编码装置;该处理装置220的熵编码处理可以包括:根据预设的编码规则,对量化处理后的该小波系数进行编码。For another example, the image processing device 200 may also be used in the processing process of an encoder. The quantization processing of the processing device 220 may include: quantizing the wavelet coefficients according to a preset quantization step size, and sending the quantized wavelet coefficients to the entropy encoding device; the entropy encoding processing of the processing device 220 may Including: encoding the wavelet coefficient after the quantization process according to a preset encoding rule.
可选的,本申请实施例还提出了一种可移动平台。具体地,图11示出了本申请实施例的可移动平台300的示意性框图。如图11所示,该可移动平台300包括:机体310;动力系统320,设于该机体310内,用于为该可移动平台300提供动力;图像采集装置330,用于采集图像;以及图像处理装置340,用于对该图像进行处理。其中,该图像处理装置340可以为本申请实施例中的图像处理装置,例如,该图像处理装置340可以为本申请实施例的图像处理装置200。该图像处理装置340可以包括本申请实施例中的DWT运算装置,例如,可以包括本申请实施例的DWT运算装置100。Optionally, the embodiment of the present application also proposes a movable platform. Specifically, FIG. 11 shows a schematic block diagram of a movable platform 300 according to an embodiment of the present application. As shown in FIG. 11, the movable platform 300 includes: a body 310; a power system 320, which is provided in the body 310, and is used to provide power for the movable platform 300; an image acquisition device 330, which is used to collect images; The processing device 340 is used to process the image. The image processing device 340 may be the image processing device in the embodiment of the application, for example, the image processing device 340 may be the image processing device 200 in the embodiment of the application. The image processing device 340 may include the DWT computing device in the embodiment of the present application, for example, may include the DWT computing device 100 in the embodiment of the present application.
本发明实施例中的可移动平台300可以指任意可移动设备,该可移动设备可以在任何合适的环境下移动,例如,空气中(例如,定翼飞机、旋翼飞机,或既没有定翼也没有旋翼的飞机)、水中(例如,轮船或潜水艇)、陆地上(例如,汽车或火车)、太空(例如,太空飞机、卫星或探测器),以及以上各种环境的任何组合。该可移动设备可以是飞机,例如无人机(Unmanned Aerial Vehicle,简称为“UAV”)。The movable platform 300 in the embodiment of the present invention can refer to any movable device that can be moved in any suitable environment, for example, in the air (for example, a fixed-wing aircraft, a rotary-wing aircraft, or a fixed-wing aircraft or a rotary-wing aircraft without fixed wings or Aircraft without rotors), water (for example, ships or submarines), on land (for example, cars or trains), space (for example, space planes, satellites or probes), and any combination of the above various environments. The movable device may be an airplane, such as a drone (Unmanned Aerial Vehicle, referred to as "UAV" for short).
机体310也可以称为机身,该机身可以包括中心架以及与中心架连接的一个或多个机臂,一个或多个机臂呈辐射状从中心架延伸出。脚架与机身连 接,用于在UAV着陆时起支撑作用。The body 310 may also be referred to as a body. The body may include a center frame and one or more arms connected to the center frame, and the one or more arms extend radially from the center frame. The tripod is connected to the fuselage to support the UAV during landing.
动力系统320可以包括电子调速器(简称为电调)、一个或多个螺旋桨以及与一个或多个螺旋桨相对应的一个或多个电机,其中电机连接在电子调速器与螺旋桨之间,电机和螺旋桨设置在对应的机臂上;电子调速器用于接收飞行控制器产生的驱动信号,并根据驱动信号提供驱动电流给电机,以控制电机的转速。电机用于驱动螺旋桨旋转,从而为UAV的飞行提供动力,该动力使得UAV能够实现一个或多个自由度的运动。应理解,电机可以是直流电机,也可以交流电机。另外,电机可以是无刷电机,也可以有刷电机。The power system 320 may include an electronic governor (referred to as an ESC for short), one or more propellers, and one or more motors corresponding to the one or more propellers, where the motors are connected between the electronic governor and the propellers, The motor and the propeller are arranged on the corresponding arm; the electronic governor is used to receive the driving signal generated by the flight controller, and provide a driving current to the motor according to the driving signal to control the speed of the motor. The motor is used to drive the propeller to rotate to provide power for the flight of the UAV, which enables the UAV to achieve one or more degrees of freedom of movement. It should be understood that the motor may be a DC motor or an AC motor. In addition, the motor can be a brushless motor or a brush motor.
所述图像采集装置330包括拍摄设备(例如,相机、摄像机等)或视觉传感器(例如,单目摄像头或双/多目摄像头等)。The image acquisition device 330 includes a photographing device (for example, a camera, a video camera, etc.) or a visual sensor (for example, a monocular camera or a dual/multi-view camera, etc.).
可选的,本申请实施例还提出了一种相机。具体地,图12示出了本申请实施例的相机400的示意性框图。如图12所示,该相机400包括:外壳410;镜头组件420,设于该外壳410内部;传感器模块430,设于该外壳410内部并设于该镜头组件420的后端,用于感知通过该镜头组件420的光并生成电信号;以及图像处理装置440,用于对该电信号进行处理。Optionally, an embodiment of the present application also proposes a camera. Specifically, FIG. 12 shows a schematic block diagram of a camera 400 according to an embodiment of the present application. As shown in FIG. 12, the camera 400 includes: a housing 410; a lens assembly 420 arranged inside the housing 410; a sensor module 430 arranged inside the housing 410 and at the rear end of the lens assembly 420 for sensing passing The light of the lens assembly 420 generates an electric signal; and an image processing device 440 for processing the electric signal.
其中,该图像处理装置440可以为本申请实施例中的图像处理装置,例如,该图像处理装置440可以为本申请实施例的图像处理装置200。该图像处理装置440可以包括本申请实施例中的DWT运算装置,例如,可以包括本申请实施例的DWT运算装置100。Wherein, the image processing device 440 may be an image processing device in an embodiment of the application, for example, the image processing device 440 may be an image processing device 200 in an embodiment of the application. The image processing device 440 may include the DWT computing device in the embodiment of the present application, for example, may include the DWT computing device 100 in the embodiment of the present application.
应理解,本申请各实施例的装置中的各个电路中还可以包括基于存储器和处理器实现的部分,其中,各存储器用于存储用于执行本申请个实施例的方法的指令,处理器执行上述指令,使得对应部分可以执行本申请各实施例的部分方法。It should be understood that each circuit in the device of each embodiment of the present application may also include a memory and processor-based part, where each memory is used to store instructions for executing the method of each embodiment of the present application, and the processor executes The foregoing instructions enable the corresponding part to execute part of the methods in the embodiments of the present application.
应理解,本申请实施例中提及的处理器可以是中央处理单元(Central Processing Unit,CPU),还可以是其他通用处理器、数字信号处理器(Digital Signal Processor,DSP)、专用集成电路(Application Specific Integrated Circuit,ASIC)、现成可编程门阵列(Field Programmable Gate Array,FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。It should be understood that the processor mentioned in the embodiments of this application may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), and application-specific integrated circuits ( Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
还应理解,本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器,或可包括易失性和非易失性存储器两者。其中,非易失性存储器 可以是只读存储器(Read-Only Memory,ROM)、可编程只读存储器(Programmable ROM,PROM)、可擦除可编程只读存储器(Erasable PROM,EPROM)、电可擦除可编程只读存储器(Electrically EPROM,EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory,RAM),其用作外部高速缓存。通过示例性但不是限制性说明,许多形式的RAM可用,例如静态随机存取存储器(Static RAM,SRAM)、动态随机存取存储器(Dynamic RAM,DRAM)、同步动态随机存取存储器(Synchronous DRAM,SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM,DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM,ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM,SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM,DR RAM)。It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. The volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache. By way of exemplary but not restrictive description, many forms of RAM are available, such as static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous connection dynamic random access memory (Synchlink DRAM, SLDRAM) ) And Direct Rambus RAM (DR RAM).
需要说明的是,当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时,存储器(存储模块)集成在处理器中。It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated in the processor.
应注意,本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.
本申请实施例还提供一种计算机可读存储介质,其上存储有指令,当指令在计算机上运行时,使得计算机执行上述各方法实施例的方法。The embodiments of the present application also provide a computer-readable storage medium on which instructions are stored, and when the instructions are run on a computer, the computer executes the methods of the foregoing method embodiments.
本申请实施例还提供一种计算设备,该计算设备包括上述计算机可读存储介质。An embodiment of the present application also provides a computing device, which includes the computer-readable storage medium described above.
本申请实施例可以应用在飞行器,尤其是无人机领域。The embodiments of the present application can be applied to aircraft, especially in the field of drones.
应理解,本申请各实施例的电路、子电路、子单元的划分只是示意性的。本领域普通技术人员可以意识到,本文中所公开的实施例描述的各示例的电路、子电路和子单元,能够再行拆分或组合。It should be understood that the division of circuits, sub-circuits, and sub-units in each embodiment of the present application is only illustrative. A person of ordinary skill in the art may be aware that the circuits, sub-circuits, and sub-units of the examples described in the embodiments disclosed herein can be further divided or combined.
在上述实施例中,可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时,可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机指令时,全部或部分地产生按照本申请实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中,或者从一个计算 机可读存储介质向另一个计算机可读存储介质传输,例如,计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(Digital Subscriber Line,DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质(例如,软盘、硬盘、磁带)、光介质(例如,高密度数字视频光盘(Digital Video Disc,DVD))、或者半导体介质(例如,固态硬盘(Solid State Disk,SSD))等。In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from a website, computer, server, or data center through a cable (such as Coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) to transmit to another website, computer, server, or data center. A computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrated with one or more available media. Available media can be magnetic media (for example, floppy disks, hard drives, tapes), optical media (for example, high-density digital video discs (Digital Video Disc, DVD)), or semiconductor media (for example, solid state disks (Solid State Disk, SSD)) )Wait.
应理解,本申请各实施例均是以总位宽为16位(bit)为例进行说明的,本申请各实施例可以适用于其他的位宽。It should be understood that each embodiment of the present application is described by taking a total bit width of 16 bits as an example, and each embodiment of the present application may be applicable to other bit widths.
应理解,说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此,在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外,这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment" or "in an embodiment" in various places throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner.
应理解,在本申请的各种实施例中,上述各过程的序号的大小并不意味着执行顺序的先后,各过程的执行顺序应以其功能和内在逻辑确定,而不应对本申请实施例的实施过程构成任何限定。It should be understood that, in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application. The implementation process constitutes any limitation.
应理解,在本申请实施例中,“与A相应的B”表示B与A相关联,根据A可以确定B。但还应理解,根据A确定B并不意味着仅仅根据A确定B,还可以根据A和/或其它信息确定B。It should be understood that in the embodiments of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean that B is determined only according to A, and B can also be determined according to A and/or other information.
应理解,本文中术语“和/或”,仅仅是一种描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B这三种情况。另外,本文中字符“/”,一般表示前后关联对象是一种“或”的关系。It should be understood that the term "and/or" in this article is only an association relationship describing the associated objects, indicating that there can be three types of relationships, for example, A and/or B can mean: A alone exists, and both A and B exist. , There are three cases of B alone. In addition, the character "/" in this text generally indicates that the associated objects before and after are in an "or" relationship.
本领域普通技术人员可以意识到,结合本文中所公开的实施例描述的各示例的单元及算法步骤,能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行,取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能,但是这种实现不应认为超出本申请的范 围。A person of ordinary skill in the art may be aware that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.
所属领域的技术人员可以清楚地了解到,为描述的方便和简洁,上述描述的系统、装置和单元的具体工作过程,可以参考前述方法实施例中的对应过程,在此不再赘述。Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.
在本申请所提供的几个实施例中,应该理解到,所揭露的系统、装置和方法,可以通过其它的方式实现。例如,以上所描述的装置实施例仅仅是示意性的,例如,所述单元的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个单元或组件可以结合或者可以集成到另一个系统,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或单元的间接耦合或通信连接,可以是电性,机械或其它的形式。In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的,作为单元显示的部件可以是或者也可以不是物理单元,即可以位于一个地方,或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
另外,在本申请各个实施例中的各功能单元可以集成在一个处理单元中,也可以是各个单元单独物理存在,也可以两个或两个以上单元集成在一个单元中。In addition, the functional units in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.
Claims (21)
- 一种DWT运算装置,其特征在于,包括:列电路(110)、交织器电路(120)和行电路(130),A DWT arithmetic device, characterized in that it comprises a column circuit (110), an interleaver circuit (120) and a row circuit (130),所述列电路(110)用于:接收预设的待处理数据块,对所述待处理数据块按列进行DWT运算生成中间数据块,并将所述中间数据块按列输出至所述交织器电路(120)中;The column circuit (110) is configured to: receive preset data blocks to be processed, perform DWT operations on the data blocks to be processed in columns to generate intermediate data blocks, and output the intermediate data blocks to the interleaver in columns In the device circuit (120);所述交织器电路(120)用于:对按列输入的所述中间数据块按行输出至所述行电路(130)中;The interleaver circuit (120) is used to: output the intermediate data block input in columns to the row circuit (130) in rows;所述行电路(130)用于:将按行输入的所述中间数据块进行DWT运算,以获得运算结果。The row circuit (130) is used for performing DWT operation on the intermediate data block input by row to obtain an operation result.
- 根据权利要求1所述的DWT运算装置,其特征在于,所述DWT运算包括DWT53运算和/或DWT97运算。The DWT operation device according to claim 1, wherein the DWT operation includes DWT53 operation and/or DWT97 operation.
- 根据权利要求2所述的DWT运算装置,其特征在于,所述列电路(110)包括第一DWT53单元和第一DWT97单元,所述行电路(120)包括第二DWT53单元和第二DWT97单元,The DWT operation device according to claim 2, wherein the column circuit (110) includes a first DWT53 unit and a first DWT97 unit, and the row circuit (120) includes a second DWT53 unit and a second DWT97 unit ,所述第一DWT53单元用于:对按列输入的所述待处理数据块进行所述DWT53运算;The first DWT53 unit is used to: perform the DWT53 operation on the to-be-processed data block input by column;所述第一DWT97单元用于:对按列输入的所述待处理数据块进行所述DWT97运算;The first DWT97 unit is used to: perform the DWT97 operation on the to-be-processed data block input by column;所述第二DWT53单元用于:对按行输入的所述中间数据块进行所述DWT53运算;The second DWT53 unit is used to: perform the DWT53 operation on the intermediate data block input by line;所述第二DWT97单元用于:对按行输入的所述中间数据块进行所述DWT97运算。The second DWT97 unit is used for: performing the DWT97 operation on the intermediate data block input by line.
- 根据权利要求3所述的DWT运算装置,其特征在于,所述列电路(110)包括:The DWT computing device according to claim 3, wherein the column circuit (110) comprises:第一地址计算单元,用于将按列输入的所述待处理数据块输出至所述第一DWT53单元和/或所述第一DWT97单元;A first address calculation unit, configured to output the to-be-processed data block input by column to the first DWT53 unit and/or the first DWT97 unit;所述行电路(120)包括:The row circuit (120) includes:第二地址计算单元,用于将按行输入的所述中间数据块输出至所述第二DWT53单元和/或所述第二DWT97单元。The second address calculation unit is configured to output the intermediate data block input in rows to the second DWT53 unit and/or the second DWT97 unit.
- 根据权利要求2至4中任一项所述的DWT运算装置,其特征在于,所述列电路(110)包括至少一个存储单元,所述至少一个存储单元用于:存储输入的第一列数据在经过所述DWT53运算和/或所述DWT97运算后输出的至少一个中间结果,所述至少一个中间结果用于与所述第一列数据对应的第二列数据的所述DWT53运算和/或所述DWT97运算过程,所述第一列数据为输入的所述待处理数据块中的任意一列数据。The DWT computing device according to any one of claims 2 to 4, wherein the column circuit (110) comprises at least one storage unit, and the at least one storage unit is used to store the input first column data At least one intermediate result output after the DWT53 operation and/or the DWT97 operation, and the at least one intermediate result is used for the DWT53 operation and/or the second column of data corresponding to the first column of data In the DWT97 operation process, the first column of data is any column of data in the input data block to be processed.
- 根据权利要求5所述的DWT运算装置,其特征在于,所述至少一个存储单元包括第一存储单元和第二存储单元,The DWT computing device according to claim 5, wherein the at least one storage unit comprises a first storage unit and a second storage unit,所述第一存储单元用于:存储所述第一列数据在经过所述DWT53运算或者所述DWT97运算后输出的第一中间结果,所述第一中间结果用于所述第二列数据的所述DWT53运算过程或者所述DWT97运算过程;The first storage unit is used to store the first intermediate result output after the DWT53 operation or the DWT97 operation of the first column data, and the first intermediate result is used for the second column data The DWT53 operation process or the DWT97 operation process;所述第二存储单元用于:存储所述第一列数据在经过所述DWT97运算后输出的第二中间结果,所述第二中间结果用于所述第二列数据的所述DWT53运算过程,所述第一列数据为位于所述第二列数据的正上方且与所述第二列数据相邻的一列数据。The second storage unit is used to store a second intermediate result output after the DWT97 operation of the first column of data, and the second intermediate result is used in the DWT53 operation process of the second column of data The first column of data is a column of data located directly above the second column of data and adjacent to the second column of data.
- 根据权利要求2至4中任一项所述的DWT运算装置,其特征在于,所述行电路(130)包括至少一个存储单元,所述至少一个存储单元用于:存储输入的第一行数据在经过所述DWT53运算和/或所述DWT97运算后输出的至少一个中间结果,所述至少一个中间结果用于与所述第一行数据对应的第二行数据的所述DWT53运算和/或所述DWT97运算过程,所述第一行数据为输入的所述中间数据块中的任意一行数据。The DWT computing device according to any one of claims 2 to 4, wherein the row circuit (130) comprises at least one storage unit, and the at least one storage unit is used to store the first row of input data At least one intermediate result output after the DWT53 operation and/or the DWT97 operation, the at least one intermediate result is used for the DWT53 operation and/or the second row of data corresponding to the first row of data In the DWT97 operation process, the first row of data is any row of data in the input intermediate data block.
- 根据权利要求7所述的DWT运算装置,其特征在于,所述至少一个存储单元包括第三存储单元和第四存储单元,The DWT computing device according to claim 7, wherein the at least one storage unit includes a third storage unit and a fourth storage unit,所述第三存储单元用于:存储所述第一行数据在经过所述DWT53运算或者所述DWT97运算后输出的第三中间结果,所述第三中间结果用于所述第二行数据的所述DWT5 3运算过程或者所述DWT97运算过程;The third storage unit is used to store a third intermediate result output after the DWT53 operation or the DWT97 operation of the first row of data, and the third intermediate result is used for the second row of data The DWT5 3 operation process or the DWT97 operation process;所述第四存储单元用于:存储所述第一行数据在经过所述DWT97运算后输出的第四中间结果,所述第四中间结果用于所述第二行数据的所述DWT53运算过程,所述第一行数据为位于所述第二行数据的左边且与所述第二行数据相邻的一行数据。The fourth storage unit is configured to store a fourth intermediate result output after the DWT97 operation of the first row of data, and the fourth intermediate result is used in the DWT53 operation process of the second row of data The first row of data is a row of data located to the left of the second row of data and adjacent to the second row of data.
- 根据权利要求2至8中任一项所述的DWT运算装置,其特征在于, 所述行电路(130)还包括:The DWT computing device according to any one of claims 2 to 8, wherein the row circuit (130) further comprises:定标器,用于对在行电路(130)中经过所述DWT97运算的输出结果进行放大或缩小处理。The scaler is used to enlarge or reduce the output result of the DWT97 operation in the row circuit (130).
- 一种用于DWT运算装置中处理数据的方法,其特征在于,所述DWT运算装置包括:列电路、交织器电路和行电路,所述方法包括:A method for processing data in a DWT computing device, wherein the DWT computing device includes a column circuit, an interleaver circuit, and a row circuit, and the method includes:获取预设的待处理数据块;Obtain preset data blocks to be processed;通过所述列电路对所述待处理数据块按列进行DWT运算生成中间数据块,并将所述中间数据块按列输出至所述交织器电路中;Performing a DWT operation on the to-be-processed data block by column by the column circuit to generate an intermediate data block, and output the intermediate data block to the interleaver circuit by column;通过所述交织器电路对按列输入的所述中间数据块按行输出至所述行电路中;Output the intermediate data blocks input in columns to the row circuit in rows by the interleaver circuit;通过所述行电路将按行输入的所述中间数据块进行DWT运算,以获得运算结果。DWT operation is performed on the intermediate data block input by row through the row circuit to obtain the operation result.
- 根据权利要求10所述的方法,其特征在于,所述DWT运算包括DWT53运算和/或DWT97运算。The method according to claim 10, wherein the DWT operation comprises DWT53 operation and/or DWT97 operation.
- 根据权利要求11所述的方法,其特征在于,所述列电路包括第一DWT53单元和第一DWT97单元,所述行电路包括第二DWT53单元和第二DWT97单元,The method according to claim 11, wherein the column circuit includes a first DWT53 unit and a first DWT97 unit, and the row circuit includes a second DWT53 unit and a second DWT97 unit,所述通过所述列电路对所述待处理数据块按列进行DWT运算生成中间数据块,包括:The performing DWT operation on the data block to be processed by the column circuit to generate the intermediate data block by column includes:通过所述第一DWT53单元,对按列输入的所述待处理数据块进行所述DWT53运算生成所述中间数据块,或者,Through the first DWT53 unit, perform the DWT53 operation on the to-be-processed data block input by column to generate the intermediate data block, or,通过所述第一DWT97单元,对按列输入的所述待处理数据块进行所述DWT97运算生成所述中间数据块;Using the first DWT97 unit to perform the DWT97 operation on the to-be-processed data block input by column to generate the intermediate data block;所述通过所述行电路将按行输入的所述中间数据块进行DWT运算,包括:The performing DWT operation on the intermediate data block input by row by the row circuit includes:通过所述第二DWT53单元,对按行输入的所述中间数据块进行所述DWT53运算,或者,Perform the DWT53 operation on the intermediate data block input by row through the second DWT53 unit, or,通过所述第二DWT97单元,对按行输入的所述中间数据块进行所述DWT97运算。Through the second DWT97 unit, the DWT97 operation is performed on the intermediate data block input by line.
- 根据权利要求12所述的方法,其特征在于,所述列电路还包括第一地址计算单元,所述行电路还包括第二地址计算单元,The method according to claim 12, wherein the column circuit further comprises a first address calculation unit, and the row circuit further comprises a second address calculation unit,所述方法还包括:The method also includes:通过所述第一地址计算单元,将按列输入的所述待处理数据块输出至所述第一DWT53单元和/或所述第一DWT97单元;Output the to-be-processed data block input by column to the first DWT53 unit and/or the first DWT97 unit through the first address calculation unit;通过所述第二地址计算单元,将按行输入的所述中间数据块输出至所述第二DWT53单元和/或所述第二DWT97单元。Through the second address calculation unit, the intermediate data blocks input in rows are output to the second DWT53 unit and/or the second DWT97 unit.
- 根据权利要求11至13中任一项所述的方法,其特征在于,所述列电路包括至少一个存储单元,The method according to any one of claims 11 to 13, wherein the column circuit includes at least one memory cell,所述列电路中的DWT运算包括:The DWT operation in the column circuit includes:通过所述至少一个存储单元,存储输入的第一列数据在经过所述DWT53运算和/或所述DWT97运算后输出的至少一个中间结果,所述至少一个中间结果用于与所述第一列数据对应的第二列数据的所述DWT53运算和/或所述DWT97运算过程,所述第一列数据为输入的所述待处理数据块中的任意一列数据。The at least one storage unit stores at least one intermediate result of the input first column of data after the DWT53 operation and/or the DWT97 operation, and the at least one intermediate result is used to compare with the first column For the DWT53 operation and/or the DWT97 operation process of the second column of data corresponding to the data, the first column of data is any column of data in the input data block to be processed.
- 根据权利要求14所述的方法,其特征在于,所述至少一个存储单元包括第一存储单元和第二存储单元,The method according to claim 14, wherein the at least one storage unit comprises a first storage unit and a second storage unit,所述通过所述至少一个存储单元,存储输入的第一列数据在经过所述DWT53运算和/或所述DWT97运算后输出的至少一个中间结果,包括:Said storing at least one intermediate result outputted after the DWT53 operation and/or the DWT97 operation of the input first column of data through the at least one storage unit includes:通过所述第一存储单元,存储所述第一列数据在经过所述DWT53运算或者所述DWT97运算后输出的第一中间结果,所述第一中间结果用于所述第二列数据的所述DWT5 3运算过程或者所述DWT97运算过程;The first storage unit stores the first intermediate result of the first column of data output after the DWT53 operation or the DWT97 operation, and the first intermediate result is used for all of the second column of data The DWT5 3 operation process or the DWT97 operation process;通过所述第二存储单元,存储所述第一列数据在经过所述DWT97运算后输出的第二中间结果,所述第二中间结果用于所述第二列数据的所述DWT53运算过程,所述第一列数据为位于所述第二列数据的正上方且与所述第二列数据相邻的一列数据。Through the second storage unit, the second intermediate result output after the DWT97 operation of the first column of data is stored, and the second intermediate result is used in the DWT53 operation process of the second column of data, The first column of data is a column of data located directly above the second column of data and adjacent to the second column of data.
- 根据权利要求11至13中任一项所述的方法,其特征在于,所述行电路包括至少一个存储单元,The method according to any one of claims 11 to 13, wherein the row circuit includes at least one storage unit,所述行电路中的DWT运算包括:The DWT operation in the row circuit includes:通过所述至少一个存储单元,存储输入的第一行数据在经过所述DWT53运算和/或所述DWT97运算后输出的至少一个中间结果,所述至少一个中间结果用于与所述第一行数据对应的第二行数据的所述DWT53运算和/或所述DWT97运算过程,所述第一行数据为输入的所述中间数据块中的 任意一行数据。The at least one storage unit stores at least one intermediate result of the input first row of data after the DWT53 operation and/or the DWT97 operation, and the at least one intermediate result is used to compare with the first row The DWT53 operation and/or the DWT97 operation process of the second row of data corresponding to the data, the first row of data is any row of data in the input intermediate data block.
- 根据权利要求16所述的方法,其特征在于,所述至少一个存储单元包括第三存储单元和第四存储单元,The method according to claim 16, wherein the at least one storage unit includes a third storage unit and a fourth storage unit,所述通过所述至少一个存储单元,存储输入的第一行数据在经过所述DWT53运算和/或所述DWT97运算后输出的至少一个中间结果,包括:Said storing at least one intermediate result outputted after the DWT53 operation and/or the DWT97 operation of the first row of input data by the at least one storage unit includes:通过所述第三存储单元,存储所述第一行数据在经过所述DWT53运算或者所述DWT97运算后输出的第三中间结果,所述第三中间结果用于所述第二行数据的所述DWT53运算过程或者所述DWT97运算过程;Through the third storage unit, the third intermediate result of the first row of data output after the DWT53 operation or the DWT97 operation is stored, and the third intermediate result is used for all of the second row of data. The DWT53 operation process or the DWT97 operation process;通过所述第四存储单元,存储所述第一行数据在经过所述DWT97运算后输出的第四中间结果,所述第四中间结果用于所述第二行数据的所述DWT53运算过程,所述第一行数据为位于所述第二行数据的左边且与所述第二行数据相邻的一行数据。The fourth storage unit stores the fourth intermediate result output after the DWT97 operation of the first row of data, and the fourth intermediate result is used in the DWT53 operation process of the second row of data, The first row of data is a row of data located to the left of the second row of data and adjacent to the second row of data.
- 根据权利要求11至17中任一项所述的方法,其特征在于,所述行电路还包括:定标器;The method according to any one of claims 11 to 17, wherein the row circuit further comprises: a scaler;所述方法还包括:The method also includes:通过所述定标器,对在行电路中经过所述DWT97运算的输出结果进行放大或缩小处理后按行输出。Through the scaler, the output result of the DWT97 operation in the row circuit is enlarged or reduced, and then output by row.
- 一种图像处理装置,其特征在于,包括:处理装置和如权利要求1至9中任一项所述的DWT运算装置;An image processing device, characterized by comprising: a processing device and the DWT computing device according to any one of claims 1 to 9;所述DWT运算装置用于对所述待处理数据块进行DWT运算后生成小波系数,并将所述小波系数传输至所述处理装置;The DWT operation device is configured to perform DWT operation on the data block to be processed to generate wavelet coefficients, and transmit the wavelet coefficients to the processing device;所述处理装置用于对所述小波系数进行以下一种或多种处理:The processing device is configured to perform one or more of the following processing on the wavelet coefficients:降噪处理,DWT逆运算,量化处理和熵编码处理。Noise reduction processing, DWT inverse operation, quantization processing and entropy coding processing.
- 一种可移动平台,其特征在于,包括:A movable platform, characterized in that it comprises:机体;Body动力系统,设于所述机体内,用于为所述可移动平台提供动力;The power system is arranged in the body and used to provide power for the movable platform;图像采集装置,用于采集图像;以及An image capture device for capturing images; and如权利要求19所述的图像处理装置,用于对所述图像进行处理。The image processing device according to claim 19, which is used to process the image.
- 一种相机,其特征在于,包括:A camera, characterized in that it comprises:外壳;shell;镜头组件,设于所述外壳内部;The lens assembly is arranged inside the housing;传感器模块,设于所述外壳内部并设于所述镜头组件的后端,用于感知通过所述镜头组件的光并生成电信号;以及A sensor module, arranged inside the housing and at the rear end of the lens assembly, for sensing light passing through the lens assembly and generating electrical signals; and如权利要求19所述的图像处理装置,用于对所述电信号进行处理。The image processing device according to claim 19, configured to process the electrical signal.
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