CN109168005A - A kind of two-dimensional discrete wavelet conversion construction design method improving storage efficiency - Google Patents
A kind of two-dimensional discrete wavelet conversion construction design method improving storage efficiency Download PDFInfo
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Abstract
The present invention relates to a kind of two-dimensional discrete wavelet conversion construction design methods for improving storage efficiency, it is improved based on 9/7 wavelet arithmetic, it is characterized in that, antenna scan optimization: the wavelet coefficient that input image data obtains after multilevel two-dimensional 9/7DWT resume module can enter EBCOT module and be further processed；Concurrency optimization: code data in block is reduced to the 1/2 of upper level using the higher lateral parallel scan mode of hardware efficiency, every grade of two-dimensional DWT modular concurrent degree, eliminates the structure caching between non-collapsible structural level, and every level-one control need to only modify code block size parameter；The transmitting optimization of mould data in block: each code block needs boundary on it and left margin to receive data, spreads out of number in its lower boundary and right margin；Using storage unit multiplex mode, general boundaries caching is equivalent to each two boundary of basic coding block of caching；The data transmission on boundary is median D1, D2, D3 and the D4 transmitted in conversion module.
Description
Technical field
The invention belongs to super large-scale integration (Very Large Scale Integration, abbreviation VLSI) designs
Scope designs a kind of two-dimensional discrete wavelet conversion (Discrete Wavelet Transform, abbreviation for improving storage efficiency
DWT) structure.
Background technique
JPEG2000 is one kind in the widely applied New Image compression standard in compression of images field.2-d discrete wavelet becomes
(discrete wavelet transform, DWT) is changed since its good Time-Frequency Localization performance is as JEPG2000 compression
One of core technology.Image information is decomposed into multi-stage high-frequency component and low frequency component by two-dimensional DWT, is that optimized truncation is embedded
Block coding (embedded block coding with optimized truncation, EBCOT) provides initial data.
EBCOT bit planes coding module is read wavelet coefficient in the form of code block and is processed into contextual information, after compiled through entropy
Code and rate distortion truncation coding form compressed bit stream.It is efficient hard to meet high speed processing requirement since algorithm calculation amount is larger
Part DWT design optimization is increasingly becoming research hotspot.
For single-stage 9/7DWT hardware realization, document [1] proposes a kind of dual input/dual output knot of lateral Z-type scanning
Structure, critical path is a multiplier delay, but its structure degree of parallelism is lower to cause the disposed of in its entirety time longer, it is difficult to be met
High-speed requirement.Document [2] resets input data, and carrying out module design by overturning structure reduces image disposed of in its entirety
Time, however the higher while control logic of interior data caching is complex.Hu and Jong is introduced in document [3] based on vertical
To the parallel organization of scanning, the processing speed of system is improved, but the structure needs just open after the completion of whole image storage
Begin processing data, therefore storage demand is larger.Assembly line use in document [4] and introduce canonical multiplication structure reduction critical path for
One adder delay, but the lower arithmetic eror of coefficient precision in its structure is larger, it is difficult to meet application requirement.Document
[5] multiplier-free structure of high coefficient precision is used to reduce data error, and eliminates piece external storage resource consumption, still
The structure degree of parallelism is equally lower, therefore the disposed of in its entirety time longer high-speed data that is unfavorable for handles application environment.
Multilevel structure is optimized, document [6] propose it is a kind of adjusted by degree of parallelism eliminate grade between the multilevel structure that stores,
But critical path delay is still larger.Document [7] lowers storage area by high degree of parallelism, while lowering critical path is one
Multiplier delay, but the structure is based on convolution algorithm that be designed computational complexity higher.Document [8] repeats to sweep by introducing
The mode retouched devises novel high parallel organization, eliminates transformation in the grade in first order conversion module and caches, but the structure
It is handled between calculation resources are higher and grade complex.Lai and Chung [9] proposes a kind of scanning mode of code block optimization, generates
Multilevel wavelet coefficient can directly be handled by parallel EBCOT, reduce the storage of intermodule.However which employs fold multistage knot
Structure is kept in greatly in module, while the approximate processing on code block boundary reduces compression quality in structure.Document [10] is also based on block
Scanning optimizes to cache cancellation module scanning mode, however caches between grade and excessive still seriously constrain systematicness
Energy.
It is found by the analysis to existing structure, this invention devises a kind of hard-wired new applied to JPEG2000
The non-collapsible multilevel two-dimensional 9/7DWT structure of type efficient storage, by the adjustment of improvement, data parallel degree to scanning mode with
And the optimization of mould data in block transmitting, system area is greatly reduced, hardware efficiency is improved.
Document [11] proposes optimization boosting algorithm according to having general 9/7DWT boosting algorithm, by a series of transformation,
Formula is as follows:
SL=KH (2n+1) (9)
In formula: D1 (n)~D4 (n) is 4 intermediate variables；H (2n+1) is the high-frequency wavelet coefficient before normalization；L(2n)
For the low-frequency wavelet coefficients before normalization；X (n) representative is originally inputted pixel value；N is pixel coordinate；SHAnd SLRepresentation transformation produces
Raw high-frequency wavelet coefficient and low-frequency wavelet coefficients；α, β, γ, δ and K are transformation coefficient.For two-dimensional transform, data are through space
4 wavelet coefficients i.e. low frequency-low frequency coefficient S is finally obtained after rank transformation processingLL, high frequency-low frequency coefficient SHL, low frequency-high frequency system
Number SLHWith high frequency-high frequency coefficient SHH.The present invention will improve design based on (10) by formula (1)~formula.
Bibliography:
[1]DARJI A,AGRAWAL S,OZA A,et al.Dual-scan parallel flipping
architecture for a lifting-based 2-D discrete wavelet transform[J].IEEE
Transactions on Circuits&Systems II Express Briefs,2014,61(6):433-437
[2]WANG Jianxin,ZHU En.A high-throughput VLSI design for JPEG20009/
7discrete wavelettransform[J].Journal ofSoutheastUniversity,2015,31(01):19-
24.
[3]HU Y,JONG C C.A Memory-efficient scalable architecture for
lifting-based discrete wavelet transform[J].IEEE Transactions on Circuits&
Systems II Analog&Digital Signal Processing,2013,60(8):502-506.
[4] 9/7 Wavelet Transformation Algorithm realization [J] the optical instrument of Wang Yu, Ma Junshan, Wang Hua based on FPGA, 2014,36
(05):403-408.
WANG Yu,MA Junshan,WANG Hua.FPGA implementation of 9/7wavelet
transform algorithm[J].Optical Instruments,2014,36(5):403-408.
[5] Jia Qi, Liang Yu, for a kind of no piece external storage of the Xi'an high-performance two-dimensional DWT framework [J] electronics technology it is big
Learn journal, 2017,44 (04): 150-155.
JIA Qi,LIANG Yu,ZHANG Wei.Hardware efficient 2-D DWT architecture
without Off-Chip RAM[J].Journal ofXidian University,2017,44(04):150-155.
[6]MOHANTY B K,MEHER P K.Memory efficient modular VLSI architecture
for high throughput and low-latency implementation ofmultilevel lifting 2-D
DWT[J].IEEE Transactions on Signal Processing,2011,59(5):2072-2084.
[7]MOHANTY B K,MEHER P K.Memory-efficient high-speed convolution-
based generic structure for multilevel 2-D DWT[J].IEEE Transactions on
Circuits and Systems for Video Technology,2013,23(2):353-363.
[8]HU Y,JONG C C.A memory-efficient high-throughput architecture for
lifting-based multi-level 2-D DWT[J].IEEE Transactions on Signal Processing,
2013,61(20):4975-4987.
[9]WU B F,LIN C F.Memory-efficient architecture for JPEG
2000coprocessor with large tile image[J].IEEE Transactions on Circuits&
Systems II Express Briefs,2006,53(4):304-308.
[10]YE L,HOU Z.Memory efficient multilevel discrete wavelet transform
schemes for JPEG2000[J].IEEE Transactions on Circuits&Systems for Video
Technology,2015,25(11):1773-1785.
[11]ZHANG W,JIANG Z,GAO Z,et al.An Efficient VLSI architecture for
lifting-based discrete wavelet transform[J].IEEE Transactions on Circuits&
Systems II Express Briefs,2012,59(3):158-162.
Summary of the invention
For multilevel discrete wavelet conversion module (DWT) and optimized truncation in JPEG2000 image compression encoding hardware realization
A large amount of wavelet coefficient memory bring cache problems between embedded module (EBCOT) propose a kind of new and effective storage
9/7 wavelet transform structure of multilevel two-dimensional.The present invention proposes a kind of VLSI design method of two-dimensional discrete wavelet conversion, this hair
Bright technical solution are as follows:
It is a kind of improve storage efficiency two-dimensional discrete wavelet conversion construction design method, based on 9/7 wavelet arithmetic into
Row improves, algorithmic formula such as (1)-(10):
SL=KH (2n+1) (9)
In formula: D1 (n)~D4 (n) is 4 intermediate variables；H (2n+1) is the high-frequency wavelet coefficient before normalization；L(2n)
For the low-frequency wavelet coefficients before normalization；X (n) representative is originally inputted pixel value；N is pixel coordinate；SHAnd SLRepresentation transformation produces
Raw high-frequency wavelet coefficient and low-frequency wavelet coefficients；α, β, γ, δ and K are transformation coefficient；For two-dimensional transform, data are through space
4 wavelet coefficients i.e. low frequency-low frequency coefficient S is finally obtained after rank transformation processingLL, high frequency-low frequency coefficient SHL, low frequency-high frequency system
Number SLHWith high frequency-high frequency coefficient SHH, which is characterized in that
Antenna scan optimization: according to JPEG2000 algorithm, input image data passes through multilevel two-dimensional 9/7DWT resume module
The wavelet coefficient obtained afterwards can enter EBCOT module and be further processed；For level-one two-dimensional structure, the knot based on block scan
Structure can directly obtain discrete wavelet coefficient code block, set the 9/7DWT code block size of scanning as 2H × 2H；For two-stage two dimension
Structure, the code block that the first order generates can be directly for EBCOT resume modules, and second level transformation is big by adjacent 4 in data scanning
The small code block for 2H × 2H forms DWT basic coding unit, is scanned in a manner of Z-type, and adjacent 4 sizes are the S of H × HLL1
Code block can generate EBCOT encoding block in the shortest time；It is in three-level transformation while raw to guarantee for three-level two-dimensional structure
At EBCOT encoding block, Z-type nested scan is carried out to the code block that 16 sizes are 2H × 2H；
Concurrency optimization: code data in block is using the higher lateral parallel scan mode of hardware efficiency, every grade of two-dimensional DWT mould
Block degree of parallelism is reduced to the 1/2 of upper level, eliminates the structure caching between non-collapsible structural level, it is big that every level-one control need to only modify code block
Small parameter；
The transmitting optimization of mould data in block: each code block needs boundary on it and left margin to receive data, in its lower boundary
Number is spread out of with right margin；Using storage unit multiplex mode, general boundaries caching is equivalent to caching each basic coding block both sides
Boundary；The data transmission on boundary is median D1, D2, D3 and the D4 transmitted in conversion module；Due to the multiplexing of spatial cache,
Keeping in size for the image of width N × N size, needed for the every level-one of rank transformation module isDWT basic coding unit is horizontal
To DWT module rank transformation is sequentially entered, conversion module data register only needs depth for 8 bases at once for the data transmission of right boundary
Present treatment cell size is kept in, for storing median D1, D2, D3 and D4 of H component and L * component respectively；
The present invention devises a kind of structure of new multistage two-dimensional discrete wavelet conversion, solves JPEG2000 compression of images
It is a large amount of small between multilevel discrete wavelet conversion module (DWT) and optimized truncation embedded module (EBCOT) in coded hardware realization
Wave system number stores bring cache problem.Every comparing result shows that 40% or more can be saved compared to existing optimum structure
Storage resource consumption has important practical value.
Detailed description of the invention
Fig. 1 is the basic processing unit rank transformation modular structure that the present invention designs
Fig. 2 is the two-dimentional 9/7DWT conversion module structure that the present invention designs
Fig. 3 is optimization block array sweeping mode of the invention
Fig. 4 is BORDER PROCESSING optimal way of the invention
Specific embodiment
The present invention is described in detail with reference to the accompanying drawing.
Two-dimentional 9/7DWT modular structure designed by the present invention as shown in Figure 1, initial data enter after, successively by rank transformation
Module, transposition module, row conversion module and Zoom module processing, final output discrete wavelet coefficient.Above-mentioned modules composition
Logic unit can individually to input data carry out wavelet transform processing, can also build and meet under any degree of parallelism parallel
The data processing of high-throughput.When building logic unit parallel to handle high-parallelism data, the column between any Unit two become
Size needed for changing the mold block is 4N.
The design data basic entry mode is that lateral parallel double electricity transmission enters, rank transformation module need to intermediate variables D 1, D2,
D3 is stored with D4, the input picture for being N × N for size, and required memory space is 4N.RAM1, RAM2, RAM3 in Fig. 2
Store median D1, D2, D3 and D4 respectively with RAM4.When designing parallel organization, 4 medians can be mentioned by a upper parallel modules
For, it is only necessary to median reading and writing data is carried out in the head and the tail module of parallel organization and RAM.Rank transformation is interior with row conversion module
Portion's structure is consistent, and for row conversion module, the data laterally inputted parallel are continuous data, therefore each median only needs
Want 2 data are temporary can meet data buffer storage demand.
Antenna scan optimization: according to JPEG2000 algorithm, input image data passes through multilevel two-dimensional 9/7DWT resume module
The wavelet coefficient obtained afterwards can enter EBCOT module and be further processed.For level-one two-dimensional structure, the knot based on block scan
Structure can directly obtain discrete wavelet coefficient code block, set the 9/7DWT code block size of scanning as 2H × 2H, as shown in Fig. 3 (a)；
For two-stage two-dimensional structure, code block that the first order generates can be directly for EBCOT resume module, and the input data of second level transformation
For the S of H × HLL1Code block can obtain the Wavelet Coefficient Blocks that 4 sizes are H/2 × H/2, not be able to satisfy EBCOT after transformed processing
Code requirement, therefore in data scanning by adjacent 4 sizes be 2H × 2H code block form DWT basic coding unit, with Z
Type mode is scanned as shown in Fig. 3 (b), and 4 sizes adjacent in this way are the S of H × HLL1Code block can generate in the shortest time
EBCOT encoding block；For three-level two-dimensional structure, to guarantee in three-level transformation while generating EBCOT encoding block, to 16 sizes
Z-type nested scan is carried out for the code block of 2H × 2H, as shown in Fig. 3 (c).
Concurrency optimization: code data in block is using the higher lateral parallel scan mode of hardware efficiency in the present invention.Due to
Data are every to be reduced to the 1/2 of upper level by level one data processing degree of parallelism, therefore every grade of two-dimensional DWT module in this structure
Degree of parallelism is also reduced to the 1/2 of upper level.By taking three-level system as an example, first order degree of parallelism is S, then second level degree of parallelism is S/2, the
Three-level degree of parallelism is S/4.Since data parallel degree is consistent with structure degree of parallelism, the structure between non-collapsible structural level is cached
To eliminate.For every level-one, the scanning sequence of code block is constant and the size of only code block is changed, therefore every level-one
Control need to only modify code block size parameter, greatly reduce system control complexity.
As shown in Fig. 4 (a), each code block needs boundary on it and left margin to receive data in the present invention, under it
Boundary and right margin outgoi8ng data.Since storage unit is multiplexed, general boundaries caching, which is equivalent to, is caching each basic coding block
Two boundaries, as shown in Fig. 4 (b).
The data transmission on boundary is median D1, D2, D3 and the D4 transmitted in conversion module.Due to spatial cache
Multiplexing, keeping in size for the image of width N × N size, needed for the every level-one of rank transformation module isSince DWT is compiled substantially
Code unit transverse sequentially enters DWT module rank transformation, and conversion module data register only needs depth at once for the data transmission of right boundary
Degree is the temporary of 8 basic processing unit sizes, for storing median D1, D2, D3 and D4 of H component and L * component respectively.With
For three-level 9/7DWT module, processing unit will generate the EBCOT encoding block that 10 sizes are H × H simultaneously, and occupying size is
20H2Intermodule memory space.
The present invention also analyzes the framework of proposition, and analysis result is as shown in the table:
1 Literature of table [10] reduces wavelet coefficient caching also by the mode that block scan optimizes, and is in image size
In the case that 1024 × 1024, EBCOT code block are typical sizes 32 × 32 and 64 × 64, two-stage wavelet transformation storage resource consumption
Comparison is as shown in table 1.As can be seen that this structure saves 40% or more in storage resource consumption.
1 present invention of table, two kinds of structure storage resource comparisons
The comparison of 2 three-level 9/7DWT hardware efficiency of table
The present invention is compared with other existing two-dimensional discrete wavelet conversion frameworks, and wherein institute's array structure is input number
According to the three-level mapped structure of degree of parallelism S=8, input picture size is that 512 × 512, EBCOT code block size is 64 × 64.Comparison
The results are shown in Table 2.
Document [6] represents MOHANTYB K, and one kind that MEHER P K et al. is proposed between degree of parallelism adjustment elimination grade by depositing
The multilevel structure of storage, document [7] represent MOHANTYB K, and one kind that MEHER P K et al. is proposed is deposited by high degree of parallelism attenuating
Area is stored up, while lowering the framework that critical path is the delay of a multiplier, document [8] represents HU Y S et al. (2013) proposition
Multiple scanning structure.
By the comprehensive control of table 2 as can be seen that compared with existing optimum structure, overall storage resource consumption reduces
60% or more, while the time is handled better than most of structure, it can be considered that the hardware synthesis effect of this structure is optimal.And
With the increase of dimension of picture or the reduction of EBCOT code block size, this structure is excellent to DWT module and the storage of EBCOT intermodule
Change can further embody.
Claims (1)
1. a kind of two-dimensional discrete wavelet conversion construction design method for improving storage efficiency, is carried out based on 9/7 wavelet arithmetic
It improves, algorithmic formula such as (1)-(10):
SL=KH (2n+1) (9)
In formula: D1 (n)~D4 (n) is 4 intermediate variables；H (2n+1) is the high-frequency wavelet coefficient before normalization；L (2n) is to return
Low-frequency wavelet coefficients before one change；X (n) representative is originally inputted pixel value；N is pixel coordinate；SHAnd SLWhat representation transformation generated
High-frequency wavelet coefficient and low-frequency wavelet coefficients；α, β, γ, δ and K are transformation coefficient；For two-dimensional transform, data become by ranks
4 wavelet coefficients i.e. low frequency-low frequency coefficient S is finally obtained after changing processingLL, high frequency-low frequency coefficient SHL, low frequency-high frequency coefficient SLH
With high frequency-high frequency coefficient SHH, which is characterized in that
Antenna scan optimization: according to JPEG2000 algorithm, input image data obtains after multilevel two-dimensional 9/7DWT resume module
To wavelet coefficient can enter EBCOT module be further processed；For level-one two-dimensional structure, the structure based on block scan can
To directly obtain discrete wavelet coefficient code block, the 9/7DWT code block size of scanning is set as 2H × 2H；For two-stage two-dimensional structure,
The code block that the first order generates can be directly for EBCOT resume module, and adjacent 4 sizes are 2H in data scanning by second level transformation
The code block of × 2H forms DWT basic coding unit, is scanned in a manner of Z-type, and adjacent 4 sizes are the S of H × HLL1Code block can
To generate EBCOT encoding block in the shortest time；For three-level two-dimensional structure, to guarantee in three-level transformation while generating
EBCOT encoding block carries out Z-type nested scan to the code block that 16 sizes are 2H × 2H；
Concurrency optimization: code data in block is using the higher lateral parallel scan mode of hardware efficiency, and every grade of two-dimensional DWT module is simultaneously
Row degree is reduced to the 1/2 of upper level, eliminates the structure caching between non-collapsible structural level, and every level-one control need to only modify code block size ginseng
Number；
The transmitting optimization of mould data in block: each code block needs boundary on it and left margin to receive data, on its lower boundary and the right side
Boundary spreads out of number；Using storage unit multiplex mode, general boundaries caching is equivalent to each two boundary of basic coding block of caching；Side
The data transmission on boundary is median D1, D2, D3 and the D4 transmitted in conversion module；Due to the multiplexing of spatial cache, for
The image of one width N × N size, size is kept in needed for the every level-one of rank transformation module isDWT basic coding unit is laterally suitable
Secondary to enter DWT module rank transformation, conversion module data register only needs depth for 8 basic places at once for the data transmission of right boundary
The temporary of cell size is managed, for storing median D1, D2, D3 and D4 of H component and L * component respectively.
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| WO2021016893A1 (en) * | 2019-07-30 | 2021-02-04 | 深圳市大疆创新科技有限公司 | Dwt computing device, method, image processing device, and movable platform |
| CN112364016A (en) * | 2020-10-27 | 2021-02-12 | 中国地震局地质研究所 | Construction method of time nested cache model of pilot frequency data object |
| WO2022205297A1 (en) * | 2021-04-01 | 2022-10-06 | 深圳市大疆创新科技有限公司 | Data processing method and device, chip, unmanned aerial vehicle, and storage medium |
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