WO2021010079A1 - Electronic component mounting structure, electronic component mounting method, and led display panel - Google Patents

Electronic component mounting structure, electronic component mounting method, and led display panel Download PDF

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Publication number
WO2021010079A1
WO2021010079A1 PCT/JP2020/023622 JP2020023622W WO2021010079A1 WO 2021010079 A1 WO2021010079 A1 WO 2021010079A1 JP 2020023622 W JP2020023622 W JP 2020023622W WO 2021010079 A1 WO2021010079 A1 WO 2021010079A1
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WO
WIPO (PCT)
Prior art keywords
electronic component
wiring board
bump electrode
electrode
led chip
Prior art date
Application number
PCT/JP2020/023622
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French (fr)
Japanese (ja)
Inventor
英幸 西村
康一郎 深谷
良勝 柳川
直也 大倉
Original Assignee
株式会社ブイ・テクノロジー
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Publication of WO2021010079A1 publication Critical patent/WO2021010079A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/81951—Forming additional members, e.g. for reinforcing

Definitions

  • the present invention relates to an electronic component mounting technique, and more particularly to an electronic component mounting structure, an electronic component mounting method, and an LED display panel that can improve the yield at the time of mounting the electronic component.
  • LED Light Emitting Diode
  • display panels are provided on, for example, an array of micro LED devices that emit blue or dark blue light and an array of micro LED devices that are blue or dark blue from the micro LED devices. It was provided with an array of wavelength conversion layers (fluorescent light emitting layers) that absorb the light of the above and convert the emission wavelengths of the light into the wavelengths of the red, green, and blue lights, respectively (for example,). See Patent Document 1).
  • wavelength conversion layers fluorescent light emitting layers
  • Such electrode misalignment is caused by relative slippage or rotational misalignment caused by the parallelism (for example, warpage or inclination) of the bonding surface of the wiring board and the LED chip, or the pressurizing shaft of the pressurizing mechanism. This is due to the relative slippage and rotational deviation of both bonded surfaces caused by the running accuracy.
  • the present invention addresses such a problem and provides an electronic component mounting structure, an electronic component mounting method, and an LED display panel on which an LED chip is mounted as an electronic component so as to improve the yield at the time of mounting the electronic component.
  • the purpose is to provide.
  • the first invention is an electronic component mounting structure in which a chip-type electronic component is mounted on one surface of a wiring substrate, and the electronic component is a pair having a recessed portion on the surface.
  • the wiring substrate includes a protruding bump electrode connected to a recessed portion of the electrode portion, a fixing member whose position is determined according to the arrangement of the bump electrode, and which fixes the electronic component.
  • the bump electrode is face-to-face bonded to the recessed portion of the electrode portion, and the electronic component is fixed to the wiring substrate by the fixing member.
  • the second invention is an electronic component mounting method for mounting a chip-type electronic component on one surface of a wiring board, in which a recess is formed on the surface of a pair of electrode portions provided on the electronic component.
  • the position is determined according to the arrangement of the transparent substrate on which the electronic component is formed on one surface, the protruding bump electrode connected to the recessed portion of the electrode portion, and the bump electrode, and the electronic component is placed.
  • the electronic component is added to the wiring board by the step of positioning the wiring board provided with the fixing member to be fixed on one surface for bonding and pushing from the other surface of the transparent substrate.
  • the step of peeling the electronic component from the transparent substrate is included.
  • the third invention is an LED display panel in which a plurality of LED chips are mounted on one surface of a wiring board, and the LED chips are formed in a matrix on one surface of the wiring board.
  • the wiring board is provided with a pair of electrode portions having a recessed portion on the surface, and the position of the wiring board is determined according to the arrangement of the protruding bump electrode connected to the recessed portion of the electrode portion and the bump electrode, and the LED chip.
  • the bump electrode is face-to-face bonded to the recessed portion of the electrode portion, and the LED chip is fixed to the wiring substrate by the fixing member.
  • the bump electrode is face-to-face bonded to the recessed portion of the electronic component, it is possible to prevent relative slippage and rotational deviation between the wiring board and the electronic component. Therefore, for example, it is possible to improve the yield at the time of mounting an electronic component such as an LED chip.
  • FIG. 1A is a plan view
  • FIG. 1B is an enlarged cross-sectional view of a main part focusing on one LED chip 3 in the sectional view taken along line AA of FIG. 1A.
  • FIG. 3C is a diagram showing a state before the LED chip 3 is mounted in FIG. 3B in order to facilitate understanding of the description.
  • FIG. 2 is a plan view in which the phosphor cell array 10 is further provided on the LED display panel.
  • the phosphor cell array 10 is formed by arranging the phosphor cells 10a in a matrix.
  • the phosphor cell 10a is a unit in which the red (R), green (G), and blue (B) fluorescent light emitting layers 11 are partitioned by a so-called rib structure.
  • the LED display panel has a plurality of LED chips 3 mounted on the wiring board 1, and includes a wiring board 1, a fixing member 2, and a micro LED chip (hereinafter, simply "LED chip”). It is composed of the LED array 100 provided with 3).
  • the LED display panel lights up the LED chip 3 to display an image in full color.
  • the LED chip 3 uses, for example, a single-color ultraviolet light emitting diode (UV-LED)
  • the LED display panel is further provided with the above-mentioned phosphor cell array 10 in order to display a full color.
  • the LED display panel is an example of a substrate connection structure
  • the LED chip 3 is an example of an electronic component.
  • the LED chips 3 are mounted in a matrix on one surface of the wiring board 1 by a two-dimensional arrangement of predetermined pitch intervals. Further, as shown in FIG. 1B, the LED chip 3 has a pair of electrode portions 3a and 3b having recessed portions on the surface (hereinafter, the electrode portions 3a and 3b may be collectively referred to as “electrode portion 30”). To be equipped with.
  • the pair of electrode portions 3a and 3b are, for example, electrode pads that enable the LED to be energized from an external circuit.
  • the electrode portion 3a is an n-side electrode pad (cathode electrode), and the electrode portion 3b is a p-side electrode pad (anode). Electrode).
  • the wiring board 1 is a group of projecting bump electrodes 4a and 4b (hereinafter, bump electrodes 4a and 4b) that are electrically and mechanically connected to the recesses (recesses) of the electrode portions 3a and 3b of the LED chip 3 and are "bumps". (Sometimes referred to as an electrode 4), and a fixing member 2 whose position is determined according to the arrangement of the bump electrodes 4a and 4b to which the LED chip 3 is fixed. Then, in the LED display panel, the bump electrodes 4a and 4b are face-to-face bonded to the recessed portions of the electrode portions 3a and 3b of the LED chip 3, and the LED chip 3 is fixed to the wiring board 1 by the fixing member 2. It is a feature.
  • the wiring board 1 may be, for example, a flexible board made of a polyimide film or the like.
  • a TFT (Thin Film Transistor) drive circuit for individually driving the light emission of the LED chip 3 as an on state or an off state is provided on the polyimide film substrate, and the TFT drive circuit is provided.
  • the bump electrode 4 is provided at a predetermined position.
  • the wiring board 1 is, for example, a flexible printed circuit board (FPC: Flexible Printed Circuits), which is in the form of a film composed of an insulating base film (for example, polyimide) and a wiring layer forming an electric circuit. It is a substrate of.
  • the wiring board 1 is provided with scanning wiring and data wiring (not shown) connected to an external drive device intersecting vertically and horizontally. Further, a thin film transistor is provided at the intersection of the scanning wiring and the data wiring.
  • the LED chip 3 is mounted when the LED chip 3 is mounted.
  • a fixing member 2 for guiding the LED chip 3 is provided so that the electrode portion 30 of the LED chip 3 and the bump electrode 4 provided on the wiring substrate 1 can be electrically contacted with each other.
  • the wiring 1a schematically shows the wiring of the TFT drive circuit.
  • the position of the fixing member 2 is determined according to the arrangement of the bump electrodes 4, and the LED chip 3 is fixed to the wiring board 1.
  • the fixing member 2 is a resin that supports the LED chip 3 by elastic deformation, and in a state where the LED chip 3 is fixed to the wiring substrate 1, it contracts in response to the pressure from the LED chip 3 to form the LED chip 3.
  • the recessed portion of the electrode portion 3a is guided to the bump electrode 4a to be face-to-face bonded, and the recessed portion of the electrode portion 3b of the LED chip 3 is guided to the bump electrode 4b to be face-to-face bonded. That is, the fixing member 2 has a function as a guide member.
  • the fixing member 2 is formed by patterning the resin as a photosensitive thermosetting adhesive and having photosensitivity, and is a region surrounding the bump electrodes 4a and 4b of the wiring board 1.
  • the LED chip 3 is fixed to the wiring board 1 by thermosetting.
  • thermosetting adhesive a photosensitive and thermosetting resin or the like is preferably used.
  • a resin containing an epoxy resin, an acrylic resin, a phenol resin, a polyimide resin, a silicone resin, a styrene resin or the like as a main component is desirable.
  • the adhesive can be accurately placed at a predetermined position as the fixing member 2 by exposing and developing the adhesive by photolithography after applying the adhesive.
  • a photosensitive thermosetting adhesive having a thermosetting function is adopted as a photosensitive adhesive.
  • the LED chip 3 is manufactured using, for example, gallium nitride (GaN) as a main material.
  • the LED chip 3 may be an ultraviolet light emitting diode (UV-LED) or an LED that emits blue light.
  • UV-LED ultraviolet light emitting diode
  • a wavelength of 385 nm may be selected in consideration of the conversion efficiency of the phosphor and the like.
  • the LED chip 3 has, for example, an external size of about 15 ⁇ 45 ⁇ m.
  • the thickness of the electrode portion 30 of the LED chip 3 is about 3 ⁇ m.
  • the thickness of the bump electrode 4 is about 8 ⁇ m
  • the film thickness of the fixing member 2 is about 11 to 12 ⁇ m.
  • a method of realizing full-color display by combining an LED that emits light having a short wavelength such as an ultraviolet light emitting diode (UV-LED) and an RGB phosphor is adopted.
  • a phosphor cell 10a having a fluorescence light emitting layer 11 having an RGB phosphor that converts light in the ultraviolet or blue wavelength band into a predetermined corresponding color is provided on the light emitting surface side of the LED chip 3. ..
  • the LED display panel has phosphor cells 10a including the fluorescence light emitting layer 11 arranged in a matrix on the wiring substrate 1 via the LED chip 3 and the fixing member 2.
  • the phosphor cell array 10 is provided.
  • the fluorescence light emitting layer 11 is surrounded by a light-shielding wall with a rib structure of a fluorescent material that is excited by light (excitation light) emitted from the LED chip 3 and that converts the wavelength into fluorescence of a predetermined corresponding color.
  • the area is filled.
  • the predetermined corresponding color is determined by the RGB phosphor and is a color corresponding to the three primary colors of light, red (R), green (G), and blue (B).
  • a plurality of phosphor cells 10a for realizing full-color display are arranged in a matrix.
  • a plurality of phosphor cells 10a are arranged in 4 rows and 5 columns in the phosphor cell array 10.
  • FIG. 3 is an explanatory diagram of the phosphor cell.
  • 3A is an enlarged plan view of the phosphor cell 10a shown in FIG. 2, and
  • FIG. 3B is a sectional view taken along line BB of FIG. 2A.
  • (C) is a front view of the LED chip 3 shown in (b).
  • the fluorescent light emitting layer 11 includes a fluorescent material layer 11R filled with a red fluorescent dye, a fluorescent material layer 11G filled with a green fluorescent dye, and a fluorescent material layer 11B filled with a blue fluorescent dye. doing. These fluorescent dyes are examples of RGB phosphors. Then, as shown in FIG. 3B, the fluorescent light emitting layer 11 has red (R), green (G), and blue for the red, green, and blue fluorescent dyes (an example of the fluorescent material) to realize full-color display. The wavelength is converted to the fluorescence of (B), respectively.
  • each fluorescent material when the fluorescent dyes of the fluorescent material layers 11R, 11G, and 11B transition to the excited state by the light (excitation light) emitted from the LED chip 3, and then return to the basal state, each fluorescent material is used. It emits fluorescence corresponding to the visible spectra of red (R), green (G), and blue (B), which are wavelength-converted by.
  • These fluorescent material layers 11R, 11G, and 11B are partitioned by a partition wall 14 having a metal film 13 on the surface.
  • a partition wall 14 is an example of a light-shielding wall, and separates the fluorescent material layers 11R, 11G, and 11B from each other.
  • the metal film 13 and the partition wall 14 are constituent elements of the rib structure.
  • a metal film 13 having a function as a reflective film is provided on the surface of the partition wall 14.
  • the metal film 13 is for preventing the excitation light and fluorescence emitted from the light emitting surface 32 from passing through the partition wall 14 and mixing with fluorescence of another adjacent color. Fluorescence is emitted when each fluorescent dye of each fluorescent material layer 11R, 11G, 11B is excited by excitation light.
  • the metal film 13 is formed with a thickness capable of sufficiently blocking excitation light and fluorescence. In this case, as the metal film 13, a thin film such as aluminum or an aluminum alloy that easily reflects excitation light is suitable.
  • the LED array 100 and the phosphor cell array 10 are bonded to each other to form a display panel (see FIG. 3B).
  • the LED array 100 further includes a flat plate-shaped flattening film 12 that adheres and supports the phosphor cell array 10.
  • the LED chip 3 has electrode portions 3a and 3b for emitting light at predetermined positions on the upper surface (one surface) of the compound semiconductor 31 which is an ultraviolet light emitting diode (UV-LED).
  • the electrode portion 3a has a recessed portion 30a
  • the electrode portion 3b has a recessed portion 30b (hereinafter, the recessed portions 30a and 30b may be collectively referred to as a “dented portion 33”).
  • the LED chip 3 has a light emitting surface 32 that emits light from a light source (a light emitting layer that emits specific ultraviolet light) on the lower surface (the other surface) of the compound semiconductor 31.
  • FIG. 4 is an explanatory view showing a plurality of shapes of the recessed portion of the electrode portion of the LED chip.
  • FIG. 4 illustrates a plurality of groove shapes of the electrode portions 3a and 3b (see FIGS. 4A to 4F). This groove shape forms the recessed portions 30a and 30b.
  • the shapes of the bump electrodes 4a and 4b are determined according to the shapes of the recessed portions 30a and 30b. That is, in the present embodiment, for example, the concave portions of the recessed portions 30a and 30b may be joined so as to be fitted with the convex portions of the bump electrodes 4a and 4b, respectively.
  • "fitting" does not necessarily mean fitting and joining without a gap.
  • the protruding tip surfaces of the bump electrodes 4a and 4b may be face-to-face bonded to the surfaces of the recessed portions 30a and 30b of the electrode portions 3a and 3b, respectively.
  • the recessed portion 30a and the bump electrode 4a, and the recessed portion 30b and the bump electrode 4b may be electrically and mechanically connected. This mechanical connection includes chemical bonds such as eutectic and solder.
  • the bump electrode 4 is face-to-face bonded to the recessed portion 33 of the LED chip 3 according to the above-described configuration, so that the wiring substrate 1 and the LED chip 3 are relatively slippery or rotationally displaced. Can be prevented.
  • the LED display panel can improve the yield when the LED chip 3 is mounted, and by lighting the LED chip 3 that can be normally lit, the image can be displayed in full color via the phosphor cell 10a. ..
  • FIG. 5 and 6 are explanatory views showing an electronic component mounting method and preprocessing according to the present invention.
  • FIGS. 5 and 6 three LED chips 3 are illustrated for easy explanation.
  • FIG. 7 is a flow chart showing a process of a manufacturing method of an LED display panel adopting the electronic component mounting method according to the present invention.
  • the processes of steps S4 to S5 shown in FIG. 7 correspond to the processes of the electronic component mounting method.
  • the processes of steps S1 to S3 shown in FIG. 7 correspond to the preprocessing of the electronic component mounting method.
  • step S1 the LED chips 3 are formed in a matrix on the sapphire substrate 7 according to a predetermined arrangement (n rows and m columns) at predetermined pitch intervals.
  • FIG. 1 the LED chips 3 are formed in a matrix on the sapphire substrate 7 according to a predetermined arrangement (n rows and m columns) at predetermined pitch intervals.
  • FIG. 5A shows a state in which the LED chip 3 is formed on the sapphire substrate 7. The details of the formation of the LED chip will be described later with reference to FIGS. 9 to 11.
  • FIG. 5A corresponds to the three LED chips 3 in the region R1 surrounded by the broken line shown in FIG.
  • the present invention is not limited to the sapphire substrate 7, and a synthetic quartz substrate may be adopted.
  • the protruding bump electrode 4 is formed on the wiring board 1 corresponding to the arrangement of the LED chips 3.
  • the bump electrode 4 is preferably a metal bump electrode, a solder bump electrode that can be connected by solder, or a resist bump electrode on which a metal film is laminated.
  • the bump electrode 4 can be well connected by selecting any of a metal bump electrode, a solder bump electrode, and a resist bump electrode.
  • a metal bump electrode is formed as the bump electrode 4 as an example.
  • step S2 for example, by adopting the gas deposition method, a mask having fine holes is placed only on the portion where the bump electrode 4 is formed on the wiring board 1, and fine gold particles are deposited on the mask.
  • a protruding bump electrode 4 is formed.
  • the "protruding" shape is not limited to a conical shape or a tapered shape, and includes, for example, a cylindrical shape. That is, the shape of the bump electrode 4 may be any shape that can be face-to-face bonded to the recessed portion 33.
  • the photosensitive thermosetting adhesive 6 is formed on the wiring substrate 1 on which the bump electrode 4 is formed by using a coating device such as a spray device or a spinner (spin coater). Is uniformly applied to a predetermined thickness (see FIG. 5 (c)).
  • the photosensitive thermosetting adhesive 6 can be patterned into a specific shape by photolithography.
  • FIG. 8 is a graph showing the relationship between the viscosity and elastic modulus of the photosensitive thermosetting adhesive with respect to temperature.
  • the photosensitive thermosetting adhesive 6 has viscous / elastic temperature characteristics as shown in FIG. 8 after photocuring.
  • the region I has reversibility with the temperature T1 in FIG. 8 as a boundary, and the region II has an irreversible property.
  • the photosensitive thermosetting adhesive 6 has an elastic modulus of 0.05 MPa to 0.1 MPa at the above temperature T1 (for example, 110 ° C.), and is adapted to the shape of the LED chip 3 according to an external force. It is deformed and has a function of gripping the LED chip 3 by utilizing the reaction force corresponding to the deformation.
  • step S3 the photosensitive thermosetting adhesive 6 is patterned by photolithography, and in the region where the LED chip 3 is mounted, for example, a bump of the wiring board 1 is formed.
  • a fixing member 2 having an opening 5 corresponding to the electrode 4 is formed.
  • FIG. 5D shows a case where the opening 5 has a shape corresponding to the outer shape of the LED chip 3. That is, in step S3, the liquid photosensitive thermosetting adhesive 6 is applied by a coating device such as a spinner, patterned, and then heated to form the elastic fixing member 2.
  • step S4 in the bonding of the wiring board and the sapphire board (step S4), first, a mounting area in which a plurality of LED chips 3 formed on one surface of the sapphire board 7 are mounted on the wiring board 1, respectively. Positioning to (see FIG. 5 (e)). Subsequently, in step S4, after the LED chip 3 is brought into contact with the wiring board 1 (see FIG. 6A), the LED chip 3 is pressed by the pressure P from the other surface of the sapphire board 7. The recessed portion 33 of the electrode portion 30 and the bump electrode 4 of the wiring board 1 are joined face-to-face so as to be conductive (see FIG. 6B). Further, in step S4, the LED chip 3 and the wiring board 1 are maintained in a conductive state and the LED chip 3 is fixed to the wiring board 1 by heat curing (see FIG. 6C).
  • step S4 by using a mounting device such as a flip chip bonder device, a plurality of LED chips 3 formed on one surface of the sapphire substrate 7 as shown in FIG. 5 (e). Are respectively positioned on the fixing member 2 of the mounting region to be mounted on the wiring board 1.
  • a mounting device such as a flip chip bonder device
  • LED chips 3 formed on one surface of the sapphire substrate 7 as shown in FIG. 5 (e).
  • an alignment mark provided on the wiring board 1 and an alignment mark provided on the sapphire board 7 are photographed by an alignment camera by a mounting device, and both alignment marks match or have a predetermined positional relationship. It is aligned and executed so as to form.
  • step S4 as shown in FIG. 6A, the LED chip 3 and the wiring board 1 are moved relatively close to each other to prebond the LED chip 3 to the fixing member 2, and then FIG. 6B ), The pressure P is relatively applied in the direction of the arrow in the drawing to electrically and mechanically connect the electrode portion 30 of the LED chip 3 and the bump electrode 4 of the wiring substrate 1.
  • preheating is performed from prebonding to before the next heat curing to lower the elastic modulus of the photosensitive thermosetting adhesive 6 (a state in which it is easily deformed), and the pressure P is applied. It is pressurizing.
  • the temperature of this preheating is preferably about T1 (for example, 110 ° C.) to 120 ° C. shown in FIG.
  • step S4 the photosensitive thermosetting adhesive 6 is heat-cured using heat H from the external heater 20 for a predetermined time, and the LED chip 3 is heat-cured on the wiring board 1. Stick to. Specifically, in step S4, the photosensitive thermosetting adhesive 6 is applied at 180 ° C. for 90 minutes, 200 ° C. for 60 minutes, or 230 ° C. for 30 minutes while maintaining the energized state and holding the LED chip 3. The LED chip 3 is fixed to the wiring substrate 1 by heating and curing in any of the minutes.
  • the LED chip 3 is laser-lifted off from the sapphire substrate 7 by using the laser lift-off device.
  • step S5 the sapphire is moved from the sapphire substrate 7 side in the direction (X direction) in which the line-shaped laser beam L of ultraviolet rays intersects the long axis thereof.
  • the interface between the substrate 7 and the LED chip 3 is irradiated to laser lift off the LED chip 3 from the sapphire substrate 7.
  • FIG. 6E the mounting of the LED chip 3 on the wiring board 1 is completed.
  • the flattening film 12 is further formed by applying a photosensitive thermosetting adhesive to the LED array 100 in which the LED chip 3 has been mounted on the wiring substrate 1. Laminate.
  • step S7 a plurality of phosphor cells 10a whose arrangement is determined according to the arrangement of the LED chips 3 are formed on the display panel shown in FIG. 1 to produce the phosphor cell array 10. ..
  • step S8 the display panel is formed by laminating and mounting the LED array 100 and the phosphor cell array 10 shown in FIG.
  • step S1 the processes from the formation of the LED chip (step S1) to the formation of the display panel (step S8) have been described.
  • step S1 the formation of the LED chip (step S1) and the formation of the flattening film (step S6) fluorescence. Details of the formation of the body cell (step S7) and the formation of the display panel (step S8) will be described.
  • FIG. 9 is an explanatory diagram showing a process of forming the LED chip. It is a flow chart which shows the forming process of the LED chip.
  • the blue LED and the UV-LED are mainly composed of a gallium nitride (GaN) -based semiconductor laminated structure, and various semiconductor laminated structures can be formed.
  • the present invention is characterized in that a recessed portion 33 is formed in the electrode portion 30 of the LED chip 3 so that the bump electrode 4 is face-to-face bonded to the recessed portion 33.
  • the present invention is not limited to the semiconductor laminated structure of the LED chip 3 described below.
  • a gallium nitride based light emitting diode is formed by using a metalorganic vapor phase epitaxy (MOVPE) method, which is a kind of vapor phase epitaxy (Vapour Phase. Epitaxy).
  • MOVPE metalorganic vapor phase epitaxy
  • the epi crystal layer used is grown.
  • a laminate of n-type GaN, MQW (MultiQuantum Well) layer and p-type GaN is grown as the epi crystal layer.
  • the MOVPE method in a semiconductor laminated structure such as an epi crystal layer, parameters such as growth temperature, growth pressure, material gas flow rate, material gas type, and flow velocity are obtained so that the characteristics required for the crystal layer of each semiconductor can be obtained. Crystal growth is performed while controlling the above.
  • the process of partitioning each region where the LED chip 3 is formed is performed.
  • one LED chip 3 is used for convenience of explanation. I draw with an eye on the formation of.
  • step S11 the pn-junctioned n-type gallium nitride 3c is laminated on the sapphire substrate 7.
  • step S11 an n-type gallium nitride 3c is laminated after laminating a GaN low-temperature buffer layer (not shown) on the sapphire substrate 7 by the MOVPE method (see FIG. 9A).
  • the MOVPE method is applied to laminate the quantum well (MQW) layer (light emitting layer) using InGaN or the like on the n-type gallium nitride 3c, and the upper layer thereof.
  • a p-type gallium nitride layer is laminated on the surface.
  • the quantum well layer and the p-type gallium nitride layer are collectively represented by reference numeral 3d.
  • each region where the LED chip 3 is formed is divided. Perform the processing to be performed. In this case, in order to form a through hole of the n-side electrode pad, the n-type GaN layer is etched.
  • step S13 for example, photolithography is applied to mask the area other than the region where ITO is laminated with a resist mask, and then a physical vapor deposition method (PVD: Physical Vapor Deposition) such as a sputtering vapor deposition method is applied. Then, as a transparent electrode material, an ITO (Indium Tin Oxide) layer 3e is further laminated (see FIG. 9 (c)).
  • PVD Physical Vapor Deposition
  • the insulating film (SiO 2 ) 3f is further laminated as a protective film by using, for example, a chemical vapor deposition (CVD) (see FIG. 9D). ..
  • CVD chemical vapor deposition
  • step S15 for example, photolithography is applied to mask the regions other than the regions for forming through holes for conduction of the electrode portions 3a and 3b with a resist mask, and then dry etching is performed. , A through hole is formed (see FIG. 9E).
  • the electrode materials 3a and 3b are formed by vacuum vapor deposition.
  • the electrode material may be, for example, an alloy containing gold.
  • the dents may be the dents 30a and 30b, but if necessary, FIG. It may be processed so as to form the recessed portions 30a and 30b as shown in (see FIG. 9F).
  • FIG. 11 is a diagram showing a configuration of an embodiment of a sapphire substrate on which an LED chip is formed.
  • (A) is a plan view
  • (b) is an enlarged plan view of the LED chip 3 shown in (a).
  • FIG. 11A shows, as an example, a sapphire substrate 7 in which LED chips 3 are formed in 12 rows and 5 columns.
  • the process proceeds to the formation of the bump electrode shown in FIG. 7 (step S2).
  • the formation of the LED chip (step S1) may be executed after the formation of the fixing member (step S3).
  • FIG. 12 is an explanatory view showing a step of forming a flattening film.
  • A is a plan view of the LED array 100 in which the flattening film 12 is further laminated.
  • B is a cross-sectional view taken along the line CC of the three LED chips 3 in the region R2 surrounded by the broken line in (a).
  • a microdispenser is used to apply the photosensitive thermosetting adhesive onto the LED array 100 while controlling the height direction to be constant.
  • the photosensitive thermosetting adhesive is exposed to form a flattening film 12 by photolithography. As a result, the flattening film 12 is formed. At this time, it is preferable that the photosensitive thermosetting adhesive is not formed on the light emitting surface 32 of the LED chip 3.
  • FIG. 13 is an explanatory diagram showing a process of forming a phosphor cell.
  • Step S7 comprises forming a rib structure and filling with a fluorescent material.
  • the formation of the rib structure includes the formation of the partition wall 14, the formation of the metal film 13, and the laser processing of the metal film 13.
  • a fluorescent resist is applied to the entire surface of the sapphire substrate 7a, and a pattern of the partition wall 14 is formed by photolithography.
  • step S7 in order to prevent color mixing, the inside of the partition wall 14 is metal-coated with a metal film 13, and only the bottom surface is irradiated with a pulse laser to peel off the metal film 13 by ablation. Further, in step S7, as shown in FIG. 13, the fluorescent material layer 11R, the fluorescent material layer 11G, and the fluorescent material layer 11B are filled. As a result, the phosphor cell array 10 as shown in FIG. 2, for example, is formed on the sapphire substrate 7a.
  • FIG. 14 is an explanatory diagram showing a process of forming a display panel.
  • step S8 the LED array 100 and the phosphor cell array 10 are bonded and mounted by using a mounting device such as a flip chip bonder device.
  • FIG. 14A shows a state in which the LED array 100 and the phosphor cell array 10 are bonded together.
  • the fluorescent cell 10a which is a constituent unit of the fluorescent cell array 10 is focused on.
  • step S8 the flattening film 12 is heat-cured and the phosphor cell array 10 is fixed to the LED array 100 in the same manner as in the bonding of the wiring board and the sapphire substrate (step S4).
  • step S8 the phosphor cell array 10 is laser lifted off from the sapphire substrate 7a in the same manner as in the laser lift-off (step S5) (see FIG. 14B).
  • the manufacturing method of the LED display panel adopting the electronic component mounting method of mounting the plurality of LED chips 3 on the wiring board 1, the time of mounting the electronic component such as the LED chip 3 is applied.
  • An LED display panel with improved yield can be manufactured.
  • FIG. 15 is an explanatory diagram showing an example of defects in LED chip mounting in the prior art.
  • FIG. 15A shows the LED chip 3 formed on one surface of the sapphire substrate 7 (not shown) positioned in the mounting area for mounting on the wiring board 1, and then the other of the sapphire substrate 7 (not shown).
  • the case where the LED chip 3 is pressurized by the pressure P from the surface of the above surface to bring the electrode portion 8 of the LED chip 3 into contact with the electrode 1b of the wiring board 1 is illustrated.
  • the LED chip 3 may be rotationally displaced as shown in FIG. 15B, resulting in an open defect.
  • slippage may occur, resulting in a short defect.
  • the LED chip 3 has the bump electrode 4 face-to-face bonded to the recessed portion 33 of the LED chip 3 according to the above-described configuration, so that the wiring substrate 1 and the LED chip 3 are relative to each other. It is possible to prevent slippage and rotation deviation.
  • FIG. 16 is an explanatory diagram showing elastic deformation of the fixing member when the LED chip is mounted. Further, in the present invention, as shown in FIGS. 16A to 16C, when the LED chip is mounted, the LED chip 3 is guided by the opening 5 of the fixing member 2 and inside the opening 5 of the fixing member 2. The electrode portions 3a and 3b of the LED chip 3 and the bump electrodes 4a and 4b of the wiring substrate 1 are electrically contacted with each other. That is, after the LED chip 3 is positioned with respect to the wiring board 1 (see FIG. 16A), when the LED chip 3 is pressurized with the pressure P, the pressure P1 acts on the fixing member 2 (FIG. 16). See (b)).
  • reaction force P2 of the pressure P1 acts to grip the LED chip 3 by the fixing member 2 (see FIG. 16C).
  • the structure is such that misalignment is less likely to occur.
  • the sapphire substrate 7 is not shown.
  • the wiring board 1 and the electrons of the LED chip 3 and the like are electronically bonded. It is possible to suppress misalignment such as slippage and rotational misalignment due to pressurization during bonding with the sapphire substrate 7 on which the component is formed. As a result, a reliable energized state can be obtained.
  • the display panel has been described by using a single color ultraviolet light emitting diode (UV-LED) as a micro LED in which the LED chip 3 emits light in the ultraviolet or blue wavelength band.
  • UV-LED ultraviolet light emitting diode
  • the LED chip 3 is one of three types of micro LEDs that emit light corresponding to the three primary color lights, and the micro LEDs corresponding to each color are arranged according to a predetermined arrangement.
  • the display panel may be configured as arranged above. In this case, in the display panel, the LED chips 3 that emit red (R), green (G), and blue (B) lights are arranged on the wiring board 1 so as to realize full-color display. It is not necessary to adopt the phosphor cell array 10 as shown.
  • the metal bump electrode is applied to the bump electrode 4, but when the resist bump electrode is pressurized by using the conductive resist bump electrode, the resist bump electrode is crushed and corresponds to the resist bump electrode. It may be configured so that it is connected to the electrode portion 30. As a result, in a state where the resist bump electrode is crushed, the fixing member 2 is cured and both substrates are joined, so that a good electrical connection is maintained.
  • the electronic component is the LED chip 3
  • the present invention is not limited to this, and the electronic component may be an IC chip or the like as long as it is in the form of a chip.
  • the present invention can be applied even when there is one electronic component.
  • an electronic component mounting method a case where a plurality of electronic components are mounted on a wiring board is applied, but the present invention can be applied even when there is one electronic component.

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Abstract

The present invention pertains to an electronic component mounting structure for mounting chip-type LED chips 3 on one surface of a wiring substrate 1. The LED chips 3 are each provided with a pair of electrode parts 30 each having a recess in the surface thereof. The wiring substrate 1 is provided with: salient bump electrodes 4 which are connected to the respective recesses of the electrode parts 30; and fixing members 2, the position of which is determined in accordance with the arrangement of said bump electrodes 4 and which is for fixing the LED chips 3. The bump electrodes 4 are joined face-to-face with the respective recesses of the electrode parts. The LED chips 3 are fixed to the wiring substrate 1 via the fixing members 2. With this configuration, it is possible to improve the mounting yield of the LED chips 3.

Description

電子部品実装構造、電子部品実装方法及びＬＥＤ表示パネルElectronic component mounting structure, electronic component mounting method and LED display panel
　本発明は、電子部品の実装技術に関し、特に、電子部品の実装時の歩留りを向上し得るようにした電子部品実装構造、電子部品実装方法及びＬＥＤ表示パネルに係るものである。 The present invention relates to an electronic component mounting technique, and more particularly to an electronic component mounting structure, an electronic component mounting method, and an LED display panel that can improve the yield at the time of mounting the electronic component.
　従来のＬＥＤ（Light Emitting Diode）表示パネルは、例えば、青色又は紺青色の光を放出するマイクロＬＥＤデバイスのアレイと、このマイクロＬＥＤデバイスのアレイ上に設けられ、マイクロＬＥＤデバイスからの青色又は紺青色の光を吸収して、その光の発光波長を赤色、緑色及び青色の各光の波長に夫々変換する波長変換層（蛍光発光層）のアレイと、を備えたものとなっていた（例えば、特許文献１参照）。 Conventional LED (Light Emitting Diode) display panels are provided on, for example, an array of micro LED devices that emit blue or dark blue light and an array of micro LED devices that are blue or dark blue from the micro LED devices. It was provided with an array of wavelength conversion layers (fluorescent light emitting layers) that absorb the light of the above and convert the emission wavelengths of the light into the wavelengths of the red, green, and blue lights, respectively (for example,). See Patent Document 1).
特表２０１６―５２３４５０号公報Special Table 2016-523450
　しかし、このような従来のＬＥＤ表示パネルの製造段階においては、配線基板とＬＥＤチップとを貼り合せ、配線基板の電極とＬＥＤチップの電極とを電気的に接触させるようにしている。この場合、貼り合せ時の電極同士の位置ずれによりＬＥＤが不点灯となるおそれがあった。したがって、この問題は、配線基板へのＬＥＤチップの実装時の歩留りの向上を阻害する阻害要因となっていた。 However, in the manufacturing stage of such a conventional LED display panel, the wiring board and the LED chip are bonded together so that the electrodes of the wiring board and the electrodes of the LED chip are in electrical contact with each other. In this case, there is a risk that the LED will not light due to the misalignment of the electrodes during bonding. Therefore, this problem has been an impediment to the improvement of the yield at the time of mounting the LED chip on the wiring board.
　このような電極の位置ずれは、配線基板及びＬＥＤチップの貼り合せ面の平行度（例えば、反りや傾き）に起因して生じる相対的な滑りや回転ずれ、又は加圧機構の加圧軸の走り精度に起因して生じる両貼り合せ面の相対的な滑りや回転ずれによるものである。 Such electrode misalignment is caused by relative slippage or rotational misalignment caused by the parallelism (for example, warpage or inclination) of the bonding surface of the wiring board and the LED chip, or the pressurizing shaft of the pressurizing mechanism. This is due to the relative slippage and rotational deviation of both bonded surfaces caused by the running accuracy.
　そこで、本発明は、このような問題に対処し、電子部品の実装時の歩留りを向上し得るようにした電子部品実装構造、電子部品実装方法及び電子部品としてＬＥＤチップを実装したＬＥＤ表示パネルを提供することを目的とする。 Therefore, the present invention addresses such a problem and provides an electronic component mounting structure, an electronic component mounting method, and an LED display panel on which an LED chip is mounted as an electronic component so as to improve the yield at the time of mounting the electronic component. The purpose is to provide.
　上記目的を達成するために、第１の発明は、配線基板の一方の面上にチップ型の電子部品を実装する電子部品実装構造であって、上記電子部品は、表面に窪み部を有する一対の電極部を備え、上記配線基板は、上記電極部の窪み部に接続する突状のバンプ電極と、該バンプ電極の配置に応じて位置が定められ、上記電子部品を固着する固着部材と、を備え、上記電極部の窪み部に上記バンプ電極が対面接合すると共に、上記固着部材により上記電子部品を上記配線基板に固着するものである。 In order to achieve the above object, the first invention is an electronic component mounting structure in which a chip-type electronic component is mounted on one surface of a wiring substrate, and the electronic component is a pair having a recessed portion on the surface. The wiring substrate includes a protruding bump electrode connected to a recessed portion of the electrode portion, a fixing member whose position is determined according to the arrangement of the bump electrode, and which fixes the electronic component. The bump electrode is face-to-face bonded to the recessed portion of the electrode portion, and the electronic component is fixed to the wiring substrate by the fixing member.
　また、第２の発明は、配線基板の一方の面上にチップ型の電子部品を実装する電子部品実装方法であって、上記電子部品に設けられた一対の電極部の表面に窪み部が形成され、一方の面上に上記電子部品が形成された透明基板と、上記電極部の窪み部に接続する突状のバンプ電極及び該バンプ電極の配置に応じて位置が定められ、上記電子部品を固着する固着部材を一方の面上に備えた上記配線基板とを、貼り合せるために位置決めする工程と、上記透明基板の他方の面から押すことにより、上記電子部品を上記配線基板に対して加圧し、上記電極部の窪み部と上記配線基板のバンプ電極とを導通可能に対面接合させる工程と、上記固着部材を熱硬化させることにより、上記配線基板に上記電子部品を固着する工程と、上記透明基板から上記電子部品を剥離する工程と、を含む。 The second invention is an electronic component mounting method for mounting a chip-type electronic component on one surface of a wiring board, in which a recess is formed on the surface of a pair of electrode portions provided on the electronic component. The position is determined according to the arrangement of the transparent substrate on which the electronic component is formed on one surface, the protruding bump electrode connected to the recessed portion of the electrode portion, and the bump electrode, and the electronic component is placed. The electronic component is added to the wiring board by the step of positioning the wiring board provided with the fixing member to be fixed on one surface for bonding and pushing from the other surface of the transparent substrate. A step of pressing and joining the recessed portion of the electrode portion and the bump electrode of the wiring board so as to be conductive, a step of fixing the electronic component to the wiring board by heat-curing the fixing member, and the step of fixing the electronic component to the wiring board. The step of peeling the electronic component from the transparent substrate is included.
　さらに、第３の発明は、配線基板の一方の面上に複数のＬＥＤチップを実装したＬＥＤ表示パネルであって、上記ＬＥＤチップは、上記配線基板の一方の面上に行列状に形成され、表面に窪み部を有する一対の電極部を備え、上記配線基板は、上記電極部の窪み部に接続する突状のバンプ電極と、該バンプ電極の配置に応じて位置が定められ、上記ＬＥＤチップを固着させる固着部材と、を備え、上記電極部の窪み部に上記バンプ電極が対面接合すると共に、上記固着部材により上記ＬＥＤチップを上記配線基板に固着するものである。 Further, the third invention is an LED display panel in which a plurality of LED chips are mounted on one surface of a wiring board, and the LED chips are formed in a matrix on one surface of the wiring board. The wiring board is provided with a pair of electrode portions having a recessed portion on the surface, and the position of the wiring board is determined according to the arrangement of the protruding bump electrode connected to the recessed portion of the electrode portion and the bump electrode, and the LED chip. The bump electrode is face-to-face bonded to the recessed portion of the electrode portion, and the LED chip is fixed to the wiring substrate by the fixing member.
　本発明によれば、上記電子部品の上記窪み部に上記バンプ電極が対面接合するようにしているので、上記配線基板と上記電子部品との相対的な滑りや回転ずれを防止することができる。したがって、例えば、ＬＥＤチップ等の電子部品の実装時の歩留りを向上させることができる。 According to the present invention, since the bump electrode is face-to-face bonded to the recessed portion of the electronic component, it is possible to prevent relative slippage and rotational deviation between the wiring board and the electronic component. Therefore, for example, it is possible to improve the yield at the time of mounting an electronic component such as an LED chip.
本発明によるＬＥＤ表示パネルの一実施形態の構成を示す説明図である。It is explanatory drawing which shows the structure of one Embodiment of the LED display panel by this invention. 本発明によるＬＥＤ表示パネルの一実施形態の構成を示す説明図である。It is explanatory drawing which shows the structure of one Embodiment of the LED display panel by this invention. 蛍光体セルの説明図である。It is explanatory drawing of a fluorescent substance cell. ＬＥＤチップの電極部の窪み部について、複数の形状を示す説明図である。It is explanatory drawing which shows a plurality of shapes about the recessed part of the electrode part of the LED chip. 本発明による電子部品実装方法及び前処理を示す説明図である。It is explanatory drawing which shows the electronic component mounting method and pretreatment by this invention. 本発明による電子部品実装方法及び前処理を示す説明図である。It is explanatory drawing which shows the electronic component mounting method and pretreatment by this invention. 本発明による電子部品実装方法を採用したＬＥＤ表示パネルの製造方法の工程を示す流れ図である。It is a flow chart which shows the process of the manufacturing method of the LED display panel which adopted the electronic component mounting method by this invention. 感光性熱硬化型接着剤の温度に対する粘度及び弾性率の関係を示すグラフである。It is a graph which shows the relationship between the viscosity and elastic modulus with respect to the temperature of a photosensitive thermosetting adhesive. ＬＥＤチップの形成工程を示す説明図である。It is explanatory drawing which shows the forming process of the LED chip. ＬＥＤチップの形成工程を示す流れ図である。It is a flow chart which shows the forming process of the LED chip. ＬＥＤチップを形成したサファイア基板の一実施形態の構成を示す説明図である。It is explanatory drawing which shows the structure of one Embodiment of the sapphire substrate which formed the LED chip. 平坦化膜の形成工程を示す説明図である。It is explanatory drawing which shows the formation process of the flattening film. 蛍光体セルの形成工程を示す説明図である。It is explanatory drawing which shows the formation process of a fluorescent substance cell. 表示パネルの形成工程を示す説明図である。It is explanatory drawing which shows the forming process of a display panel. 従来技術におけるＬＥＤチップ実装の欠陥例を示す説明図である。It is explanatory drawing which shows the defect example of the LED chip mounting in the prior art. ＬＥＤチップ実装時の固着部材の弾性変形について示す説明図である。It is explanatory drawing which shows the elastic deformation of the fixing member at the time of mounting an LED chip.
　以下、本発明の実施形態を添付図面に基づいて詳細に説明する。図１、２は、本発明によるＬＥＤ表示パネルの一実施形態の構成を示す説明図である。図１（ａ）は平面図、（ｂ）は、（ａ）のＡ－Ａ線断面図のうち、１つのＬＥＤチップ３に着目した要部拡大断面図である。（ｃ）は、説明の理解を容易にするため、（ｂ）において、ＬＥＤチップ３が実装される前の状態を示す図である。また、図２は、詳細には、蛍光体セルアレイ１０をさらにＬＥＤ表示パネルに設けた平面図である。蛍光体セルアレイ１０は、蛍光体セル１０ａを行列（マトリクス）状に配置したものである。蛍光体セル１０ａは、赤（Ｒ）、緑（Ｇ）、青（Ｂ）の蛍光発光層１１をいわゆるリブ構造で区画して一つの単位としたものである。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 are explanatory views showing a configuration of an embodiment of an LED display panel according to the present invention. 1A is a plan view, and FIG. 1B is an enlarged cross-sectional view of a main part focusing on one LED chip 3 in the sectional view taken along line AA of FIG. 1A. FIG. 3C is a diagram showing a state before the LED chip 3 is mounted in FIG. 3B in order to facilitate understanding of the description. Further, FIG. 2 is a plan view in which the phosphor cell array 10 is further provided on the LED display panel. The phosphor cell array 10 is formed by arranging the phosphor cells 10a in a matrix. The phosphor cell 10a is a unit in which the red (R), green (G), and blue (B) fluorescent light emitting layers 11 are partitioned by a so-called rib structure.
　ＬＥＤ表示パネルは、図１（ａ）において、配線基板１上に複数のＬＥＤチップ３を実装したものであって、配線基板１と、固着部材２と、マイクロＬＥＤチップ（以下、単に「ＬＥＤチップ」という）３と、を備えたＬＥＤアレイ１００により構成されている。ＬＥＤ表示パネルは、ＬＥＤチップ３を点灯させて映像をフルカラー表示するものである。但し、ＬＥＤ表示パネルは、ＬＥＤチップ３として、例えば、単一色の紫外光発光ダイオード（ＵＶ－ＬＥＤ）を用いる場合には、フルカラー表示をさせるために、上記の蛍光体セルアレイ１０をさらに備える構成としている。なお、このＬＥＤ表示パネルは基板接続構造の一例であり、ＬＥＤチップ３は電子部品の一例である。 In FIG. 1A, the LED display panel has a plurality of LED chips 3 mounted on the wiring board 1, and includes a wiring board 1, a fixing member 2, and a micro LED chip (hereinafter, simply "LED chip"). It is composed of the LED array 100 provided with 3). The LED display panel lights up the LED chip 3 to display an image in full color. However, when the LED chip 3 uses, for example, a single-color ultraviolet light emitting diode (UV-LED), the LED display panel is further provided with the above-mentioned phosphor cell array 10 in order to display a full color. There is. The LED display panel is an example of a substrate connection structure, and the LED chip 3 is an example of an electronic component.
　ＬＥＤチップ３は、図１（ａ）に示すとおり、予め定められたピッチ間隔の２次元配列により、配線基板１の一方の面上に行列状に実装されている。また、ＬＥＤチップ３は、図１（ｂ）に示すとおり、表面に窪み部を有する一対の電極部３ａ、３ｂ（以下、電極部３ａ、３ｂをまとめて「電極部３０」ということがある）を備える。一対の電極部３ａ、３ｂは、例えば、外部回路からＬＥＤへ通電を可能とする電極パッドであって、電極部３ａがｎ側電極パッド（カソード電極）、電極部３ｂがｐ側電極パッド（アノード電極）である。 As shown in FIG. 1 (a), the LED chips 3 are mounted in a matrix on one surface of the wiring board 1 by a two-dimensional arrangement of predetermined pitch intervals. Further, as shown in FIG. 1B, the LED chip 3 has a pair of electrode portions 3a and 3b having recessed portions on the surface (hereinafter, the electrode portions 3a and 3b may be collectively referred to as “electrode portion 30”). To be equipped with. The pair of electrode portions 3a and 3b are, for example, electrode pads that enable the LED to be energized from an external circuit. The electrode portion 3a is an n-side electrode pad (cathode electrode), and the electrode portion 3b is a p-side electrode pad (anode). Electrode).
　配線基板１は、ＬＥＤチップ３の電極部３ａ、３ｂの窪み部（凹部）に電気的及び機械的に接続する突状のバンプ電極４ａ、４ｂ（以下、バンプ電極４ａ、４ｂをまとめて「バンプ電極４」ということがある）と、各バンプ電極４ａ、４ｂの配置に応じて位置が定められ、ＬＥＤチップ３を固着する固着部材２と、を備える。そして、ＬＥＤ表示パネルは、ＬＥＤチップ３の電極部３ａ、３ｂの窪み部にバンプ電極４ａ、４ｂが各々対面接合していると共に、固着部材２によりＬＥＤチップ３を配線基板１に固着することを特徴とするものである。 The wiring board 1 is a group of projecting bump electrodes 4a and 4b (hereinafter, bump electrodes 4a and 4b) that are electrically and mechanically connected to the recesses (recesses) of the electrode portions 3a and 3b of the LED chip 3 and are "bumps". (Sometimes referred to as an electrode 4), and a fixing member 2 whose position is determined according to the arrangement of the bump electrodes 4a and 4b to which the LED chip 3 is fixed. Then, in the LED display panel, the bump electrodes 4a and 4b are face-to-face bonded to the recessed portions of the electrode portions 3a and 3b of the LED chip 3, and the LED chip 3 is fixed to the wiring board 1 by the fixing member 2. It is a feature.
　配線基板１は、例えば、ポリイミドフィルム等から成るフレキシブル基板であってもよい。本実施形態では、例えば、ポリイミドフィルム基板上にＬＥＤチップ３の発光を個別にオン状態又はオフ状態として駆動するためのＴＦＴ（薄膜トランジスタ、Thin Film Transistor）駆動回路が設けられ、そのＴＦＴ駆動回路上の所定位置にバンプ電極４が設けられている。詳細には、配線基板１は、例えばフレキシブルプリント回路基板（ＦＰＣ：Flexible Printed Circuits）であって、絶縁性を有するベースフィルム（例えば、ポリイミド）と、電気回路を形成した配線層とからなるフィルム状の基板である。配線基板１は、外部の駆動装置に接続される走査配線及びデータ配線（図示省略）が縦横に交差して設けられている。また、走査配線及びデータ配線の交点には、薄膜トランジスタが設けられている。 The wiring board 1 may be, for example, a flexible board made of a polyimide film or the like. In the present embodiment, for example, a TFT (Thin Film Transistor) drive circuit for individually driving the light emission of the LED chip 3 as an on state or an off state is provided on the polyimide film substrate, and the TFT drive circuit is provided. The bump electrode 4 is provided at a predetermined position. Specifically, the wiring board 1 is, for example, a flexible printed circuit board (FPC: Flexible Printed Circuits), which is in the form of a film composed of an insulating base film (for example, polyimide) and a wiring layer forming an electric circuit. It is a substrate of. The wiring board 1 is provided with scanning wiring and data wiring (not shown) connected to an external drive device intersecting vertically and horizontally. Further, a thin film transistor is provided at the intersection of the scanning wiring and the data wiring.
　走査配線及びデータ配線の交点にて、ＬＥＤチップ３を配線基板１上に実装する実装領域には、図１（ｂ）、（ｃ）に示すように、ＬＥＤチップ３の実装時に、ＬＥＤチップ３を受け入れて該ＬＥＤチップ３の電極部３０と配線基板１に設けられたバンプ電極４とを電気的に接触させ得るようにＬＥＤチップ３を案内する固着部材２が設けられている。ここで、図１（ｂ）、（ｃ）において配線１ａはＴＦＴ駆動回路の配線を模式的に示している。 As shown in FIGS. 1 (b) and 1 (c), in the mounting area where the LED chip 3 is mounted on the wiring board 1 at the intersection of the scanning wiring and the data wiring, the LED chip 3 is mounted when the LED chip 3 is mounted. A fixing member 2 for guiding the LED chip 3 is provided so that the electrode portion 30 of the LED chip 3 and the bump electrode 4 provided on the wiring substrate 1 can be electrically contacted with each other. Here, in FIGS. 1B and 1C, the wiring 1a schematically shows the wiring of the TFT drive circuit.
　固着部材２は、バンプ電極４の配置に応じて位置が定められ、ＬＥＤチップ３を配線基板１に固着させるものである。固着部材２は、弾性変形によりＬＥＤチップ３を支持する樹脂であって、ＬＥＤチップ３が配線基板１に固着された状態で、ＬＥＤチップ３からの圧力に応じて収縮して、ＬＥＤチップ３の電極部３ａの窪み部をバンプ電極４ａに誘導して対面接合させると共に、ＬＥＤチップ３の電極部３ｂの窪み部をバンプ電極４ｂに誘導して対面接合させているものである。つまり、固着部材２は、ガイド部材としての機能を有する。 The position of the fixing member 2 is determined according to the arrangement of the bump electrodes 4, and the LED chip 3 is fixed to the wiring board 1. The fixing member 2 is a resin that supports the LED chip 3 by elastic deformation, and in a state where the LED chip 3 is fixed to the wiring substrate 1, it contracts in response to the pressure from the LED chip 3 to form the LED chip 3. The recessed portion of the electrode portion 3a is guided to the bump electrode 4a to be face-to-face bonded, and the recessed portion of the electrode portion 3b of the LED chip 3 is guided to the bump electrode 4b to be face-to-face bonded. That is, the fixing member 2 has a function as a guide member.
　詳細には、固着部材２は、樹脂が感光性熱硬化型接着剤であって、感光性を有することによりパターニングして形成されたものであり、配線基板１のバンプ電極４ａ、４ｂを囲む領域に設けられており、熱硬化によりＬＥＤチップ３を配線基板１に固着させるものである。 Specifically, the fixing member 2 is formed by patterning the resin as a photosensitive thermosetting adhesive and having photosensitivity, and is a region surrounding the bump electrodes 4a and 4b of the wiring board 1. The LED chip 3 is fixed to the wiring board 1 by thermosetting.
　なお、感光性熱硬化型接着剤としては、感光性かつ熱硬化性を有する樹脂等が好適に用いられる。例えば、エポキシ樹脂、アクリル樹脂、フェノール樹脂、ポリイミド樹脂、シリコーン樹脂、スチレン樹脂等を主成分に含む樹脂が望ましい。このように、感光性を有するものを接着剤として用いれば、その接着剤を塗布した後にフォトリソグラフィーにより露光及び現像することで、所定の位置に正確に接着剤を固着部材２として配置できるようになる。本実施形態では、感光性を有する接着剤に熱硬化の機能をさらに備えた感光性熱硬化型接着剤を採用している。 As the photosensitive thermosetting adhesive, a photosensitive and thermosetting resin or the like is preferably used. For example, a resin containing an epoxy resin, an acrylic resin, a phenol resin, a polyimide resin, a silicone resin, a styrene resin or the like as a main component is desirable. In this way, if a photosensitive material is used as an adhesive, the adhesive can be accurately placed at a predetermined position as the fixing member 2 by exposing and developing the adhesive by photolithography after applying the adhesive. Become. In the present embodiment, a photosensitive thermosetting adhesive having a thermosetting function is adopted as a photosensitive adhesive.
　ＬＥＤチップ３は、例えば窒化ガリウム（ＧａＮ）を主材料として製造される。具体的には、ＬＥＤチップ３は、紫外光発光ダイオード（ＵＶ－ＬＥＤ）であっても青色光を発光するＬＥＤであってもよい。紫外光発光ダイオード（ＵＶ－ＬＥＤ）としては、例えばピーク波長が、３５５、３６０、３６５、３７０、３７５、３８５、３９５、４００、４０５ｎｍに対応する光を発光するものが知られている。本実施形態では、例えば、蛍光体の変換効率等を考慮して、３８５ｎｍの波長を選択してもよい。なお、図１において、ＬＥＤチップ３は、例えば、外形サイズが１５×４５μｍ程度である。ＬＥＤチップ３の電極部３０の厚みは約３μｍである。また、バンプ電極４の厚みは約８μｍであり、固着部材２の膜厚は、１１～１２μｍ程度である。 The LED chip 3 is manufactured using, for example, gallium nitride (GaN) as a main material. Specifically, the LED chip 3 may be an ultraviolet light emitting diode (UV-LED) or an LED that emits blue light. As an ultraviolet light emitting diode (UV-LED), for example, one that emits light corresponding to a peak wavelength of 355, 360, 365, 370, 375, 385, 395, 400, 405 nm is known. In the present embodiment, for example, a wavelength of 385 nm may be selected in consideration of the conversion efficiency of the phosphor and the like. In FIG. 1, the LED chip 3 has, for example, an external size of about 15 × 45 μm. The thickness of the electrode portion 30 of the LED chip 3 is about 3 μm. The thickness of the bump electrode 4 is about 8 μm, and the film thickness of the fixing member 2 is about 11 to 12 μm.
　本実施形態においては、例えば、紫外光発光ダイオード（ＵＶ－ＬＥＤ）等の短波長の光を発光するＬＥＤとＲＧＢ蛍光体とを組み合わせてフルカラー表示を実現する方式を採用する。この場合、ＬＥＤチップ３の光放出面側には、紫外又は青色波長帯の光を予め定められた対応色に各々変換するＲＧＢ蛍光体を有する蛍光発光層１１を有する蛍光体セル１０ａが設けられる。 In this embodiment, for example, a method of realizing full-color display by combining an LED that emits light having a short wavelength such as an ultraviolet light emitting diode (UV-LED) and an RGB phosphor is adopted. In this case, a phosphor cell 10a having a fluorescence light emitting layer 11 having an RGB phosphor that converts light in the ultraviolet or blue wavelength band into a predetermined corresponding color is provided on the light emitting surface side of the LED chip 3. ..
　詳細には、ＬＥＤ表示パネルは、図２に示すとおり、その配線基板１上に、ＬＥＤチップ３及び固着部材２を介して、蛍光発光層１１を含む蛍光体セル１０ａがマトリクス状に配置された蛍光体セルアレイ１０を備える。蛍光発光層１１は、ＬＥＤチップ３から放出された光（励起光）によって励起されて、予め定められた対応色の蛍光に波長変換する蛍光材を、リブ構造により周囲を遮光壁により囲まれた領域に充填したものである。ここで、予め定められた対応色は、ＲＧＢ蛍光体によって定まり、光の三原色である赤（Ｒ）、緑（Ｇ）、青（Ｂ）に相当する色である。これにより、ＬＥＤ表示パネルは、フルカラー表示を実現するための複数の蛍光体セル１０ａがマトリクス状に配置されたことになる。図２では、説明をわかりやすくするため、蛍光体セルアレイ１０について、複数の蛍光体セル１０ａを４行５列の配置としている。 Specifically, as shown in FIG. 2, the LED display panel has phosphor cells 10a including the fluorescence light emitting layer 11 arranged in a matrix on the wiring substrate 1 via the LED chip 3 and the fixing member 2. The phosphor cell array 10 is provided. The fluorescence light emitting layer 11 is surrounded by a light-shielding wall with a rib structure of a fluorescent material that is excited by light (excitation light) emitted from the LED chip 3 and that converts the wavelength into fluorescence of a predetermined corresponding color. The area is filled. Here, the predetermined corresponding color is determined by the RGB phosphor and is a color corresponding to the three primary colors of light, red (R), green (G), and blue (B). As a result, in the LED display panel, a plurality of phosphor cells 10a for realizing full-color display are arranged in a matrix. In FIG. 2, in order to make the explanation easy to understand, a plurality of phosphor cells 10a are arranged in 4 rows and 5 columns in the phosphor cell array 10.
　図３は、蛍光体セルの説明図である。図３（ａ）は、図２に示す蛍光体セル１０ａの拡大平面図、（ｂ）は、（ａ）のＢ－Ｂ線断面図である。（ｃ）は、（ｂ）に示すＬＥＤチップ３の正面図である。 FIG. 3 is an explanatory diagram of the phosphor cell. 3A is an enlarged plan view of the phosphor cell 10a shown in FIG. 2, and FIG. 3B is a sectional view taken along line BB of FIG. 2A. (C) is a front view of the LED chip 3 shown in (b).
　図３（ａ）において、蛍光発光層１１は、赤色の蛍光色素を充填した蛍光材層１１Ｒ、緑色の蛍光色素を充填した蛍光材層１１Ｇ、青色の蛍光色素を充填した蛍光材層１１Ｂを有している。これらの蛍光色素は、ＲＧＢ蛍光体の一例である。そして、蛍光発光層１１は、図３（ｂ）に示すとおり、赤色、緑色、青色の蛍光色素（蛍光材の一例）がフルカラー表示を実現するための赤（Ｒ）、緑（Ｇ）、青（Ｂ）の蛍光に夫々波長変換するものである。具体的には、ＬＥＤチップ３から放出された光（励起光）によって、各蛍光材層１１Ｒ、１１Ｇ、１１Ｂの蛍光色素が励起状態に遷移し、その後、基底状態に戻るときに、各蛍光材によって各々波長変換された赤（Ｒ）、緑（Ｇ）、青（Ｂ）の可視スペクトルに相当する蛍光を発光する。 In FIG. 3A, the fluorescent light emitting layer 11 includes a fluorescent material layer 11R filled with a red fluorescent dye, a fluorescent material layer 11G filled with a green fluorescent dye, and a fluorescent material layer 11B filled with a blue fluorescent dye. doing. These fluorescent dyes are examples of RGB phosphors. Then, as shown in FIG. 3B, the fluorescent light emitting layer 11 has red (R), green (G), and blue for the red, green, and blue fluorescent dyes (an example of the fluorescent material) to realize full-color display. The wavelength is converted to the fluorescence of (B), respectively. Specifically, when the fluorescent dyes of the fluorescent material layers 11R, 11G, and 11B transition to the excited state by the light (excitation light) emitted from the LED chip 3, and then return to the basal state, each fluorescent material is used. It emits fluorescence corresponding to the visible spectra of red (R), green (G), and blue (B), which are wavelength-converted by.
　これらの蛍光材層１１Ｒ、１１Ｇ、１１Ｂは、金属膜１３を表面に有する隔壁１４で区画されている。このような隔壁１４は、遮光壁の一例であって、蛍光材層１１Ｒ、１１Ｇ、１１Ｂを互いに隔てるものである。なお、金属膜１３、隔壁１４がリブ構造の構成要素である。 These fluorescent material layers 11R, 11G, and 11B are partitioned by a partition wall 14 having a metal film 13 on the surface. Such a partition wall 14 is an example of a light-shielding wall, and separates the fluorescent material layers 11R, 11G, and 11B from each other. The metal film 13 and the partition wall 14 are constituent elements of the rib structure.
　隔壁１４の表面には、図３（ｂ）に示すように、反射膜としての機能を有する金属膜１３が設けられている。この金属膜１３は、光放出面３２から放出される励起光及び蛍光が隔壁１４を透過して隣接する他の色の蛍光と混色するのを防止するためのものである。蛍光は、各蛍光材層１１Ｒ、１１Ｇ、１１Ｂの各蛍光色素が励起光により励起されることにより、発光する。金属膜１３は、励起光及び蛍光を十分に遮断できる厚みで形成されている。この場合、金属膜１３としては、励起光を反射し易いアルミニウムやアルミ合金等の薄膜が好適である。 As shown in FIG. 3B, a metal film 13 having a function as a reflective film is provided on the surface of the partition wall 14. The metal film 13 is for preventing the excitation light and fluorescence emitted from the light emitting surface 32 from passing through the partition wall 14 and mixing with fluorescence of another adjacent color. Fluorescence is emitted when each fluorescent dye of each fluorescent material layer 11R, 11G, 11B is excited by excitation light. The metal film 13 is formed with a thickness capable of sufficiently blocking excitation light and fluorescence. In this case, as the metal film 13, a thin film such as aluminum or an aluminum alloy that easily reflects excitation light is suitable.
　また、ＬＥＤアレイ１００と蛍光体セルアレイ１０とは、貼り合されることにより表示パネルが形成される（図３（ｂ）参照）。この場合、ＬＥＤアレイ１００は、蛍光体セルアレイ１０を接着して支持する平板状の平坦化膜１２をさらに備える。ＬＥＤチップ３は、図３（ｃ）に示すとおり、紫外光発光ダイオード（ＵＶ－ＬＥＤ）である化合物半導体３１の上面（一方の面）の予め定められた位置に発光用の電極部３ａ、３ｂを有し、電極部３ａは窪み部３０ａを有し、電極部３ｂは窪み部３０ｂを有している（以下、窪み部３０ａ、３０ｂをまとめて「窪み部３３」ということがある）。また、ＬＥＤチップ３は、化合物半導体３１の下面（他方の面）に光源（特定の紫外光を発光する発光層）からの光を放出する光放出面３２を有している。 Further, the LED array 100 and the phosphor cell array 10 are bonded to each other to form a display panel (see FIG. 3B). In this case, the LED array 100 further includes a flat plate-shaped flattening film 12 that adheres and supports the phosphor cell array 10. As shown in FIG. 3C, the LED chip 3 has electrode portions 3a and 3b for emitting light at predetermined positions on the upper surface (one surface) of the compound semiconductor 31 which is an ultraviolet light emitting diode (UV-LED). The electrode portion 3a has a recessed portion 30a, and the electrode portion 3b has a recessed portion 30b (hereinafter, the recessed portions 30a and 30b may be collectively referred to as a “dented portion 33”). Further, the LED chip 3 has a light emitting surface 32 that emits light from a light source (a light emitting layer that emits specific ultraviolet light) on the lower surface (the other surface) of the compound semiconductor 31.
　図４は、ＬＥＤチップの電極部の窪み部について、複数の形状を示す説明図である。図４では、電極部３ａ、３ｂの複数の溝形状を例示している（図４（ａ）～（ｆ）参照）。この溝形状が窪み部３０ａ、３０ｂを形成している。但し、窪み部３０ａ、３０ｂの形状に応じて、バンプ電極４ａ、４ｂの形状が定まる。すなわち、本実施形態では、例えば、窪み部３０ａ、３０ｂの凹部が、バンプ電極４ａ、４ｂの凸部とそれぞれ嵌まり合うように接合すればよい。但し、ここで、「嵌まり合う」とは、必ずしも隙間なく嵌まり合って接合することを意味するものではない。つまり、バンプ電極４ａ、４ｂの突状の先端面が、電極部３ａ、３ｂの窪み部３０ａ、３０ｂの面に各々対面接合すればよい。換言すると、窪み部３０ａとバンプ電極４ａ、窪み部３０ｂとバンプ電極４ｂとは、電気的及び機械的に接続していればよい。この機械的な接続には、共晶や半田等の化学的な結合が含まれる。 FIG. 4 is an explanatory view showing a plurality of shapes of the recessed portion of the electrode portion of the LED chip. FIG. 4 illustrates a plurality of groove shapes of the electrode portions 3a and 3b (see FIGS. 4A to 4F). This groove shape forms the recessed portions 30a and 30b. However, the shapes of the bump electrodes 4a and 4b are determined according to the shapes of the recessed portions 30a and 30b. That is, in the present embodiment, for example, the concave portions of the recessed portions 30a and 30b may be joined so as to be fitted with the convex portions of the bump electrodes 4a and 4b, respectively. However, here, "fitting" does not necessarily mean fitting and joining without a gap. That is, the protruding tip surfaces of the bump electrodes 4a and 4b may be face-to-face bonded to the surfaces of the recessed portions 30a and 30b of the electrode portions 3a and 3b, respectively. In other words, the recessed portion 30a and the bump electrode 4a, and the recessed portion 30b and the bump electrode 4b may be electrically and mechanically connected. This mechanical connection includes chemical bonds such as eutectic and solder.
　以上より、ＬＥＤ表示パネルは、上述した構成により、ＬＥＤチップ３の窪み部３３にバンプ電極４が対面接合するようにしているので、配線基板１とＬＥＤチップ３との相対的な滑りや回転ずれを防止することができる。これにより、ＬＥＤ表示パネルは、ＬＥＤチップ３の実装時の歩留りを向上させて、正常に点灯可能なＬＥＤチップ３を点灯させることにより、蛍光体セル１０ａを介して映像をフルカラー表示することができる。 From the above, in the LED display panel, the bump electrode 4 is face-to-face bonded to the recessed portion 33 of the LED chip 3 according to the above-described configuration, so that the wiring substrate 1 and the LED chip 3 are relatively slippery or rotationally displaced. Can be prevented. As a result, the LED display panel can improve the yield when the LED chip 3 is mounted, and by lighting the LED chip 3 that can be normally lit, the image can be displayed in full color via the phosphor cell 10a. ..
　次に、上述したＬＥＤ表示パネルを製造するため、配線基板１に電子部品として複数のＬＥＤチップ３を実装する電子部品実装方法、及び、この電子部品実装方法を採用したＬＥＤ表示パネルの製造方法について説明する。 Next, in order to manufacture the above-mentioned LED display panel, an electronic component mounting method for mounting a plurality of LED chips 3 as electronic components on the wiring board 1 and a method for manufacturing an LED display panel using this electronic component mounting method. explain.
　図５、図６は、本発明による電子部品実装方法及び前処理を示す説明図である。図５、図６では、説明をわかりやすくするため、３つのＬＥＤチップ３について例示している。図７は、本発明による電子部品実装方法を採用したＬＥＤ表示パネルの製造方法の工程を示す流れ図である。図７に示す工程Ｓ４～Ｓ５の処理が、電子部品実装方法の処理に対応している。そして、図７に示す工程Ｓ１～Ｓ３の処理が、電子部品実装方法の前処理に対応している。先ず、ＬＥＤチップの形成（工程Ｓ１）では、サファイア基板７上に、所定のピッチ間隔でＬＥＤチップ３を予め定められた配列（ｎ行ｍ列）に従って行列状に形成する。図５（ａ）は、サファイア基板７上にＬＥＤチップ３が形成された状態を示している。なお、ＬＥＤチップの形成の詳細については、図９～図１１を用いて後述する。ここで、図５（ａ）は、図１１に示す破線で囲む領域Ｒ１の３つのＬＥＤチップ３に対応している。また、本実施形態では、サファイア基板７に限られず、合成石英基板を採用してもよい。 5 and 6 are explanatory views showing an electronic component mounting method and preprocessing according to the present invention. In FIGS. 5 and 6, three LED chips 3 are illustrated for easy explanation. FIG. 7 is a flow chart showing a process of a manufacturing method of an LED display panel adopting the electronic component mounting method according to the present invention. The processes of steps S4 to S5 shown in FIG. 7 correspond to the processes of the electronic component mounting method. The processes of steps S1 to S3 shown in FIG. 7 correspond to the preprocessing of the electronic component mounting method. First, in the formation of the LED chips (step S1), the LED chips 3 are formed in a matrix on the sapphire substrate 7 according to a predetermined arrangement (n rows and m columns) at predetermined pitch intervals. FIG. 5A shows a state in which the LED chip 3 is formed on the sapphire substrate 7. The details of the formation of the LED chip will be described later with reference to FIGS. 9 to 11. Here, FIG. 5A corresponds to the three LED chips 3 in the region R1 surrounded by the broken line shown in FIG. Further, in the present embodiment, the present invention is not limited to the sapphire substrate 7, and a synthetic quartz substrate may be adopted.
　次に、バンプ電極の形成（工程Ｓ２）では、図５（ｂ）に示すように、先ず、突状のバンプ電極４を、ＬＥＤチップ３の配列に対応して配線基板１上に形成する。なお、バンプ電極４は、金属バンプ電極、半田による接続を行なえるソルダーバンプ電極、金属膜が積層されたレジストバンプ電極の何れかであることが好ましい。バンプ電極４は、金属バンプ電極、ソルダーバンプ電極、レジストバンプ電極の何れかを選択することにより、良好な接続を行なうことができる。 Next, in the formation of the bump electrode (step S2), as shown in FIG. 5B, first, the protruding bump electrode 4 is formed on the wiring board 1 corresponding to the arrangement of the LED chips 3. The bump electrode 4 is preferably a metal bump electrode, a solder bump electrode that can be connected by solder, or a resist bump electrode on which a metal film is laminated. The bump electrode 4 can be well connected by selecting any of a metal bump electrode, a solder bump electrode, and a resist bump electrode.
　具体的には、工程Ｓ２では、一例としてバンプ電極４として金属バンプ電極を形成する。工程Ｓ２では、例えば、ガスデポジション法を採用して、配線基板１上にバンプ電極４を形成する箇所のみに微細な穴があいたマスクを載置して、金の微粒子を堆積させて、マスクを取り除くことにより、突状のバンプ電極４を形成する。なお、本実施形態において、「突状」の形状とは、円錐状やテーパ状に限定されるものではなく、例えば、円柱状のような形態も含まれる。つまり、バンプ電極４の形状は、窪み部３３と対面接合可能な形状であればよい。 Specifically, in step S2, a metal bump electrode is formed as the bump electrode 4 as an example. In step S2, for example, by adopting the gas deposition method, a mask having fine holes is placed only on the portion where the bump electrode 4 is formed on the wiring board 1, and fine gold particles are deposited on the mask. By removing the above, a protruding bump electrode 4 is formed. In the present embodiment, the "protruding" shape is not limited to a conical shape or a tapered shape, and includes, for example, a cylindrical shape. That is, the shape of the bump electrode 4 may be any shape that can be face-to-face bonded to the recessed portion 33.
　次に、固着部材の形成（工程Ｓ３）では、バンプ電極４が形成された配線基板１上に、例えばスプレー装置やスピナー（スピンコータ）等の塗布装置を使用して感光性熱硬化型接着剤６を所定の厚みで均一に塗布する（図５（ｃ）参照）。なお、感光性熱硬化型接着剤６は、フォトリソグラフィーにより特定の形状にパターニングされることが可能である。 Next, in the formation of the fixing member (step S3), the photosensitive thermosetting adhesive 6 is formed on the wiring substrate 1 on which the bump electrode 4 is formed by using a coating device such as a spray device or a spinner (spin coater). Is uniformly applied to a predetermined thickness (see FIG. 5 (c)). The photosensitive thermosetting adhesive 6 can be patterned into a specific shape by photolithography.
　図８は、感光性熱硬化型接着剤の温度に対する粘度及び弾性率の関係を示すグラフである。感光性熱硬化型接着剤６は、光硬化後において、図８に示すような粘性／弾性の温度特性を有している。この場合、領域Ｉは、図８の温度Ｔ１を境として可逆性を有し、領域IIは、不可逆性の性質を有している。本実施形態においては、感光性熱硬化型接着剤６は、上記温度Ｔ１（例えば１１０℃）で弾性率が０．０５ＭＰａ～０．１ＭＰａであり、外力に応じてＬＥＤチップ３の形状に合せて変形すると共に、変形に応じた反力を利用してＬＥＤチップ３を把持する機能を有する。 FIG. 8 is a graph showing the relationship between the viscosity and elastic modulus of the photosensitive thermosetting adhesive with respect to temperature. The photosensitive thermosetting adhesive 6 has viscous / elastic temperature characteristics as shown in FIG. 8 after photocuring. In this case, the region I has reversibility with the temperature T1 in FIG. 8 as a boundary, and the region II has an irreversible property. In the present embodiment, the photosensitive thermosetting adhesive 6 has an elastic modulus of 0.05 MPa to 0.1 MPa at the above temperature T1 (for example, 110 ° C.), and is adapted to the shape of the LED chip 3 according to an external force. It is deformed and has a function of gripping the LED chip 3 by utilizing the reaction force corresponding to the deformation.
　続いて、工程Ｓ３では、図５（ｄ）に示すように、フォトリソグラフィーにより、感光性熱硬化型接着剤６をパターニングし、ＬＥＤチップ３が実装される領域に、例えば、配線基板１のバンプ電極４に対応する開口部５を設けた固着部材２を形成する。なお、図５（ｄ）においては、開口部５がＬＥＤチップ３の外形形状に対応した形状を有するものである場合を示している。すなわち、工程Ｓ３では、液体状の感光性熱硬化型接着剤６をスピナー等の塗布装置により塗布し、パターニングした後に加熱することで弾性を有する固着部材２を形成することができる。 Subsequently, in step S3, as shown in FIG. 5D, the photosensitive thermosetting adhesive 6 is patterned by photolithography, and in the region where the LED chip 3 is mounted, for example, a bump of the wiring board 1 is formed. A fixing member 2 having an opening 5 corresponding to the electrode 4 is formed. Note that FIG. 5D shows a case where the opening 5 has a shape corresponding to the outer shape of the LED chip 3. That is, in step S3, the liquid photosensitive thermosetting adhesive 6 is applied by a coating device such as a spinner, patterned, and then heated to form the elastic fixing member 2.
　次に、配線基板とサファイア基板との貼り合せ（工程Ｓ４）では、先ず、サファイア基板７の一方の面上に形成された複数のＬＥＤチップ３を、夫々、配線基板１上に実装する実装領域に位置決めする（図５（ｅ）参照）。続いて、工程Ｓ４では、ＬＥＤチップ３を配線基板１に対して接触させた後（図６（ａ）参照）、サファイア基板７の他方の面から圧力Ｐで加圧することにより、ＬＥＤチップ３の電極部３０の窪み部３３と配線基板１のバンプ電極４とを導通可能に対面接合させる（図６（ｂ）参照）。さらに、工程Ｓ４では、ＬＥＤチップ３と配線基板１の導通状態を維持してＬＥＤチップ３を加熱硬化により配線基板１に固着する（図６（ｃ）参照）。 Next, in the bonding of the wiring board and the sapphire board (step S4), first, a mounting area in which a plurality of LED chips 3 formed on one surface of the sapphire board 7 are mounted on the wiring board 1, respectively. Positioning to (see FIG. 5 (e)). Subsequently, in step S4, after the LED chip 3 is brought into contact with the wiring board 1 (see FIG. 6A), the LED chip 3 is pressed by the pressure P from the other surface of the sapphire board 7. The recessed portion 33 of the electrode portion 30 and the bump electrode 4 of the wiring board 1 are joined face-to-face so as to be conductive (see FIG. 6B). Further, in step S4, the LED chip 3 and the wiring board 1 are maintained in a conductive state and the LED chip 3 is fixed to the wiring board 1 by heat curing (see FIG. 6C).
　具体的には、工程Ｓ４において、フリップチップボンダ装置等の実装装置を使用することにより、図５（ｅ）に示すように、サファイア基板７の一方の面上に形成された複数のＬＥＤチップ３は、夫々、配線基板１上に実装する実装領域の固着部材２上に位置決めされる。この位置決めは、一例として、実装装置により、配線基板１に設けられたアライメントマークとサファイア基板７に設けられたアライメントマークとをアライメント用のカメラにより撮影し、両アライメントマークが合致又は所定の位置関係を成すようにアライメントして実行される。 Specifically, in step S4, by using a mounting device such as a flip chip bonder device, a plurality of LED chips 3 formed on one surface of the sapphire substrate 7 as shown in FIG. 5 (e). Are respectively positioned on the fixing member 2 of the mounting region to be mounted on the wiring board 1. For this positioning, as an example, an alignment mark provided on the wiring board 1 and an alignment mark provided on the sapphire board 7 are photographed by an alignment camera by a mounting device, and both alignment marks match or have a predetermined positional relationship. It is aligned and executed so as to form.
　続いて、工程Ｓ４では、図６（ａ）に示すように、ＬＥＤチップ３と配線基板１とを相対的に近接移動してＬＥＤチップ３を固着部材２にプリボンディングした後、図６（ｂ）に示すように、相対的に図中の矢印方向に圧力Ｐで加圧し、ＬＥＤチップ３の電極部３０と配線基板１のバンプ電極４とを電気的及び機械的に接続させる。この場合、工程Ｓ４では、プリボンディングから次の加熱硬化実施前まで、予備加熱を行い、感光性熱硬化型接着剤６の弾性率を下げた状態（変形しやすい状態）にして、圧力Ｐで加圧している。この予備加熱の温度としては、図８に示す温度Ｔ１（例えば１１０℃）～１２０℃程度であることが好ましい。 Subsequently, in step S4, as shown in FIG. 6A, the LED chip 3 and the wiring board 1 are moved relatively close to each other to prebond the LED chip 3 to the fixing member 2, and then FIG. 6B ), The pressure P is relatively applied in the direction of the arrow in the drawing to electrically and mechanically connect the electrode portion 30 of the LED chip 3 and the bump electrode 4 of the wiring substrate 1. In this case, in step S4, preheating is performed from prebonding to before the next heat curing to lower the elastic modulus of the photosensitive thermosetting adhesive 6 (a state in which it is easily deformed), and the pressure P is applied. It is pressurizing. The temperature of this preheating is preferably about T1 (for example, 110 ° C.) to 120 ° C. shown in FIG.
　さらに、工程Ｓ４では、図６（ｃ）に示すように、感光性熱硬化型接着剤６を外部ヒータ２０からの熱Ｈを用いて所定の時間で加熱硬化させてＬＥＤチップ３を配線基板１に固着する。具体的には、工程Ｓ４では、上記通電状態を維持してＬＥＤチップ３を保持した状態で、感光性熱硬化型接着剤６を１８０℃で９０分間、２００℃で６０分間又は２３０℃で３０分間の何れかで加熱硬化し、ＬＥＤチップ３を配線基板１に固着する。 Further, in step S4, as shown in FIG. 6C, the photosensitive thermosetting adhesive 6 is heat-cured using heat H from the external heater 20 for a predetermined time, and the LED chip 3 is heat-cured on the wiring board 1. Stick to. Specifically, in step S4, the photosensitive thermosetting adhesive 6 is applied at 180 ° C. for 90 minutes, 200 ° C. for 60 minutes, or 230 ° C. for 30 minutes while maintaining the energized state and holding the LED chip 3. The LED chip 3 is fixed to the wiring substrate 1 by heating and curing in any of the minutes.
　次に、レーザリフトオフ（工程Ｓ５）では、レーザリフトオフ用の装置を使用することにより、サファイア基板７からＬＥＤチップ３をレーザリフトオフする。具体的には、工程Ｓ５では、図６（ｄ）に示すように、上記サファイア基板７側から紫外線のライン状レーザ光Ｌをその長軸と交差する方向（Ｘ方向）に移動しながら、サファイア基板７とＬＥＤチップ３との界面に照射してサファイア基板７からＬＥＤチップ３をレーザリフトオフする。これにより、図６（ｅ）に示すように、配線基板１へのＬＥＤチップ３の実装が終了する。 Next, in the laser lift-off (process S5), the LED chip 3 is laser-lifted off from the sapphire substrate 7 by using the laser lift-off device. Specifically, in step S5, as shown in FIG. 6D, the sapphire is moved from the sapphire substrate 7 side in the direction (X direction) in which the line-shaped laser beam L of ultraviolet rays intersects the long axis thereof. The interface between the substrate 7 and the LED chip 3 is irradiated to laser lift off the LED chip 3 from the sapphire substrate 7. As a result, as shown in FIG. 6E, the mounting of the LED chip 3 on the wiring board 1 is completed.
　次に、平坦化膜の形成（工程Ｓ６）では、配線基板１へのＬＥＤチップ３の実装が終了したＬＥＤアレイ１００に感光性熱硬化型接着剤を塗布することにより、平坦化膜１２をさらに積層する。 Next, in the formation of the flattening film (step S6), the flattening film 12 is further formed by applying a photosensitive thermosetting adhesive to the LED array 100 in which the LED chip 3 has been mounted on the wiring substrate 1. Laminate.
　次に、蛍光体セルの形成（工程Ｓ７）では、図１に示す表示パネル上にＬＥＤチップ３の配列に応じて配置が定まる蛍光体セル１０ａを複数形成して、蛍光体セルアレイ１０を作製する。 Next, in the formation of the phosphor cells (step S7), a plurality of phosphor cells 10a whose arrangement is determined according to the arrangement of the LED chips 3 are formed on the display panel shown in FIG. 1 to produce the phosphor cell array 10. ..
　次に、表示パネルの形成（工程Ｓ８）では、図１に示すＬＥＤアレイ１００と蛍光体セルアレイ１０とを貼り合せて実装することにより、表示パネルを形成する。 Next, in the formation of the display panel (step S8), the display panel is formed by laminating and mounting the LED array 100 and the phosphor cell array 10 shown in FIG.
　以上より、ＬＥＤチップの形成（工程Ｓ１）から表示パネルの形成（工程Ｓ８）までの処理を説明したが、ここで、ＬＥＤチップの形成（工程Ｓ１）、平坦化膜の形成（工程Ｓ６）蛍光体セルの形成（工程Ｓ７）及び表示パネルの形成（工程Ｓ８）の詳細について説明する。 From the above, the processes from the formation of the LED chip (step S1) to the formation of the display panel (step S8) have been described. Here, the formation of the LED chip (step S1) and the formation of the flattening film (step S6) fluorescence. Details of the formation of the body cell (step S7) and the formation of the display panel (step S8) will be described.
　図９は、ＬＥＤチップの形成工程を示す説明図である。ＬＥＤチップの形成工程を示す流れ図である。ここで、青色ＬＥＤやＵＶ－ＬＥＤは、主に窒化ガリウム（ＧａＮ）系半導体積層構造で構成され、様々な半導体積層構造を形成することが可能である。本実施形態では、ＬＥＤチップ３の電極部３０に窪み部３３を形成して、その窪み部３３にバンプ電極４が対面接合するようにしている点に特徴を有しているので、本発明は、以下に説明するＬＥＤチップ３の半導体積層構造に限定されるものではない。 FIG. 9 is an explanatory diagram showing a process of forming the LED chip. It is a flow chart which shows the forming process of the LED chip. Here, the blue LED and the UV-LED are mainly composed of a gallium nitride (GaN) -based semiconductor laminated structure, and various semiconductor laminated structures can be formed. The present invention is characterized in that a recessed portion 33 is formed in the electrode portion 30 of the LED chip 3 so that the bump electrode 4 is face-to-face bonded to the recessed portion 33. , The present invention is not limited to the semiconductor laminated structure of the LED chip 3 described below.
　ＬＥＤチップの形成（工程Ｓ１）では、例えば、気相成長法（Vapour Phase. Epitaxy）の一種である有機金属気相エピタキシー（ＭＯＶＰＥ：Metalorganic vapor phase epitaxy）法を用いて、窒化ガリウム系発光ダイオードに用いられるエピ結晶層を成長させる。本実施形態では、説明を簡単にするため、エピ結晶層として、ｎ型ＧａＮ、ＭＱＷ（Multi Quantum Well）層及びｐ型ＧａＮの積層を成長させることとする。なお、ＭＯＶＰＥ法では、エピ結晶層等の半導体積層構造において、各半導体の結晶層で必要とされる特性が得られるように成長温度、成長圧力、材料ガス流量、材料ガス種、流速等のパラメータを制御しながら、結晶成長を行なっている。本実施形態では、サファイア基板７上にエピ結晶層を形成した後に、ＬＥＤチップ３が形成される領域毎に区画する処理を行なっているが、図９では、説明の便宜上、１つのＬＥＤチップ３の形成に着眼して描いている。 In the formation of the LED chip (step S1), for example, a gallium nitride based light emitting diode is formed by using a metalorganic vapor phase epitaxy (MOVPE) method, which is a kind of vapor phase epitaxy (Vapour Phase. Epitaxy). The epi crystal layer used is grown. In the present embodiment, in order to simplify the explanation, a laminate of n-type GaN, MQW (MultiQuantum Well) layer and p-type GaN is grown as the epi crystal layer. In the MOVPE method, in a semiconductor laminated structure such as an epi crystal layer, parameters such as growth temperature, growth pressure, material gas flow rate, material gas type, and flow velocity are obtained so that the characteristics required for the crystal layer of each semiconductor can be obtained. Crystal growth is performed while controlling the above. In the present embodiment, after the epi crystal layer is formed on the sapphire substrate 7, the process of partitioning each region where the LED chip 3 is formed is performed. However, in FIG. 9, one LED chip 3 is used for convenience of explanation. I draw with an eye on the formation of.
　先ず、ｎ型ＧａＮの積層（工程Ｓ１１）では、サファイア基板７上に、ｐｎ接合のｎ型窒化ガリウム３ｃを積層する。工程Ｓ１１では、ＭＯＶＰＥ法により、サファイア基板７上にＧａＮの低温バッファ層（図示省略）を積層した後にｎ型窒化ガリウム３ｃを積層している（図９（ａ）参照）。 First, in the lamination of n-type GaN (step S11), the pn-junctioned n-type gallium nitride 3c is laminated on the sapphire substrate 7. In step S11, an n-type gallium nitride 3c is laminated after laminating a GaN low-temperature buffer layer (not shown) on the sapphire substrate 7 by the MOVPE method (see FIG. 9A).
　ＭＱＷ層及びｐ型ＧａＮの積層（工程Ｓ１２）では、ＭＯＶＰＥ法を適用して、ｎ型窒化ガリウム３ｃ上に、ＩｎＧａＮ等を用いた量子井戸（ＭＱＷ）層（発光層）を積層し、その上層にｐ型窒化ガリウム層を積層する。なお、図９（ｂ）では、量子井戸層及びｐ型窒化ガリウム層をまとめて符号３ｄで表している。 In the lamination of the MQW layer and the p-type GaN (step S12), the MOVPE method is applied to laminate the quantum well (MQW) layer (light emitting layer) using InGaN or the like on the n-type gallium nitride 3c, and the upper layer thereof. A p-type gallium nitride layer is laminated on the surface. In FIG. 9B, the quantum well layer and the p-type gallium nitride layer are collectively represented by reference numeral 3d.
　続いて、本実施形態では、流れ図には示していないが、例えばフォトリソグラフィーにより、レジストマスクがパターニングされたエピ結晶層に対してドライエッチングすることにより、ＬＥＤチップ３が形成される領域毎に区画する処理を行なう。この場合、ｎ側電極パッドのスルーホールを形成するために、ｎ型ＧａＮ層までエッチングしている。 Subsequently, although not shown in the flow chart in the present embodiment, for example, by dry etching the epi crystal layer in which the resist mask is patterned by photolithography, each region where the LED chip 3 is formed is divided. Perform the processing to be performed. In this case, in order to form a through hole of the n-side electrode pad, the n-type GaN layer is etched.
　ＩＴＯの積層（工程Ｓ１３）では、例えばフォトリソグラフィーを適用してＩＴＯを積層させる領域以外をレジストマスクでマスクした後、スパッタリング蒸着法等の物理的気相法（ＰＶＤ：Physical Vapor Deposition）を適用して、透明電極材料として、ＩＴＯ（Indium Tin Oxide）層３ｅをさらに積層する（図９（ｃ）参照）。 In the lamination of ITO (step S13), for example, photolithography is applied to mask the area other than the region where ITO is laminated with a resist mask, and then a physical vapor deposition method (PVD: Physical Vapor Deposition) such as a sputtering vapor deposition method is applied. Then, as a transparent electrode material, an ITO (Indium Tin Oxide) layer 3e is further laminated (see FIG. 9 (c)).
　絶縁膜の積層（工程Ｓ１４）では、さらに、例えば化学的気相法（ＣＶＤ：Chemical Vapor Deposition）を用いて、絶縁膜（SiO2）３ｆを保護膜として積層する（図９（ｄ）参照）。ＴＨ（Through-Hole）の形成（工程Ｓ１５）では、例えばフォトリソグラフィーを適用して電極部３ａ、３ｂの導通用のスルーホールを形成する領域以外をレジストマスクでマスクした後、ドライエッチングすることにより、スルーホールを形成する（図９（ｅ）参照）。 In the lamination of the insulating film (step S14), the insulating film (SiO 2 ) 3f is further laminated as a protective film by using, for example, a chemical vapor deposition (CVD) (see FIG. 9D). .. In the formation of TH (Through-Hole) (step S15), for example, photolithography is applied to mask the regions other than the regions for forming through holes for conduction of the electrode portions 3a and 3b with a resist mask, and then dry etching is performed. , A through hole is formed (see FIG. 9E).
　ＬＥＤチップの電極部及び窪み部の形成（工程Ｓ１６）では、例えば、電極材料を真空蒸着により電極部３ａ、３ｂを形成する。電極材料としては、例えば、金を含んだ合金であってもよい。工程Ｓ１６では、電極部３ａ、３ｂを形成する際にプロセスの特性上、電極部３ａ、３ｂに窪みが生じるため、その窪みを窪み部３０ａ、３０ｂとしてもよいが、必要に応じて、図４に示すような窪み部３０ａ、３０ｂを形成するように加工してもよい（図９（ｆ）参照）。 In the formation of the electrode portion and the recessed portion of the LED chip (step S16), for example, the electrode materials 3a and 3b are formed by vacuum vapor deposition. The electrode material may be, for example, an alloy containing gold. In step S16, since the electrode portions 3a and 3b have dents due to the characteristics of the process when the electrode portions 3a and 3b are formed, the dents may be the dents 30a and 30b, but if necessary, FIG. It may be processed so as to form the recessed portions 30a and 30b as shown in (see FIG. 9F).
　図１１は、ＬＥＤチップを形成したサファイア基板の一実施形態の構成を示す図である。（ａ）は平面図であり、（ｂ）は（ａ）に示すＬＥＤチップ３の拡大平面図である。図１１（ａ）では、一例として、ＬＥＤチップ３を１２行５列に形成したサファイア基板７を示している。このようにして、ＬＥＤチップ３が形成されると、既に上述したとおり、図７に示すバンプ電極の形成（工程Ｓ２）に移行する。なお、本実施形態では、ＬＥＤチップの形成（工程Ｓ１）を固着部材の形成（工程Ｓ３）の後に実行するようにしてもよい。 FIG. 11 is a diagram showing a configuration of an embodiment of a sapphire substrate on which an LED chip is formed. (A) is a plan view, and (b) is an enlarged plan view of the LED chip 3 shown in (a). FIG. 11A shows, as an example, a sapphire substrate 7 in which LED chips 3 are formed in 12 rows and 5 columns. When the LED chip 3 is formed in this way, as described above, the process proceeds to the formation of the bump electrode shown in FIG. 7 (step S2). In this embodiment, the formation of the LED chip (step S1) may be executed after the formation of the fixing member (step S3).
　次に、平坦化膜の形成（工程Ｓ６）の詳細について説明する。図１２は、平坦化膜の形成工程を示す説明図である。（ａ）は、平坦化膜１２をさらに積層したＬＥＤアレイ１００の平面図である。（ｂ）は、（ａ）の破線で囲む領域Ｒ２の３つのＬＥＤチップ３のＣ－Ｃ線断面図である。工程Ｓ６では、例えばマイクロディスペンサーを用いて、ＬＥＤアレイ１００上に感光性熱硬化型接着剤を高さ方向が一定になるように制御しながら塗布する。続いて、工程Ｓ６では、フォトリソグラフィーにより、感光性熱硬化型接着剤を露光して平坦化膜１２を成膜する。これにより、平坦化膜１２が形成される。この際、ＬＥＤチップ３の光放出面３２には、感光性熱硬化型接着剤が成膜されないようにすることが好ましい。 Next, the details of the formation of the flattening film (step S6) will be described. FIG. 12 is an explanatory view showing a step of forming a flattening film. (A) is a plan view of the LED array 100 in which the flattening film 12 is further laminated. (B) is a cross-sectional view taken along the line CC of the three LED chips 3 in the region R2 surrounded by the broken line in (a). In step S6, for example, a microdispenser is used to apply the photosensitive thermosetting adhesive onto the LED array 100 while controlling the height direction to be constant. Subsequently, in step S6, the photosensitive thermosetting adhesive is exposed to form a flattening film 12 by photolithography. As a result, the flattening film 12 is formed. At this time, it is preferable that the photosensitive thermosetting adhesive is not formed on the light emitting surface 32 of the LED chip 3.
　次に、蛍光体セルの形成（工程Ｓ７）の詳細について説明する。図１３は、蛍光体セルの形成工程を示す説明図である。工程Ｓ７では、リブ構造の形成及び蛍光材の充填からなる。リブ構造の形成には、隔壁１４の形成、金属膜１３の形成、金属膜１３のレーザ加工が含まれる。詳細には、工程Ｓ７では、サファイア基板７ａ上に蛍光レジストを全面に塗布して、フォトリソグラフィーにより隔壁１４のパターンを形成する。 Next, the details of the formation of the phosphor cell (step S7) will be described. FIG. 13 is an explanatory diagram showing a process of forming a phosphor cell. Step S7 comprises forming a rib structure and filling with a fluorescent material. The formation of the rib structure includes the formation of the partition wall 14, the formation of the metal film 13, and the laser processing of the metal film 13. Specifically, in step S7, a fluorescent resist is applied to the entire surface of the sapphire substrate 7a, and a pattern of the partition wall 14 is formed by photolithography.
　続いて、工程Ｓ７では、混色を防止するために、隔壁１４内部を金属膜１３でメタルコートし、底面のみをパルスレーザを照射してアブレーションにより金属膜１３を剥離する。さらに、工程Ｓ７では、図１３に示すとおり、蛍光材層１１Ｒ、蛍光材層１１Ｇ、蛍光材層１１Ｂを充填する。これによりサファイア基板７ａ上に例えば図２に示すような蛍光体セルアレイ１０が形成される。 Subsequently, in step S7, in order to prevent color mixing, the inside of the partition wall 14 is metal-coated with a metal film 13, and only the bottom surface is irradiated with a pulse laser to peel off the metal film 13 by ablation. Further, in step S7, as shown in FIG. 13, the fluorescent material layer 11R, the fluorescent material layer 11G, and the fluorescent material layer 11B are filled. As a result, the phosphor cell array 10 as shown in FIG. 2, for example, is formed on the sapphire substrate 7a.
　次に、表示パネルの形成工程（工程Ｓ８）の詳細について説明する。図１４は、表示パネルの形成工程を示す説明図である。工程Ｓ８では、フリップチップボンダ装置等の実装装置を使用することにより、ＬＥＤアレイ１００と蛍光体セルアレイ１０とを貼り合せて実装する。図１４（ａ）は、ＬＥＤアレイ１００と蛍光体セルアレイ１０とを貼り合せた状態を示している。但し、図１４では、蛍光体セルアレイ１０の構成単位である蛍光体セル１０ａに着目して描いている。そして、工程Ｓ８では、配線基板とサファイア基板との貼り合せ（工程Ｓ４）と同様にして、平坦化膜１２を加熱硬化し、蛍光体セルアレイ１０をＬＥＤアレイ１００に固着する。 Next, the details of the display panel forming step (step S8) will be described. FIG. 14 is an explanatory diagram showing a process of forming a display panel. In step S8, the LED array 100 and the phosphor cell array 10 are bonded and mounted by using a mounting device such as a flip chip bonder device. FIG. 14A shows a state in which the LED array 100 and the phosphor cell array 10 are bonded together. However, in FIG. 14, the fluorescent cell 10a, which is a constituent unit of the fluorescent cell array 10, is focused on. Then, in step S8, the flattening film 12 is heat-cured and the phosphor cell array 10 is fixed to the LED array 100 in the same manner as in the bonding of the wiring board and the sapphire substrate (step S4).
　続いて、工程Ｓ８では、レーザリフトオフ（工程Ｓ５）と同様にして、サファイア基板７ａから蛍光体セルアレイ１０をレーザリフトオフする（図１４（ｂ）参照）。 Subsequently, in step S8, the phosphor cell array 10 is laser lifted off from the sapphire substrate 7a in the same manner as in the laser lift-off (step S5) (see FIG. 14B).
　以上より、本実施形態では、配線基板１に複数のＬＥＤチップ３を実装する電子部品実装方法を採用したＬＥＤ表示パネルの製造方法を適用することにより、ＬＥＤチップ３等の電子部品の実装時の歩留りを向上させたＬＥＤ表示パネルを製造することができる。 From the above, in the present embodiment, by applying the manufacturing method of the LED display panel adopting the electronic component mounting method of mounting the plurality of LED chips 3 on the wiring board 1, the time of mounting the electronic component such as the LED chip 3 is applied. An LED display panel with improved yield can be manufactured.
　図１５は、従来技術におけるＬＥＤチップ実装の欠陥例を示す説明図である。図１５（ａ）は、サファイア基板７（図示省略）の一方の面上に形成されたＬＥＤチップ３を配線基板１上に実装する実装領域に位置付けた後、サファイア基板７（図示省略）の他方の面から圧力ＰでＬＥＤチップ３を加圧してＬＥＤチップ３の電極部８と配線基板１の電極１ｂとを接触させようとした場合を例示している。この場合、上述した加圧機構軸の走り精度や貼付け面の反り又は傾きに起因して、図１５（ｂ）に示すようにＬＥＤチップ３に回転ずれが生じてオープン欠陥となったり、図１５（ｃ）に示すように滑りが生じてショート欠陥となったりするおそれがあった。 FIG. 15 is an explanatory diagram showing an example of defects in LED chip mounting in the prior art. FIG. 15A shows the LED chip 3 formed on one surface of the sapphire substrate 7 (not shown) positioned in the mounting area for mounting on the wiring board 1, and then the other of the sapphire substrate 7 (not shown). The case where the LED chip 3 is pressurized by the pressure P from the surface of the above surface to bring the electrode portion 8 of the LED chip 3 into contact with the electrode 1b of the wiring board 1 is illustrated. In this case, due to the running accuracy of the pressurizing mechanism shaft and the warp or inclination of the sticking surface, the LED chip 3 may be rotationally displaced as shown in FIG. 15B, resulting in an open defect. As shown in (c), slippage may occur, resulting in a short defect.
　これに対し、本発明においては、ＬＥＤチップ３は、上述した構成により、ＬＥＤチップ３の窪み部３３にバンプ電極４が対面接合するようにしているので、配線基板１とＬＥＤチップ３との相対的な滑りや回転ずれを防止することができる。 On the other hand, in the present invention, the LED chip 3 has the bump electrode 4 face-to-face bonded to the recessed portion 33 of the LED chip 3 according to the above-described configuration, so that the wiring substrate 1 and the LED chip 3 are relative to each other. It is possible to prevent slippage and rotation deviation.
　図１６は、ＬＥＤチップ実装時の固着部材の弾性変形について示す説明図である。本発明においては、さらに、図１６（ａ）～（ｃ）に示すとおり、ＬＥＤチップ実装時において、ＬＥＤチップ３が、固着部材２の開口部５により案内されて固着部材２の開口部５内に侵入し、ＬＥＤチップ３の電極部３ａ、３ｂと配線基板１のバンプ電極４ａ、４ｂとが各々電気的に接触される。すなわち、ＬＥＤチップ３が配線基板１に対して位置決めされた後（図１６（ａ）参照）、ＬＥＤチップ３が圧力Ｐで加圧されると、固着部材２に圧力Ｐ１が作用する（図１６（ｂ）参照）。さらに、圧力Ｐ１の反力Ｐ２が作用することにより、ＬＥＤチップ３が固着部材２に把持される（図１６（ｃ）参照）。これにより、さらに位置ずれが起きにくい構造になっている。なお、図１６では、サファイア基板７の図示を省略している。 FIG. 16 is an explanatory diagram showing elastic deformation of the fixing member when the LED chip is mounted. Further, in the present invention, as shown in FIGS. 16A to 16C, when the LED chip is mounted, the LED chip 3 is guided by the opening 5 of the fixing member 2 and inside the opening 5 of the fixing member 2. The electrode portions 3a and 3b of the LED chip 3 and the bump electrodes 4a and 4b of the wiring substrate 1 are electrically contacted with each other. That is, after the LED chip 3 is positioned with respect to the wiring board 1 (see FIG. 16A), when the LED chip 3 is pressurized with the pressure P, the pressure P1 acts on the fixing member 2 (FIG. 16). See (b)). Further, the reaction force P2 of the pressure P1 acts to grip the LED chip 3 by the fixing member 2 (see FIG. 16C). As a result, the structure is such that misalignment is less likely to occur. In FIG. 16, the sapphire substrate 7 is not shown.
　以上より、本発明によれば、例えば、ＬＥＤチップ３の電極部３０の窪み部３３とバックプレーン電極として上記のバンプ電極４とを対面接合することにより、配線基板１とＬＥＤチップ３等の電子部品を形成したサファイア基板７との貼り合せ時における加圧による滑りや回転ずれ等の位置ずれを抑制することができる。これにより、確実な通電状態が得られることになる。 From the above, according to the present invention, for example, by face-to-face joining the recessed portion 33 of the electrode portion 30 of the LED chip 3 and the bump electrode 4 as a backplane electrode, the wiring board 1 and the electrons of the LED chip 3 and the like are electronically bonded. It is possible to suppress misalignment such as slippage and rotational misalignment due to pressurization during bonding with the sapphire substrate 7 on which the component is formed. As a result, a reliable energized state can be obtained.
　なお、上記実施形態においては、ＬＥＤチップ３が、紫外又は青色波長帯の光を放出するマイクロＬＥＤとして、単一色の紫外光発光ダイオード（ＵＶ－ＬＥＤ）を用いて、表示パネルを説明したが、本発明は、これに限られない。例えば、上記実施形態においてＬＥＤチップ３が、三原色光に対応する光を放出する三種類のマイクロＬＥＤの何れか１つであって、各色対応のマイクロＬＥＤが予め定められた配列に従って、配線基板１上に配置されているように表示パネルを構成してもよい。この場合、表示パネルは、赤（Ｒ）、緑（Ｇ）、青（Ｂ）の光を発光するＬＥＤチップ３が、フルカラー表示を実現可能に配線基板１上に配列されるため、図２に示すような、蛍光体セルアレイ１０を採用しないで済む。 In the above embodiment, the display panel has been described by using a single color ultraviolet light emitting diode (UV-LED) as a micro LED in which the LED chip 3 emits light in the ultraviolet or blue wavelength band. The present invention is not limited to this. For example, in the above embodiment, the LED chip 3 is one of three types of micro LEDs that emit light corresponding to the three primary color lights, and the micro LEDs corresponding to each color are arranged according to a predetermined arrangement. The display panel may be configured as arranged above. In this case, in the display panel, the LED chips 3 that emit red (R), green (G), and blue (B) lights are arranged on the wiring board 1 so as to realize full-color display. It is not necessary to adopt the phosphor cell array 10 as shown.
　上記実施形態においては、バンプ電極４は、金属バンプ電極を適用したが、導電性を有するレジストバンプ電極を用いて加圧した場合には、レジストバンプ電極が押し潰され、レジストバンプ電極と対応する電極部３０とが接続されるように構成してもよい。その結果、レジストバンプ電極が押し潰された状態で、固着部材２が硬化し、両基板が接合されるので、良好な電気的な接続が維持されることとなる。 In the above embodiment, the metal bump electrode is applied to the bump electrode 4, but when the resist bump electrode is pressurized by using the conductive resist bump electrode, the resist bump electrode is crushed and corresponds to the resist bump electrode. It may be configured so that it is connected to the electrode portion 30. As a result, in a state where the resist bump electrode is crushed, the fixing member 2 is cured and both substrates are joined, so that a good electrical connection is maintained.
　上記実施形態においては、電子部品がＬＥＤチップ３である場合について述べたが、本発明はこれに限られず、電子部品は、チップ状のものであれば、ＩＣチップ等であってもよい。 In the above embodiment, the case where the electronic component is the LED chip 3 has been described, but the present invention is not limited to this, and the electronic component may be an IC chip or the like as long as it is in the form of a chip.
　上記実施形態においては、電子部品実装構造として、複数の電子部品を配線基板に実装した場合について、説明したが、電子部品が１つの場合にも本発明は適用可能である。また、上記実施形態においては、電子部品実装方法として、複数の電子部品を配線基板に実装する場合について適用したが、電子部品が１つの場合にも本発明は適用可能である。 In the above embodiment, the case where a plurality of electronic components are mounted on the wiring board as the electronic component mounting structure has been described, but the present invention can be applied even when there is one electronic component. Further, in the above embodiment, as an electronic component mounting method, a case where a plurality of electronic components are mounted on a wiring board is applied, but the present invention can be applied even when there is one electronic component.
　１…配線基板
　２…固着部材
　３…ＬＥＤチップ（電子部品）
　３ａ、３ｂ、３０…電極部
　４、４ａ、４ｂ…バンプ電極
　６…感光性熱硬化型接着剤
　７…サファイア基板（透明基板）
　１１…蛍光発光層
　３０ａ、３０ｂ、３３…窪み部 1 ... Wiring board 2 ... Fixed member 3 ... LED chip (electronic component)
3a, 3b, 30 ... Electrodes 4, 4a, 4b ... Bump electrodes 6 ... Photosensitive thermosetting adhesive 7 ... Sapphire substrate (transparent substrate)
11 ... Fluorescent light emitting layer 30a, 30b, 33 ... Recessed portion

Claims (13)

  1. 　配線基板の一方の面上にチップ型の電子部品を実装する電子部品実装構造であって、
    　前記電子部品は、表面に窪み部を有する一対の電極部を備え、
    　前記配線基板は、前記電極部の窪み部に接続する突状のバンプ電極と、該バンプ電極の配置に応じて位置が定められ、前記電子部品を固着する固着部材と、を備え、
    　前記電極部の窪み部に前記バンプ電極が対面接合すると共に、前記固着部材により前記電子部品を前記配線基板に固着することを特徴とする電子部品実装構造。     It is an electronic component mounting structure in which chip-type electronic components are mounted on one surface of a wiring board.
    The electronic component includes a pair of electrode portions having recesses on the surface thereof.
    The wiring board includes a protruding bump electrode connected to a recessed portion of the electrode portion, and a fixing member whose position is determined according to the arrangement of the bump electrode and which fixes the electronic component.
    An electronic component mounting structure characterized in that the bump electrode is face-to-face bonded to a recessed portion of the electrode portion and the electronic component is fixed to the wiring board by the fixing member.
  2. 　前記固着部材は、弾性変形により前記電子部品を支持する樹脂であって、前記電極部の窪み部を前記バンプ電極に誘導して対面接合させることを特徴とする請求項１に記載の電子部品実装構造。 The electronic component mounting according to claim 1, wherein the fixing member is a resin that supports the electronic component by elastic deformation, and the recessed portion of the electrode portion is guided to the bump electrode to be face-to-face bonded. Construction.
  3. 　前記固着部材は、前記樹脂が感光性熱硬化型接着剤であって、感光性を有することによりパターニングして形成されたものであり、前記配線基板の前記バンプ電極を囲む領域に設けられており、熱硬化により前記電子部品を前記配線基板に固着させることを特徴とする請求項２に記載の電子部品実装構造。 The fixing member is formed by patterning the resin as a photosensitive thermosetting adhesive and having photosensitivity, and is provided in a region surrounding the bump electrode of the wiring board. The electronic component mounting structure according to claim 2, wherein the electronic component is fixed to the wiring board by thermosetting.
  4. 　前記バンプ電極は、金属バンプ電極、ソルダーバンプ電極、金属膜が積層されたレジストバンプ電極の何れかであることを特徴とする請求項１～３の何れか１項に記載の電子部品実装構造。 The electronic component mounting structure according to any one of claims 1 to 3, wherein the bump electrode is any one of a metal bump electrode, a solder bump electrode, and a resist bump electrode on which a metal film is laminated.
  5. 　前記電子部品は、ＬＥＤチップであることを特徴とする請求項１～３の何れか１項に記載の電子部品実装構造。 The electronic component mounting structure according to any one of claims 1 to 3, wherein the electronic component is an LED chip.
  6. 　配線基板の一方の面上にチップ型の電子部品を実装する電子部品実装方法であって、
    　前記電子部品に設けられた一対の電極部の表面に窪み部が形成され、一方の面上に前記電子部品が形成された透明基板と、前記電極部の窪み部に接続する突状のバンプ電極及び該バンプ電極の配置に応じて位置が定められ、前記電子部品を固着する固着部材を一方の面上に備えた前記配線基板とを、貼り合せるために位置決めする工程と、
    　前記透明基板の他方の面から押すことにより、前記電子部品を前記配線基板に対して加圧し、前記電極部の窪み部と前記配線基板のバンプ電極とを導通可能に対面接合させる工程と、
    　前記固着部材を熱硬化させることにより、前記配線基板に前記電子部品を固着する工程と、
    　前記透明基板から前記電子部品を剥離する工程と、
    を含むことを特徴とする電子部品実装方法。     This is an electronic component mounting method in which chip-type electronic components are mounted on one surface of a wiring board.
    A transparent substrate in which a recess is formed on the surface of a pair of electrode portions provided on the electronic component and the electronic component is formed on one surface, and a protruding bump electrode connected to the recessed portion of the electrode portion. A step of positioning the wiring board, which is positioned according to the arrangement of the bump electrodes and has a fixing member for fixing the electronic component on one surface, for bonding.
    A step of pressurizing the electronic component against the wiring board by pushing from the other surface of the transparent substrate, and conducting face-to-face bonding between the recessed portion of the electrode portion and the bump electrode of the wiring board.
    A step of fixing the electronic component to the wiring board by thermosetting the fixing member, and
    The step of peeling the electronic component from the transparent substrate and
    A method for mounting an electronic component, which comprises.
  7. 　前記固着部材は、弾性変形により前記電子部品を支持する樹脂であって、前記電極部の窪み部を前記バンプ電極に誘導して対面接合させることを特徴とする請求項６に記載の電子部品実装方法。 The electronic component mounting according to claim 6, wherein the fixing member is a resin that supports the electronic component by elastic deformation, and the recessed portion of the electrode portion is guided to the bump electrode to be face-to-face bonded. Method.
  8. 　前記固着部材は、前記樹脂が感光性熱硬化型接着剤であって、感光性を有することによりパターニングして形成されるものであり、前記配線基板の前記バンプ電極を囲む領域に設けられており、熱硬化により前記電子部品を前記配線基板に固着させることを特徴とする請求項７に記載の電子部品実装方法。 The fixing member is formed by patterning the resin because the resin is a photosensitive thermosetting adhesive and has photosensitivity, and is provided in a region surrounding the bump electrode of the wiring board. The method for mounting an electronic component according to claim 7, wherein the electronic component is fixed to the wiring board by thermosetting.
  9. 　前記バンプ電極は、金属バンプ電極、ソルダーバンプ電極、金属膜が積層されたレジストバンプ電極の何れかであることを特徴とする請求項６～８の何れか１項に記載の電子部品実装方法。 The electronic component mounting method according to any one of claims 6 to 8, wherein the bump electrode is any one of a metal bump electrode, a solder bump electrode, and a resist bump electrode on which a metal film is laminated.
  10. 　前記電子部品は、ＬＥＤチップであることを特徴とする請求項６～８の何れか１項に記載の電子部品実装方法。 The electronic component mounting method according to any one of claims 6 to 8, wherein the electronic component is an LED chip.
  11. 　配線基板の一方の面上に複数のＬＥＤチップを実装したＬＥＤ表示パネルであって、
    　前記ＬＥＤチップは、前記配線基板の一方の面上に行列状に形成され、表面に窪み部を有する一対の電極部を備え、
    　前記配線基板は、前記電極部の窪み部に接続する突状のバンプ電極と、該バンプ電極の配置に応じて位置が定められ、前記ＬＥＤチップを固着させる固着部材と、を備え、
    　前記電極部の窪み部に前記バンプ電極が対面接合すると共に、前記固着部材により前記ＬＥＤチップを前記配線基板に固着することを特徴とするＬＥＤ表示パネル。     An LED display panel in which a plurality of LED chips are mounted on one surface of a wiring board.
    The LED chip is formed in a matrix on one surface of the wiring board, and includes a pair of electrode portions having recesses on the surface.
    The wiring board includes a protruding bump electrode connected to a recessed portion of the electrode portion, and a fixing member whose position is determined according to the arrangement of the bump electrode and which fixes the LED chip.
    An LED display panel characterized in that the bump electrode is face-to-face bonded to a recessed portion of the electrode portion and the LED chip is fixed to the wiring board by the fixing member.
  12. 　前記ＬＥＤチップが、紫外又は青色波長帯の光を放出するマイクロＬＥＤであって、
    　各前記ＬＥＤチップの光放出面側には、前記紫外又は青色波長帯の光を予め定められた対応色に各々変換するＲＧＢ蛍光体を有する蛍光発光層が設けられていることを特徴とする請求項１１に記載のＬＥＤ表示パネル。     The LED chip is a micro LED that emits light in the ultraviolet or blue wavelength band.
    A claim characterized in that a fluorescent light emitting layer having an RGB phosphor that converts light in the ultraviolet or blue wavelength band into a predetermined corresponding color is provided on the light emitting surface side of each LED chip. Item 11. The LED display panel according to Item 11.
  13. 　前記ＬＥＤチップが、三原色光に対応する光を放出する三種類のマイクロＬＥＤの何れか１つであって、各色対応の前記マイクロＬＥＤが予め定められた配列に従って、前記配線基板上に配置されていることを特徴とする請求項１１に記載のＬＥＤ表示パネル。 The LED chip is one of three types of micro LEDs that emit light corresponding to the three primary color lights, and the micro LEDs corresponding to each color are arranged on the wiring board according to a predetermined arrangement. The LED display panel according to claim 11, wherein the LED display panel is provided.
PCT/JP2020/023622 2019-07-18 2020-06-16 Electronic component mounting structure, electronic component mounting method, and led display panel WO2021010079A1 (en)

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