WO2021002200A1 - Circuit board and circuit board module - Google Patents

Circuit board and circuit board module Download PDF

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Publication number
WO2021002200A1
WO2021002200A1 PCT/JP2020/023799 JP2020023799W WO2021002200A1 WO 2021002200 A1 WO2021002200 A1 WO 2021002200A1 JP 2020023799 W JP2020023799 W JP 2020023799W WO 2021002200 A1 WO2021002200 A1 WO 2021002200A1
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WO
WIPO (PCT)
Prior art keywords
circuit
layer
circuit board
drive
wiring
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Application number
PCT/JP2020/023799
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French (fr)
Japanese (ja)
Inventor
セルゲイ モイセエフ
直毅 加藤
伊藤 賢
佳孝 岩田
田中 克典
Original Assignee
株式会社豊田自動織機
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Application filed by 株式会社豊田自動織機 filed Critical 株式会社豊田自動織機
Publication of WO2021002200A1 publication Critical patent/WO2021002200A1/en

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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details

Definitions

  • This disclosure relates to circuit boards and circuit board modules.
  • Patent Document 1 discloses a circuit board in which a plurality of layers having a circuit are stacked.
  • a first layer having a power circuit and a second layer having a control circuit are overlapped.
  • the power circuit includes a power element.
  • the control circuit includes a control element that controls the power element.
  • An object of the present disclosure is to provide a circuit board and a circuit board module capable of reducing the influence of magnetic flux.
  • the circuit board includes a first layer having a first circuit and a second layer having a second circuit different from the first circuit, and the first layer.
  • the layer and the second layer are arranged so as to overlap each other, and the second circuit is viewed from the stacking direction in which the first layer and the second layer overlap each other.
  • the second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the circuit, and the current generated in the overlapping portion due to the magnetic flux generated by the current flowing through the wiring of the first circuit is the allowable value. It is arranged so as to be.
  • the circuit board module includes a first circuit board having a first circuit and a second circuit board having a second circuit different from the first circuit.
  • the first circuit board and the second circuit board are arranged so as to overlap each other, and the second circuit is from the stacking direction in which the first circuit board and the second circuit board overlap each other.
  • the second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the first circuit, and the second circuit has the overlapping portion due to the magnetic flux generated by the current flowing through the wiring of the first circuit. It is arranged so that the current generated in is an allowable value.
  • FIG. 1 Schematic diagram of the motor and the motor drive device.
  • the schematic block diagram of the drive circuit included in the motor drive device of FIG. The perspective view which shows typically the circuit board.
  • the motor drive device 10 is a device for driving the motor 11.
  • the motor 11 of the present embodiment is a three-phase AC motor including three coils U, V, and W.
  • the motor drive device 10 includes a battery BA, a smoothing capacitor C, a control device 12, an inverter circuit 21 which is a first circuit, and a drive circuit D which is a second circuit.
  • the inverter circuit 21 includes a conversion unit 22 and output wirings 23, 24, and 25, which are wirings for the first circuit.
  • the conversion unit 22 includes six switching elements Q1 to Q6, which are power elements.
  • the switching element Q1 forming the U-phase upper arm and the switching element Q2 forming the U-phase lower arm are connected in series with each other.
  • the switching element Q3 constituting the V-phase upper arm and the switching element Q4 constituting the V-phase lower arm are connected in series with each other.
  • the switching element Q5 forming the W phase upper arm and the switching element Q6 forming the W phase lower arm are connected in series with each other.
  • Output wirings 23, 24, and 25 are connected to the connection points of the upper arm switching elements Q1, Q3, and Q5 and the corresponding lower arm switching elements Q2, Q4, and Q6 for each phase.
  • the output wirings 23, 24, and 25 are connected to the motor 11.
  • a battery BA is connected to the switching elements Q1 to Q6 via a smoothing capacitor C.
  • the conversion unit 22 converts the DC power of the battery BA into AC power.
  • the output wirings 23, 24, and 25 output the AC power output from the conversion unit 22 to the motor 11. As a result, the motor 11 is driven.
  • the inverter circuit 21 is a power circuit that performs power conversion.
  • the control device 12 is mainly composed of, for example, a microcomputer.
  • the process executed by the control device 12 may be performed by the CPU executing the program stored in the storage unit, or may be performed through the hardware process executed by the dedicated electronic circuit.
  • the control device 12 controls the motor 11 via the inverter circuit 21 by performing current feedback control using a vector control method based on, for example, the target torque of the motor 11 requested by another control device or the like.
  • the control device 12 outputs a control signal for controlling the switching elements Q1 to Q6 to the drive circuit D.
  • the drive circuit D controls the switching elements Q1 to Q6 according to the control signal.
  • each drive circuit D is individually provided for each of the switching elements Q1 to Q6. As shown in FIG. 2, each drive circuit D includes a first drive switching element T1, a second drive switching element T2, two resistance elements R1 and R2, a drive capacitor C1, and a gate resistor. It includes R3, two connection resistors R4 and R5, and two connection capacitors C2 and C3.
  • the first drive switching element T1 for example, an NPN type transistor is used.
  • the second drive switching element T2 for example, a PNP type transistor is used.
  • the two drive switching elements T1 and T2 and the two resistance elements R1 and R2 are connected in series with each other.
  • the emitter of the first drive switching element T1 and the emitter of the second drive switching element T2 are connected to each other.
  • the first end of the resistance element R1 is connected to the collector of the first drive switching element T1.
  • the first end of the resistance element R2 is connected to the collector of the second drive switching element T2.
  • the collector of the second drive switching element T2 is grounded via the resistance element R2.
  • the drive switching elements T1 and T2 and the resistance elements R1 and R2 form a series connection.
  • the drive capacitor C1 is connected in parallel to a series connector composed of drive switching elements T1 and T2 and resistance elements R1 and R2.
  • the first end of the drive capacitor C1 is connected to the second end of the resistance element R1.
  • the second end of the drive capacitor C1 is connected to the second end of the resistance element R2. Therefore, the drive switching elements T1 and T2, the resistance elements R1 and R2, and the drive capacitor C1 constituting the series connection form a closed circuit 31.
  • the connection points of the two drive switching elements T1 and T2 are connected to one end of the gate resistor R3.
  • the other end of the gate resistor R3 is connected to any of the gates of the switching elements Q1 to Q6.
  • the base of the first drive switching element T1 and the base of the second drive switching element T2 are connected to the control device 12 via a resistor.
  • connection resistor R4 and the connection capacitor C2 are connected in parallel to each other.
  • the first end of the connection resistor R4 is connected to the base of the drive switching element T1.
  • the second end of the connection resistor R4 is connected to the second end of the resistor element R1 and the first end of the drive capacitor C1.
  • connection capacitor C2 The first end of the connection capacitor C2 is connected to the base of the drive switching element T1.
  • the second end of the connection capacitor C2 is connected to the second end of the resistance element R1 and the first end of the drive capacitor C1. That is, the closed circuit 33 is formed by the resistance element R1, the connection capacitor C2, and the first drive switching element T1, and the closed circuit 34 is formed by the resistance element R1, the connection resistor R4, and the first drive switching element T1. Will be done.
  • connection resistor R5 and the connection capacitor C3 are connected in parallel to each other.
  • the first end of the connection resistor R5 is connected to the base of the drive switching element T2.
  • the second end of the connection resistor R5 is connected to the second end of the resistor element R2 and the second end of the drive capacitor C1.
  • connection capacitor C3 The first end of the connection capacitor C3 is connected to the base of the drive switching element T2.
  • the second end of the connection capacitor C3 is connected to the second end of the resistance element R2 and the second end of the drive capacitor C1. That is, the closed circuit 35 is formed by the resistance element R2, the connection capacitor C3, and the second drive switching element T2, and the closed circuit 36 is formed by the resistance element R2, the connection resistor R5, and the second drive switching element T2. Will be done.
  • the drive circuit D configured as described above switches the switching elements Q1 to Q6 on and off by the operation of the two drive switching elements T1 and T2.
  • the two drive switching elements T1 and T2 are control elements that control the switching elements Q1 to Q6.
  • the drive circuit D is a control circuit.
  • the drive circuit D is driven by a power supply from a power supply circuit that generates electric power to drive the drive circuit D.
  • the drive circuit D amplifies the control signal from the control device 12, and outputs the control signal as a drive signal to the gates of the corresponding switching elements Q1 to Q6.
  • the upper arm switching elements Q1, Q3 and Q5 and the lower arm switching elements Q2, Q4 and Q6 are alternately turned on.
  • the circuit board 20 includes a first layer 26 having an inverter circuit 21 and a second layer 32 having a drive circuit D.
  • the first layer 26 and the second layer 32 are arranged so as to overlap each other.
  • the "state in which the first layer 26 and the second layer 32 are arranged in an overlapping manner" is a state in which the first layer 26 and the second layer 32 are arranged in contact with each other.
  • the first layer 26 and the second layer 32 may be arranged so as to be separated from each other and face each other. That is, "a state in which the first layer 26 and the second layer 32 are arranged so as to overlap each other" means that the first layer 26 and the second layer 32 are arranged so as to be in contact with or separated from each other.
  • the circuit board 20 is a multilayer board in which a plurality of insulating layers are laminated, and the first layer 26 and the second layer 32 are insulating layers.
  • the output wirings 23, 24, and 25 are bus bars connected to the conversion unit 22. That is, the output wirings 23, 24, and 25 are wide wirings in which the width direction is longer than the thickness direction. Assuming that the overlapping direction of the first layer 26 and the second layer 32 is the stacking direction, the thickness direction of the output wirings 23, 24, 25 and the stacking direction are the same direction.
  • each drive circuit D is arranged so as to be overlapped with any of the output wirings 23, 24, and 25 when viewed from the stacking direction. That is, each drive circuit D is arranged so as to have an overlapping portion that overlaps any of the output wirings 23, 24, and 25 when viewed from the stacking direction.
  • the drive circuit D arranged so as to overlap the output wiring 25 among the six drive circuits D corresponding to the six switching elements Q1 to Q6 will be described, but each of the drive circuits D will be described. It overlaps with any of the three output wirings 23, 24, and 25 when viewed from the stacking direction.
  • two drive circuits D for driving U-phase switching elements Q1 and Q2 are arranged so as to overlap the U-phase output wiring 23, and the drive circuits D of each phase are arranged on the same-phase output wirings 23, 24, 25. It may be arranged in layers. Further, all the drive circuits D may be arranged so as to overlap one of the three output wirings 23, 24, 25.
  • the entire closed circuit 31 of the drive circuit D when viewed from the stacking direction, is arranged so as to overlap the output wiring 25.
  • the closed circuit 31 is an overlapping portion.
  • the closed circuit 31 will be described as a square frame-shaped wiring for convenience of explanation.
  • the drive circuit D When a current flows through the output wiring 25, a magnetic flux is generated in the direction according to the right-handed screw rule. As a result, an induced voltage due to electromagnetic induction is generated in the drive circuit D, and a current flows through the drive circuit D.
  • the drive circuit D is arranged so that the current induced in the drive circuit D due to the current flowing through the output wiring 25 becomes an allowable value.
  • the magnetic flux generated by the current flowing through the output wiring 25 is represented by the magnetic flux line L. In FIG. 6, only one magnetic flux line L is shown, but when the magnetic flux actually generated is represented by the magnetic flux line L, the magnetic flux lines L are plural.
  • a current flows through the drive circuit D due to the induced voltage caused by the magnetic flux.
  • the induced voltage V generated in the planar circuit having an area S can be expressed by the following equation (1).
  • is the angle formed by the plane of the planar circuit and the virtual line extending in the direction orthogonal to the direction of the magnetic flux.
  • the induced voltage V generated in the closed circuit 31 by the current flowing through the output wiring 25 can be expressed by the following equation (2).
  • first position P1 One of the positions where the magnetic flux interlinking twice in the closed circuit 31 passes through the closed circuit 31 is set as the first position P1, and the position where the magnetic flux interlinking twice in the closed circuit 31 passes through the closed circuit 31.
  • the position different from the first position P1 is referred to as the second position P2.
  • ⁇ 1 is an angle formed by the virtual line L1 orthogonal to the direction of the magnetic flux passing through the first position P1 and the virtual surface VS including the entire closed circuit 31.
  • ⁇ 2 is the angle between the virtual line L2 orthogonal to the direction of the magnetic flux passing through the second position P2 and the virtual surface VS including the entire closed circuit 31.
  • the virtual surface VS including the entire closed circuit 31 is a surface including all the wirings constituting the outer frame of the closed circuit 31. It can be said that the width direction of the output wiring 25 is orthogonal to the direction of the current flowing through the output wiring 25 and the thickness direction of the output wiring 25.
  • the shape of the wiring forming the closed circuit 31 has been described as a square frame shape, but even if the shape of the wiring forming the closed circuit 31 is not a square frame shape, the inside of the closed circuit 31 is twice. If the closed circuit 31 and the output wiring 25 are provided so as to overlap each other so that the magnetic flux interlinking exists, the induced voltage generated in the closed circuit 31 becomes low. Therefore, the value of the current generated in the closed circuit 31 is low regardless of the shape of the wiring forming the closed circuit 31.
  • the current generated in the drive circuit D due to the magnetic flux changes according to the positional relationship between the output wirings 23, 24, 25 and the drive circuit D. Therefore, by adjusting the positional relationship between the output wirings 23, 24, 25 and the drive circuit D, the current generated in the drive circuit D due to the magnetic flux from the output wirings 23, 24, 25 can be set as an allowable value.
  • the permissible value differs depending on the type of the second circuit.
  • the allowable value is set so that the drive switching elements T1 and T2 do not operate unintentionally due to the current generated in the drive circuit D by the magnetic flux.
  • the closed circuit 31 and the bases of the driving switching elements T1 and T2 are connected via connection resistors R4 and R5 and connection capacitors C2 and C3.
  • the driving switching elements T1 and T2 may be unintentionally turned on by a current flowing between the base and the emitter of the driving switching elements T1 and T2. If the drive switching elements T1 and T2 perform an unintended operation, the switching elements Q1 to Q6 are erroneously switched on and off.
  • the switching elements Q1 to Q6 are switched on and off by the current flowing through the closed circuit 31 including the driving switching elements T1 and T2.
  • the positional relationship between the drive circuit D and the output wirings 23, 24, 25 may be adjusted in consideration of the current flowing through the closed circuit 31.
  • the induced voltage generated in the closed circuit 31 is generated as can be grasped from the equation (1). It gets higher. Since the current flowing through the closed circuit 31 becomes large due to the magnetic flux, the switching elements Q1 to Q6 may be erroneously switched on and off. On the other hand, in the embodiment, the induced voltage generated in the closed circuit 31 is lowered so that the current generated in the drive circuit D due to the magnetic flux becomes an allowable value.
  • the first circuit and the second circuit may be mounted on a circuit board module having a plurality of circuit boards instead of the circuit board 20.
  • the circuit board module includes a first circuit board having a first circuit and a second circuit board having a second circuit different from the first circuit.
  • As the first circuit for example, an inverter circuit 21 can be used.
  • As the second circuit for example, a drive circuit D can be used.
  • the first circuit board is an insulating board on which the first circuit is mounted.
  • the second circuit board is an insulating board on which the second circuit is mounted.
  • the first circuit board and the second circuit board are arranged at intervals from each other.
  • the first circuit board and the second circuit board are arranged so as to be overlapped in the stacking direction (in other words, to face the stacking direction).
  • the first layer 26 and the second layer 32 can be regarded as insulating boards, respectively, and the two insulating boards are regarded as each other. Arranged at intervals.
  • the second circuit is arranged so as to overlap the wiring of the first circuit at least partially when viewed from the direction in which the first circuit board and the second circuit board overlap. That is, the second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the first circuit when viewed from the direction in which the first circuit board and the second circuit board overlap.
  • the second circuit is arranged so that the current generated in the overlapping portion due to the magnetic flux generated by the current flowing through the wiring of the first circuit becomes an allowable value.
  • the first circuit may be other than the power circuit.
  • the first circuit may be a circuit on which an element such as a smoothing capacitor C is mounted.
  • the second circuit may be an arithmetic circuit used for the sensor.
  • the arithmetic circuit may be used for a current sensor.
  • the current sensor includes a shunt resistor and an arithmetic circuit.
  • the arithmetic circuit calculates the value of the current flowing through the detection target from the current flowing through the shunt resistor and the voltage across the shunt resistor.
  • an error may occur in the detection result of the sensor due to the current generated by the magnetic flux.
  • the permissible value of the current generated by the magnetic flux is set within the range of the error permissible as the detection result of the sensor.
  • the arithmetic circuit may be arranged so that the value of the current generated in the arithmetic circuit due to the magnetic flux becomes a value allowed by the sensor and the mounting target.
  • the power circuit may be any one that converts electric power, and may be, for example, a converter circuit used in a DC / DC converter.
  • Examples of the power element included in the power circuit include a diode and a thyristor in addition to the switching element.
  • the second circuit 40 includes a first portion 41 which is an overlapping portion overlapping the output wiring 25 and a second portion 42 which does not overlap the output wiring 25 when viewed from the stacking direction. , May be provided.
  • the current generated by the magnetic flux tends to be larger in the second portion 42 than in the first portion 41.
  • a capacitor 43 is connected to the connection wiring 44 that interconnects the first portion 41 and the second portion 42 in order to suppress the current generated in the second portion 42 from flowing to the first portion 41. ..
  • the capacitor 43 is connected in parallel to the first portion 41 and the second portion 42. The capacitor 43 overlaps the output wiring 25 when viewed from the stacking direction.
  • the second circuit 40 may be arranged so that the current generated in the first portion 41 by the magnetic flux becomes an allowable value.
  • the first portion 41 may be arranged so that the current generated in the first portion 41 due to the magnetic flux becomes an allowable value.
  • a part of the closed circuit 31 does not have to overlap with the output wiring 25 when viewed from the stacking direction.
  • the second circuit does not have to be a closed circuit.
  • the drive circuit D is arranged so that the current flowing in at least one of the closed circuits 33, 34, 35, 36 due to the magnetic flux generated by the current flowing in the output wirings 23, 24, 25 becomes an allowable value. May be good. That is, in the case of a closed circuit in which the driving switching elements T1 and T2 may perform unintended operations due to the flow of the current generated by the magnetic flux, the current flowing in at least one of the closed circuits shall be an allowable value.
  • the drive circuit D may be arranged.
  • the wiring of the first circuit does not have to be the output wirings 23, 24, 25, and the wiring for input for inputting the power from the battery BA to the inverter circuit 21 and the pattern wiring constituting the inverter circuit 21 are instantaneous. Any wiring may be used as long as the wiring allows current to flow in one direction.
  • the virtual surface VS including the entire closed circuit 31 may be arranged so as to be inclined with respect to the surfaces of the output wirings 23 to 25 facing the virtual surface VS including the entire closed circuit 31.
  • a shield layer may be provided between the first layer 26 and the second layer 32.
  • the shield layer can be made thinner by reducing the current generated in the drive circuit D due to the magnetic flux by setting the arrangement relationship between the drive circuit D and the output wirings 23, 24, 25.
  • the circuit board 20 may include at least a first layer 26 and a second layer 32, and may include three or more layers.
  • the drive circuit D may include one of the connection resistor R4 and the connection capacitor C2.
  • the drive circuit D may include one of the connection resistor R5 and the connection capacitor C3.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Inverter Devices (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

This circuit board comprises a first layer having a first circuit and a second layer having a second circuit that is different from the first circuit. The first layer and the second layer are arranged to overlap each other. The second circuit is disposed to have an overlapping part that overlaps wiring of the first circuit when viewed from a lamination direction that is a direction in which the first layer and the second layer overlap each other. The second circuit is disposed such that a current generated in the overlapping part due to a magnetic flux caused by the current flowing in the wiring of the first circuit has an allowable value.

Description

回路基板及び回路基板モジュールCircuit board and circuit board module
 本開示は、回路基板及び回路基板モジュールに関する。 This disclosure relates to circuit boards and circuit board modules.
 回路を有する層を複数重ねた回路基板が、例えば特許文献1に開示されている。特許文献1に開示された回路基板では、パワー回路を有する第1の層と、制御回路を有する第2の層とが重ねられている。パワー回路は、パワー素子を備える。制御回路は、パワー素子を制御する制御素子を備える。 For example, Patent Document 1 discloses a circuit board in which a plurality of layers having a circuit are stacked. In the circuit board disclosed in Patent Document 1, a first layer having a power circuit and a second layer having a control circuit are overlapped. The power circuit includes a power element. The control circuit includes a control element that controls the power element.
特開2016-225656号公報Japanese Unexamined Patent Publication No. 2016-225656
 回路に電流が流れると、磁束が生じる。回路を有する層を複数重ねた場合、各回路を流れる電流によって生じた磁束が他の回路に電流を誘起させ得る。すると、磁束により誘起された電流によって不具合が生じる場合がある。例えば、特許文献1のように、パワー回路を有する第1の層と、制御回路を有する第2の層とが重ねられている場合、パワー回路に流れる電流によって生じる磁束を原因として、制御素子が意図しない動作を行う場合がある。 When a current flows through the circuit, magnetic flux is generated. When a plurality of layers having circuits are stacked, the magnetic flux generated by the current flowing through each circuit can induce a current in another circuit. Then, a problem may occur due to the current induced by the magnetic flux. For example, when the first layer having a power circuit and the second layer having a control circuit are overlapped as in Patent Document 1, the control element causes the magnetic flux generated by the current flowing in the power circuit. It may perform unintended operation.
 本開示の目的は、磁束の影響を低減することができる回路基板及び回路基板モジュールを提供することにある。 An object of the present disclosure is to provide a circuit board and a circuit board module capable of reducing the influence of magnetic flux.
 本開示の一態様に係る回路基板は、第1の回路を有する第1の層と、前記第1の回路とは異なる第2の回路を有する第2の層と、を備え、前記第1の層と前記第2の層とは重ねて配置されており、前記第2の回路は、前記第1の層と前記第2の層とが重なる方向である積層方向から見て、前記第1の回路の配線と重なる重なり部分を有するように配置されており、前記第2の回路は、前記第1の回路の配線に流れる電流によって生じる磁束に起因して前記重なり部分に生じる電流が許容値となるように配置されている。 The circuit board according to one aspect of the present disclosure includes a first layer having a first circuit and a second layer having a second circuit different from the first circuit, and the first layer. The layer and the second layer are arranged so as to overlap each other, and the second circuit is viewed from the stacking direction in which the first layer and the second layer overlap each other. The second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the circuit, and the current generated in the overlapping portion due to the magnetic flux generated by the current flowing through the wiring of the first circuit is the allowable value. It is arranged so as to be.
 本開示の一態様に係る回路基板モジュールは、第1の回路を有する第1の回路基板と、前記第1の回路とは異なる第2の回路を有する第2の回路基板と、を備え、前記第1の回路基板と前記第2の回路基板とは重ねて配置されており、前記第2の回路は、前記第1の回路基板と前記第2の回路基板とが重なる方向である積層方向から見て、前記第1の回路の配線と重なる重なり部分を有するように配置されており、前記第2の回路は、前記第1の回路の配線に流れる電流によって生じる磁束に起因して前記重なり部分に生じる電流が許容値となるように配置されている。 The circuit board module according to one aspect of the present disclosure includes a first circuit board having a first circuit and a second circuit board having a second circuit different from the first circuit. The first circuit board and the second circuit board are arranged so as to overlap each other, and the second circuit is from the stacking direction in which the first circuit board and the second circuit board overlap each other. As seen, the second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the first circuit, and the second circuit has the overlapping portion due to the magnetic flux generated by the current flowing through the wiring of the first circuit. It is arranged so that the current generated in is an allowable value.
モータ及びモータ駆動装置の概略構成図。Schematic diagram of the motor and the motor drive device. 図1のモータ駆動装置が備えるドライブ回路の概略構成図。The schematic block diagram of the drive circuit included in the motor drive device of FIG. 回路基板を模式的に示す斜視図。The perspective view which shows typically the circuit board. 出力配線と閉回路との位置関係を示す斜視図。The perspective view which shows the positional relationship between the output wiring and a closed circuit. 出力配線と閉回路との位置関係を示す平面図。A plan view showing the positional relationship between the output wiring and the closed circuit. 閉回路と出力配線に電流が流れることで生じる磁束との関係を説明するための図。The figure for demonstrating the relationship between the closed circuit and the magnetic flux generated by the current flowing through the output wiring. 比較例の回路基板を示す図。The figure which shows the circuit board of the comparative example. 変形例における第2の回路を模式的に示す図。The figure which shows typically the 2nd circuit in the modification.
 以下、回路基板の一実施形態について説明する。 Hereinafter, one embodiment of the circuit board will be described.
 図1に示すように、モータ駆動装置10は、モータ11を駆動するための装置である。本実施形態のモータ11は、3つのコイルU,V,Wを備える3相交流モータである。モータ駆動装置10は、バッテリBAと、平滑コンデンサCと、制御装置12と、第1の回路であるインバータ回路21と、第2の回路であるドライブ回路Dと、を備える。 As shown in FIG. 1, the motor drive device 10 is a device for driving the motor 11. The motor 11 of the present embodiment is a three-phase AC motor including three coils U, V, and W. The motor drive device 10 includes a battery BA, a smoothing capacitor C, a control device 12, an inverter circuit 21 which is a first circuit, and a drive circuit D which is a second circuit.
 インバータ回路21は、変換部22と、第1の回路の配線である出力配線23,24,25と、を備える。変換部22は、パワー素子である6つのスイッチング素子Q1~Q6を備える。スイッチング素子Q1~Q6としては、例えば、IGBT(絶縁ゲートバイポーラトランジスタ)或いはMOSFETが用いられる。U相上アームを構成するスイッチング素子Q1と、U相下アームを構成するスイッチング素子Q2とは互いに直列接続されている。V相上アームを構成するスイッチング素子Q3と、V相下アームを構成するスイッチング素子Q4とは互いに直列接続されている。W相上アームを構成するスイッチング素子Q5と、W相下アームを構成するスイッチング素子Q6とは互いに直列接続されている。各上アームスイッチング素子Q1,Q3,Q5と、それに対応する下アームスイッチング素子Q2,Q4,Q6との接続点には、相毎に出力配線23,24,25が接続されている。出力配線23,24,25は、モータ11に接続されている。スイッチング素子Q1~Q6には、平滑コンデンサCを介してバッテリBAが接続されている。変換部22は、バッテリBAの直流電力を交流電力に変換する。出力配線23,24,25は、変換部22から出力される交流電力をモータ11に出力する。これにより、モータ11は駆動する。インバータ回路21は、電力変換を行うパワー回路である。 The inverter circuit 21 includes a conversion unit 22 and output wirings 23, 24, and 25, which are wirings for the first circuit. The conversion unit 22 includes six switching elements Q1 to Q6, which are power elements. As the switching elements Q1 to Q6, for example, IGBTs (insulated gate bipolar transistors) or MOSFETs are used. The switching element Q1 forming the U-phase upper arm and the switching element Q2 forming the U-phase lower arm are connected in series with each other. The switching element Q3 constituting the V-phase upper arm and the switching element Q4 constituting the V-phase lower arm are connected in series with each other. The switching element Q5 forming the W phase upper arm and the switching element Q6 forming the W phase lower arm are connected in series with each other. Output wirings 23, 24, and 25 are connected to the connection points of the upper arm switching elements Q1, Q3, and Q5 and the corresponding lower arm switching elements Q2, Q4, and Q6 for each phase. The output wirings 23, 24, and 25 are connected to the motor 11. A battery BA is connected to the switching elements Q1 to Q6 via a smoothing capacitor C. The conversion unit 22 converts the DC power of the battery BA into AC power. The output wirings 23, 24, and 25 output the AC power output from the conversion unit 22 to the motor 11. As a result, the motor 11 is driven. The inverter circuit 21 is a power circuit that performs power conversion.
 制御装置12は、例えば、マイクロコンピュータを主体として構成される。制御装置12が実行する処理は、記憶部に記憶されたプログラムをCPUが実行することにより行われてもよいし、専用の電子回路が実行するハードウェア処理を通じて行われてもよい。制御装置12は、例えば、他の制御装置等から要求されるモータ11の目標トルクに基づいて、ベクトル制御法を用いた電流フィードバック制御を行って、インバータ回路21を介してモータ11を制御する。制御装置12は、スイッチング素子Q1~Q6を制御するための制御信号をドライブ回路Dに出力する。ドライブ回路Dは、制御信号に応じてスイッチング素子Q1~Q6を制御する。 The control device 12 is mainly composed of, for example, a microcomputer. The process executed by the control device 12 may be performed by the CPU executing the program stored in the storage unit, or may be performed through the hardware process executed by the dedicated electronic circuit. The control device 12 controls the motor 11 via the inverter circuit 21 by performing current feedback control using a vector control method based on, for example, the target torque of the motor 11 requested by another control device or the like. The control device 12 outputs a control signal for controlling the switching elements Q1 to Q6 to the drive circuit D. The drive circuit D controls the switching elements Q1 to Q6 according to the control signal.
 ドライブ回路Dは、スイッチング素子Q1~Q6毎に個別に設けられている。図2に示すように、各ドライブ回路Dは、第1の駆動用スイッチング素子T1と、第2の駆動用スイッチング素子T2と、2つの抵抗素子R1,R2と、駆動用コンデンサC1と、ゲート抵抗R3と、2つの接続抵抗R4,R5と、2つの接続コンデンサC2,C3と、を備える。 The drive circuit D is individually provided for each of the switching elements Q1 to Q6. As shown in FIG. 2, each drive circuit D includes a first drive switching element T1, a second drive switching element T2, two resistance elements R1 and R2, a drive capacitor C1, and a gate resistor. It includes R3, two connection resistors R4 and R5, and two connection capacitors C2 and C3.
 第1の駆動用スイッチング素子T1としては、例えば、NPN型トランジスタが用いられる。第2の駆動用スイッチング素子T2としては、例えば、PNP型トランジスタが用いられる。 As the first drive switching element T1, for example, an NPN type transistor is used. As the second drive switching element T2, for example, a PNP type transistor is used.
 2つの駆動用スイッチング素子T1,T2と、2つの抵抗素子R1,R2とは互いに直列接続されている。第1の駆動用スイッチング素子T1のエミッタと第2の駆動用スイッチング素子T2のエミッタとは互いに接続されている。第1の駆動用スイッチング素子T1のコレクタには、抵抗素子R1の第1端部が接続されている。第2の駆動用スイッチング素子T2のコレクタには、抵抗素子R2の第1端部が接続されている。第2の駆動用スイッチング素子T2のコレクタは、抵抗素子R2を介して接地されている。駆動用スイッチング素子T1,T2と抵抗素子R1,R2とは、直列接続体を構成する。 The two drive switching elements T1 and T2 and the two resistance elements R1 and R2 are connected in series with each other. The emitter of the first drive switching element T1 and the emitter of the second drive switching element T2 are connected to each other. The first end of the resistance element R1 is connected to the collector of the first drive switching element T1. The first end of the resistance element R2 is connected to the collector of the second drive switching element T2. The collector of the second drive switching element T2 is grounded via the resistance element R2. The drive switching elements T1 and T2 and the resistance elements R1 and R2 form a series connection.
 駆動用コンデンサC1は、駆動用スイッチング素子T1,T2と抵抗素子R1,R2とで構成される直列接続体に並列接続されている。駆動用コンデンサC1の第1端部は抵抗素子R1の第2端部に接続されている。駆動用コンデンサC1の第2端部は抵抗素子R2の第2端部に接続されている。したがって、直列接続体を構成している駆動用スイッチング素子T1,T2及び抵抗素子R1,R2と、駆動用コンデンサC1とは、閉回路31を構成している。2つの駆動用スイッチング素子T1,T2の接続点は、ゲート抵抗R3の一端に接続されている。ゲート抵抗R3の他端は、スイッチング素子Q1~Q6のいずれかのゲートに接続されている。 The drive capacitor C1 is connected in parallel to a series connector composed of drive switching elements T1 and T2 and resistance elements R1 and R2. The first end of the drive capacitor C1 is connected to the second end of the resistance element R1. The second end of the drive capacitor C1 is connected to the second end of the resistance element R2. Therefore, the drive switching elements T1 and T2, the resistance elements R1 and R2, and the drive capacitor C1 constituting the series connection form a closed circuit 31. The connection points of the two drive switching elements T1 and T2 are connected to one end of the gate resistor R3. The other end of the gate resistor R3 is connected to any of the gates of the switching elements Q1 to Q6.
 第1の駆動用スイッチング素子T1のベース及び第2の駆動用スイッチング素子T2のベースは、抵抗を介して制御装置12に接続されている。 The base of the first drive switching element T1 and the base of the second drive switching element T2 are connected to the control device 12 via a resistor.
 接続抵抗R4と接続コンデンサC2は、互いに並列接続されている。接続抵抗R4の第1端部は、駆動用スイッチング素子T1のベースに接続されている。接続抵抗R4の第2端部は、抵抗素子R1の第2端部及び駆動用コンデンサC1の第1端部に接続されている。 The connection resistor R4 and the connection capacitor C2 are connected in parallel to each other. The first end of the connection resistor R4 is connected to the base of the drive switching element T1. The second end of the connection resistor R4 is connected to the second end of the resistor element R1 and the first end of the drive capacitor C1.
 接続コンデンサC2の第1端部は、駆動用スイッチング素子T1のベースに接続されている。接続コンデンサC2の第2端部は、抵抗素子R1の第2端部及び駆動用コンデンサC1の第1端部に接続されている。つまり、抵抗素子R1と接続コンデンサC2と第1の駆動用スイッチング素子T1とにより閉回路33が形成され、抵抗素子R1と接続抵抗R4と第1の駆動用スイッチング素子T1とにより閉回路34が形成される。 The first end of the connection capacitor C2 is connected to the base of the drive switching element T1. The second end of the connection capacitor C2 is connected to the second end of the resistance element R1 and the first end of the drive capacitor C1. That is, the closed circuit 33 is formed by the resistance element R1, the connection capacitor C2, and the first drive switching element T1, and the closed circuit 34 is formed by the resistance element R1, the connection resistor R4, and the first drive switching element T1. Will be done.
 接続抵抗R5と接続コンデンサC3は、互いに並列接続されている。接続抵抗R5の第1端部は、駆動用スイッチング素子T2のベースに接続されている。接続抵抗R5の第2端部は、抵抗素子R2の第2端部及び駆動用コンデンサC1の第2端部に接続されている。 The connection resistor R5 and the connection capacitor C3 are connected in parallel to each other. The first end of the connection resistor R5 is connected to the base of the drive switching element T2. The second end of the connection resistor R5 is connected to the second end of the resistor element R2 and the second end of the drive capacitor C1.
 接続コンデンサC3の第1端部は、駆動用スイッチング素子T2のベースに接続されている。接続コンデンサC3の第2端部は、抵抗素子R2の第2端部及び駆動用コンデンサC1の第2端部に接続されている。つまり、抵抗素子R2と接続コンデンサC3と第2の駆動用スイッチング素子T2とにより閉回路35が形成され、抵抗素子R2と接続抵抗R5と第2の駆動用スイッチング素子T2とにより閉回路36が形成される。 The first end of the connection capacitor C3 is connected to the base of the drive switching element T2. The second end of the connection capacitor C3 is connected to the second end of the resistance element R2 and the second end of the drive capacitor C1. That is, the closed circuit 35 is formed by the resistance element R2, the connection capacitor C3, and the second drive switching element T2, and the closed circuit 36 is formed by the resistance element R2, the connection resistor R5, and the second drive switching element T2. Will be done.
 以上のように構成されたドライブ回路Dは、2つの駆動用スイッチング素子T1,T2の動作により、スイッチング素子Q1~Q6のオンとオフとを切り替える。2つの駆動用スイッチング素子T1,T2は、スイッチング素子Q1~Q6を制御する制御素子である。また、ドライブ回路Dは、制御回路である。ドライブ回路Dは、ドライブ回路Dを駆動させるための電力を生成する電源回路からの電力供給によって駆動する。ドライブ回路Dは、制御装置12からの制御信号を増幅し、これを駆動信号として対応するスイッチング素子Q1~Q6のゲートに出力する。これにより、インバータ回路21の各相において、上アームスイッチング素子Q1,Q3,Q5と下アームスイッチング素子Q2,Q4,Q6とが交互にオン状態とされる。 The drive circuit D configured as described above switches the switching elements Q1 to Q6 on and off by the operation of the two drive switching elements T1 and T2. The two drive switching elements T1 and T2 are control elements that control the switching elements Q1 to Q6. The drive circuit D is a control circuit. The drive circuit D is driven by a power supply from a power supply circuit that generates electric power to drive the drive circuit D. The drive circuit D amplifies the control signal from the control device 12, and outputs the control signal as a drive signal to the gates of the corresponding switching elements Q1 to Q6. As a result, in each phase of the inverter circuit 21, the upper arm switching elements Q1, Q3 and Q5 and the lower arm switching elements Q2, Q4 and Q6 are alternately turned on.
 次に、インバータ回路21とドライブ回路Dとが実装された回路基板20について説明する。 Next, the circuit board 20 on which the inverter circuit 21 and the drive circuit D are mounted will be described.
 図3に示すように、回路基板20は、インバータ回路21を有する第1の層26と、ドライブ回路Dを有する第2の層32と、を備える。第1の層26と第2の層32とは重ねて配置されている。なお、「第1の層26と第2の層32とが重ねて配置されている状態」とは、第1の層26と第2の層32とが接触して配置された状態であってもよいし、第1の層26と第2の層32とが互いに離間して対向するように配置された状態であってもよい。すなわち、「第1の層26と第2の層32とが重ねて配置されている状態」とは、第1の層26と第2の層32とが接触又は離間して対向するように配置された状態である。本実施形態において、第1の層26と第2の層32とは、第1の層26の厚み方向と第2の層32の厚み方向とが一致するように重ねられている。「第1の層26の厚み方向と第2の層32の厚み方向とが一致する状態」は、公差等を原因とする若干のずれを許容する。回路基板20は、複数の絶縁層を積層した多層基板であり、第1の層26及び第2の層32は、絶縁層である。 As shown in FIG. 3, the circuit board 20 includes a first layer 26 having an inverter circuit 21 and a second layer 32 having a drive circuit D. The first layer 26 and the second layer 32 are arranged so as to overlap each other. The "state in which the first layer 26 and the second layer 32 are arranged in an overlapping manner" is a state in which the first layer 26 and the second layer 32 are arranged in contact with each other. Alternatively, the first layer 26 and the second layer 32 may be arranged so as to be separated from each other and face each other. That is, "a state in which the first layer 26 and the second layer 32 are arranged so as to overlap each other" means that the first layer 26 and the second layer 32 are arranged so as to be in contact with or separated from each other. It is in a state of being done. In the present embodiment, the first layer 26 and the second layer 32 are overlapped so that the thickness direction of the first layer 26 and the thickness direction of the second layer 32 coincide with each other. The "state in which the thickness direction of the first layer 26 and the thickness direction of the second layer 32 coincide with each other" allows a slight deviation due to a tolerance or the like. The circuit board 20 is a multilayer board in which a plurality of insulating layers are laminated, and the first layer 26 and the second layer 32 are insulating layers.
 出力配線23,24,25は、変換部22に接続されたバスバーである。即ち、出力配線23,24,25は、厚み方向の寸法に比べて幅方向の寸法のほうが長い幅広の配線である。第1の層26と第2の層32との重なる方向を積層方向とすると、出力配線23,24,25の厚み方向と積層方向とは同一方向である。 The output wirings 23, 24, and 25 are bus bars connected to the conversion unit 22. That is, the output wirings 23, 24, and 25 are wide wirings in which the width direction is longer than the thickness direction. Assuming that the overlapping direction of the first layer 26 and the second layer 32 is the stacking direction, the thickness direction of the output wirings 23, 24, 25 and the stacking direction are the same direction.
 各ドライブ回路Dの少なくとも一部分は、積層方向から見て、出力配線23,24,25のいずれかに重ねて配置されている。すなわち、各ドライブ回路Dは、積層方向から見て、出力配線23,24,25のいずれかに重なる重なり部分を有するように配置されている。以下、説明の便宜上、6つのスイッチング素子Q1~Q6にそれぞれ対応した6つのドライブ回路Dのうち出力配線25に重ねて配置されたドライブ回路Dについて説明するが、全てのドライブ回路Dの各々が、3つの出力配線23,24,25のいずれかと積層方向から見て重なっている。例えば、U相のスイッチング素子Q1,Q2を駆動する2つのドライブ回路DをU相の出力配線23に重ねて配置する等、各相のドライブ回路Dを同じ相の出力配線23,24,25に重ねて配置してもよい。また、3つの出力配線23,24,25のうちの1つに全てのドライブ回路Dを重ねて配置してもよい。 At least a part of each drive circuit D is arranged so as to be overlapped with any of the output wirings 23, 24, and 25 when viewed from the stacking direction. That is, each drive circuit D is arranged so as to have an overlapping portion that overlaps any of the output wirings 23, 24, and 25 when viewed from the stacking direction. Hereinafter, for convenience of explanation, the drive circuit D arranged so as to overlap the output wiring 25 among the six drive circuits D corresponding to the six switching elements Q1 to Q6 will be described, but each of the drive circuits D will be described. It overlaps with any of the three output wirings 23, 24, and 25 when viewed from the stacking direction. For example, two drive circuits D for driving U-phase switching elements Q1 and Q2 are arranged so as to overlap the U-phase output wiring 23, and the drive circuits D of each phase are arranged on the same- phase output wirings 23, 24, 25. It may be arranged in layers. Further, all the drive circuits D may be arranged so as to overlap one of the three output wirings 23, 24, 25.
 図4及び図5に示すように、積層方向から見て、ドライブ回路Dのうち閉回路31の全体が出力配線25に重ねて配置されている。閉回路31は、重なり部分である。なお、図4及び図5に示すように、説明の便宜上、閉回路31を四角枠状の配線として説明する。 As shown in FIGS. 4 and 5, when viewed from the stacking direction, the entire closed circuit 31 of the drive circuit D is arranged so as to overlap the output wiring 25. The closed circuit 31 is an overlapping portion. As shown in FIGS. 4 and 5, the closed circuit 31 will be described as a square frame-shaped wiring for convenience of explanation.
 出力配線25に電流が流れると、右ねじの法則に従った方向への磁束が生じる。これにより、ドライブ回路Dには電磁誘導による誘起電圧が生じて電流が流れる。ドライブ回路Dは、出力配線25に流れる電流に起因してドライブ回路Dに誘起される電流が許容値となるように配置されている。図6には、出力配線25に電流が流れることで生じる磁束を磁束線Lで表している。図6では、1つの磁束線Lのみを図示しているが、実際に生じる磁束を磁束線Lで表すと、磁束線Lは複数になる。磁束を原因とする誘起電圧により、ドライブ回路Dには電流が流れる。一般に、面積Sの平面回路を磁界内に置くと、面積Sの平面回路に生じる誘起電圧Vは、以下の式(1)で表すことができる。 When a current flows through the output wiring 25, a magnetic flux is generated in the direction according to the right-handed screw rule. As a result, an induced voltage due to electromagnetic induction is generated in the drive circuit D, and a current flows through the drive circuit D. The drive circuit D is arranged so that the current induced in the drive circuit D due to the current flowing through the output wiring 25 becomes an allowable value. In FIG. 6, the magnetic flux generated by the current flowing through the output wiring 25 is represented by the magnetic flux line L. In FIG. 6, only one magnetic flux line L is shown, but when the magnetic flux actually generated is represented by the magnetic flux line L, the magnetic flux lines L are plural. A current flows through the drive circuit D due to the induced voltage caused by the magnetic flux. In general, when a planar circuit having an area S is placed in a magnetic field, the induced voltage V generated in the planar circuit having an area S can be expressed by the following equation (1).
Figure JPOXMLDOC01-appb-M000001
 θは、平面回路の面と、磁束の方向に直交する方向に延びる仮想線とのなす角度である。出力配線25に流れる電流によって閉回路31に生じる誘起電圧Vは、以下の式(2)で表すことができる。
Figure JPOXMLDOC01-appb-M000001
θ is the angle formed by the plane of the planar circuit and the virtual line extending in the direction orthogonal to the direction of the magnetic flux. The induced voltage V generated in the closed circuit 31 by the current flowing through the output wiring 25 can be expressed by the following equation (2).
Figure JPOXMLDOC01-appb-M000002
 閉回路31内を2回鎖交する磁束が閉回路31内を通過する位置の1つを第1位置P1とし、閉回路31内を2回鎖交する磁束が閉回路31内を通過する位置のうち第1位置P1とは異なる位置を第2位置P2とする。θ1は、第1位置P1を通過する磁束の方向に直交する仮想線L1と、閉回路31全体を含む仮想面VSとのなす角度である。θ2は、第2位置P2を通過する磁束の方向に直交する仮想線L2と、閉回路31全体を含む仮想面VSとのなす角の角度である。
Figure JPOXMLDOC01-appb-M000002
One of the positions where the magnetic flux interlinking twice in the closed circuit 31 passes through the closed circuit 31 is set as the first position P1, and the position where the magnetic flux interlinking twice in the closed circuit 31 passes through the closed circuit 31. The position different from the first position P1 is referred to as the second position P2. θ1 is an angle formed by the virtual line L1 orthogonal to the direction of the magnetic flux passing through the first position P1 and the virtual surface VS including the entire closed circuit 31. θ2 is the angle between the virtual line L2 orthogonal to the direction of the magnetic flux passing through the second position P2 and the virtual surface VS including the entire closed circuit 31.
 ここで、出力配線25と閉回路31全体を含む仮想面VSとは、互いに平行となり、かつ、出力配線25の幅方向における出力配線25の中心CP1と、出力配線25の幅方向における閉回路31の中心CP2とを結ぶ仮想線が、出力配線25を流れる電流の方向及び出力配線25の幅方向と直交する方向に延びているとする。この場合、閉回路31の中心CP2を軸として第1位置P1と第2位置P2とは対称に位置する。従って、θ1-θ2=0°が成立し、式(2)から閉回路31に生じる誘起電圧は0になる。閉回路31全体を含む仮想面VSとは、閉回路31の外枠を構成する配線全部を含む面である。出力配線25の幅方向は、出力配線25を流れる電流の方向及び出力配線25の厚さ方向と直交する方向ともいえる。 Here, the output wiring 25 and the virtual surface VS including the entire closed circuit 31 are parallel to each other, and the center CP1 of the output wiring 25 in the width direction of the output wiring 25 and the closed circuit 31 in the width direction of the output wiring 25. It is assumed that the virtual line connecting the center CP2 of the above extends in the direction of the current flowing through the output wiring 25 and the direction orthogonal to the width direction of the output wiring 25. In this case, the first position P1 and the second position P2 are located symmetrically with respect to the center CP2 of the closed circuit 31. Therefore, θ1-θ2 = 0 ° is established, and the induced voltage generated in the closed circuit 31 from the equation (2) becomes 0. The virtual surface VS including the entire closed circuit 31 is a surface including all the wirings constituting the outer frame of the closed circuit 31. It can be said that the width direction of the output wiring 25 is orthogonal to the direction of the current flowing through the output wiring 25 and the thickness direction of the output wiring 25.
 上記したように、閉回路31内を2回鎖交する磁束が閉回路31を対称に通過した場合にはθ1とθ2とは同一の値になるため、閉回路31に生じる誘起電圧は0となり、磁束を原因とする電流は生じない。一方で、出力配線25と閉回路31全体を含む仮想面VSとが互いに平行ではない場合など、閉回路31内を2回鎖交する磁束が閉回路31に対して非対称に通過した場合にはθ1とθ2とは異なる値になるため、誘起電圧は0より高くなり、磁束を原因として閉回路31には電流が生じる。また、閉回路31を1回通過する磁束が存在する場合、式(1)に従い誘起電圧が生じる。出力配線25の中心CP1と、閉回路31の中心CP2とが出力配線25の幅方向に離れるに従い、閉回路31を1回通過する磁束が多くなることで、閉回路31に生じる誘起電圧は高くなる。閉回路31の全体が出力配線25に向かい合っている場合、閉回路31の一部のみが出力配線25に向かい合っている場合に比べて、誘起電圧が低くなる。 As described above, when the magnetic flux interlinking twice in the closed circuit 31 passes symmetrically through the closed circuit 31, θ1 and θ2 have the same value, so that the induced voltage generated in the closed circuit 31 becomes 0. , No current is generated due to magnetic flux. On the other hand, when the magnetic flux interlinking twice in the closed circuit 31 passes asymmetrically with respect to the closed circuit 31, such as when the output wiring 25 and the virtual surface VS including the entire closed circuit 31 are not parallel to each other. Since the values of θ1 and θ2 are different, the induced voltage becomes higher than 0, and a current is generated in the closed circuit 31 due to the magnetic flux. Further, when there is a magnetic flux that passes through the closed circuit 31 once, an induced voltage is generated according to the equation (1). As the center CP1 of the output wiring 25 and the center CP2 of the closed circuit 31 are separated from each other in the width direction of the output wiring 25, the magnetic flux passing through the closed circuit 31 once increases, so that the induced voltage generated in the closed circuit 31 becomes high. Become. When the entire closed circuit 31 faces the output wiring 25, the induced voltage is lower than when only a part of the closed circuit 31 faces the output wiring 25.
 説明の便宜上、閉回路31を形成する配線の形状を四角枠状として説明したが、閉回路31を形成する配線の形状が四角枠状ではない場合であっても、閉回路31内を2回鎖交する磁束が存在するように、閉回路31と出力配線25とを重なるように設けると、閉回路31に発生する誘起電圧が低くなる。従って、閉回路31を形成する配線の形状がどのような形状であっても、閉回路31に発生する電流の値が低くなる。 For convenience of explanation, the shape of the wiring forming the closed circuit 31 has been described as a square frame shape, but even if the shape of the wiring forming the closed circuit 31 is not a square frame shape, the inside of the closed circuit 31 is twice. If the closed circuit 31 and the output wiring 25 are provided so as to overlap each other so that the magnetic flux interlinking exists, the induced voltage generated in the closed circuit 31 becomes low. Therefore, the value of the current generated in the closed circuit 31 is low regardless of the shape of the wiring forming the closed circuit 31.
 上記したように、出力配線23,24,25とドライブ回路Dとの位置関係に応じて、磁束によりドライブ回路Dに生じる電流は変化する。従って、出力配線23,24,25とドライブ回路Dとの位置関係を調整することで、出力配線23,24,25からの磁束によりドライブ回路Dに生じる電流を許容値とすることができる。なお、許容値とは、第2の回路の種類に応じて異なる。本実施形態のように、第2の回路がドライブ回路Dの場合には、磁束によりドライブ回路Dに生じる電流によって駆動用スイッチング素子T1,T2が意図しない動作を行わないように許容値が設定される。閉回路31と、駆動用スイッチング素子T1,T2のベースとは、接続抵抗R4,R5及び接続コンデンサC2,C3を介して接続されている。閉回路31に磁束により誘起電圧が生じると、駆動用スイッチング素子T1,T2のベース-エミッタ間に電流が流れることで駆動用スイッチング素子T1,T2が意図せずにオンされる場合がある。駆動用スイッチング素子T1,T2が意図しない動作を行うと、スイッチング素子Q1~Q6のオンとオフとが誤って切り替えられる。スイッチング素子Q1~Q6のオンとオフとは、駆動用スイッチング素子T1,T2を含む閉回路31を流れる電流によって切り替わる。本実施形態では、閉回路31に流れる電流を考慮して、ドライブ回路Dと出力配線23,24,25との位置関係を調整すればよい。 As described above, the current generated in the drive circuit D due to the magnetic flux changes according to the positional relationship between the output wirings 23, 24, 25 and the drive circuit D. Therefore, by adjusting the positional relationship between the output wirings 23, 24, 25 and the drive circuit D, the current generated in the drive circuit D due to the magnetic flux from the output wirings 23, 24, 25 can be set as an allowable value. The permissible value differs depending on the type of the second circuit. When the second circuit is the drive circuit D as in the present embodiment, the allowable value is set so that the drive switching elements T1 and T2 do not operate unintentionally due to the current generated in the drive circuit D by the magnetic flux. To. The closed circuit 31 and the bases of the driving switching elements T1 and T2 are connected via connection resistors R4 and R5 and connection capacitors C2 and C3. When an induced voltage is generated by magnetic flux in the closed circuit 31, the driving switching elements T1 and T2 may be unintentionally turned on by a current flowing between the base and the emitter of the driving switching elements T1 and T2. If the drive switching elements T1 and T2 perform an unintended operation, the switching elements Q1 to Q6 are erroneously switched on and off. The switching elements Q1 to Q6 are switched on and off by the current flowing through the closed circuit 31 including the driving switching elements T1 and T2. In the present embodiment, the positional relationship between the drive circuit D and the output wirings 23, 24, 25 may be adjusted in consideration of the current flowing through the closed circuit 31.
 本実施形態の作用について説明する。 The operation of this embodiment will be described.
 出力配線23,24,25に電流が流れると、磁束が生じる。出力配線23,24,25とドライブ回路Dとの間には、シールド層が設けられていないため、電磁誘導によりドライブ回路Dには電流が生じる場合がある。 When a current flows through the output wirings 23, 24, 25, magnetic flux is generated. Since the shield layer is not provided between the output wirings 23, 24, 25 and the drive circuit D, a current may be generated in the drive circuit D due to electromagnetic induction.
 図7に示すように、閉回路31が第1の層26の厚み方向に拡がるようにし、θを90°に近付けると、式(1)から把握できるように、閉回路31に生じる誘起電圧が高くなる。磁束を原因として閉回路31に流れる電流が大きくなるので、スイッチング素子Q1~Q6のオンとオフとが誤って切り替えられる場合がある。これに対し、実施形態では、閉回路31に生じる誘起電圧を低くすることで、磁束によりドライブ回路Dに生じる電流が許容値となるようにしている。 As shown in FIG. 7, when the closed circuit 31 expands in the thickness direction of the first layer 26 and θ is brought close to 90 °, the induced voltage generated in the closed circuit 31 is generated as can be grasped from the equation (1). It gets higher. Since the current flowing through the closed circuit 31 becomes large due to the magnetic flux, the switching elements Q1 to Q6 may be erroneously switched on and off. On the other hand, in the embodiment, the induced voltage generated in the closed circuit 31 is lowered so that the current generated in the drive circuit D due to the magnetic flux becomes an allowable value.
 本実施形態の効果について説明する。 The effect of this embodiment will be described.
 (1)出力配線23,24,25に電流が流れることによって生じる磁束を考慮してドライブ回路Dを配置することで、磁束によりドライブ回路Dに生じる電流が許容値となるようにしている。従って、ドライブ回路Dへの磁束の影響を低減することができる。 (1) By arranging the drive circuit D in consideration of the magnetic flux generated by the current flowing through the output wirings 23, 24, 25, the current generated in the drive circuit D due to the magnetic flux becomes an allowable value. Therefore, the influence of the magnetic flux on the drive circuit D can be reduced.
 (2)積層方向から見て、閉回路31の全体が出力配線23,24,25のいずれかに重なっている。閉回路31の一部のみが出力配線23,24,25のいずれかに重なっている場合に比べて、ドライブ回路Dに発生する誘起電圧が低くなる。これにより、磁束によりドライブ回路Dに生じる電流を低減することができる。 (2) When viewed from the stacking direction, the entire closed circuit 31 overlaps with any of the output wirings 23, 24, and 25. The induced voltage generated in the drive circuit D is lower than that in the case where only a part of the closed circuit 31 overlaps with any of the output wirings 23, 24, and 25. As a result, the current generated in the drive circuit D due to the magnetic flux can be reduced.
 (3)磁束によりドライブ回路Dに生じる電流が許容値となるようにすることで、駆動用スイッチング素子T1,T2が意図しない動作を行うことが抑制される。従って、スイッチング素子Q1~Q6のオンとオフとが誤って切り替えられることを抑制できる。 (3) By making the current generated in the drive circuit D due to the magnetic flux an allowable value, it is possible to prevent the drive switching elements T1 and T2 from performing unintended operations. Therefore, it is possible to prevent the switching elements Q1 to Q6 from being erroneously switched on and off.
 実施形態は、以下のように変更して実施することができる。実施形態及び以下の変形例は、技術的に矛盾しない範囲で互いに組み合わせて実施することができる。 The embodiment can be changed and implemented as follows. The embodiments and the following modifications can be implemented in combination with each other to the extent that they are technically consistent.
 ○第1の回路及び第2の回路は、回路基板20に代えて、複数の回路基板を有する回路基板モジュールに実装されてもよい。回路基板モジュールは、第1の回路を有する第1の回路基板と、第1の回路とは異なる第2の回路を有する第2の回路基板と、を備える。第1の回路としては、例えば、インバータ回路21を用いることができる。第2の回路としては、例えば、ドライブ回路Dを用いることができる。第1の回路基板は、絶縁基板に第1の回路を実装したものである。第2の回路基板は、絶縁基板に第2の回路を実装したものである。第1の回路基板と第2の回路基板とは、互いに間隔を空けて配置される。第1の回路基板と第2の回路基板とは、積層方向に重ねて(換言すれば、積層方向に対向して)配置される。即ち、図3に示した実施形態の回路基板20を回路基板モジュールとみなした場合、第1の層26及び第2の層32はそれぞれ絶縁基板とみなすことができ、この2つの絶縁基板が互いに間隔を空けて配置される。第2の回路は、第1の回路基板と第2の回路基板とが重なる方向から見て、少なくとも部分的に、第1の回路の配線と重なるように配置される。すなわち、第2の回路は、第1の回路基板と第2の回路基板とが重なる方向から見て、第1の回路の配線と重なる重なり部分を有するように配置される。第2の回路は、第1の回路の配線に流れる電流によって生じる磁束に起因して重なり部分に生じる電流が許容値となるように配置されている。 ○ The first circuit and the second circuit may be mounted on a circuit board module having a plurality of circuit boards instead of the circuit board 20. The circuit board module includes a first circuit board having a first circuit and a second circuit board having a second circuit different from the first circuit. As the first circuit, for example, an inverter circuit 21 can be used. As the second circuit, for example, a drive circuit D can be used. The first circuit board is an insulating board on which the first circuit is mounted. The second circuit board is an insulating board on which the second circuit is mounted. The first circuit board and the second circuit board are arranged at intervals from each other. The first circuit board and the second circuit board are arranged so as to be overlapped in the stacking direction (in other words, to face the stacking direction). That is, when the circuit board 20 of the embodiment shown in FIG. 3 is regarded as a circuit board module, the first layer 26 and the second layer 32 can be regarded as insulating boards, respectively, and the two insulating boards are regarded as each other. Arranged at intervals. The second circuit is arranged so as to overlap the wiring of the first circuit at least partially when viewed from the direction in which the first circuit board and the second circuit board overlap. That is, the second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the first circuit when viewed from the direction in which the first circuit board and the second circuit board overlap. The second circuit is arranged so that the current generated in the overlapping portion due to the magnetic flux generated by the current flowing through the wiring of the first circuit becomes an allowable value.
 ○第1の回路は、パワー回路以外であってもよい。例えば、第1の回路は、平滑コンデンサC等の素子が実装された回路であってもよい。 ○ The first circuit may be other than the power circuit. For example, the first circuit may be a circuit on which an element such as a smoothing capacitor C is mounted.
 ○第2の回路は、センサに用いられる演算回路であってもよい。例えば、演算回路は、電流センサに用いられるものであってもよい。電流センサは、シャント抵抗と、演算回路と、を備える。演算回路は、シャント抵抗に流れる電流及びシャント抵抗の両端電圧から、検出対象に流れる電流の値を演算する。演算回路を磁束の影響下に配置した場合、磁束により生じる電流によって、センサの検出結果に誤差が生じる場合がある。センサに用いられる演算回路を本開示の第2の回路とした場合、磁束により生じる電流の許容値は、センサの検出結果として許容される誤差の範囲内に設定される。センサの検出結果として許容される誤差は、センサが搭載される搭載対象によって異なる。従って、磁束により演算回路に生じる電流の値がセンサや搭載対象の許容する値となるように演算回路を配置すればよい。 ○ The second circuit may be an arithmetic circuit used for the sensor. For example, the arithmetic circuit may be used for a current sensor. The current sensor includes a shunt resistor and an arithmetic circuit. The arithmetic circuit calculates the value of the current flowing through the detection target from the current flowing through the shunt resistor and the voltage across the shunt resistor. When the arithmetic circuit is arranged under the influence of magnetic flux, an error may occur in the detection result of the sensor due to the current generated by the magnetic flux. When the arithmetic circuit used in the sensor is the second circuit of the present disclosure, the permissible value of the current generated by the magnetic flux is set within the range of the error permissible as the detection result of the sensor. The permissible error as a result of sensor detection depends on the mounting target on which the sensor is mounted. Therefore, the arithmetic circuit may be arranged so that the value of the current generated in the arithmetic circuit due to the magnetic flux becomes a value allowed by the sensor and the mounting target.
 ○パワー回路としては、電力の変換を行うものであればよく、例えば、DC/DCコンバータに用いられるコンバータ回路であってもよい。パワー回路の有するパワー素子としては、スイッチング素子の他に、ダイオードや、サイリスタを挙げることができる。 ○ The power circuit may be any one that converts electric power, and may be, for example, a converter circuit used in a DC / DC converter. Examples of the power element included in the power circuit include a diode and a thyristor in addition to the switching element.
 ○図8に示すように、第2の回路40は、積層方向から見て、出力配線25に重なる重なり部分である第1の部位41と、出力配線25に重なり合わない第2の部位42と、を備えていてもよい。この場合、第1の部位41に比べて、第2の部位42のほうが磁束によって生じる電流が大きくなりやすい。第2の部位42で生じた電流が第1の部位41に流れることを抑制するため、第1の部位41と第2の部位42とを相互接続する接続配線44にはコンデンサ43が接続される。コンデンサ43は、第1の部位41及び第2の部位42に並列接続されている。コンデンサ43は、積層方向から見て、出力配線25に重なり合っている。出力配線25と重なり合わず、電磁誘導により電流が生じ易い第2の部位42の影響を抑制することで、第1の部位41への磁束の影響を低減できる。この場合、第2の回路40は、磁束により第1の部位41に生じる電流が許容値となるように配置すればよい。 ○ As shown in FIG. 8, the second circuit 40 includes a first portion 41 which is an overlapping portion overlapping the output wiring 25 and a second portion 42 which does not overlap the output wiring 25 when viewed from the stacking direction. , May be provided. In this case, the current generated by the magnetic flux tends to be larger in the second portion 42 than in the first portion 41. A capacitor 43 is connected to the connection wiring 44 that interconnects the first portion 41 and the second portion 42 in order to suppress the current generated in the second portion 42 from flowing to the first portion 41. .. The capacitor 43 is connected in parallel to the first portion 41 and the second portion 42. The capacitor 43 overlaps the output wiring 25 when viewed from the stacking direction. By suppressing the influence of the second portion 42, which does not overlap with the output wiring 25 and tends to generate a current due to electromagnetic induction, the influence of the magnetic flux on the first portion 41 can be reduced. In this case, the second circuit 40 may be arranged so that the current generated in the first portion 41 by the magnetic flux becomes an allowable value.
 また、第2の部位42の面積が小さければ、式(1)から把握できるように、第2の部位42に生じる誘起電圧が低くなる。従って、第2の回路40の面積が小さく、磁束により第2の回路40に生じる電流が小さければ、接続配線44にコンデンサ43を設けなくてもよい。この場合、第1の部位41は、磁束により第1の部位41に生じる電流が許容値となるように配置すればよい。 Further, if the area of the second portion 42 is small, the induced voltage generated in the second portion 42 becomes low, as can be grasped from the equation (1). Therefore, if the area of the second circuit 40 is small and the current generated in the second circuit 40 by the magnetic flux is small, it is not necessary to provide the capacitor 43 in the connection wiring 44. In this case, the first portion 41 may be arranged so that the current generated in the first portion 41 due to the magnetic flux becomes an allowable value.
 ○閉回路31の一部が積層方向から見て、出力配線25と重なっていなくてもよい。 ○ A part of the closed circuit 31 does not have to overlap with the output wiring 25 when viewed from the stacking direction.
 ○第2の回路は、閉回路でなくてもよい。 ○ The second circuit does not have to be a closed circuit.
 ○ドライブ回路Dは、出力配線23,24,25に流れる電流によって生じる磁束に起因して閉回路33,34,35,36の少なくともいずれかに流れる電流が許容値となるように配置されていてもよい。即ち、磁束により生じる電流が流れることで駆動用スイッチング素子T1,T2に意図しない動作を行わせるおそれがある閉回路であれば、少なくともいずれか一つの閉回路に流れる電流が許容値となるようにドライブ回路Dは配置されていてもよい。 ○ The drive circuit D is arranged so that the current flowing in at least one of the closed circuits 33, 34, 35, 36 due to the magnetic flux generated by the current flowing in the output wirings 23, 24, 25 becomes an allowable value. May be good. That is, in the case of a closed circuit in which the driving switching elements T1 and T2 may perform unintended operations due to the flow of the current generated by the magnetic flux, the current flowing in at least one of the closed circuits shall be an allowable value. The drive circuit D may be arranged.
 ○第1の回路の配線は、出力配線23,24,25でなくてもよく、インバータ回路21にバッテリBAからの電力を入力する入力用の配線やインバータ回路21を構成するパターン配線など、瞬間的に一方向に電流が流れる配線であれば、どのような配線であってもよい。 ○ The wiring of the first circuit does not have to be the output wirings 23, 24, 25, and the wiring for input for inputting the power from the battery BA to the inverter circuit 21 and the pattern wiring constituting the inverter circuit 21 are instantaneous. Any wiring may be used as long as the wiring allows current to flow in one direction.
 ○閉回路31全体を含む仮想面VSは、閉回路31全体を含む仮想面VSと対向する出力配線23~25の面に対して傾斜するように配置されていてもよい。 ○ The virtual surface VS including the entire closed circuit 31 may be arranged so as to be inclined with respect to the surfaces of the output wirings 23 to 25 facing the virtual surface VS including the entire closed circuit 31.
 ○第1の層26と第2の層32との間にシールド層を設けてもよい。この場合、ドライブ回路Dと出力配線23,24,25との配置関係の設定により、磁束によってドライブ回路Dに生じる電流を低減することで、シールド層を薄くすることができる。 ○ A shield layer may be provided between the first layer 26 and the second layer 32. In this case, the shield layer can be made thinner by reducing the current generated in the drive circuit D due to the magnetic flux by setting the arrangement relationship between the drive circuit D and the output wirings 23, 24, 25.
 ○回路基板20は、少なくとも第1の層26と第2の層32とを備えていればよく、3つ以上の層を備えるものであってもよい。 ○ The circuit board 20 may include at least a first layer 26 and a second layer 32, and may include three or more layers.
 ○ドライブ回路Dは、接続抵抗R4と接続コンデンサC2とのうち一方を備えたものでもよい。ドライブ回路Dは、接続抵抗R5と接続コンデンサC3とのうち一方を備えたものでもよい。 ○ The drive circuit D may include one of the connection resistor R4 and the connection capacitor C2. The drive circuit D may include one of the connection resistor R5 and the connection capacitor C3.

Claims (5)

  1.  第1の回路を有する第1の層と、
     前記第1の回路とは異なる第2の回路を有する第2の層と、を備え、
     前記第1の層と前記第2の層とは重ねて配置されており、
     前記第2の回路は、前記第1の層と前記第2の層とが重なる方向である積層方向から見て、前記第1の回路の配線と重なる重なり部分を有するように配置されており、
     前記第2の回路は、前記第1の回路の配線に流れる電流によって生じる磁束に起因して前記重なり部分に生じる電流が許容値となるように配置されている回路基板。
    A first layer with a first circuit and
    A second layer having a second circuit different from the first circuit is provided.
    The first layer and the second layer are arranged so as to overlap each other.
    The second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the first circuit when viewed from the stacking direction in which the first layer and the second layer overlap.
    The second circuit is a circuit board arranged so that the current generated in the overlapping portion due to the magnetic flux generated by the current flowing through the wiring of the first circuit becomes an allowable value.
  2.  前記第2の回路は、閉回路を含み、
     前記積層方向から見て、前記閉回路の全体が前記第1の回路の配線と重なる請求項1に記載の回路基板。
    The second circuit includes a closed circuit.
    The circuit board according to claim 1, wherein the entire closed circuit overlaps with the wiring of the first circuit when viewed from the stacking direction.
  3.  前記第1の回路は、パワー素子を備えるパワー回路であり、
     前記第2の回路は、前記パワー素子を制御する制御素子を備える制御回路である請求項1又は請求項2に記載の回路基板。
    The first circuit is a power circuit including a power element.
    The circuit board according to claim 1 or 2, wherein the second circuit is a control circuit including a control element that controls the power element.
  4.  前記第2の回路は、
      前記重なり部分である第1の部位と、
      前記積層方向から見て前記第1の回路の配線に重なり合わない第2の部位と、
      前記第1の部位と前記第2の部位とを相互接続する接続配線と、
      前記第1の部位と前記第2の部位とに並列接続されるように前記接続配線に接続されたコンデンサであって、前記積層方向から見て前記第1の回路の配線と重なるコンデンサと、を備える請求項1に記載の回路基板。
    The second circuit is
    The first part, which is the overlapping part, and
    A second portion that does not overlap the wiring of the first circuit when viewed from the stacking direction, and
    The connection wiring that interconnects the first part and the second part,
    A capacitor connected to the connection wiring so as to be connected in parallel to the first portion and the second portion, and which overlaps with the wiring of the first circuit when viewed from the stacking direction. The circuit board according to claim 1.
  5.  第1の回路を有する第1の回路基板と、
     前記第1の回路とは異なる第2の回路を有する第2の回路基板と、を備え、
     前記第1の回路基板と前記第2の回路基板とは重ねて配置されており、
     前記第2の回路は、前記第1の回路基板と前記第2の回路基板とが重なる方向である積層方向から見て、前記第1の回路の配線と重なる重なり部分を有するように配置されており、
     前記第2の回路は、前記第1の回路の配線に流れる電流によって生じる磁束に起因して前記重なり部分に生じる電流が許容値となるように配置されている回路基板モジュール。
    A first circuit board having a first circuit and
    A second circuit board having a second circuit different from the first circuit is provided.
    The first circuit board and the second circuit board are arranged so as to overlap each other.
    The second circuit is arranged so as to have an overlapping portion that overlaps with the wiring of the first circuit when viewed from the stacking direction in which the first circuit board and the second circuit board overlap. Ori,
    The second circuit is a circuit board module arranged so that the current generated in the overlapping portion due to the magnetic flux generated by the current flowing in the wiring of the first circuit becomes an allowable value.
PCT/JP2020/023799 2019-07-01 2020-06-17 Circuit board and circuit board module WO2021002200A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-122899 2019-07-01
JP2019122899A JP7136023B2 (en) 2019-07-01 2019-07-01 Circuit boards and circuit board modules

Publications (1)

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WO2021002200A1 true WO2021002200A1 (en) 2021-01-07

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Application Number Title Priority Date Filing Date
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WO (1) WO2021002200A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009188271A (en) * 2008-02-07 2009-08-20 Jtekt Corp Multilayer circuit board, and motor drive circuit board
JP2014528167A (en) * 2011-09-16 2014-10-23 エスエムエー ソーラー テクノロジー アーゲー Circuit layout to reduce vibration tendency

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009188271A (en) * 2008-02-07 2009-08-20 Jtekt Corp Multilayer circuit board, and motor drive circuit board
JP2014528167A (en) * 2011-09-16 2014-10-23 エスエムエー ソーラー テクノロジー アーゲー Circuit layout to reduce vibration tendency

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JP7136023B2 (en) 2022-09-13

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