WO2020258958A1

WO2020258958A1 - Time synchronization method and server

Info

Publication number: WO2020258958A1
Application number: PCT/CN2020/081834
Authority: WO
Inventors: 郭中天
Original assignee: 华为技术有限公司
Priority date: 2019-06-28
Filing date: 2020-03-27
Publication date: 2020-12-30
Also published as: CN112148065A

Abstract

A time synchronization method and a server. Said method comprises: a BMC can firstly acquire a first time, and then store the acquired first time into a time register of a CPLD; the CPLD can start timing on the basis of the first time and record a timing result; when the timing result reaches a preset threshold value, the CPLD determines a second time according to the first time and the timing result; and the time register is updated according to the second time. The time recorded by the time register in the CPLD in real time can be provided for other components of the server, so as to ensure normal operation of the components in the server, and more important components can be deployed on the PCB in the server, thereby improving the performance of the server and effectively reducing hardware costs of the server.

Description

A time synchronization method and server

Technical field

This application relates to the field of server technology, and in particular to a time synchronization method and server.

Background technique

One or more real-time clock (RTC) circuits can be provided on the printed circuit board (PCB) in each server. The RTC circuit is connected to each component in the server through a programmable logic device (PLD), obtains time information from the RTC through the PLD, and then the PLD shares the time information to each component to provide time information to each component. Among them, components such as baseboard management controller (baseboard management controller, BMC), central processing unit (central processing unit, CPU), etc. When the server is not powered on for a long time, the RTC circuit can still provide real-time time. If the server is powered on again, the RTC circuit can provide real-time time to each component of the server to ensure that each component of the server can be based on the real-time time obtained Realize functions such as business docking and log recording. However, the RTC circuit in the traditional server will occupy a large area of the PCB, which affects the layout of the components in the PCB. It is impossible to increase the number of other important components in the limited space provided by the same PCB, resulting in the limited processing capacity of the server. When meeting higher business requirements, the only way to meet their requirements is to increase the number of servers, which increases the cost of server hardware.

Summary of the invention

This application provides a time synchronization method and server to reduce the occupied area of the RTC circuit on the PCB in the server and reduce the cost of the server.

In the first aspect, this application provides a method of time synchronization. The method can be applied to a server. The RTC circuit may not be set in the server. The server includes BMC and CPLD. The BMC is connected to the CPLD. The method includes: BMC can be obtained first The first time, after that, store the acquired first time in the CPLD time register; the time stored in the time register can be updated in real time to store the real-time time; the first time is the time when the BMC obtains the first time operation; CPLD can Based on the first time, start timing and record the timing result. When the timing result reaches the preset threshold, the CPLD determines the second time according to the first time and the timing result; and updates the time register according to the second time.

Through the above method, the BMC in the server obtains the first time and saves the obtained first time in the CPLD, and because the CPLD has a timing function, the time register in the CPLD can record the real-time time so that the time register in the CPLD can record Real-time time can be provided to other components of the server to ensure the normal operation of each component in the server. In this way, RTC circuits are not required to be deployed in the server, and more important components can be deployed on the PCB in the server, which can improve server performance and effectively reduce Server hardware cost.

In a possible design, the BMC and the CPLD may communicate through the first interface. When the BMC stores the acquired first time in the time register of the CPLD, the first time may be stored in the time register of the CPLD through the first interface.

Through the above method, the CPLD is provided with the first interface connected with the BMC, so that the BMC can update the first time to the time register more quickly and conveniently.

In a possible design, the processor and the CPLD can communicate through the second interface, and the processor can read the second time from the time register through the second interface; the processor starts timing and records the real time based on the second time.

Through the above method, the processor can obtain the second time from the CPLD and start timing to perform some operations that require real-time time as a reference, such as business docking, log recording, etc., so that the processor can operate normally.

In a possible design, the CPLD timing method is different, and the timing result is also different; for example, the CPLD can be timed by recording the time value. In this way, the CPLD timing result can be the time value, correspondingly, preset The threshold indicates the time interval for CPLD to update the time register; in this way, the CPLD updates the time stored in the time register after each time interval, so that the time recorded by the time register is guaranteed to be consistent with the time of the NTP server.

For another example, the CPLD can record the number of counts and count the number of times. In this way, the timing result of the CPLD is the number of counts. Accordingly, the preset threshold indicates the maximum number of counts of the CPLD. In this way, the CPLD updates the time stored in the time register whenever the number of counts reaches the maximum number of counts, which can also ensure that the time recorded by the time register is consistent with the time of the NTP server.

In a possible design, when the CPLD determines the second time according to the first time and the timing result, the second time can be determined by an accumulation method; for example, the CPLD can determine the second time according to the accumulation result of the first time and the timing result, Determine the second time.

Through the above method, the CPLD determines the second time by using an accumulation method, and the second time can be more accurately reflected as the time at the current moment.

In a possible design, when the BMC obtains the first time, it can obtain the first time from an NTP server, or it can obtain the first time from a time-calibrated server.

Through the above method, the first time obtained by the BMC is relatively accurate, which ensures that the second time that can be determined by the subsequent CPLD through timing can be consistent with the real-time time of the NTP server.

In a possible design, the processor may also obtain user configuration data from the storage medium in the server, and start based on the user configuration data. The storage medium may be a non-volatile storage medium, or may be powered by a power supply, The storage medium that does not lose data when the server is powered off.

Through the above method, the processor can still obtain user configuration data under the condition that the server does not deploy the RTC circuit, so that the processor can operate normally.

In the second aspect, this application provides a time synchronization device, which has the functions implemented by the BMC, the processor, and the CPLD in any one of the possible designs of the first aspect and the first aspect. The function can be realized by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions. In a possible design, the structure of the device includes a management unit, a timing unit, and a processing unit. The timing unit also includes a storage unit. These units can perform the corresponding functions of the BMC, the processor, and the CPLD in the example of the first aspect. The detailed description in the example of the first aspect will not be repeated here.

In the third aspect, the present application also provides a server. For beneficial effects, please refer to the description of the first aspect and any possible design of the first aspect and will not be repeated here. The structure of the server includes a baseboard management controller, a complex programmable logic device, a processor, and a memory. The processor is configured to support the processor to execute any one of the aforementioned first aspect and any one of the possible designs of the first aspect. The function of the memory is coupled with the processor, which stores the necessary program instructions and data. The baseboard management controller is configured to support the baseboard management controller to execute the corresponding function in the baseboard management controller of any possible design of the first aspect and the first aspect; the complex programmable logic device is configured to support complex programmable logic The device executes the corresponding function in the complex programmable logic device of the first aspect and any one of the possible designs of the first aspect; the communication interface is used to communicate with other devices.

In a fourth aspect, this application also provides a computer-readable storage medium that stores instructions in the computer-readable storage medium, which when run on a computer, causes the computer to execute the BMC, processor, and CPLD execution methods of the above aspects .

In a fifth aspect, this application also provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the BMC, processor, and CPLD execution methods of the foregoing aspects.

In a sixth aspect, the present application also provides a computer chip, which is connected to the memory, and the chip is used to read and execute the software program stored in the memory, and execute the BMC, processor and CPLD execution methods of the above aspects.

Description of the drawings

Figure 1 is a schematic diagram of a server provided by this application;

Figure 2 is a schematic diagram of the architecture of a system provided by this application;

FIG. 3 is a schematic diagram of three stages of server startup provided by this application;

FIG. 4 is a schematic diagram of a time synchronization method provided by this application;

FIG. 5 is a schematic structural diagram of a time synchronization device provided by this application;

Fig. 6 is a schematic structural diagram of a server provided by this application.

Detailed ways

In order to reduce server costs in this application, RTC circuits are no longer deployed in the server, but the BMC in the server obtains the time from an external server (such as T0 in the embodiment of this application), and stores the obtained time in complex programmable logic In a complex programmable logic device (CPLD), it is convenient for subsequent processors to obtain time from the CPLD so that the processor can perform a series of startup operations after power-on based on the obtained time.

The following describes the architecture of the server and the system to which the embodiments of the present application are applied in conjunction with the accompanying drawings.

FIG. 1 is a schematic diagram of a time synchronization system provided by an embodiment of the application. As shown in FIG. 1, the system includes a server 100 and a network time protocol (NTP) server 200. Optionally, the system also includes a server 300. The NTP server 200 and the server 300 can be used to provide time synchronization information for the server 100, such as real-time time.

As shown in FIG. 1, the server 100 includes a BMC 110, a processor 120, and a complex programmable logic device (CPLD) 130.

The BMC110 and the processor 120 are connected through the CPLD130. In the embodiment of the present application, the CPLD 130 may include a time register 1301, and the time register 1301 may be used to store the current real-time time; such as the time T0 and the updated T1 in the embodiment of the present application. CPLD130 also has a timing function, which can time based on the time T0 sent by BMC110, obtain the current real-time time, and update the time stored in the time register 1301.

BMC110 is used to monitor and manage various components in the server. For example, the BMC 110 can monitor the temperature and voltage of components in the server 100 (such as the processor 120, the storage medium in the server 100, etc.); it can also control the speed of the fan in the server 110.

The BMC110 may also have a timing function. For example, the BMC110 may include a clock circuit, which can be used for timing.

It should be noted that only one processor 120 in the server 100 is exemplarily drawn in FIG. 1. The embodiment of the present application does not limit the number of processors 120 included in the server 100. When there are multiple processors 120 in the server 100, the BMC 110 can be connected to each processor 120 through a CPLD 130. In other words, the BMC 110 A CPLD130 is set between each processor 120; the BMC110 can update the acquired time to the time register 1301 in each CPLD130, and the processor 120 obtains real-time time from the time register 1301 of the connected CPLD130. As a possible implementation, BMC110 can also be connected to some processors 120 of multiple processors 120 through one CPLD130, that is, multiple processors 120 can be connected to one CPLD130; BMC110 can obtain time Update to the time register 1301 in each CPLD 130 connected to it, and the processor 120 obtains the real-time time from the time register 1301 of the connected CPLD 130.

Optionally, when there are multiple processors 120 in the server 100, the BMC 110 may be connected to one of the processors 120 (for convenience of description, the processor may be called the first processor) through the CPLD 130, and the multiple processors 120 The remaining processors except the first processor (for convenience of description, the remaining processors may be referred to as second processors) may be connected to the first processor. The second processor can be used as a coprocessor of the first processor to perform some operations in cooperation with the first processor; the second processor can also be a processor with the same functions as the first processor, and the embodiment of the present application does not Define the type and function of the second processor.

The BMC 110 may update the acquired time to the time register 1301 in the CPLD 130, and the first processor obtains the real-time time from the time register 1301 of the CPLD 130 connected to it. The second processor can obtain the real-time time from the connected first processor; in the above description, a first processor is taken as an example for description. The embodiment of the present application does not limit the number of first processors. The BMC110 can be The multiple first processors are connected through the CPLD130, and the remaining processors can be connected to any one of the multiple first processors to obtain real-time time.

As shown in FIG. 1, in addition to the time register 1301, the CPLD 130 also includes a counter 1302, a BMC interface 1303 and a processor interface 1304.

The BMC110 can store the acquired time T0 in the time register 1301 through the BMC interface 1303; the counter 1302 can acquire the time T0 from the time register 1301 and start timing, and can also update the time register 1301. As time progresses, the time register The time stored in 1301 is continuously updated, and the real-time time at the current moment can always be recorded; the processor 120 can read the real-time time at the current moment (such as time T1) from the time register 1301 through the processor interface 1304.

The embodiment of the present application does not limit the timing of the counter 1302. For example, the counter 1302 may include a clock circuit, and the counter 1302 may use the clock circuit to perform timing based on T0.

Optionally, the counter 1302 can also be based on a clock circuit to generate a pulse signal S1 of a fixed period (for example, the fixed period is 1 second); then, the counter 1302 uses the pulse signal S1 to time the clock, the starting value of the time is T0, and the counter 1302 generates A pulse signal S1 accumulates 1 to T0 for timing.

The embodiment of the present application also does not limit the manner in which the counter 1302 updates the time register 1301. For example, it may be updated at a preset time interval or may be updated at a preset maximum count. For details, please refer to the following description.

It is worth noting that, in addition to the functions of the timer 1302 and the time register 1301, the CPLD in the system architecture can also be used for other calculation or storage functions in the server, which is not limited in this application.

2 is a schematic diagram of another system architecture provided by an embodiment of the application. As shown in FIG. 2, the system includes a manager 400 and multiple servers 100. The structure of each server 100 is similar to that shown in FIG. The server 100 is similar and will not be repeated here.

In the system shown in FIG. 3, the manager 400 can be connected to multiple servers 100 to manage and control multiple servers 100. For example, the manager 400 can count the number of servers 100 connected to the manager 400 and each server. The type and location of 100 can also be obtained from the BMC 110 in the server 100 to obtain information about some components in the server 100. The embodiment of the present application does not limit the connection manner of the manager 400 and each server 100. For example, the manager 400 may be connected to the server 100 in a wired manner, or may be connected via a network (such as a wireless network such as Ethernet).

The embodiment of the present application does not limit the specific form of the manager 400, and it may be a server, a chip, or other types of modules.

In the embodiment of the present application, the manager 400 can communicate with a server outside the system. The server can be an NTP server 200 or a server 300 whose time has been calibrated; for example, the manager 400 can communicate directly with the system. To communicate with a server outside the system, you can also communicate with a server outside the system through a switch. For example, the manager 400 may obtain the time T0 from a server outside the system, and notify the server 100 connected to the manager 400 of the time T0. For example, the manager 400 may send the time T0 to the BMC 110 in the server 100.

The embodiment of the present application does not limit the specific form of the system shown in FIG. 2. The system shown in FIG. 2 may be a blade server, the manager 400 is a manager in the blade server, and the service 100 may be a blade server. The server; the system shown in FIG. 2 may also be a rack server cluster, the manager 400 is a management board in the rack server cluster, and the server 100 is any server in the rack server cluster.

First, each stage of the server 100 startup will be described. FIG. 3 is a description of the startup process of the server 100 provided by an embodiment of the application. As shown in FIG. 3, the startup process of the server 100 can be divided into three stages. The power supply mode in the server 100 can be divided into two domains: main power ( main) and standby (standby). After the server 100 is powered on, the components in the server 100 are powered on in a preset order. First, the backup power supplies power to the BMC 110 in the server 100 (the first stage); then, the BMC 110 can send a control command, which is used to control the main power to supply power to the processor 120; after the processor 120 is powered on, the processor 120 To start booting, first boot the basic input output system (BIOS), which corresponds to the second stage; finally, boot the operating system (OS), which corresponds to the third stage.

Next, further introduce the power-on process of each stage:

In the first stage, BMC110 starts.

After the BMC110 is powered on, the functions of the BMC110 are initialized. For example, the BMC110 can complete the initialization with the BMC interface 1303. The initialization operation includes loading the driver of the interface and connecting to the CPLD130. When the initialization of the BMC 110 is completed, the server 100 can be controlled to enter the second stage; the BMC 110 can control the main power to supply power to the processor 120 by sending a control command to enter the second stage.

In the second stage, the BIOS starts.

After the processor 120 is powered on, it can load the BIOS, read the system configuration information of the server 100, configure the underlying hardware of the processor 120 based on the system configuration information, and execute the boot program (Boot) in the boot record (Boot Record), Complete the boot action initiated by the OS, and then enter the next stage.

In the third stage, the OS starts.

Entering the third stage, the processor 120 loads the OS kernel, performs initialization, and opens up the connection between the OS and the underlying hardware of the processor 120.

In the third stage, the processor 120 can communicate with an external server. For example, a more accurate real-time time can be obtained from the NTP server. After the processor 120 obtains the real-time time from the NTP server, it performs timing based on the real-time time.

Taking the time synchronization system shown in FIG. 1 as an example, the time synchronization method provided in the embodiment of the present application will be described in conjunction with FIG. 4. As shown in FIG. 4, the method includes:

Step 401: In the first stage of the server 100 startup, after the BMC 110 is powered on, it synchronizes time with other servers to obtain the time T0.

The other server may be an NTP server 200 or a server 300 whose time has been calibrated in other times.

After BMC110 is powered on, it can synchronize time with NTP server 200. If the connection between BMC110 and NTP server 200 is interrupted or the NTP server fails, BMC110 cannot obtain the current time from NTP server 200. BMC110 can synchronize with the time shown in Figure 1. Communication with other servers in the system to obtain the current time T0. The time T0 refers to the moment when the BMC 110 performs the operation of acquiring the time T0, and the time T0 can specifically indicate information such as year, month, date, hour, minute, or second. The above-mentioned other servers may be servers 300 whose time has been calibrated.

Step 402: BMC110 writes time T0 into time register 1301 of CPLD130.

The BMC110 can write the time T0 into the time register 1301 of the CPLD130 through the BMC interface 1303.

Step 403: The counter 1302 in the CPLD 130 can start timing based on the time T0, record the timing result, and update the time register 1301 according to the time T0 and the timing result.

The counter 1302 will keep timing and continue to update the time register 1301 (that is, the counter 1302 will continue to update the time stored in the time register 1301), so that the time stored in the register is the current time, so that the server 100 and the NTP server 200 record The time remains consistent.

When the counter 1302 updates the time stored in the time register 1301, a preset threshold can be set. When the timing result reaches the preset threshold, the counter 1302 updates the time stored in the time register 1301; for the counter 1302, the timing method is different, the recorded timing The results are also different. For example, the counter 1302 can count by accumulating the time value, or it can record the number of counts, and count by accumulating the product of the number of counts and the counting interval. Other methods can also be used. The embodiment of the application is not limited For different timing modes, the time stored in the update register of the counter 1302 is different. Two of them are listed below:

Manner 1: The counter 1302 can update the time register 1301 at a preset time interval.

When the timing result of the counter 1302 is a time value, for example, the timing result may be the time length elapsed after the counter 1302 obtains the time T0. When the time length reaches the preset time interval, the time T0 can be added to the time value generated by the time length as The time T1 is updated to the time register 1301.

Exemplarily, if T0 is 9:00, the time interval is 5 seconds; the counter 1302 starts timing after obtaining T0 from the time register 1301, and when the time recorded by the clock circuit or pulse signal of the counter 1302 reaches 5 seconds, you can change Accumulate 5 seconds at 9:00 to get 9:05, and update 9:05 to time register 1301; then use a similar method to update time register 1301, for example, counter 1302 starts after 9:05 is obtained from time register 1301 For timing, for example, when the time recorded by the clock circuit of the counter 1302 or the pulse signal S1 reaches 5 seconds, 9:05 can be accumulated for 5 seconds to obtain 9:10, and 9:10 can be updated to the time register 1301. In the above manner, the counter 1302 can update the time stored in the time register 1301, and the time stored in the time register 1301 can be the real time at the current moment.

Manner 2: The counter 1302 can update the time register 1301 according to the preset maximum count times.

When the timing result of the counter 1302 is the number of counts, for example, the timing result can be the number of counts after the counter 1302 obtains the time T0. For example, taking one time per second as an example, the count result can be 5 times, which means that the counter 1302 counted after obtaining the time T0 Five times, indicating that the time elapsed after the counter 1302 acquires the time T0 is 5*1 seconds. When the count number reaches the preset maximum count number, the time T0 can be accumulated to the time value generated by the duration, as the time T1 is updated to Time register 1301.

Exemplarily, if T0 is 9:00, the maximum number of counts is 5, the counting frequency of counter 1302 is once per second; counter 1302 starts timing after obtaining T0 from time register 1301, for example, according to the clock circuit of counter 1302 or The pulse signal is counted. When the number of counts reaches 5, you can accumulate 5*1 seconds at 9:00 to get 9:05, and update 9:05 to the time register 1301; follow up the time register 1301 in a similar way For example, the counter 1302 starts timing after obtaining the time 9:05 from the time register 1301. For example, it can count according to the clock circuit of the counter 1302 or the pulse signal S1. When the count reaches 5 times, 9:05 can be accumulated by 5*1 Second, get 9:10, and update 9:10 in the time register 1301. In the above manner, the counter 1302 can update the time stored in the time register 1301, so that the time stored in the time register 1301 is the real time at the current moment.

In the second method, the manner in which the counter 1302 determines that the timing result reaches the preset maximum number of counts is not limited in the embodiment of the present application. For example, the counter 1302 can record the number of counts, and each time it counts, it will increase by one by comparing the recorded count number with The maximum number of counts determines whether the count result reaches the preset maximum number of counts; for example, the counter 1302 can maintain the count value, and the initial set value of the count value is the maximum number of counts. The counter 1302 can decrement the count value every time it counts. 1. When the count value is reduced to zero, it is determined that the count result reaches the preset maximum count times.

It should be noted that the process of obtaining the time T0 by the BMC110 and writing the time T0 into the time register 1301 takes a period of time. That is, the current time when the BMC110 writes the time T0 into the time register 1301 is not the time T0, and It is a moment after time T0; in order to ensure that the time register 1301 can more accurately record the real-time time of the current moment, the counter 1302 can increase the time length △T1 on the basis of the time T0 after acquiring the time T0, that is to say When the counter 1302 gets the time T0 and updates the time register 1301 for the first time, it can increase the duration △T1 on the basis of the accumulated result of the time T0 and the timing result, generate the time T1, and write it into the time register 1301. The duration △T1 can be estimated The BMC110 obtains the time T0 and writes the time T0 into the duration of the time register 1301, which can also be an empirical value. Optionally, after the counter 1302 updates the time register 1301 for the first time, each subsequent time the time register 1301 is updated, it can also increase the duration △T2 on the basis of the accumulated result of the time obtained from the time register 1301 and the timing result. The accumulated result of the time length ΔT2 is updated to the time register 1301. The time length ΔT2 can be the estimated time length obtained by the counter 1302 from the time register 1301, or an empirical value.

In a possible implementation manner, after the BMC110 obtains the time T0, it can also use the clock circuit in the BMC110 to perform timing and record the timing result. The timing result is the real-time time recorded by the BMC110. For the BMC110 timing based on T0, refer to the counter 1301 The timing method is not repeated here. BMC110 can use the timing results recorded by BMC110 to update the time stored in the time register 1301 in CPLD130. The counter 1302 in CPLD130 then counts based on the updated time of BMC110. . This ensures that the time stored in the CPLD130 can be consistent with the time recorded by the BMC110, and the accuracy of the time stored in the CPLD130 is improved.

It should be noted that the BMC110 uses the timing results recorded by the BMC110 to update the time stored in the time register 1301 in the CPLD130 at regular intervals; in order to ensure that the time register 1301 can more accurately record the real-time time at the current moment, the counter 1302 can be After BMC110 updates the time stored in the time register 1301, obtain the time T2 stored in the time register 1301, and increase the duration △T3 on the basis of the obtained time T2, which means that the counter 1302 updates the time for the first time after the time stored in the BMC110 update time register 1301 When register 1301, you can increase the duration △T3 on the basis of the accumulated result of the acquired time T2 and the timing result, generate the current real-time time T3, and write it into the time register 1301. The duration △T3 can be the estimated time written by BMC110 The time required to enter the time register 1301 may also be an empirical value.

The embodiment of the present application does not limit the specific numerical values of the duration ΔT1, the duration ΔT2, and the duration ΔT3. The duration ΔT1, the duration ΔT2, and the duration ΔT3 can be the same or different.

Step 404: In the second stage of the server 100 startup, the processor 120 is powered on, and the processor 120 can read the time from the CPLD130 (such as the time register 1301 in the CPLD130) through the processor interface 1304, and the time is the current time stored by the CPLD130 time.

In the embodiment of the present application, when the processor 120 reads the time from the CPLD130, the current time stored in the time register 1301 in the CPLD130 is T1 as an example. T1 indicates that the processor 120 can read the time from the CPLD130, and the CPLD130 is updated recently time.

After the processor 120 is powered on, the time T1 can be read from the CPLD 130, and the subsequent BMC 110 may not update the time stored in the CPLD 130. Exemplarily, the BMC 110 may not update the time stored in the CPLD 130 after sending a control instruction to control the main power to supply power to the processor 120.

The CPLD 130 may also stop timing after the processor 120 obtains the time T1 and stop updating the time register 1301.

Step 405: After obtaining the time T1, the processor 120 performs timing based on the time T1, records the real-time time, and performs operations such as data synchronization and log recording based on the recorded real-time time.

In the third stage when the server 100 is started, the processor 120 may communicate with the NTP server 200 or the time-calibrated server 300 to obtain the real-time time and update the timing result saved by the current processor 120.

As a possible embodiment, the embodiment shown in FIG. 4 can also be applied to the system architecture shown in FIG. 2. The difference is that in step 401, the BMC 110 needs to obtain the time T0 from the manager 400, and the manager 400 can obtain the time T0 from a server outside the system (such as the NTP server 200 or the time-calibrated server 300). In this way, in a multi-server scenario, there is no need to set RTC circuits in each server, and it can also ensure time synchronization and obtain real-time time, which can effectively reduce the PCB area occupied by the RTC circuit in the server and reduce the server hardware. Cost, more components can be set on the PCB of the server, which is beneficial to improve the performance of the server.

In addition, in a traditional time synchronization system, the RTC circuit includes an RTC chip and a power supply. The power supply in the RTC circuit can supply power to the RTC chip. The RTC power supply connected to the processor is also used to control the platform controller in the processor. hub, PCH) power supply, used to ensure that the data saved in the PCH is not lost when the server is powered off. PCH is used to store user configuration data, such as the user configuration data for the processor 120 to start (such as the second stage, the third stage) Required information. Exemplarily, these user configuration data include, but are not limited to, the processor's high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe) port bandwidth setting, OS boot area setting (such as hard disk boot, CD drive boot). When using the technical solution of the present application to cancel the RTC circuit, it is necessary to consider how to save the user configuration data stored in the original PCH. When the server is powered off, the user configuration data will not be lost. As a possible embodiment, these user configuration data may be stored in a storage medium in the server 100. The storage medium may be a non-volatile storage medium. For example, the storage medium may be a BIOS flash memory (Flash), or may have other power supplies. The storage medium maintained by the power supply and the data will not be lost when the server 100 is powered off. The processor 120 can read the user configuration data from the storage medium when entering the second stage of the server 100 startup. It is ensured that when the server 100 is not provided with a PTC circuit, the processor 120 in the server 100 can still obtain the user configuration data and can start normally, which ensures the normal performance of the server.

As a possible embodiment, in addition to the system architectures shown in Figures 1 and 2 provided by the embodiments of this application, the invention of this application can also be used in other system architectures. The extended system architecture can use other than CPLD The other components or logic circuits of the following methods implement the CPLD function. For example, there is a logic circuit in the server, which can communicate with the BMC and the processor, and confirm and record the current time T1 based on the acquired time T0 Correspondingly, the processor can obtain the time T1 through the logic circuit, and calculate the time at the current moment based on the time T1, so as to implement the configuration of the log and other information during the OS startup process.

The foregoing describes in detail the time synchronization method provided by the embodiment of the present application with reference to Figs. 1 to 4, and the following further describes the time synchronization apparatus and server provided by the embodiment of the present application with reference to Figs. 5 and 6.

5 is a time synchronization device provided by an embodiment of the application. As shown in the figure, the device includes a management unit 510, a timing unit 520, and a processing unit 530. The timing unit 520 includes a storage unit 521, and the storage unit 521 is used for storing Current time

The management unit 510 is configured to store the obtained first time in the storage unit 521, and the first time is used to indicate the moment of the operation of obtaining the first time; the management unit 510 may be used to perform the steps in the embodiment shown in FIG. 4 401.

The timing unit 520 is used to start timing and record the timing result; when the timing result reaches a preset threshold, the second time is determined according to the first time and the timing result; the storage unit 521 is updated according to the second time. The management unit 510 may be used to execute steps 402 to 403 in the embodiment shown in FIG. 4.

Optionally, the management unit 510 and the timing unit 520 may communicate through a first interface; when the management unit 510 stores the acquired first time in the storage unit 521, the first time may be stored in the storage unit 521 through the first interface.

Optionally, the device further includes a processing unit 530, and the processing unit 530 and the timing unit 520 can communicate through a second interface:

The processing unit 530 may read the second time from the storage unit 521 through the second interface, and based on the second time, start timing and record the real-time time. The processing unit 530 may be used to execute steps 404 to 405 in the embodiment shown in FIG. 4.

Optionally, the timing mode of the timing unit 520 is different, and the timing result is also different. Two of them are listed below:

Manner 1: The timing unit 520 performs timing by accumulating time values. In this manner, the timing result is a time value, and the preset threshold indicates the time interval for updating the storage unit 521 of the timing unit 520.

Manner 2: The timing unit 520 records the count times and performs timing by accumulating the product of the count times and the counting interval. In this manner, the timing result is the count times, and the preset threshold indicates the maximum count times of the timing unit 520.

Optionally, when the timing unit 520 determines the second time according to the first time and the timing result, the second time may be determined according to the accumulation result of the first time and the timing result.

Optionally, when obtaining the first time, the management unit 510 may obtain the first time from an NTP server, or obtain the first time from a server whose time has been calibrated.

It should be understood that the time synchronization device in the embodiment of the present application can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The above PLD can be a complex program logic. Device (complex programmable logical device, CPLD), field-programmable gate array (field-programmable gate array, FPGA), general array logic (generic array logic, GAL) or any combination thereof. When the time synchronization method shown in FIG. 4 can also be implemented by software, the time synchronization device and its various modules can also be software modules.

The time synchronization device according to the embodiment of the present application can correspond to the method described in the embodiment of the present invention, and the above and other operations and/or functions of each unit in the time synchronization device are to implement the corresponding methods in FIG. 4 For the sake of brevity, the process will not be repeated here.

FIG. 6 is a schematic diagram of a server structure provided by an embodiment of the application. As shown in the figure, the server 600 includes a BMC 610, a processor 620, and a CPLD 630.

Optionally, the server 600 may further include a memory 640, a communication interface 650, and a storage medium 660.

The BMC610, the processor 620, the CPLD630, the communication interface 650, and the storage medium 660 are connected by a bus 670.

The processor 620 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or artificial intelligence (AI). ) Chip, system on chip (system on chip, SoC) or complex programmable logic device (CPLD), graphics processing unit (GPU), this application does not limit the type and number of processors .

The memory 640 is used to store computer program instructions. It can be a volatile memory, such as a random access memory; it can also be a non-volatile memory, such as a read-only memory, flash memory, hard disk drive (HDD) or solid state drive ( solid-state drive, SSD), etc.

In the embodiment of the present application, the storage medium 660, also called external storage, may be used to store data required for the operation of the server. The storage medium may be a non-volatile memory, such as a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape) , Optical media (such as optical discs), or semiconductor media (such as solid state drives), etc.

In addition to the data bus, the bus 670 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are marked as the bus 670 in the figure.

As a possible embodiment, CPLD630 can also realize the connection between BMC610 and processor 620 through other types of internal buses. The internal bus includes link control protocol (LCP), local bus, and I2C bus. (inter-integrated circuit) or serial peripheral interface (serial peripheral interface, SPI) bus connection.

In the server 600 as shown in FIG. 6, an independent data transceiving module, such as a communication interface 650, can also be provided for sending and receiving data; when the BMC 610 or processor 620 communicates with other devices, data can be performed through the communication interface 650. For transmission, as in the embodiment of the present application, the BMC 610 can obtain the first time from the NTP server 200 or the time-calibrated server 300 through the communication interface 650.

When the server adopts the form shown in FIG. 6, the processor 620 in FIG. 6 can call the computer program instructions in the memory 640 to execute the method executed by the processor 120 in FIG. 4; the BMC 610 executes the method executed by the BMC 110 in FIG. method. The CPLD630 can perform the method performed by the CPLD130 in Figure 4.

Specifically, the memory 640 stores computer-executable instructions for implementing the functions of the processing unit in FIG. 5, and the functions/implementation processes of the processing unit in FIG. 5 can all be called by the processor 620 in FIG. 6 stored in the memory 640. The computer executes instructions to achieve.

It should be understood that the server according to the embodiment of the present application may correspond to the time synchronization device in the embodiment of the present application, and may correspond to the corresponding main body that executes the method shown in FIG. 4 according to the embodiment of the present application, and each module in the server The above-mentioned and other operations and/or functions are used to implement the corresponding procedures of each method in FIG. 4, and are not repeated here for brevity.

The foregoing embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above-mentioned embodiments may be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on the computer, the processes or functions according to the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website site, computer, server or data center via wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more sets of available media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium may be a solid state drive (SSD).

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

The above are only specific embodiments of the present invention. Those skilled in the art can think of changes or substitutions according to the specific implementation manners provided by the present invention, which should all fall within the protection scope of the present invention.

Claims

A time synchronization method, characterized in that the method includes:

The baseboard management controller BMC stores the obtained first time in the time register of the complex programmable logic circuit CPLD; the time register is used to store the time at the current moment; the first time is used to indicate the operation of obtaining the first time The moment; the BMC is connected to the CPLD;

The CPLD starts timing and records a timing result, and when the timing result reaches a preset threshold, the CPLD determines a second time according to the first time and the timing result;

The CPLD updates the time register according to the second time.
The method of claim 1, wherein:

The connection between the BMC and the CPLD includes: the BMC and the CPLD communicate through a first interface;

Then the BMC stores the obtained first time in the time register of the CPLD, including:

The BMC stores the first time in a time register of the CPLD through the first interface.
The method of claim 1, wherein:

The processor communicates with the CPLD through a second interface, and the method further includes:

The processor reads the second time from the time register through the second interface;

The processor starts timing and records real-time time based on the second time.
The method of claim 1, wherein the timing result is a time value, and the preset threshold value indicates a time interval for the CPLD to update the time register; or

The timing result is the number of counts, and the preset threshold value indicates the maximum number of counts of the CPLD.
The method of claim 4, wherein the CPLD determining the second time according to the first time and a timing result comprises:

The CPLD determines the second time according to the accumulation result of the first time and the timing result.
The method according to claim 1, wherein the acquiring the first time by the BMC comprises:

The BMC obtains the first time from a network time protocol NTP server or another server that has completed time calibration.
A server, characterized in that the server includes a baseboard management controller BMC and a complex programmable logic circuit CPLD, the BMC is connected to the CPLD, and the CPLD includes a time register, and the time register is used to store the current time time;

The BMC is configured to store the acquired first time in the time register, and the first time is used to indicate the time of the operation of acquiring the first time;

The CPLD is used to start timing and record the timing result; when the timing result reaches a preset threshold, determine a second time according to the first time and the timing result; update the time according to the second time register.
8. The server of claim 7, wherein the BMC communicates with the CPLD through a first interface;

The BMC is also used to store the first time in the time register through the first interface.
8. The server according to claim 7, wherein the server further comprises a processor, and the processor communicates with the CPLD through a second interface;

The processor is configured to read the second time from the time register through a second interface, and based on the second time, start timing and record real-time time.
The server according to claim 7, wherein:

The timing result is a time value, and the preset threshold value indicates the time interval for the CPLD to update the time register; or

The timing result is the number of counts, and the preset threshold value indicates the maximum number of counts of the CPLD.
The server of claim 10, wherein:

The CPLD is also used to determine the second time according to the accumulation result of the first time and the timing result.
The server according to claim 7, wherein:

The BMC is also used to obtain the first time from a network time protocol NTP server or a time-calibrated server.