WO2020258683A1 - 太阳能电池及其制作方法 - Google Patents

太阳能电池及其制作方法 Download PDF

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WO2020258683A1
WO2020258683A1 PCT/CN2019/118909 CN2019118909W WO2020258683A1 WO 2020258683 A1 WO2020258683 A1 WO 2020258683A1 CN 2019118909 W CN2019118909 W CN 2019118909W WO 2020258683 A1 WO2020258683 A1 WO 2020258683A1
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Prior art keywords
silicon substrate
solar cell
grid
main
fine
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PCT/CN2019/118909
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English (en)
French (fr)
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李华
童洪波
张洪超
刘继宇
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泰州隆基乐叶光伏科技有限公司
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Priority to AU2019453945A priority Critical patent/AU2019453945B2/en
Priority to US17/622,212 priority patent/US20220320355A1/en
Priority to EP19935146.1A priority patent/EP3979332A4/en
Publication of WO2020258683A1 publication Critical patent/WO2020258683A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022433—Particular geometry of the grid contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1864—Annealing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells

Definitions

  • This application generally relates to the technical field of solar photovoltaic power generation, and specifically relates to a solar cell and a manufacturing method thereof.
  • Crystalline silicon solar cells have become the solar cells with the highest market share due to their high energy conversion efficiency. How to improve the photoelectric conversion efficiency of crystalline silicon solar cells while reducing their production costs is the biggest problem facing the industry. How to improve the efficiency of solar cells by providing a novel solar cell structure or a novel solar cell manufacturing process to enhance the advantages of solar energy as an alternative energy source is an important research direction in this field.
  • the metallization process of solar cells is usually realized by screen printing silver paste.
  • the precision of screen printing is limited, and the printed electrode topography fluctuates.
  • screen printing is used The contact resistance between the electrode and the silicon substrate is large, and the large amount of silver paste makes the production cost high.
  • this application provides a solar cell including a silicon substrate
  • a plurality of fine gates are deposited on the silicon substrate, and the fine gates are in ohmic contact with the silicon substrate;
  • a plurality of main grids are provided on the silicon substrate; the main grids intersect with the thin grids and are in electrical contact;
  • At least part of the main grid is formed by sintering electrode paste.
  • each of the main grids includes alternately arranged first electrode bodies and second electrode bodies, the first electrode bodies are formed by sintering electrode paste, and the second electrode bodies are formed by deposition.
  • the first electrode body is a pad
  • the second electrode body is a connecting gate line connecting the fine gate
  • the width of the connecting gate line is less than or equal to the width of the pad.
  • the number of the pads in each main grid is 2-20.
  • the fine grid includes two or more metal layers stacked.
  • a front surface dielectric layer is formed on the front surface of the silicon substrate, the main gate is formed on the front surface dielectric layer, and the main gate is at least partially sintered to penetrate the front surface dielectric layer;
  • the back surface of the silicon substrate is formed with a back surface dielectric layer
  • the main gate is formed on the back surface dielectric layer
  • the main gate is at least partially sintered to penetrate the back surface dielectric layer.
  • the thin grid and the main grid both extend along a straight line, and the thin grid is perpendicular to the main grid.
  • this application provides a method for manufacturing the above-mentioned solar cell, which includes the following steps:
  • the printed electrode paste is sintered to sinter the electrode paste to form at least part of the main grid.
  • the deposition is selected from any one or a combination of two or more of laser transfer, electroless plating, sputtering, electrodeposition, physical vapor deposition, chemical vapor deposition and atomic layer deposition.
  • the annealing temperature is 300°C-900°C; the sintering temperature is 700°C-1000°C.
  • the temperature of the heat treatment is 500°C-900°C.
  • the deposition is electrodeposition; before the electrodeposition, the step of sintering the silicon substrate printed with the electrode paste is first performed; in the electrodeposition process, at least part of the main grid formed by sintering serves as The contact plated without the seed layer is connected to the negative electrode of the power supply.
  • the main grid includes alternately arranged pads and connecting gate lines; the width of the connecting gate lines is less than or equal to the width of the pads; during the electrodeposition process, the pads serve as seedless The contact of the layer plating is connected to the negative pole of the power supply.
  • the above scheme through the combination of high-temperature metallization (sintering) and low-temperature metallization (deposition) to form the thin grid and the main grid, overcomes the problem of high cost caused by the use of screen printing silver paste.
  • the thin The gate forms an ohmic contact with the silicon substrate, which has the advantages of low contact resistance and high current collection efficiency.
  • FIG. 1 is a schematic structural diagram of a solar cell provided by an embodiment of the application.
  • FIG. 2 is a flowchart of a method for manufacturing a solar cell provided by the first embodiment of the application
  • FIG. 3 is a flowchart of a method for manufacturing a solar cell provided by the second embodiment of the application.
  • the solar cell provided by the present application includes a silicon substrate 1.
  • the silicon substrate 1 is prepared by, for example, but not limited to, the following processes.
  • the silicon wafers are sequentially cleaned, textured, textured diffusion, edge etched, and removed. Phosphosilicate glass, etc.
  • a plurality of thin gates 2 are deposited on the silicon substrate 1, and the thin gates 2 are in ohmic contact with the silicon substrate 1.
  • the fine grids are linear, and the fine grids are arranged in parallel.
  • the thin grid may also be an arc, a broken line or a curve.
  • a plurality of main grids are formed on the silicon substrate 1, and the main grids intersect and electrically contact the fine grids, wherein at least part of the main grids is formed by sintering electrode paste.
  • the width of the main grid is larger than the width of the fine grid 2.
  • the fine grid 2 is used to collect the current generated by the solar cell.
  • the main grid is used to collect the current collected by the fine grid 2 and to interconnect the cells.
  • the above solution uses a combination of high-temperature metallization (sintering) and low-temperature metallization (deposition) to form the fine grid 2 and the main grid, which overcomes the problem of high cost caused by the use of screen printing silver paste
  • the fine gate 2 and the silicon substrate 1 due to the ohmic contact between the fine gate 2 and the silicon substrate 1, it has the advantages of low contact resistance and high current collection efficiency.
  • each main grid includes a first electrode body 3 and a second electrode body 4 alternately arranged in sequence, and the first electrode body 3 is formed by sintering electrode paste.
  • the second electrode body 4 is formed by deposition; this solution can minimize the amount of electrode paste (such as but not limited to silver paste) used to reduce production costs.
  • the first electrode body 3 and the second electrode body 4 alternately arranged in this article can be understood as a first electrode body 3 electrically connected to a second electrode body 4, and the second electrode body 4 is electrically connected to another one.
  • the first electrode body 3, the other first electrode body 3 is electrically connected to another second electrode body 4, and so on.
  • the first electrode body 3 is a pad
  • the second electrode body 4 is a connecting grid line that connects the thin grid 2.
  • the width of the connecting grid line is less than or equal to the width of the pad, and the pad is formed by sintering the electrode paste
  • the electrode paste can be silver paste, and the corresponding sintered formed silver pad, and the width of the pad is the widest in the main grid, so it has the advantage of good welding performance.
  • each bus grid has 4 pads.
  • the foregoing deposition includes any one or a combination of any two or more of laser transfer, electroless plating, sputtering, electrodeposition, physical vapor deposition, chemical vapor deposition, and atomic layer deposition.
  • the fine grid 2 includes two or more metal layers stacked.
  • the two or more metal layers can be deposited by the same process, or can be deposited by different processes.
  • it includes two metal layers, the first layer is electroless plating, and the second layer is electrodeposited; or the first layer is atomic layer deposition or physical vapor deposition, and the second layer is electrodeposited; or the first layer is sputtering or laser For transfer, the second layer is electrodeposited, and so on.
  • the fine gate 2 can adopt any one of the following metal layered structures, for example but not limited to: Ni layer/Ag layer, Co layer/Ag layer, Ni layer/Cu layer, Co layer/Cu layer, Ni layer/Cu layer /Sn layer, Co layer/Cu layer/Sn layer, Ni layer/Cu layer/Ag layer, or Co layer/Cu layer/Ag layer.
  • the front surface of the silicon substrate may also be formed with a front surface dielectric layer.
  • the main grid is formed on the front dielectric layer, and the main grid is at least partially sintered to penetrate the front dielectric layer. Since an ohmic contact is formed between the fine gate and the silicon substrate, the front dielectric layer is opened on the corresponding part of the fine gate, that is, the fine gate is deposited on the front dielectric layer to expose the part of the silicon substrate.
  • the back surface of the silicon substrate may also be formed with a back surface dielectric layer.
  • the backside dielectric layer is present, the main grid is formed on the backside dielectric layer, and the main grid is at least partially sintered to penetrate the backside dielectric layer. Since an ohmic contact is formed between the fine gate and the silicon substrate, the back dielectric layer is opened on the corresponding part of the fine gate, that is, the fine gate is deposited on the front dielectric layer to expose the part of the silicon substrate.
  • the main gate does not have to be in ohmic contact with the silicon substrate, so the main gate can also be selected from non-fire-through paste.
  • the thin grid 2 and the main grid both extend along a straight line, and the thin grid 2 is perpendicular to the main grid. This structure is convenient for processing and has a strong current collecting ability.
  • the present application provides a method for manufacturing the solar cell of the above embodiment, including the following steps:
  • the deposition is selected from any one or a combination of any two or more of laser transfer, electroless plating, sputtering, electrodeposition, physical vapor deposition, chemical vapor deposition, and atomic layer deposition.
  • the fine gate 2 formed by deposition can be a single metal layer or a stacked multi-layer metal layer. In the case of a multi-layer metal layer, it is formed by multiple deposition processes.
  • the deposition process can be any of the above , Or any combination of two or more.
  • the fine gate 2 can adopt any one of the following metal layered structures, for example but not limited to: Ni layer/Ag layer, Co layer/Ag layer, Ni layer/Cu layer, Co layer/Cu layer, Ni layer/Cu layer /Sn layer, Co layer/Cu layer/Sn layer, Ni layer/Cu layer/Ag layer, or Co layer/Cu layer/Ag layer.
  • the electrode paste is screen printed on the silicon substrate.
  • multiple electrode pastes can be printed, or multiple dot-shaped electrode pastes can be printed.
  • a part of the main grid is formed by sintering in the following step S30.
  • S30 Heat the silicon substrate to make the fine grid and the silicon substrate form an ohmic contact, while sintering the electrode paste to form at least part of the main grid.
  • step S10 may be performed first and then the above step S20 may be performed, or the above step S20 may be performed and then the above step S10 may be performed.
  • the metal at the bottom of the fine gate and the silicon in the silicon substrate form a metal silicide, and an ohmic contact is formed between the fine gate and the silicon substrate.
  • the ohmic contact has the advantages of low contact resistance and high current collection efficiency.
  • the electrode paste is sintered in the heat treatment to form the main grid. Since the ohmic contact between the fine grid and the silicon substrate and the firing of the electrode paste into the main grid are completed in the same heat treatment, the process flow is simplified, the damage and performance of the cell caused by the high temperature process are reduced, and the Form the thermal budget of the fine grid and the main grid.
  • the temperature of the heat treatment is 500°C-900°C.
  • the heat treatment is, for example, but not limited to, annealing, and the above heat treatment can be performed in an annealing furnace.
  • the manufacturing method of the solar cell provided by another embodiment of the present application includes the following steps:
  • the annealing temperature can be 300°C-900°C.
  • the annealing time can vary from a few seconds to a few minutes, depending on the annealing temperature and process requirements.
  • the contact material of the main gate and the silicon substrate is nickel (when the main gate is a single-layer structure, the main gate is a nickel metal layer; when the main gate is a multilayer structure, the lowermost layer of the main gate is nickel metal Layer), the annealing temperature can be 370°C, and the annealing time can be 3 minutes.
  • the contact material of the main gate and the silicon substrate is cobalt
  • the annealing temperature is 500° C.
  • the annealing time is 30 s.
  • Good ohmic contacts can be formed under different annealing temperatures and annealing times.
  • the material contacting the main gate and the silicon substrate is nickel, low-resistance nickel silicide (NiSi) is formed after annealing; for the case where the material contacting the main gate and the silicon substrate is cobalt, the low-resistance cobalt silicide is formed after annealing (CoSi2).
  • the annealing temperature may be 500°C-900°C.
  • the electrode slurry forming the first electrode body is a low-temperature electrode slurry, and the sintering temperature of the low-temperature electrode slurry is between 550°C and 600°C.
  • Annealing can be divided into one annealing and two annealing. If it is two annealing, the annealing temperature of the latter one is required to be higher than the annealing temperature of the previous one. In one embodiment, two annealings are used to form low-resistance nickel silicide. The first annealing temperature is 260°C-310°C for 30 seconds, and the second annealing temperature is 400°C-500°C for 30 seconds. In another embodiment, two annealings are used to form cobalt silicide, and the first annealing temperature is 400°C-550°C, and the second annealing temperature is 700°C-850°C. Two annealing can effectively inhibit ion diffusion, reduce damage to the silicon substrate, and form a silicide film with low resistivity and uniform properties between the main grid and the silicon substrate, and the morphology between the metal silicide and the silicon substrate is smooth.
  • S21 Sintering the printed electrode paste to sinter the electrode paste to form at least part of the main grid.
  • the sintering temperature can be, but is not limited to, 700°C-1000°C.
  • sintering the electrode paste can be carried out by placing the entire silicon substrate printed with the electrode paste in a sintering furnace for sintering, or locally sintering the electrode paste printing area by means such as laser.
  • laser heating can be used to direct the laser beam to the electrode paste to perform local heating and curing of the electrode paste.
  • the laser beam may have a pulse duration in the range of 1 nanosecond to 10 milliseconds.
  • the laser beam can be emitted by a continuous wave laser or a pulsed laser.
  • the laser beam has a wavelength in the range of 100 nanometers to 2000 nanometers.
  • the deposition may be electrodeposition; before electrodeposition, the step of sintering the printed electrode paste is performed; during the electrodeposition process, at least part of the main grid formed by sintering is electroplated without a seed layer The contact is connected to the negative pole of the power supply.
  • the seed-free electroplating mentioned in this article means that there is no need to form a seed layer at the corresponding positions where the fine grid and the main grid are formed before electroplating. In this way, seed layer-free electroplating can be realized.
  • the previous sintering step provides contacts for subsequent electrodeposition and simplifies the process steps.
  • the main grid includes alternately arranged pads and connecting gate lines; the width of the connecting gate lines is less than or equal to the width of the pads; in the electrodeposition process, the pads are connected to the negative electrode of the power supply as contacts without seed layer plating.
  • the pad may be a part of the main grid formed by sintering dot-shaped electrode paste, and the connecting gate line may be a metal layer deposited between adjacent pads.
  • connection grid lines are formed at intervals by deposition, and then a dot-shaped electrode paste is formed between two adjacent connection grid lines by screen printing. , And then sinter the electrode paste.
  • the dielectric layer can be formed on the surface of the silicon substrate by deposition.
  • any one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon carbide, amorphous silicon and polysilicon can be used. Or any combination to form a dielectric layer.
  • the dielectric layer is patterned to form a plurality of thin gate forming opening regions exposing the silicon substrate, and at least one main grid forming opening region exposing the silicon substrate is formed, and the fine grid forming opening regions are formed
  • the area intersects the main grid forming opening area.
  • the thin gate forming area is used for deposition to form the thin gate, and the main gate forming area is used to form the main grid.
  • patterning for example, but not limited to, can adopt an etching method.
  • a plurality of electrode pastes for forming the first electrode body are printed at intervals in the open film area of the main grid forming, and the electrode paste is sintered (for example, a partial sintering method), and the electrode paste is sintered to form a second An electrode body forms an ohmic connection with the silicon substrate.
  • bus grid pattern can also be used; a plurality of bus grid forming belts are formed, each of the bus grid forming belts includes a plurality of second electrode body forming opening regions, each of the second The open film area of the electrode body is exposed to the silicon substrate, and the open film area of the fine grid is intersected with the main grid forming belt.
  • any reference signs placed between parentheses should not be constructed as a limitation to the claims.
  • the word “comprising” does not exclude the presence of elements or steps not listed in the claims.
  • the word “a” or “an” preceding an element does not exclude the presence of multiple such elements.
  • the application can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims enumerating several devices, several of these devices may be embodied by the same hardware item.
  • the use of the words first, second, and third, etc. do not indicate any order. These words can be interpreted as names.

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Abstract

一种太阳能电池及其制作方法，其中，太阳能电池，包括硅基底，硅基底上沉积有多条细栅，所述细栅与所述硅基底欧姆接触；所述硅基底上设置有多条主栅；所述主栅与所述细栅相交且电接触；所述主栅的至少部分通过烧结电极浆料形成。上述方案，通过高温金属化(烧结)和低温金属化(沉积)相结合的方式来形成细栅和主栅，克服了采用丝网印刷银浆所带来的成本高，此外，由于细栅与硅基底欧姆接触，具有接触电阻小，电流收集效率高的优点。

Description

太阳能电池及其制作方法
本申请要求在2019年06月24日提交中国专利局、申请号为201910548291.0、发明名称为“太阳能电池及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请一般涉及太阳能光伏发电技术领域，具体涉及一种太阳能电池及其制作方法。
背景技术
晶体硅太阳电池由于其能量转换效率高，已成为目前市场占有率最高的太阳能电池。如何提高晶体硅太阳电池的光电转换效率的同时降低其生产成本是业界面临的最大难题。如何通过提供新颖的太阳能电池结构或提供新颖的太阳能电池制造工艺，用于提高太阳能电池效率，以增强太阳能作为替代能源的优势，是本领域的重要研究方向。
目前大规模的硅太阳电池制造中，通常采用丝网印刷银浆的方式来实现太阳电池的金属化制程，但丝网印刷的精度有限，印刷的电极形貌高低起伏，另外丝网印刷制成的电极与硅基底之间的接触电阻较大，并且大量采用银浆使得生产成本高。
发明内容
鉴于现有技术中的上述缺陷或不足，期望提供一种太阳能电池及其制作方法用以降低电极与硅基底之间的接触电阻，并降低生产成本。
第一方面，本申请提供一种太阳能电池，包括硅基底，
所述硅基底上沉积有多条细栅，所述细栅与所述硅基底欧姆接触；
所述硅基底上设置有多条主栅；所述主栅与所述细栅相交且电接触；
所述主栅的至少部分通过烧结电极浆料形成。
优选地，每条所述主栅包括交替设置的第一电极体和第二电极体，所述第一电极体通过烧结电极浆料形成，所述第二电极体通过沉积形成。
优选地，所述第一电极体为焊盘，所述第二电极体为连接所述细栅的连接栅线，所述连接栅线的宽度小于或等于所述焊盘的宽度。
优选地，每条所述主栅中所述焊盘的个数为2-20个。
优选地，所述细栅包括层叠设置的两层以上金属层。
优选地，所述硅基底的正面形成有正面介电层，所述主栅形成于所述正面介电层上，且所述主栅至少部分烧结穿透所述正面介电层；
和/或，
所述硅基底的背面形成有背面介电层，所述主栅形成于所述背面介电层上，且所述主栅至少部分烧结穿透所述背面介电层。
优选地，所述细栅及所述主栅均沿直线延伸，且所述细栅垂直于所述主栅。
第二方面，本申请提供一种上述的太阳能电池的制作方法，包括以下步骤：
在硅基底上沉积形成多条细栅；
在所述硅基底上印刷电极浆料；
对所述硅基底进行热处理，使所述细栅与所述硅基底形成欧姆接触，同时使所述电极浆料烧结形成主栅的至少部分；
或，包括如下步骤：
在所述硅基底上沉积形成多条细栅；
对形成有多条细栅的硅基底进行退火，使所述细栅与所述硅基底形成欧姆接触；
在所述硅基底上印刷电极浆料；
对印刷的所述电极浆料进行烧结，使所述电极浆料烧结形成主栅的至少部分。
优选地，所述沉积选自激光转印、化学镀、溅射、电沉积、物理气相沉积、化学气相沉积和原子层沉积中的任意一种或两种以上的组合。
优选地，所述退火的温度为300℃-900℃；所述烧结的温度为700℃-1000℃。
优选地，所述热处理的温度为500℃-900℃。
优选地，所述沉积为电沉积；在所述电沉积之前，先进行对印刷有电极浆料的硅基底进行烧结的步骤；在所述电沉积过程中，烧结形成的主栅的至少部分作为无种子层电镀的触点与电源负极相连。
优选地，所述主栅包括交替设置的焊盘和连接栅线；所述连接栅线的宽度小于或等于所述焊盘的宽度；在所述电沉积过程中，所述焊盘作为无种子层电镀的触点与电源负极相连。
上述方案，通过高温金属化(烧结)和低温金属化(沉积)相结合的方式来形成细栅和主栅，克服了采用丝网印刷银浆所带来的成本高的问题，此外，由于细栅与硅基底形成了欧姆接触，具有接触电阻小，电流收集效率高的优点。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的太阳能电池的结构示意图；
图2为本申请第一实施例提供的太阳能电池的制作方法的流程图；
图3为本申请第二实施例提供的太阳能电池的制作方法的流程图。
具体实施例
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
如图1所示，本申请提供的太阳能电池，包括硅基底1，硅基底1例如但不限于通过以下工艺制取，依次对硅片进行清洗、制绒、绒面扩散、边缘刻蚀、去除磷硅玻璃等。
硅基底1上沉积多条细栅2，细栅2与硅基底1之间欧姆接触。该实施例中细栅是直线状的，各细栅平行设置。当然，细栅还可以是弧线、折线或曲线等。
硅基底1上形成有多条主栅，主栅与细栅相交且电接触，其中，主栅的至少部分是通过烧结电极浆料形成的。
一般地，主栅的宽度大于细栅2的宽度。细栅2是用于收集该太阳能电池产生的电流的。主栅是用于汇集细栅2收集的电流，以及用于电池片之间的互联。
综上所述，上述方案通过高温金属化(烧结)和低温金属化(沉积)相结合的方式来形成细栅2和主栅，克服了采用丝网印刷银浆所带来的成本高的问题，此外，由于细栅2与硅基底1之间欧姆接触，具有接触电阻小，电流收集效率高的优点。
作为另外一种实现方式，硅基底1上形成多条主栅，每条主栅包括顺次交替设置的第一电极体3和第二电极体4，第一电极体3通过烧结电极浆料形成，第二电极体4通过沉积形成；采用此种方案可以尽最大限度的降低电极浆料(例如但不限于银浆)的使用量，以降低生产成本。本文中的顺次交替设置的第一电极体3和第二电极体4，可以理解为一个第一电极体3电连接一个第二电极体4，该第二电极体4再电连接另外的一个第一电极体3，该另外的第一电极体3再电连接另外一个第二电极体4，依次类推。
进一步地，第一电极体3为焊盘，第二电极体4为连接细栅2的连接栅线，连接栅线的宽度小于或等于焊盘的宽度，焊盘是通过烧结电极浆料形成的，作为其中一个实现方式，电极浆料可以采用银浆，对应的烧结成型银质焊盘，且焊盘的宽度在主栅中是最宽的，因此具有焊接性能好的优点。
进一步地，每条主栅中焊盘的个数为2-20个，具体的焊盘数量可以根据该太阳能电池的尺寸及焊接的点位来确定。如图1所示，每一条主 栅设置了4个焊盘。
作为可实现的方式，上述沉积包括激光转印、化学镀、溅射、电沉积、物理气相沉积、化学气相沉积和原子层沉积中的任意一种或任意两种以上的组合。
进一步地，细栅2包括层叠设置的两层以上金属层。该两层以上的金属层可以通过相同的工艺沉积，也可以通过不同的工艺沉积。例如包括两层金属层，第一层采用化学镀、第二层采用电沉积；或第一层采用原子层沉积或物理气相沉积、第二层采用电沉积；或第一层采用溅射或激光转印，第二层采用电沉积，诸如此类。细栅2例如但不限于可以采用以下的金属层状结构中的任意一种：Ni层/Ag层、Co层/Ag层、Ni层/Cu层、Co层/Cu层、Ni层/Cu层/Sn层、Co层/Cu层/Sn层、Ni层/Cu层/Ag层或Co层/Cu层/Ag层。
进一步地，硅基底的正面还可以形成有正面介电层。当存在正面介电层时，主栅形成于正面介电层上，且主栅至少部分烧结穿透正面介电层。由于细栅与硅基底之间形成欧姆接触，故而正面介电层在细栅对应部分开膜，也就是说，细栅沉积于正面介电层露出硅基底的部分。
同样地，硅基底的背面还可以形成有背面介电层。当存在背面介电层时，主栅形成于背面介电层上，且主栅至少部分烧结穿透背面介电层。由于细栅与硅基底之间形成欧姆接触，故而背面介电层在细栅对应部分开膜，也就是说，细栅沉积于正面介电层露出硅基底的部分。
当然，根据实际情况的不同，主栅不一定要与硅基底欧姆接触，故而主栅也可以选自非烧穿浆料。
进一步地，细栅2及主栅均沿直线延伸，且细栅2垂直于主栅，采用此种结构便于加工，且电流收集能力强。
第二方面，如图2所述，本申请提供一种上述实施例的太阳能电池的制作方法，包括以下步骤：
S10：在硅基底上沉积形成多条细栅；
例如但不限于，沉积选自激光转印、化学镀、溅射、电沉积、物理气相沉积、化学气相沉积和原子层沉积中的任意一种或任意两种以上的组合。沉积形成的细栅2可以是单层金属层，也可以是堆叠设置的多层 金属层，在为多层金属层时，是通过多次沉积工艺形成，沉积的工艺可以是上述的任一种，或任意两种以上的组合。
例如包括两层金属层，第一层采用化学镀、第二层采用电沉积；或第一层采用原子层沉积或物理气相沉积、第二层采用电沉积；或第一层采用溅射或激光转印，第二层采用电沉积，诸如此类。细栅2例如但不限于可以采用以下的金属层状结构中的任意一种：Ni层/Ag层、Co层/Ag层、Ni层/Cu层、Co层/Cu层、Ni层/Cu层/Sn层、Co层/Cu层/Sn层、Ni层/Cu层/Ag层或Co层/Cu层/Ag层。
S20：在硅基底上印刷电极浆料；
在硅基底上通过丝网印刷电极浆料，例如但不限于可以印刷多条电极浆料，也可以印刷多个点状的电极浆料。在某些实施例中，以印刷点状的电极浆料为例，以在下述步骤S30中烧结形成主栅的其中一部分。
S30：对所述硅基底进行热处理，使所述细栅与所述硅基底形成欧姆接触，同时使所述电极浆料烧结形成主栅的至少部分。
需要说明的是，本文中的步骤序号不是对步骤的先后顺序的限定，仅是为了区分不同步骤，除非另有说明的除外。例如，在实际工艺中，可以先进行上述步骤S10然后进行上述步骤S20，也可以进行上述步骤S20然后进行上述步骤S10。
该方案，经热处理，细栅中位于底部的金属与硅基底中的硅形成金属硅化物，在细栅与硅基底之间形成欧姆接触，欧姆接触具有接触电阻小，电流收集效率高的优点。并且电极浆料在热处理中被烧结形成主栅。由于细栅与硅基底形成欧姆接触和电极浆料烧成主栅是在同一次热处理中完成的，简化了工艺流程，降低了高温过程对电池片的损伤和性能的不利影响，且大大降低了形成细栅及主栅的热预算。
作为一种可实现方式，热处理的温度为500℃-900℃。热处理例如但不限于为退火，可以在退火炉内进行上述的热处理。
进一步地，如图3所示，本申请另一实施例提供的太阳能电池的制作方法，包括以下步骤：
S10：在硅基底上沉积形成多条细栅；
S11：对形成有多条细栅的硅基底进行退火，使所述细栅与所述硅基 底形成欧姆接触；
作为可实现的方式，在退火时，退火温度可以为300℃-900℃。退火的时间可以从几秒到几分钟不等，这取决于退火的温度和工艺制程的要求。例如，在一个实施例中，主栅与硅基底接触的材料为镍(主栅为单层结构时，主栅为镍金属层；主栅为多层结构时，主栅的最下层为镍金属层)，则退火温度可以为370℃，退火时间可以为3min。在另一个实施例中主栅与硅基底接触的材料为钴，退火温度为500℃，退火时间为30s。不同的退火温度和退火时间下都可以形成良好的欧姆接触。对于主栅与硅基底接触的材料为镍的情形，经过退火后形成低阻的硅化镍(NiSi)；对于主栅与硅基底接触的材料为钴的情形，经过退火后形成低阻的硅化钴(CoSi2)。
在另外的实施例中，退火的温度可以为500℃-900℃。相应地，形成第一电极体的电极浆料采用低温电极浆料，低温电极浆料的烧结温度在550℃-600℃之间。
退火可分为一次退火和两次退火，若为两次退火，要求后一次的退火温度高于前一次的退火温度。在一个实施例中，采用两次退火形成低阻的硅化镍，其第一次退火温度为260℃-310℃，时间30秒，第二次退火温度为400℃-500℃，时间30秒。在另一实施例中，采用两次退火形成硅化钴，其第一次退火温度为400℃-550℃，第二次退火温度为700℃-850℃。通过两次退火可有效抑制离子扩散，减少对硅基体的损伤，在主栅与硅基底之间形成电阻率小且性质均匀的硅化物薄膜，金属硅化物与硅基底间的形貌光滑。
S20：在硅基底上印刷电极浆料；
S21：对印刷的电极浆料进行烧结，使所述电极浆料烧结形成主栅的至少部分。
烧结的温度可以但不限于为700℃-1000℃。
在本申请中，对电极浆料进行烧结，可以是将印刷有电极浆料的硅基底整体放入烧结炉内进行烧结，也可以通过激光等方式对电极浆料印刷区域进行局部烧结。
局部加热例如但不限于可以采用激光加热，将激光束导向到电极浆 料，以对电极浆料进行局部加热固化成型。激光束可以具有1纳秒到10毫秒范围内的脉冲持续时间。激光束可以由连续波激光器或脉冲激光器发射。激光束具有100纳米到2000纳米范围的波长。
采用上述局部加热的方式，不需要对整片硅基底进行烧结，可以减小对硅基底的热损伤和对电池寿命的不利影响。
在一些实施例中，沉积可以为电沉积；在电沉积之前，先进行对印刷的电极浆料进行烧结的步骤；在电沉积过程中，烧结形成的主栅的至少部分作为无种子层电镀的触点与电源负极相连。本文所说的无种子层电镀，是指在电镀前，无需在形成细栅及主栅的对应位置形成种子层。这样可以实现无种子层电镀，前面的烧结步骤为后续的电沉积提供了触点，且简化了工艺步骤。
更进一步地，主栅包括交替设置的焊盘和连接栅线；连接栅线的宽度小于或等于焊盘的宽度；在电沉积过程中，焊盘作为无种子层电镀的触点与电源负极相连。焊盘可以是通过烧结点状的电极浆料形成的主栅的其中一部分，连接栅线可以是沉积在相邻的焊盘之间的金属层。
上述实现方式例如但不限于可以通过以下工艺形成，先通过沉积形成间隔设置的多段连接栅线，然后通过丝网印刷的方式，在相邻的两连接栅线之间形成点状的电极浆料，然后对电极浆料进行烧结。
为了降低复合，在形成细栅及主栅之前，还包括以下步骤：
在硅基底的表面形成介电层；
可以采用沉积的方式在硅基底的表面形成介电层，本文中可以采用氮化硅、氧化硅、氮氧化硅、氧化铝、氮氧化铝、碳化硅、非晶硅和多晶硅中的任意一种或任意组合形成介电层。
对所述介电层进行图案化，形成多条暴露所述硅基底的细栅成型开膜区，以及形成至少一条暴露所述硅基底的主栅成型开膜区，所述细栅成型开膜区与所述主栅成型开膜区相交。细栅成型开膜区用于沉积形成细栅，主栅成型开膜区用于形成主栅。其中，图案化例如但不限于可以采用刻蚀的方式。
在所述主栅成型开膜区内间隔印刷多个用于形成第一电极体的电极浆料，对所述电极浆料进行烧结(例如局部烧结方式)，使所述电极浆 料烧结形成第一电极体并与所述硅基底形成欧姆连接。
作为另外一种实施例，还可以采用以下的主栅图案；形成多条主栅成型带，各所述主栅成型带包括多个间隔设置第二电极体成型开膜区，各所述第二电极体成型开膜区暴露所述硅基底，所述细栅成型开膜区与所述主栅成型带相交。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本申请的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本申请的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本申请可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (13)

  1. 一种太阳能电池，包括硅基底，其特征在于，
    所述硅基底上沉积有多条细栅，所述细栅与所述硅基底欧姆接触；
    所述硅基底上设置有多条主栅；所述主栅与所述细栅相交且电接触；
    所述主栅的至少部分通过烧结电极浆料形成。
  2. 根据权利要求1所述的太阳能电池，其特征在于，每条所述主栅包括交替设置的第一电极体和第二电极体，所述第一电极体通过烧结电极浆料形成，所述第二电极体通过沉积形成。
  3. 根据权利要求2所述的太阳能电池，其特征在于，所述第一电极体为焊盘，所述第二电极体为连接所述细栅的连接栅线，所述连接栅线的宽度小于或等于所述焊盘的宽度。
  4. 根据权利要求3所述的太阳能电池，其特征在于，每条所述主栅中所述焊盘的个数为2-20个。
  5. 根据权利要求1-4任一项所述的太阳能电池，其特征在于，所述细栅包括层叠设置的两层以上金属层。
  6. 根据权利要求1-4任一项所述的太阳能电池，其特征在于，所述硅基底的正面形成有正面介电层，所述主栅形成于所述正面介电层上，且所述主栅至少部分烧结穿透所述正面介电层；
    和/或，
    所述硅基底的背面形成有背面介电层，所述主栅形成于所述背面介电层上，且所述主栅至少部分烧结穿透所述背面介电层。
  7. 根据权利要求1-4任一项所述的太阳能电池，其特征在于，所述细栅及所述主栅均沿直线延伸，且所述细栅垂直于所述主栅。
  8. 一种权利要求1所述的太阳能电池的制作方法，其特征在于，包括以下步骤：
    在硅基底上沉积形成多条细栅；
    在所述硅基底上印刷电极浆料；
    对所述硅基底进行热处理，使所述细栅与所述硅基底形成欧姆接触，同时使所述电极浆料烧结形成主栅的至少部分；
    或，包括如下步骤：
    在所述硅基底上沉积形成多条细栅；
    对形成有所述多条细栅的硅基底进行退火，使所述细栅与所述硅基底形成欧姆接触；
    在所述硅基底上印刷电极浆料；
    对印刷的所述电极浆料进行烧结，使所述电极浆料烧结形成主栅的至少部分。
  9. 根据权利要求8所述的太阳能电池的制作方法，其特征在于，所述沉积选自激光转印、化学镀、溅射、电沉积、物理气相沉积、化学气相沉积和原子层沉积中的任意一种或两种以上的组合。
  10. 根据权利要求8所述的太阳能电池的制作方法，其特征在于，所述退火的温度为300℃-900℃；所述烧结的温度为700℃-1000℃。
  11. 根据权利要求8所述的太阳能电池的制作方法，其特征在于，所述热处理的温度为500℃-900℃。
  12. 根据权利要求8所述的太阳能电池的制作方法，其特征在于，所述沉积为电沉积；在所述电沉积之前，先进行对印刷有电极浆料的硅基底进行烧结的步骤；在所述电沉积过程中，烧结形成的主栅的至少部分作为无种子层电镀的触点与电源负极相连。
  13. 根据权利要求12所述的太阳能电池的制作方法，其特征在于，
    所述主栅包括交替设置的焊盘和连接栅线；所述连接栅线的宽度小于或等于所述焊盘的宽度；在所述电沉积过程中，所述焊盘作为无种子层电镀的触点与电源负极相连。
PCT/CN2019/118909 2019-06-24 2019-11-15 太阳能电池及其制作方法 WO2020258683A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114551611A (zh) * 2022-03-11 2022-05-27 浙江爱旭太阳能科技有限公司 一种太阳能电池的栅线结构、组件及发电系统

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115148835B (zh) * 2021-03-31 2023-10-27 泰州隆基乐叶光伏科技有限公司 太阳能电池前驱体、制备方法、太阳能电池及光伏组件
CN115148834B (zh) * 2021-03-31 2023-09-15 泰州隆基乐叶光伏科技有限公司 太阳能电池及光伏组件
CN113437178A (zh) * 2021-05-28 2021-09-24 普乐新能源科技(徐州)有限公司 一种选择性激光烧结制备太阳能电池金属化电极的方法
CN113782637A (zh) * 2021-08-24 2021-12-10 天津爱旭太阳能科技有限公司 太阳能电池的制作方法和太阳能电池
CN117457788A (zh) * 2023-10-08 2024-01-26 西安隆基乐叶光伏科技有限公司 一种太阳能电池的制作方法、太阳能电池和电池串

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010087251A (ja) * 2008-09-30 2010-04-15 Dic Corp 太陽電池用導電性ペースト
CN101950781A (zh) * 2010-09-09 2011-01-19 浙江百力达太阳能有限公司 一种承载硅片的载具及选择性发射极太阳电池的掩膜工艺
CN102820343A (zh) * 2012-08-16 2012-12-12 常州天合光能有限公司 具有无发射极区的太阳能电池及其制备方法
CN106771416A (zh) * 2016-12-20 2017-05-31 常州天合光能有限公司 一种便于测试的高效太阳电池及其测试装置
CN108717950A (zh) * 2018-07-13 2018-10-30 天合光能股份有限公司 一种防断栅光伏电池片及光伏电池组件

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103390675A (zh) * 2012-05-09 2013-11-13 上海太阳能工程技术研究中心有限公司 晶体硅太阳电池及其制作方法
KR101956734B1 (ko) * 2012-09-19 2019-03-11 엘지전자 주식회사 태양 전지 및 그의 제조 방법
KR20150103163A (ko) * 2012-12-28 2015-09-09 메르크 파텐트 게엠베하 실리콘 웨이퍼들을 위한 인쇄가능한 확산 배리어들
CN104134710A (zh) * 2014-08-14 2014-11-05 无锡尚品太阳能电力科技有限公司 晶体硅太阳能电池主栅镂空结构
CN108365027A (zh) * 2018-04-24 2018-08-03 通威太阳能（合肥）有限公司 一种p型晶硅双面太阳能电池及电池制造方法
CN208256683U (zh) * 2018-06-11 2018-12-18 泰州隆基乐叶光伏科技有限公司 一种多主栅电池的正面电极结构及太阳能电池
CN109244154B (zh) * 2018-08-03 2024-09-20 浙江爱旭太阳能科技有限公司 贯孔双面直连太阳能电池组件及制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010087251A (ja) * 2008-09-30 2010-04-15 Dic Corp 太陽電池用導電性ペースト
CN101950781A (zh) * 2010-09-09 2011-01-19 浙江百力达太阳能有限公司 一种承载硅片的载具及选择性发射极太阳电池的掩膜工艺
CN102820343A (zh) * 2012-08-16 2012-12-12 常州天合光能有限公司 具有无发射极区的太阳能电池及其制备方法
CN106771416A (zh) * 2016-12-20 2017-05-31 常州天合光能有限公司 一种便于测试的高效太阳电池及其测试装置
CN108717950A (zh) * 2018-07-13 2018-10-30 天合光能股份有限公司 一种防断栅光伏电池片及光伏电池组件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3979332A4

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114551611A (zh) * 2022-03-11 2022-05-27 浙江爱旭太阳能科技有限公司 一种太阳能电池的栅线结构、组件及发电系统
CN114551611B (zh) * 2022-03-11 2024-05-31 广东爱旭科技有限公司 一种太阳能电池的栅线结构、组件及发电系统

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