WO2020258422A1 - 液晶面板、系统板和主动式矩阵显示装置 - Google Patents

液晶面板、系统板和主动式矩阵显示装置 Download PDF

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Publication number
WO2020258422A1
WO2020258422A1 PCT/CN2019/096806 CN2019096806W WO2020258422A1 WO 2020258422 A1 WO2020258422 A1 WO 2020258422A1 CN 2019096806 W CN2019096806 W CN 2019096806W WO 2020258422 A1 WO2020258422 A1 WO 2020258422A1
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WO
WIPO (PCT)
Prior art keywords
circuit
pin group
signal pin
conversion circuit
voltage
Prior art date
Application number
PCT/CN2019/096806
Other languages
English (en)
French (fr)
Inventor
行浩
吴永良
王柏钧
孙磊
常鹏刚
师俊
Original Assignee
咸阳彩虹光电科技有限公司
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Publication of WO2020258422A1 publication Critical patent/WO2020258422A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • This application relates to the field of display technology, in particular to a liquid crystal panel, a system board and an active matrix display device.
  • the timing control of the system board and the DC-DC voltage conversion circuit need to be designed differently, and the versatility of the system board is poor; if the LCD panel factory makes product design changes, the TV manufacturer may Need to make design changes at the same time.
  • embodiments of the present application provide a liquid crystal panel, a system board, and an active matrix display device.
  • a liquid crystal panel provided by an embodiment of the present application includes: a display panel including a display area and a gate drive circuit and a source drive circuit electrically connected to the display area; and a source drive circuit board assembly that is connected to the source The drive circuit contacts the connected circuit board assembly and is provided with a circuit and a connector electrically connected to the circuit; wherein the circuit is electrically connected to the gate drive circuit and the source drive circuit, and the connector includes a supply voltage pin Group, a P2P interface pin group, a data communication interface protocol pin group, and a reference timing signal pin group for transmitting all digital video image signals required by the liquid crystal panel, and the P2P interface pin group includes a plurality of differential Signal pin pair.
  • the data communication interface protocol pin group includes IIC interface protocol pin group and/or SPI interface protocol pin group, and the number of pins of the connector is 68, 60 or 51 .
  • the circuit includes a level conversion circuit, a DC voltage conversion circuit, and a Gamma correction circuit.
  • the DC voltage conversion circuit is electrically connected to the supply voltage pin group, the level conversion circuit and the Gamma correction circuit, and is configured to generate a gate according to the supply voltage input by the supply voltage pin group
  • the switching voltage and the working voltage are respectively to the level conversion circuit and the Gamma correction circuit
  • the level conversion circuit is electrically connected to the reference timing signal pin group and is configured to input according to the reference timing signal pin group
  • the reference timing signal and the gate switch voltage generate a gate control signal to the gate drive circuit
  • the Gamma correction circuit is configured to generate a plurality of Gamma voltages to the source drive circuit according to the operating voltage.
  • the circuit includes a level conversion circuit, a DC voltage conversion circuit, a Gamma correction circuit, and a timing conversion circuit.
  • the DC voltage conversion circuit is electrically connected to the supply voltage pin group, the level conversion circuit and the Gamma correction circuit, and is configured to generate a gate according to the supply voltage input by the supply voltage pin group
  • the switching voltage and the operating voltage are respectively connected to the level conversion circuit and the Gamma correction circuit
  • the timing conversion circuit is electrically connected to the reference timing signal pin group and is configured to input the reference timing signal pin group
  • the reference timing signal is converted to obtain a converted reference timing signal
  • the level conversion circuit is electrically connected to the timing conversion circuit and is configured to generate a gate control signal according to the converted reference timing signal and the gate switch voltage To the gate drive circuit
  • the Gamma correction circuit is configured to generate a plurality of Gamma voltages to the source drive circuit according to the operating voltage.
  • any one or more of the timing conversion circuit, the level conversion circuit, the DC voltage conversion circuit, and the Gamma correction circuit are integrated in the same chip.
  • the circuit includes a level conversion circuit and a DC voltage conversion circuit, and the source drive circuit is integrated with a Gamma correction circuit; wherein the DC voltage conversion circuit is electrically connected to the supply voltage source
  • the pin group, the level conversion circuit and the Gamma correction circuit are configured to generate a gate switching voltage and an operating voltage to the level conversion circuit and the Gamma correction circuit according to the supply voltage input from the supply voltage pin group.
  • the Gamma correction circuit is electrically connected to the reference timing signal pin group and is configured to generate gate control based on the reference timing signal input from the reference timing signal pin group and the gate switch voltage Signal to the gate drive circuit; and the Gamma correction circuit is configured to generate a plurality of Gamma voltages for the source drive circuit according to the operating voltage.
  • the circuit further includes a storage circuit, and the storage circuit is electrically connected to the first data communication interface protocol pin group in the data communication interface protocol pin group; and the Gamma correction The circuit and the DC voltage conversion circuit are electrically connected to a second data communication interface protocol pin group in the data communication interface protocol pin group.
  • the source drive circuit board assembly includes a plurality of drive circuit boards, and the level conversion circuit, the DC voltage conversion circuit, and the Gamma correction circuit are distributed in the multiple drive circuits On different ones of the boards, or distributed on the same one of the plurality of driving circuit boards.
  • the source drive circuit board assembly includes a plurality of drive circuit boards, and the timing conversion circuit, the level conversion circuit, the DC voltage conversion circuit, and the Gamma correction circuit are distributed in The plurality of driving circuit boards are on different ones, or distributed on the same one of the plurality of driving circuit boards.
  • the reference timing signal pin group is composed of two pins, and the two pins are a start pulse signal pin and a clock signal pin; or, the reference timing signal pin group
  • the signal pin group is composed of five pins, and the five pins are a start pulse signal pin, a first high-frequency clock signal pin, a second high-frequency clock signal pin, a low-frequency clock signal pin, and Reset signal pin; or, the reference timing signal pin group is composed of six pins, and the six pins are the start pulse signal pin, the first high-frequency clock signal pin, and the second high-frequency signal pin.
  • Clock signal pins low-frequency clock signal pins, reset signal pins, and termination signal pins; or, the reference timing signal pin group is composed of five pins, and the five pins are respectively the start pulse Signal pins, high-frequency clock signal pins, low-frequency clock signal pins, reset signal pins and termination signal pins.
  • the system board provided by the embodiment of the present application is suitable for an active matrix display device.
  • the system board is provided with a system-on-chip and a connector electrically connected to the system-on-chip; wherein, the connector includes a power supply voltage pin group, a P2P interface pin group for transmitting digital video image signals, and data communication
  • the interface protocol pin group and the reference timing signal pin group, and the P2P interface pin group includes a plurality of differential signal pin pairs.
  • the data communication interface protocol pin group includes IIC interface protocol pin group and/or SPI interface protocol pin group, and the number of pins of the connector is 68, 60 or 51 .
  • the system board is further provided with a power management circuit, and the power management circuit is electrically connected to the supply voltage pin group and the system-on-chip; and the system-on-chip is electrically connected The P2P interface pin group, the data communication interface protocol pin group, and the reference timing signal pin group of the connector.
  • the reference timing signal pin group is composed of two pins, and the two pins are a start pulse signal pin and a clock signal pin; or, the reference timing signal pin group
  • the signal pin group is composed of five pins, and the five pins are a start pulse signal pin, a first high-frequency clock signal pin, a second high-frequency clock signal pin, a low-frequency clock signal pin, and Reset signal pin; or, the reference timing signal pin group is composed of six pins, and the six pins are the start pulse signal pin, the first high-frequency clock signal pin, and the second high-frequency signal pin.
  • Clock signal pins low-frequency clock signal pins, reset signal pins, and termination signal pins; or, the reference timing signal pin group is composed of five pins, and the five pins are respectively the start pulse Signal pins, high-frequency clock signal pins, low-frequency clock signal pins, reset signal pins and termination signal pins.
  • an active matrix display device provided by an embodiment of the present application includes: a display panel, including a display area, and a gate drive circuit and a source drive circuit electrically connected to the display area; a source drive circuit board assembly is The source drive circuit contacts the connected circuit board assembly and is provided with a circuit and a first connector electrically connected to the circuit; wherein the circuit is electrically connected to the gate drive circuit and the source drive circuit, the first connection
  • the device includes a power supply voltage pin group, a P2P interface pin group used to transmit digital video image signals, a data communication interface protocol pin group, and a reference timing signal pin group, and the P2P interface pin group includes a plurality of differential signal leads Pin pair; and a system board provided with a system-on-chip and a second connector electrically connected to the system-on-chip, wherein the second connector is electrically connected to the first connector through a connector.
  • the source drive circuit board assembly is an even number of connected drive circuit boards, and the connecting member is a single flexible flat cable; and the system board only passes through the single flexible flat cable The digital video image signal is transmitted to the source driving circuit board assembly.
  • the data communication interface protocol pin group includes IIC interface protocol pin group and/or SPI interface protocol pin group, and the number of pins of the connector is 68, 60 or 51 .
  • the circuit includes a level conversion circuit, a DC voltage conversion circuit, and a Gamma correction circuit.
  • the DC voltage conversion circuit is electrically connected to the supply voltage pin group, the level conversion circuit and the Gamma correction circuit, and is configured to generate a gate according to the supply voltage input by the supply voltage pin group
  • the switching voltage and the working voltage are respectively to the level conversion circuit and the Gamma correction circuit
  • the level conversion circuit is electrically connected to the reference timing signal pin group and is configured to input according to the reference timing signal pin group
  • the reference timing signal and the gate switch voltage generate a gate control signal to the gate drive circuit
  • the Gamma correction circuit is configured to generate a plurality of Gamma voltages to the source drive circuit according to the operating voltage.
  • the circuit includes a level conversion circuit, a DC voltage conversion circuit, a Gamma correction circuit, and a timing conversion circuit.
  • the DC voltage conversion circuit is electrically connected to the supply voltage pin group, the level conversion circuit and the Gamma correction circuit, and is configured to generate a gate according to the supply voltage input by the supply voltage pin group
  • the switching voltage and the operating voltage are respectively connected to the level conversion circuit and the Gamma correction circuit
  • the timing conversion circuit is electrically connected to the reference timing signal pin group and is configured to input the reference timing signal pin group
  • the reference timing signal is converted to obtain a converted reference timing signal
  • the level conversion circuit is electrically connected to the timing conversion circuit and is configured to generate a gate control signal according to the converted reference timing signal and the gate switch voltage To the gate drive circuit
  • the Gamma correction circuit is configured to generate a plurality of Gamma voltages to the source drive circuit according to the operating voltage.
  • any one or more of the timing conversion circuit, the level conversion circuit, the DC voltage conversion circuit, and the Gamma correction circuit are integrated in the same chip.
  • the circuit further includes a storage circuit, and the storage circuit is electrically connected to the first data communication interface protocol pin group in the data communication interface protocol pin group; and the Gamma correction The circuit is electrically connected to the second data communication interface protocol pin group in the data communication interface protocol pin group.
  • the circuit includes a level conversion circuit and a DC voltage conversion circuit, and the source drive circuit is integrated with a Gamma correction circuit; wherein the DC voltage conversion circuit is electrically connected to the supply voltage source
  • the pin group, the level conversion circuit and the Gamma correction circuit are configured to generate a gate switching voltage and an operating voltage to the level conversion circuit and the Gamma correction circuit according to the supply voltage input from the supply voltage pin group.
  • the Gamma correction circuit is electrically connected to the reference timing signal pin group and is configured to generate gate control based on the reference timing signal input from the reference timing signal pin group and the gate switch voltage Signal to the gate drive circuit; and the Gamma correction circuit is configured to generate a plurality of Gamma voltages for the source drive circuit according to the operating voltage.
  • the circuit further includes a storage circuit, and the storage circuit is electrically connected to the first data communication interface protocol pin group in the data communication interface protocol pin group; and the Gamma correction The circuit and the DC voltage conversion circuit are electrically connected to a second data communication interface protocol pin group in the data communication interface protocol pin group.
  • the source drive circuit board assembly includes a plurality of drive circuit boards, and the level conversion circuit, the DC voltage conversion circuit, and the Gamma correction circuit are distributed in the multiple drive circuits On different ones of the boards, or distributed on the same one of the plurality of driving circuit boards.
  • the source drive circuit board assembly includes a plurality of drive circuit boards, and the timing conversion circuit, the level conversion circuit, the DC voltage conversion circuit, and the Gamma correction circuit are distributed in The plurality of driving circuit boards are on different ones, or distributed on the same one of the plurality of driving circuit boards.
  • the reference timing signal pin group is composed of two pins, and the two pins are a start pulse signal pin and a clock signal pin; or, the reference timing signal pin group
  • the signal pin group is composed of five pins, and the five pins are a start pulse signal pin, a first high-frequency clock signal pin, a second high-frequency clock signal pin, a low-frequency clock signal pin, and Reset signal pin; or, the reference timing signal pin group is composed of six pins, and the six pins are the start pulse signal pin, the first high-frequency clock signal pin, and the second high-frequency signal pin.
  • Clock signal pins low-frequency clock signal pins, reset signal pins, and termination signal pins; or, the reference timing signal pin group is composed of five pins, and the five pins are respectively the start pulse Signal pins, high-frequency clock signal pins, low-frequency clock signal pins, reset signal pins and termination signal pins.
  • the above-mentioned one or more technical solutions have one or more advantages or beneficial effects as follows:
  • the embodiment of the application optimizes the system architecture for traditional TCONLESS products, and drives the pins of the connector of the circuit board assembly and the connector of the system board.
  • the number is reduced, for example, to 68pin, 60pin or even 51Pin, or even less, and the pin function definition of the connector responsible for signal transmission between the system board and the source driver circuit board assembly is standardized, which can reduce the cost of the connector.
  • Cost and makes the public version of the system board possible; in this way, display manufacturers such as TV manufacturers can use a single system board with products from different LCD panel manufacturers, thereby greatly improving the versatility of system board design.
  • FIG. 1 is a schematic structural diagram of an active matrix display device according to an embodiment of the application.
  • FIG. 2A is a schematic diagram of a signal transmission method in the active matrix display device shown in FIG. 1.
  • FIG. 2B is a schematic diagram of another signal transmission method in the active matrix display device shown in FIG. 1.
  • FIG. 3 is a schematic structural diagram of an active matrix display device according to another embodiment of the application.
  • FIG. 4 is a schematic diagram of a signal transmission method in the active matrix display device shown in FIG. 3.
  • FIG. 5 is a schematic diagram of a signal transmission method in an active matrix display device according to another embodiment of the application.
  • FIG. 6 is a schematic structural diagram of an active matrix display device according to another embodiment of the application.
  • FIG. 7 is a schematic structural diagram of an active matrix display device according to still another embodiment of the application.
  • an active matrix display device 10 provided by an embodiment of the present application includes: an active matrix panel, a system board 13 and a connector CL1.
  • the active matrix panel is, for example, a liquid crystal panel, which includes a display panel 111 and a source drive circuit board assembly.
  • the active matrix display device 10 of this embodiment is, for example, a TCONLESS LCD TV, and its system board 13 integrates some of the functional circuits of a traditional control board, such as an optical taste adjustment IP core, like Mura elimination IP core, white balance adjustment IP Core, low color shift compensation IP core, overvoltage drive IP core and jitter processing IP core, etc., and each IP core is used for Mura elimination operation, white balance adjustment, low color shift compensation operation, overvoltage drive operation, and jitter processing. Operation; but the embodiment of the present application is not limited to this.
  • an optical taste adjustment IP core like Mura elimination IP core, white balance adjustment IP Core, low color shift compensation IP core, overvoltage drive IP core and jitter processing IP core, etc.
  • each IP core is used for Mura elimination operation, white balance adjustment, low color shift compensation operation, overvoltage drive operation, and jitter processing. Operation; but the embodiment of the present application is not limited to this.
  • the display panel 111 includes a display area 1111 and a gate drive circuit 1113 and a source drive circuit 1115 electrically connected to the display area 1111.
  • a plurality of data lines DL, a plurality of gate lines GL, and a plurality of pixels P electrically connecting each data line DL and each gate line GL are provided in the display area 1111; each pixel P is located on the corresponding gate line GL Intersection with data line DL.
  • the gate drive circuit 1113 is, for example, a single-sided GOA (Gate-On Array, gate drive circuit integrated on an array substrate) circuit or a double-sided GOA circuit; for a single-sided GOA circuit, it is located in the peripheral area on the side of the display area 1111 For example, the left side or the right side; and for the double-sided GOA circuit, it is located in the peripheral area of the display area 1111 and is provided on opposite sides of the display area 1111.
  • the gate driving circuit 1113 is electrically connected to the gate lines GL in the display area 1111, and is used to provide gate driving signals to the gate lines GL in the display area 1111.
  • the source driving circuit 1115 includes, for example, a plurality of COF-type source drivers 1115S, such as twelve COF (Chip-On-Flex, chip-on-film) source drivers 1115S shown in FIG. 1.
  • Each COF type source driver 1115S is electrically connected to the data line DL in the display area 1111 for providing image data signals to each data line DL.
  • a single COF-type source driver 1115S includes, for example, a flexible circuit board and a source driver IC (source driver IC) provided on the flexible circuit board.
  • the source drive circuit board assembly is a circuit board assembly that is in contact with the source drive circuit 1115, and includes two drive circuit boards 113a, 113b.
  • the two drive circuit boards 113a, 113b are arranged along the horizontal direction of FIG. One side, that is, as the row direction drive circuit board (commonly known as X-Board); each drive circuit board 113a, 113b adjacent to the display area 1111 is provided with a COF-type source driver 1115S connection interface such as mini-LVDS interface or P2P interface Wait.
  • the driving circuit board 113a is provided with a circuit 1130, a connector CN1, and a connector CN3.
  • the driving circuit board 113a is electrically connected to the display area 1111 through a plurality of, for example, seven COF type source drivers 1115S.
  • the drive circuit board 113b is provided with a connector CN4.
  • the driving circuit board 113b is electrically connected to the display area 1111 through a plurality of, for example, five COF type source drivers 1115S.
  • the connector CN3 of the drive circuit board 113a and the connector CN4 of the drive circuit board 113b form an electrical connection through a connector CL2, where the connector CL2 is, for example, a flexible circuit board or a flexible flat cable (FFC).
  • the system board 13 is provided with a connector CN2 and a system-on-chip 131a.
  • the connector CN2 of the system board 13 is connected to the connector CN1 of the drive circuit board 113a through the connector CL1.
  • the connector CL1 is, for example, a single flexible flat cable (FFC), especially when the number of drive circuit boards in the source drive circuit board assembly is an even number; in this way, the system board 13 only passes through a single flexible flat cable ( Instead of using multiple flexible cables) to transmit all the digital video image signals required by the active matrix panel (such as a liquid crystal panel) to the source drive circuit board assembly; all digital video image signals here include, for example, the active All RGB data required by the matrix panel.
  • FFC flexible flat cable
  • a single flexible flat cable typically includes two connectors and multiple signal lines connected between the two connectors.
  • the system board 13 of this embodiment is typically also provided with multiple audio and video input interfaces such as CVBS interface, HDMI interface, etc.; the system board 13 is also called the main board (Main Board), which is used to The video image and audio signal input by the audio and video input interface are decoded, and then the video image signal is output to the source drive circuit board assembly in a digital signal format.
  • the connector CN1 and the connector CN2 in this embodiment have the same number of pins and pin function definitions, which are shown in Table 1 or Table 2 or 3 below, for example.
  • Table 1 A function definition table of 51 pins of connector CN1/CN2
  • Table 2 Another function definition table of 51 pins of connector CN1/CN2
  • Table 3 A function definition table of the 60 pins of the connector CN1/CN2
  • the connector CN1/CN2 includes a power supply voltage pin group (Vin), a P2P interface pin group (P2P interface) used to transmit digital video image signals, and a data communication interface protocol pin Group (IIC interface and SPI interface) and reference timing signal pin group (STV, CKV), and the P2P interface pin group (P2P interface) includes a plurality of differential signal pin pairs.
  • Vin power supply voltage pin group
  • P2P interface P2P interface pin group
  • IIC interface and SPI interface data communication interface protocol pin Group
  • STV, CKV reference timing signal pin group
  • P2P interface pin group includes a plurality of differential signal pin pairs.
  • the P2P interface is a different interface type from the mini LVDS (mini Low Voltage Differential Signaling) interface, and it is very suitable for the system board 13 to the drive circuit board 113a. Inter-signal transmission, which can be known and mature USI-T, EPI, CMPI, iSP interfaces, etc.
  • the circuit 1130 includes a level conversion circuit 1131 a, a DC voltage conversion circuit 1133, a Gamma correction circuit 1135, and a storage circuit 1137.
  • the DC voltage conversion circuit 1133 is electrically connected to the supply voltage pin group Vin, the level conversion circuit 1131a, and the Gamma correction circuit 1135, and is configured to generate a gate switching voltage according to the supply voltage input from the supply voltage pin group Vin, for example +12V For example, VGH, VGL, and working voltages such as VAA to the level conversion circuit 1131a and the Gamma correction (gamma correction) circuit 1135, respectively.
  • VGH, VGL working voltages
  • VAA to the level conversion circuit 1131a and the Gamma correction (gamma correction) circuit 1135, respectively.
  • the DC voltage conversion circuit 1133 can also provide power supply voltages such as the digital voltage VDD and the analog voltage HVAA for the level conversion circuit 1131a, the Gamma correction circuit 1135, the storage circuit 1137, and the source drive circuit 1115.
  • the level conversion circuit 1131a is electrically connected to the reference timing signal pin groups STV and CKV and is configured to generate a gate control signal according to the reference timing signals input by the reference timing signal pin groups STV and CKV and the gate switch voltages VGH, VGL For example, ST, CKx, LCx, RST to the gate drive circuit 1113.
  • the Gamma correction circuit 1135 is configured to generate multiple Gamma voltages such as GMAx to the source driving circuit 1115 according to the operating voltage VAA. Furthermore, the DC voltage conversion circuit 1133 and the Gamma correction circuit 1135, for example, are also electrically connected to the IIC (Inter-Integrated Circuit) interface protocol pin group in the data communication interface protocol pin group, so that they can communicate with the system board through the IIC interface protocol.
  • the system-on-chip 131a on 13 performs serial communication.
  • the storage circuit 1137 is electrically connected to the SPI (Serial Peripheral Interface) interface protocol pin group in the data communication interface protocol pin group, and it includes, for example, a non-volatile memory such as a flash memory for storage and Panel taste-related data, such as DeMura data, Gamma data, etc.
  • SPI Serial Peripheral Interface
  • ST is the start pulse signal
  • CKx is, for example, eight high-frequency clock signals
  • LCx is, for example, two low-frequency clock signals relative to CKx
  • RST is the reset signal
  • GMAx is, for example, GMA1 ⁇ GMA14, etc.
  • VGH as the gate turn-on voltage, for example, +20V to +30V
  • VGL as the gate turn-off voltage, for example, about -5V, but the embodiment of the application is not limited to this.
  • the level conversion circuit 1131a, the DC voltage conversion circuit 1133, and the Gamma correction circuit 1135 in the embodiment shown in FIG. 2A are, for example, integrated into three different chips; for example, the DC voltage conversion circuit 1133 uses a known mature
  • the level shift circuit 1131a adopts the level shift (Level Shift) chip in the known mature technology
  • the Gamma correction circuit 1135 adopts the P-Gamma chip in the known mature technology.
  • the DC voltage conversion circuit 1133 and the level conversion circuit 1131a can be integrated in the same chip and the Gamma correction circuit 1135 can be integrated in another chip, or the DC voltage The conversion circuit 1133 and the Gamma correction circuit 1135 are integrated in the same chip and the level conversion circuit 1131a is integrated in another chip, or the level conversion circuit 1131a and the Gamma correction circuit 1135 are integrated in the same chip and the DC voltage conversion circuit 1133 is integrated in the same chip It is even possible to integrate the DC voltage conversion circuit 1133, the level conversion circuit 1131a, and the Gamma correction circuit 1135 on the same chip.
  • the Gamma correction circuit 1135 can be integrated into the source driving circuit 1115.
  • the foregoing embodiments of the present application optimize the system architecture for traditional TCONLESS products, and reduce the number of pins of the connector CN1 on the drive circuit board 113a and the connector CN2 on the system board 13, for example, to 51Pin.
  • the standard design of the pin function definition of the connectors CN1 and CN2 responsible for signal transmission between the system board 13 and the LCD panel can reduce the cost of the connector and make the public version system board possible; this way, display manufacturers For example, TV manufacturers can use a single system board with products from different LCD panel manufacturers, thereby greatly improving the versatility of system board design.
  • the circuit 1130 in the embodiment shown in FIGS. 3 and 4 includes: a level conversion circuit 1131b, a DC voltage conversion circuit 1133, a Gamma correction circuit 1135, and a storage circuit 1137 and timing conversion circuit 1139.
  • the DC voltage conversion circuit 1133 is electrically connected to the supply voltage pin group Vin, the level conversion circuit 1131b, and the Gamma correction circuit 1135, and is configured to generate the gate switching voltage according to the supply voltage input from the supply voltage pin group Vin, for example +12V
  • VGH, VGL, and working voltages such as VAA to the level conversion circuit 1131b and the Gamma correction circuit 1135, respectively.
  • the DC voltage conversion circuit 1133 can also provide power supply voltages such as digital voltage VDD and analog voltage for the level conversion circuit 1131b, the Gamma correction circuit 1135, the storage circuit 1137, the timing conversion circuit 1139, and the source drive circuit 1115. HVAA.
  • the timing conversion circuit 1139 is electrically connected to the reference timing signal pin groups STV and CKV and is configured to convert the reference timing signals input by the reference timing signal pin groups STV and CKV to obtain converted reference timing signals such as ST_in, CK1_in, CK2_in, LC_in, RST_in.
  • the level conversion circuit 1131b is electrically connected to the timing conversion circuit 1139 and is configured to generate gate control signals such as ST_in, CK1_in, CK2_in, LC_in, RST_in and the gate switch voltages VGH, VGL according to the converted reference timing signals ST_in, CK1_in, CK2_in, CKx, LCx, RST to the gate drive circuit 1113.
  • gate control signals such as ST_in, CK1_in, CK2_in, LC_in, RST_in and the gate switch voltages VGH, VGL according to the converted reference timing signals ST_in, CK1_in, CK2_in, CKx, LCx, RST to the gate drive circuit 1113.
  • the Gamma correction circuit 1135 is configured to generate multiple Gamma voltages such as GMAx to the source driving circuit 1115 according to the operating voltage VAA. Furthermore, the Gamma correction circuit 1135 is also electrically connected to the IIC (Inter-Integrated Circuit) interface protocol pin group in the data communication interface protocol pin group, so that it can communicate with the system-on-chip on the system board 13 through the IIC interface protocol. 131a performs serial communication.
  • IIC Inter-Integrated Circuit
  • the storage circuit 1137 is electrically connected to the SPI (Serial Peripheral Interface) interface protocol pin group in the data communication interface protocol pin group, and it includes, for example, a non-volatile memory such as a flash memory for storage and Panel taste-related data, such as DeMura data, Gamma data, etc.
  • SPI Serial Peripheral Interface
  • any one or more of the timing conversion circuit 1139, the level conversion circuit 1131b, the DC voltage conversion circuit 1133, and the Gamma correction circuit 1135 are integrated in the same chip
  • the timing conversion circuit 1139 and the level conversion circuit 1131b are integrated in the same chip
  • the timing conversion circuit 1139 and the DC voltage conversion circuit 1133 are integrated in the same chip
  • the timing conversion circuit 1139 and the Gamma correction circuit 1135 are integrated in the same chip Or
  • the timing conversion circuit 1139, the level conversion circuit 1131b, the DC voltage conversion circuit 1133, and the Gamma correction circuit 1135 are integrated into the same chip, and so on.
  • Table 4 A function definition table of 68 pins of connector CN1/CN2
  • the connector CN1/CN2 includes a power supply voltage pin group (Vin), a P2P interface pin group (P2P interface) used to transmit digital video image signals, and a data communication interface protocol pin group (IIC interface, SPI Interface) and reference timing signal pin groups (ST_in, CK1_in, CK2_in, LC_in, RST_in), and the P2P interface pin group (P2P interface) includes a plurality of differential signal pin pairs. Furthermore, a ground pin (GND) is provided between every two adjacent differential signal pin pairs, which can improve the anti-interference ability of the P2P interface signal.
  • the System-On Chip (SOC) 131b shown in Figure 5 directly outputs the reference timing signal pins such as ST_in, CK1_in, CK2_in, LC_in, through the connector CN1 RST_in, correspondingly, the level conversion circuit 1131b is electrically connected to the reference timing signal pin group (ST_in, CK1_in, CK2_in, LC_in, RST_in) and is configured according to the reference timing signal pin group (ST_in, CK1_in, CK2_in, LC_in, RST_in)
  • the input reference timing signal and gate switching voltages such as VGH and VGL generate gate control signals such as ST, CKx, LCx, RST to the gate driving circuit 1113.
  • the source driving circuit board assembly in the embodiment of the present application is not limited to the two driving circuit boards 113a and 113b shown in FIGS. 1 and 3, and may also include other numbers of driving circuit boards.
  • the source driving circuit board assembly includes only a single driving circuit board 113a; or, as shown in FIG. 7, the source driving circuit board assembly includes three driving circuit boards 113a, 113b, and 113b.
  • the system board 131a is further provided with a power management circuit 133 such as a PMIC chip, which is electrically connected to the connector CN2 to provide a DC voltage such as + to the supply voltage pin group Vin. 12V, and is also electrically connected to the system-on-chip 131a to provide a power supply voltage thereto.
  • the embodiment of the application optimizes the system architecture for the traditional TCONLESS product, and reduces the number of pins of the connector CN1 of the drive circuit board 113a and the connector CN2 of the system board 13, for example, to 68pin, 60pin, even 51Pin, or even less, and standardized design of the pin function definition of the connectors CN1 and CN2 responsible for signal transmission between the system board 13 and the LCD panel, which can reduce the cost of the connector and make the public Version of the system board becomes possible; in this way, display manufacturers such as TV manufacturers can use a single system board with products from different LCD panel manufacturers, thereby greatly improving the versatility of system board design.
  • connector CN1/CN2 of the embodiment of the present application may also have other different pin function definitions, for example, as shown in Table 5 and Table 6 below.
  • Table 5 Another function definition table of the 60 pins of the connector CN1/CN2
  • Table 6 Another function definition table of the 60 pins of the connector CN1/CN2
  • the data communication interface protocol pin group only includes one data communication interface protocol pin, such as SPI interface, instead of the inclusion shown in Table 1, Table 2, Table 3, and Table 4.
  • Two kinds of data communication interface protocol pins such as IIC interface and SPI interface.
  • the number of reference timing signal pins in Table 5 is two, namely the start pulse signal STV pin and the clock signal CKV pin; the number of reference timing signal pins in Table 6 is six, respectively Start pulse signal ST_in pin, high-frequency clock signal CK1_in pin, high-frequency clock signal CK2_in pin, low-frequency clock signal LC_in pin, reset signal RST_in pin and termination signal Terminate_in pin.
  • the number of reference timing signal pins is five, which are the start pulse signal ST_in pin, the high-frequency clock signal CK_in pin, the termination signal Terminate_in pin, and the reset signal. RST_in pin and low-frequency clock signal LC_in pin.
  • Table 7 Another function definition table of 68 pins of connector CN1/CN2
  • the foregoing embodiments are only exemplary descriptions of the present application, and the technical solutions of the various embodiments can be combined arbitrarily, provided that the technical features do not conflict, the structure does not contradict, and does not violate the purpose of the invention of the present application.
  • the DC voltage conversion circuit 1133, the level conversion circuit 1131a/1131b, and the Gamma correction circuit 1135 of the circuit 1130 in the foregoing various embodiments are not limited to being distributed on a single driving circuit board 113a, and they may also be distributed. On a plurality of driving circuit boards, for example, the driving circuit boards 113a and 113b in FIG.
  • the IIC interface protocol pin group and the SPI interface protocol pin group can also be partially or completely idle.
  • the connector responsible for signal transmission between the system board 13 and the source drive circuit board assembly in the embodiment of the present application is not limited to the 68Pin connector, the 60Pin connector, and the 51Pin connector, nor does it limit the functions of each connector.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units.

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Abstract

一种液晶面板，匹配液晶面板的系统板以及采用系统板的主动式矩阵显示装置。液晶面板包括：显示面板（111），包括显示区域（1111）和电连接显示区域（1111）的栅驱动电路（1113）及源驱动电路（1115）；以及源驱动电路板组件，为与源驱动电路（1115）接触连接的电路板组件且设置有电路和电连接电路的连接器。其中，电路电连接栅驱动电路（1113）和源驱动电路（1115），连接器包含供电电压引脚组、用于传输液晶面板所需全部数字视频图像信号的P2P接口引脚组、数据通信接口协议引脚组和基准时序信号引脚组，且P2P接口引脚组包括多个差分信号引脚对。

Description

液晶面板、系统板和主动式矩阵显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种液晶面板、一种系统板以及一种主动式矩阵显示装置。
背景技术
目前一些液晶电视(Liquid Crystal TV)厂商为节约成本，在设计时会将控制板(Control Board，或称TCON板)集成在系统板(System Board，或称Main Board)上，因此采购液晶面板时不需采购控制板，这类产品被称为TCONLESS型TV产品。这类TCONLESS型TV产品由于将控制板的功能设计在系统板上，系统板的集成度高，但是在与液晶面板进行信号传递时，传递的信号类型增多，传递信号所需的连接器引脚数量也需要增多，导致连接器成本上升；通常，与液晶面板传递信号所用的连接器会增加到80Pin。再者，针对采用不同液晶面板的TCONLESS型TV产品，系统板的时序控制及DC-DC电压转换电路均需进行不同设计，系统板的通用性差；如果液晶面板厂进行产品设计变更，TV厂商可能需要同时进行设计变更。
申请内容
为克服相关技术中的至少部分缺陷和不足，本申请实施例提供了一种液晶面板、一种系统板以及一种主动式矩阵显示装置。
一方面，本申请实施例提供的一种液晶面板，包括：显示面板，包括显示区域和电连接所述显示区域的栅驱动电路及源驱动电路；以及源驱动电路板组件，为与所述源驱动电路接触连接的电路板组件且设置有电路和电连接所述电路的连接器；其中，所述电路电连接所述栅驱动电路和所述源驱动电路，所述连接器包含供电电压引脚组、用于传输所述液晶面板所需全部数字视频图像信号的P2P接口引脚组、数据通信接口协议引脚组和基准时序信号引脚组，且所述P2P接口引脚组包括多个差分信号引脚对。
在本申请的一个实施例中，所述数据通信接口协议引脚组包括IIC接口协议引脚组和/或SPI接口协议引脚组，以及所述连接器的引脚数量为68、60或51。
在本申请的一个实施例中，所述电路包括电平转换电路、直流电压转换电路和Gamma校正电路。其中，所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
在本申请的一个实施例中，所述电路包括电平转换电路、直流电压转换电路、Gamma校正电路和时序转换电路。其中，所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；所述时序转换电路电连接所述基准时序信号引脚组且被配置成对所述基准时序信号引脚组输入的基准时序信号进行转换以得到转换后基准时序信号；所述电平转换电路电连接所述时序转换电路且被配置成根据所述转换后基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
在本申请的一个实施例中，所述时序转换电路和所述电平转换电路、所述直流电压转换电路及所述Gamma校正电路中的任意一者或多者整合于同一个芯片。
在本申请的一个实施例中，所述电路包括电平转换电路和直流电压转换电路，且所述源驱动电路整合有Gamma校正电路；其中，所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压供所述源驱动电路使用。
在本申请的一个实施例中，所述电路还包括存储电路，且所述存储电路电连接所述数据通信接口协议引脚组中的第一数据通信接口协议引脚组；以及所述Gamma校正电路和所述直流电压转换电路电连接所述数据通信接口协议引脚组中的第二数据通信接口协议引脚组。
在本申请的一个实施例中，所述源驱动电路板组件包括多个驱动电路板，所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
在本申请的一个实施例中，所述源驱动电路板组件包括多个驱动电路板，所述时序转换电路、所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
在本申请的一个实施例中，所述基准时序信号引脚组由两个引脚构成且所述两个引脚分别为起始脉冲信号引脚和时钟信号引脚；或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚和复位信号引脚；或者，所述基准时序信号引脚组由六个引脚构成且所述六个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚；又或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚。
另一方面，本申请实施例提供的一种系统板，适用于一种主动式矩阵显示装置。所述系统板设置有系统级芯片和电连接所述系统级芯片的连接器；其中，所述连接器包含供电电压引脚组、用于传输数字视频图像信号的P2P接口引脚组、数据通信接口协议引脚组和基准时序信号引脚组，且所述P2P接口引脚组包括多个差分信号引脚对。
在本申请的一个实施例中，所述数据通信接口协议引脚组包括IIC接口协议引脚组和/或SPI接口协议引脚组，以及所述连接器的引脚数量为68、60或51。
在本申请的一个实施例中，所述系统板还设置有电源管理电路，且所述电源管理电路电连接所述供电电压引脚组和所述系统级芯片；以及所述系统级芯片电连接所述连接器的所述P2P接口引脚组、所述数据通信接口协议引脚组和所述基准时序信号引脚组。
在本申请的一个实施例中，所述基准时序信号引脚组由两个引脚构成且所述两个引脚分别为起始脉冲信号引脚和时钟信号引脚；或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚和复位信号引脚；或者，所述基准时序信号引脚组由六个引脚构成且所述六个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号 引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚；又或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚。
再一方面，本申请实施例提供的一种主动式矩阵显示装置，包括：显示面板，包括显示区域和电连接所述显示区域的栅驱动电路及源驱动电路；源驱动电路板组件，为与所述源驱动电路接触连接的电路板组件且设置有电路和电连接所述电路的第一连接器；其中所述电路电连接所述栅驱动电路和所述源驱动电路，所述第一连接器包含供电电压引脚组、用于传输数字视频图像信号的P2P接口引脚组数据通信接口协议引脚组和基准时序信号引脚组，且所述P2P接口引脚组包括多个差分信号引脚对；以及系统板，设置有系统级芯片和电连接所述系统级芯片的第二连接器，其中所述第二连接器通过连接件电连接所述第一连接器。
在本申请的一个实施例中，所述源驱动电路板组件为偶数个相连接的驱动电路板，且所述连接件为单条软排线；以及所述系统板仅通过所述单条软排线向所述源驱动电路板组件传输数字视频图像信号。
在本申请的一个实施例中，所述数据通信接口协议引脚组包括IIC接口协议引脚组和/或SPI接口协议引脚组，以及所述连接器的引脚数量为68、60或51。
在本申请的一个实施例中，所述电路包括电平转换电路、直流电压转换电路和Gamma校正电路。其中，所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
在本申请的一个实施例中，所述电路包括电平转换电路、直流电压转换电路、Gamma校正电路和时序转换电路。其中，所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；所述时序转换电路电连接所述基准时序信号引脚组且被配置成对所述基准时序信号引脚组输入的基准时序信号进行转换以得到转换后基准时序信号；所述电平转换电路电连接所述时序转换电路且被配置成根据所述转换后基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
在本申请的一个实施例中，所述时序转换电路和所述电平转换电路、所述直流电压转换电路及所述Gamma校正电路中的任意一者或多者整合于同一个芯片。
在本申请的一个实施例中，所述电路还包括存储电路，且所述存储电路电连接所述数据通信接口协议引脚组中的第一数据通信接口协议引脚组；以及所述Gamma校正电路电连接所述数据通信接口协议引脚组中的第二数据通信接口协议引脚组。
在本申请的一个实施例中，所述电路包括电平转换电路和直流电压转换电路，且所述源驱动电路整合有Gamma校正电路；其中，所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号 引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压供所述源驱动电路使用。
在本申请的一个实施例中，所述电路还包括存储电路，且所述存储电路电连接所述数据通信接口协议引脚组中的第一数据通信接口协议引脚组；以及所述Gamma校正电路和所述直流电压转换电路电连接所述数据通信接口协议引脚组中的第二数据通信接口协议引脚组。
在本申请的一个实施例中，所述源驱动电路板组件包括多个驱动电路板，所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
在本申请的一个实施例中，所述源驱动电路板组件包括多个驱动电路板，所述时序转换电路、所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
在本申请的一个实施例中，所述基准时序信号引脚组由两个引脚构成且所述两个引脚分别为起始脉冲信号引脚和时钟信号引脚；或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚和复位信号引脚；或者，所述基准时序信号引脚组由六个引脚构成且所述六个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚；又或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚。
上述一个或多个技术方案具有如下一个或多个优点或有益效果：本申请实施例针对传统TCONLESS产品，进行系统架构优化，将源驱动电路板组件的连接器和系统板的连接器的引脚数量进行缩减，例如缩减至68pin，60pin甚至51Pin，乃至更少，并对系统板与源驱动电路板组件之间负责信号传输的连接器的引脚功能定义进行标准化设计，其可以降低连接器的成本，并使得公版系统板成为可能；如此一来显示器厂商例如TV厂商可以使用单一系统板搭配不同液晶面板厂商的产品，从而大幅提升系统板设计的通用性。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一个实施例的一种主动式矩阵显示装置的结构示意图。
图2A为图1所示主动式矩阵显示装置中的一种信号传递方式示意图。
图2B为图1所示主动式矩阵显示装置中的另一种信号传递方式示意图。
图3为本申请另一个实施例的一种主动式矩阵显示装置的结构示意图。
图4为图3所示主动式矩阵显示装置中的一种信号传递方式示意图。
图5为本申请再一个实施例的一种主动式矩阵显示装置中的一种信号传递方式示意图。
图6为本申请又一个实施例的一种主动式矩阵显示装置的结构示意图。
图7为本申请再又一个实施例的一种主动式矩阵显示装置的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整 地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，本申请一个实施例提供的一种主动式矩阵显示装置10，包括：主动式矩阵面板、系统板13以及连接件CL1。其中，主动式矩阵面板例如是液晶面板，其包括显示面板111和源驱动电路板组件。本实施例的主动式矩阵显示装置10例如是TCONLESS型液晶电视，其系统板13整合有传统控制板的部分功能电路，比如整合有光学品味调整IP核，像Mura消除IP核、白平衡调整IP核、低色偏补偿IP核、过压驱动IP核和抖动处理IP核等，且各个IP核分别用于进行Mura消除操作、白平衡调整、低色偏补偿操作、过压驱动操作和抖动处理操作；但本申请实施例并不以此为限。
具体地，显示面板111包括显示区域1111和电连接显示区域1111的栅驱动电路1113及源驱动电路1115。显示区域1111内设置有多条数据线DL、多条栅极线GL和电连接各条数据线DL与各条栅极线GL的多个像素P；各个像素P位于相对应的栅极线GL与数据线DL的交叉处。所述栅驱动电路1113例如单侧GOA(Gate-On Array，栅驱动电路集成在阵列基板上)电路或双侧GOA电路；就单侧GOA电路而言，其位于显示区域1111一侧的周边区域例如左侧或右侧；而对于双侧GOA电路，其位于显示区域1111的周边区域且分设于显示区域1111的相对两侧。栅驱动电路1113电连接显示区域1111内的栅极线GL，用于向显示区域1111的各条栅极线GL提供栅极驱动信号。源驱动电路1115例如包括多个COF型源驱动器1115S，比如图1中所示的十二个COF(Chip-On-Flex，覆晶薄膜)型源驱动器1115S。各个COF型源驱动器1115S电连接显示区域1111内的数据线DL，用于向各个数据线DL提供图像数据信号。更具体地，单个COF型源驱动器1115S例如包括柔性电路板和设置在柔性电路板上的源驱动器芯片(source driver IC)。
源驱动电路板组件为与源驱动电路1115接触连接的电路板组件，其包括两个驱动电路板113a、113b，这两个驱动电路板113a、113b沿着图1水平方向排列于显示面板111的一侧，也即作为行方向驱动电路板(俗称X-Board)；各个驱动电路板113a、113b邻近显示区域1111的一侧设置有COF型源驱动器1115S的连接介面例如mini-LVDS接口或P2P接口等。具体而言，驱动电路板113a设置有电路1130、连接器CN1和连接器CN3。驱动电路板113a通过多个例如七个COF型源驱动器1115S电连接显示区域1111。驱动电路板113b设置有连接器CN4。驱动电路板113b通过多个例如五个COF型源驱动器1115S电连接显示区域1111。驱动电路板113a的连接器CN3和驱动电路板113b的连接器CN4之间通过连接件CL2形成电连接，此处的连接件CL2例如是柔性电路板或软排线(Flexible Flat Cable，FFC)。
系统板13设置有连接器CN2和系统级芯片131a。系统板13的连接器CN2通过连接件CL1连接驱动电路板113a的连接器CN1。连接件CL1例如是单条软排线(Flexible Flat Cable，FFC)，尤其是在源驱动电路板组件中的驱动电路板数量为偶数的场合；如此一来，系统板13仅通过单条软排线(而非通过多条软排线)向所述源驱动电路板组件传输所述主动式矩阵面板(例如液晶面板)所需全部数字视频图像信号；此处的全部数字视频图像信号例如包含所述主动式矩阵面板所需的全部RGB数据。此处需要说明的是，单条软排线典型地包括两个连接器和连接在所述两个连接器之间的多条信号线。此外，值得一提的是，本实施例的系统板13典型地还设置有多个音视频输入接口例如CVBS接口、HDMI接口等；系统板13又称主板(Main Board)，其用于对经由音视频输入接口输入的视频图像和音频信号进行解码处理，再将视频图像信号以数字信号格式输出至所述源驱动电路板组件。
承上述，本实施例中的连接器CN1和连接器CN2具有相同的引脚数量和引脚功能定义， 其例如为下附的表1或表2或3所示。
表1连接器CN1/CN2的51个引脚的一种功能定义表
Figure PCTCN2019096806-appb-000001
表2连接器CN1/CN2的51个引脚的另一种功能定义表
Figure PCTCN2019096806-appb-000002
表3连接器CN1/CN2的60个引脚的一种功能定义表
Figure PCTCN2019096806-appb-000003
从表1、表2和表3可知，连接器CN1/CN2包含供电电压引脚组(Vin)、用于传输数字视频图像信号的P2P接口引脚组(P2P接口)、数据通信接口协议引脚组(IIC接口及SPI接口)和基准时序信号引脚组(STV、CKV)，且所述P2P接口引脚组(P2P接口)包括多个差分信号引脚对。此处值得一提的是，P2P接口为一种不同于mini LVDS(mini Low Voltage Differential Signaling，微型低压差分信号)接口的另一种接口类型，而且非常适用于系统板13到驱动电路板113a之间的信号传输，其可以是已知成熟的USI-T、EPI、CMPI、iSP接口等。
请一并参见图1和图2A，电路1130包括包括电平转换电路1131a、直流电压转换电路1133、Gamma校正电路1135和存储电路1137。
其中，直流电压转换电路1133电连接供电电压引脚组Vin、电平转换电路1131a和Gamma校正电路1135，且被配置成根据供电电压引脚组Vin输入的供电电压例如+12V产生栅极开关电压例如VGH、VGL和工作电压例如VAA分别至电平转换电路1131a和Gamma校正(伽马校正)电路1135。当然，可以理解的是，直流电压转换电路1133还可以为电平转换电路1131a、Gamma校正电路1135、存储电路1137和源驱动电路1115等提供电源电压例如数字电压VDD和模拟电压HVAA。
电平转换电路1131a电连接基准时序信号引脚组STV、CKV且被配置成根据基准时序信号引脚组STV、CKV输入的基准时序信号和所述栅极开关电压VGH、VGL产生栅极控制信号例如ST、CKx、LCx、RST至栅驱动电路1113。
Gamma校正电路1135被配置成根据所述工作电压VAA产生多个Gamma电压例如GMAx至源驱动电路1115。再者，直流电压转换电路1133和Gamma校正电路1135例如还电连接所述数据通信接口协议引脚组中的IIC(Inter-Integrated Circuit)接口协议引脚组，从而可以通过IIC接口协议与系统板13上的系统级芯片131a进行串行通信。
存储电路1137电连接所述数据通信接口协议引脚组中的SPI(Serial Peripheral Interface，串行外设接口)接口协议引脚组，其例如包含非易失性存储器比如闪存，以用于存储与面板品味相关的资料，比如DeMura资料、Gamma资料等等。
在一个具体例子中，ST为起始脉冲信号，CKx例如为八路高频时钟信号，LCx例如为相对于CKx而言的两路低频时钟信号，RST为复位信号，GMAx例如为GMA1～GMA14等十四路Gamma电压，VGH作为栅极开启电压例如是+20V～+30V，VGL作为栅极关闭电压例如选取-5V左右，但本申请实施例并不以此为限。
另外，值得说明的是，图2A所示实施例中的电平转换电路1131a、直流电压转换电路1133和Gamma校正电路1135例如分别整合于三个不同芯片；例如直流电压转换电路1133采用已知成熟技术的PMIC芯片，电平转换电路1131a采用已知成熟技术中的电平转换(Level Shift)芯片，以及Gamma校正电路1135采用已知成熟技术中的P-Gamma芯片。此外，为了进一步提升电路1130的集成度，在其他实施例中，还可以将直流电压转换电路1133和电平转换电路1131a整合于同一芯片且Gamma校正电路1135整合于另一芯片，或者将直流电压转换电路1133和Gamma校正电路1135整合于同一芯片且电平转换电路1131a整合于另一芯片，或者将电平转换电路1131a和Gamma校正电路1135整合于同一芯片且直流电压转换电路1133整合于同一芯片，甚至还可以将直流电压转换电路1133、电平转换电路1131a和Gamma校正电路1135三者整合于同一芯片。
再者，再另一个实施方式中，如图2B所示，可以将Gamma校正电路1135整合于源驱动电路1115中。
综上所述，本申请前述实施例针对传统TCONLESS产品，进行系统架构优化，将驱动电路板113a的连接器CN1和系统板13上的连接器CN2的引脚数量进行缩减，例如缩减至51Pin，并对系统板13与液晶面板之间负责信号传输的连接器CN1、CN2的引脚功能定义进行标准化设计，其可以降低连接器的成本，并使得公版系统板成为可能；如此一来显示器厂商例如TV厂商可以使用单一系统板搭配不同液晶面板厂商的产品，从而大幅提升系统板设计的通用性。
再者，不同于图1和图2A所示实施例，图3和图4所示实施例中的电路1130包括：包括电平转换电路1131b、直流电压转换电路1133、Gamma校正电路1135、存储电路1137和时序转换电路1139。
其中，直流电压转换电路1133电连接供电电压引脚组Vin、电平转换电路1131b和Gamma校正电路1135，且被配置成根据供电电压引脚组Vin输入的供电电压例如+12V产生栅极开关电压例如VGH、VGL和工作电压例如VAA分别至电平转换电路1131b和Gamma校正电路1135。当然，可以理解的是，直流电压转换电路1133还可以为电平转换电路1131b、Gamma校正电路1135、存储电路1137、时序转换电路1139和源驱动电路1115等提供电源电压例如数字电压VDD和模拟电压HVAA。
时序转换电路1139电连接基准时序信号引脚组STV、CKV且被配置成对基准时序信号引脚组STV、CKV输入的基准时序信号进行转换以得到转换后基准时序信号例如ST_in、CK1_in、CK2_in、LC_in、RST_in。
电平转换电路1131b电连接时序转换电路1139且被配置成根据所述转换后基准时序信 号ST_in、CK1_in、CK2_in、LC_in、RST_in和所述栅极开关电压VGH、VGL产生栅极控制信号例如ST、CKx、LCx、RST至栅驱动电路1113。
Gamma校正电路1135被配置成根据所述工作电压VAA产生多个Gamma电压例如GMAx至源驱动电路1115。再者，Gamma校正电路1135例如还电连接所述数据通信接口协议引脚组中的IIC(Inter-Integrated Circuit)接口协议引脚组，从而可以通过IIC接口协议与系统板13上的系统级芯片131a进行串行通信。
存储电路1137电连接所述数据通信接口协议引脚组中的SPI(Serial Peripheral Interface，串行外设接口)接口协议引脚组，其例如包含非易失性存储器比如闪存，以用于存储与面板品味相关的资料，比如DeMura资料、Gamma资料等等。
再者，值得一提的是，在一个具体实施方式中，时序转换电路1139和电平转换电路1131b、直流电压转换电路1133及Gamma校正电路1135中的任意一者或多者整合于同一个芯片，例如时序转换电路1139和电平转换电路1131b整合于同一个芯片，或者时序转换电路1139和直流电压转换电路1133整合于同一个芯片，或者时序转换电路1139和Gamma校正电路1135整合于同一个芯片，又或者时序转换电路1139、电平转换电路1131b、直流电压转换电路1133和Gamma校正电路1135四者整合于同一个芯片，等等。
另外，不同于前述表1、表2和表3所示的连接器CN1/CN2的引脚数据和功能定义，下附表4提供了一种含68Pin的连接器CN1/CN2。
表4连接器CN1/CN2的68个引脚的一种功能定义表
Figure PCTCN2019096806-appb-000004
从表4可知，连接器CN1/CN2包含供电电压引脚组(Vin)、用于传输数字视频图像信号的P2P接口引脚组(P2P接口)、数据通信接口协议引脚组(IIC接口、SPI接口)和基准时序信号引脚组(ST_in、CK1_in、CK2_in、LC_in、RST_in)，且所述P2P接口引脚组(P2P接口) 包括多个差分信号引脚对。再者，每相邻两个差分信号引脚对之间设置有接地引脚(GND)，其可以提升P2P接口信号的抗干扰能力。
对应于前述表4的68Pin连接器CN1/CN2，图5所示的系统级芯片(System-On Chip，SOC)131b通过连接器CN1直接输出基准时序信号引脚例如ST_in、CK1_in、CK2_in、LC_in、RST_in，相应地电平转换电路1131b电连接基准时序信号引脚组(ST_in、CK1_in、CK2_in、LC_in、RST_in)且被配置成根据基准时序信号引脚组(ST_in、CK1_in、CK2_in、LC_in、RST_in)输入的基准时序信号和栅极开关电压例如VGH、VGL产生栅极控制信号例如ST、CKx、LCx、RST至栅驱动电路1113。
另外，值得说明的是，本申请实施例中源驱动电路板组件并不限于图1和图3所示包括两个驱动电路板113a及113b，还可以包括其他数量的驱动电路板。例如图6所示，源驱动电路板组件仅包括单个驱动电路板113a；又或者，如图7所示，源驱动电路板组件包括三个驱动电路板113a、113b及113b。再者，从图6和图7还可以得知，系统板131a例如还设置有电源管理电路133例如采用PMIC芯片，其电连接至连接器CN2以向供电电压引脚组Vin提供直流电压例如+12V，以及还电连接系统级芯片131a以向其提供电源电压。
至此，由前述实施例可知，本申请实施例针对传统TCONLESS产品，进行系统架构优化，将驱动电路板113a的连接器CN1和系统板13上的连接器CN2的引脚数量进行缩减，例如缩减至68pin，60pin，甚至51Pin，乃至更少，并对系统板13与液晶面板之间负责信号传输的连接器CN1、CN2的引脚功能定义进行标准化设计，其可以降低连接器的成本，并使得公版系统板成为可能；如此一来显示器厂商例如TV厂商可以使用单一系统板搭配不同液晶面板厂商的产品，从而大幅提升系统板设计的通用性。
另外，值得说明的是，本申请实施例的连接器CN1/CN2还可以有其他不同的引脚功能定义，例如下列的表5和表6所示。
表5连接器CN1/CN2的60个引脚的另一种功能定义表
Figure PCTCN2019096806-appb-000005
表6连接器CN1/CN2的60个引脚的再一种功能定义表
Figure PCTCN2019096806-appb-000006
具体地，在表5和表6中，数据通信接口协议引脚组仅包含一种数据通信接口协议引脚例如SPI接口，而非前述表1、表2、表3和表4所示的包含两种数据通信接口协议引脚例如IIC接口和SPI接口。再者，表5中的基准时序信号引脚数为两个，分别为起始脉冲信号STV引脚和时钟信号CKV引脚；表6中的基准时序信号引脚数为六个，分别为起始脉冲信号ST_in引脚、高频时钟信号CK1_in引脚、高频时钟信号CK2_in引脚、低频时钟信号LC_in引脚、复位信号RST_in引脚和终止信号Terminate_in引脚。
又或者，在如下表7所示的实施例中，基准时序信号引脚数为五个，分别为起始脉冲信号ST_in引脚、高频时钟信号CK_in引脚、终止信号Terminate_in引脚、复位信号RST_in引脚和低频时钟信号LC_in引脚。
表7连接器CN1/CN2的68个引脚的另一种功能定义表
Figure PCTCN2019096806-appb-000007
Figure PCTCN2019096806-appb-000008
此外，可以理解的是，前述各个实施例仅为本申请的示例性说明，在技术特征不冲突、结构不矛盾、不违背本申请的发明目的前提下，各个实施例的技术方案可以任意组合、搭配使用。再者，可以理解的是，前述各个实施例中电路1130的直流电压转换电路1133、电平转换电路1131a/1131b和Gamma校正电路1135并不限于分布在单个驱动电路板113a上，其也可以分布在多个驱动电路板上例如图1中的驱动电路板113a和113b上，或者图7中的驱动电路板113a、113b和113c上。此外，可以理解的是，对于源驱动电路板组件上的连接器CN1，在实际应用时，其IIC接口协议引脚组和SPI接口协议引脚组也可以部分或全部闲置不使用。另外，需要说明的是，本申请实施例中负责系统板13和源驱动电路板组件之间信号传输的连接器不局限于68Pin连接器、60Pin连接器、51Pin连接器，也不限制各个功能引脚的具体排列顺序，但凡包含P2P接口、供电电压引脚组、数据通信接口协议引脚组和基准时序信号引脚组，均应在本申请保护范围内。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多路单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多路网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (25)

  1. 一种液晶面板，其特征在于，包括：
    显示面板，包括显示区域和电连接所述显示区域的栅驱动电路及源驱动电路；以及
    源驱动电路板组件，为与所述源驱动电路接触连接的电路板组件且设置有电路和电连接所述电路的连接器；
    其中，所述电路电连接所述栅驱动电路和所述源驱动电路，所述连接器包含供电电压引脚组、用于传输所述液晶面板所需全部数字视频图像信号的P2P接口引脚组、数据通信接口协议引脚组和基准时序信号引脚组，且所述P2P接口引脚组包括多个差分信号引脚对。
  2. 根据权利要求1所述的液晶面板，其特征在于，所述数据通信接口协议引脚组包括IIC接口协议引脚组和/或SPI接口协议引脚组，以及所述连接器的引脚数量为68、60或51。
  3. 根据权利要求1所述的液晶面板，其特征在于，所述电路包括电平转换电路、直流电压转换电路和Gamma校正电路；其中，
    所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；
    所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及
    所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
  4. 根据权利要求1所述的液晶面板，其特征在于，所述电路包括电平转换电路、直流电压转换电路、Gamma校正电路和时序转换电路；其中，
    所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路所述Gamma校正电路；
    所述时序转换电路电连接所述基准时序信号引脚组且被配置成对所述基准时序信号引脚组输入的基准时序信号进行转换以得到转换后基准时序信号；
    所述电平转换电路电连接所述时序转换电路且被配置成根据所述转换后基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及
    所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
  5. 根据权利要求4所述的液晶面板，其特征在于，所述时序转换电路和所述电平转换电路、所述直流电压转换电路及所述Gamma校正电路中的任意一者或多者整合于同一个芯片。
  6. 根据权利要求1所述的液晶面板，其特征在于，所述电路包括电平转换电路和直流电压转换电路，且所述源驱动电路整合有Gamma校正电路；其中，
    所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；
    所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及
    所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压供所述源驱动电路使用。
  7. 根据权利要求3或4或5所述的液晶面板，其特征在于，所述电路还包括存储电路，且所述存储电路电连接所述数据通信接口协议引脚组中的第一数据通信接口协议引脚组；以及所述Gamma校正电路和所述直流电压转换电路电连接所述数据通信接口协议引脚组中的第二数据通信接口协议引脚组。
  8. 根据权利要求3所述的液晶面板，其特征在于，所述源驱动电路板组件包括多个驱动电路板，所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
  9. 根据权利要求4或5所述的液晶面板，其特征在于，所述源驱动电路板组件包括多个驱动电路板，所述时序转换电路、所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
  10. 根据权利要求1所述的液晶面板，其特征在于，所述基准时序信号引脚组由两个引脚构成且所述两个引脚分别为起始脉冲信号引脚和时钟信号引脚；或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚和复位信号引脚；或者，所述基准时序信号引脚组由六个引脚构成且所述六个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚；又或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚。
  11. 一种系统板，适用于一种主动式矩阵显示装置，其特征在于，所述系统板设置有系统级芯片和电连接所述系统级芯片的连接器；其中，所述连接器包含供电电压引脚组、用于传输数字视频图像信号的P2P接口引脚组、数据通信接口协议引脚组和基准时序信号引脚组，且所述P2P接口引脚组包括多个差分信号引脚对。
  12. 根据权利要求11所述的系统板，其特征在于，所述数据通信接口协议引脚组包括IIC接口协议引脚组和/或SPI接口协议引脚组，以及所述连接器的引脚数量为68、60或51。
  13. 根据权利要求11所述的系统板，其特征在于，所述系统板还设置有电源管理电路，且所述电源管理电路电连接所述供电电压引脚组和所述系统级芯片；以及所述系统级芯片电连接所述连接器的所述P2P接口引脚组、所述数据通信接口协议引脚组和所述基准时序信号引脚组。
  14. 根据权利要求11所述的系统板，其特征在于，所述基准时序信号引脚组由两个引脚构成且所述两个引脚分别为起始脉冲信号引脚和时钟信号引脚；或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚和复位信号引脚；或者，所述基准时序信号引脚组由六个引脚构成且所述六个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚；又或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚。
  15. 一种主动式矩阵显示装置，其特征在于，包括：
    显示面板，包括显示区域和电连接所述显示区域的栅驱动电路及源驱动电路；
    源驱动电路板组件，为与所述源驱动电路接触连接的电路板组件且设置有电路和电连 接所述电路的第一连接器；其中所述电路电连接所述栅驱动电路和所述源驱动电路，所述第一连接器包含供电电压引脚组、用于传输数字视频图像信号的P2P接口引脚组数据通信接口协议引脚组和基准时序信号引脚组，且所述P2P接口引脚组包括多个差分信号引脚对；以及
    系统板，设置有系统级芯片和电连接所述系统级芯片的第二连接器，其中所述第二连接器通过连接件电连接所述第一连接器。
  16. 根据权利要求15所述的主动式矩阵显示装置，其特征在于，所述源驱动电路板组件为偶数个相连接的驱动电路板，且所述连接件为单条软排线；以及所述系统板仅通过所述单条软排线向所述源驱动电路板组件传输数字视频图像信号。
  17. 根据权利要求15所述的主动式矩阵显示装置，其特征在于，所述数据通信接口协议引脚组包括IIC接口协议引脚组和/或SPI接口协议引脚组，以及所述连接器的引脚数量为68、60或51。
  18. 根据权利要求15所述的主动式矩阵显示装置，其特征在于，所述电路包括电平转换电路、直流电压转换电路和Gamma校正电路；其中，
    所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；
    所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及
    所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
  19. 根据权利要求15所述的主动式矩阵显示装置，其特征在于，所述电路包括电平转换电路、直流电压转换电路、Gamma校正电路和时序转换电路；其中，
    所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；
    所述时序转换电路电连接所述基准时序信号引脚组且被配置成对所述基准时序信号引脚组输入的基准时序信号进行转换以得到转换后基准时序信号；
    所述电平转换电路电连接所述时序转换电路且被配置成根据所述转换后基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及
    所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压至所述源驱动电路。
  20. 根据权利要求19所述的主动式矩阵显示装置，其特征在于，所述时序转换电路和所述电平转换电路、所述直流电压转换电路及所述Gamma校正电路中的任意一者或多者整合于同一个芯片。
  21. 根据权利要求15所述的主动式矩阵显示装置，其特征在于，所述电路包括电平转换电路和直流电压转换电路，且所述源驱动电路整合有Gamma校正电路；其中，
    所述直流电压转换电路电连接所述供电电压引脚组、所述电平转换电路和所述Gamma校正电路，且被配置成根据所述供电电压引脚组输入的供电电压产生栅极开关电压和工作电压分别至所述电平转换电路和所述Gamma校正电路；
    所述电平转换电路电连接所述基准时序信号引脚组且被配置成根据所述基准时序信号 引脚组输入的基准时序信号和所述栅极开关电压产生栅极控制信号至所述栅驱动电路；以及
    所述Gamma校正电路被配置成根据所述工作电压产生多个Gamma电压供所述源驱动电路使用。
  22. 根据权利要求18、19或20所述的主动式矩阵显示装置，其特征在于，所述电路还包括存储电路，且所述存储电路电连接所述数据通信接口协议引脚组中的第一数据通信接口协议引脚组；以及所述Gamma校正电路和所述直流电压转换电路电连接所述数据通信接口协议引脚组中的第二数据通信接口协议引脚组。
  23. 根据权利要求18所述的主动式矩阵显示装置，其特征在于，所述源驱动电路板组件包括多个驱动电路板，所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
  24. 根据权利要求19或20所述的主动式矩阵显示装置，其特征在于，所述源驱动电路板组件包括多个驱动电路板，所述时序转换电路、所述电平转换电路、所述直流电压转换电路和所述Gamma校正电路分布于所述多个驱动电路板中不同者上，或者分布于所述多个驱动电路板中同一者上。
  25. 根据权利要求15所述的主动式矩阵显示装置，其特征在于，所述基准时序信号引脚组由两个引脚构成且所述两个引脚分别为起始脉冲信号引脚和时钟信号引脚；或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚和复位信号引脚；又或者，所述基准时序信号引脚组由六个引脚构成且所述六个引脚分别为起始脉冲信号引脚、第一高频时钟信号引脚、第二高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚；又或者，所述基准时序信号引脚组由五个引脚构成且所述五个引脚分别为起始脉冲信号引脚、高频时钟信号引脚、低频时钟信号引脚、复位信号引脚和终止信号引脚。
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