WO2020253515A1 - 像素电路及其控制方法、显示装置 - Google Patents

像素电路及其控制方法、显示装置 Download PDF

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Publication number
WO2020253515A1
WO2020253515A1 PCT/CN2020/093880 CN2020093880W WO2020253515A1 WO 2020253515 A1 WO2020253515 A1 WO 2020253515A1 CN 2020093880 W CN2020093880 W CN 2020093880W WO 2020253515 A1 WO2020253515 A1 WO 2020253515A1
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Prior art keywords
switching
electrode
control signal
sub
transistor
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PCT/CN2020/093880
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English (en)
French (fr)
Inventor
孙佳
雷嗣军
高贤永
高亮
曾凡建
孙艳生
李云松
吴欢
张朋
冉博
廖海军
Original Assignee
京东方科技集团股份有限公司
重庆京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 重庆京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/254,877 priority Critical patent/US11335262B2/en
Publication of WO2020253515A1 publication Critical patent/WO2020253515A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit, a control method thereof, and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • the driving transistor when a data signal is input to the pixel circuit, the driving transistor will output a driving current.
  • the driving current can drive a light emitting device (for example, an OLED (Organic Light Emitting Diode, organic light emitting diode)) to emit light.
  • the size of the drive current can be controlled by controlling the voltage difference between the data signal and the power supply voltage, and thus the brightness of the display of the light-emitting device.
  • a pixel circuit including: a pixel driving circuit configured to output a driving current; a light emitting device configured to emit light according to different light emission modes under the driving of the driving current
  • the light emitting device includes a first electrode structure, a second electrode structure, and a functional layer between the first electrode structure and the second electrode structure; and a mode selection circuit configured to be configured according to different The mode selection signal selects different light emission modes
  • the mode selection circuit includes: a first switch sub-circuit, which is electrically connected to the pixel driving circuit and the first electrode structure, and is configured to respond to different mode selection signals Performing different first conduction modes; and a second switch sub-circuit, electrically connected to the first voltage terminal and the second electrode structure, respectively, and configured to perform different second conduction modes in response to different mode selection signals ;
  • the mode selection circuit is configured to determine the light emitting mode according to the first conduction mode and the second conduction mode.
  • the functional layer includes a light-emitting layer; and at least one of the first electrode structure and the second electrode structure includes a plurality of electrodes spaced apart.
  • the first electrode structure includes a plurality of first electrodes spaced apart; and the second electrode structure includes a plurality of second electrodes spaced apart.
  • the light-emitting device is disposed on the initial structure layer; and the plurality of first electrodes includes a first sub-electrode and a second sub-electrode, and the plurality of second electrodes includes a third sub-electrode and a second sub-electrode.
  • the orthographic projection of the first sub-electrode on the initial structure layer and the orthographic projection of the third sub-electrode on the initial structure layer at least partially overlap
  • the second sub-electrode is on the The orthographic projection on the initial structure layer and the orthographic projection of the fourth sub-electrode on the initial structure layer at least partially overlap.
  • the first switching sub-circuit includes a first switching device and at least one first switching transistor
  • the second switching sub-circuit includes a second switching device and at least one second switching transistor
  • the mode The selection signal includes: a first control signal for controlling the first switching device, a second control signal for controlling the second switching device, and a third control signal for controlling the at least one first switching transistor And a fourth control signal for controlling the at least one second switching transistor.
  • the first connection terminal of the first switching device is electrically connected to the pixel driving circuit, and the plurality of second connection terminals of the first switching device are connected to the plurality of first electrodes of the light emitting device.
  • the first switching device is electrically connected in a one-to-one correspondence, and the first switching device is configured to respond to the first control signal to connect a first connection end of the first switching device to a plurality of second connections of the first switching device One of the terminals is connected; a first switching transistor is provided between any two adjacent first electrodes of the plurality of first electrodes, wherein the first electrode of the first switching transistor is electrically connected to the One first electrode of any two adjacent first electrodes, a second electrode of the first switching transistor is electrically connected to the other first electrode of any two adjacent first electrodes, the first switch The gate of the transistor is configured to receive the third control signal; the first connection terminal of the second switching device is electrically connected to the first voltage terminal, and the plurality of second connection terminals of the second switching device are electrically connected to the The pluralit
  • One of the plurality of second connection terminals of the second switching device is connected; and a second switching transistor is provided between any two adjacent second electrodes of the plurality of second electrodes, wherein the first The first electrode of the two switching transistors is electrically connected to one of the two adjacent second electrodes, and the second electrode of the second switching transistor is electrically connected to the two adjacent second electrodes The other second electrode of the second switching transistor is configured to receive the fourth control signal.
  • the first switching device includes a first PMOS transistor and a first NMOS transistor electrically connected to the first PMOS transistor; and the second switching device includes a second PMOS transistor and a first NMOS transistor electrically connected to the first PMOS transistor.
  • the second NMOS transistor electrically connected to the two PMOS transistors.
  • the plurality of second connecting ends of the first switching device includes two second connecting ends, and the plurality of second connecting ends of the second switching device includes two second connecting ends;
  • the at least A first switching transistor includes a first switching transistor; and the at least one second switching transistor includes a second switching transistor.
  • the first switch sub-circuit includes a plurality of third switch transistors
  • the second switch sub-circuit includes a plurality of fourth switch transistors
  • the mode selection signal includes a plurality of fifth control signals and multiple A sixth control signal
  • the plurality of first electrodes of the plurality of third switching transistors are electrically connected to the plurality of first electrodes of the light emitting device in one-to-one correspondence, and the plurality of first electrodes of the plurality of third switching transistors
  • the two electrodes are electrically connected to the pixel driving circuit, the gate of each third switching transistor is configured to receive a corresponding fifth control signal; and the plurality of first electrodes of the plurality of fourth switching transistors and the light emitting
  • the plurality of second electrodes of the device are electrically connected in one-to-one correspondence, the plurality of second electrodes of the plurality of fourth switching transistors are electrically connected to the first voltage terminal, and the gate of each fourth switching transistor is configured as Receive the corresponding sixth control signal.
  • the plurality of third switching transistors include two third switching transistors; the plurality of fourth switching transistors include two fourth switching transistors.
  • the light emitting mode includes a first light emitting mode, a second light emitting mode, and a third light emitting mode; wherein, when the pixel driving circuit is input with the same gray scale data, the light emitting device is The light-emitting brightness in the first light-emitting mode is less than the light-emitting brightness of the light-emitting device in the second light-emitting mode, and the light-emitting brightness of the light-emitting device in the second light-emitting mode is less than that of the light-emitting device in the first light-emitting mode. Luminous brightness in three-emission mode.
  • the pixel driving circuit includes a fifth switching transistor, a capacitor, and a driving transistor, wherein the first electrode of the fifth switching transistor is electrically connected to a data signal line, and the first electrode of the fifth switching transistor is electrically connected to a data signal line.
  • the two electrodes are electrically connected to the gate of the driving transistor, the gate of the fifth switching transistor is electrically connected to the gate control line, the first end of the capacitor is electrically connected to the gate of the driving transistor, the The second terminal of the capacitor is electrically connected to the second voltage terminal, the first electrode of the driving transistor is electrically connected to the second voltage terminal, and the second electrode of the driving transistor is electrically connected to the mode selection circuit.
  • the first sub-electrode and the second sub-electrode both have a comb-like structure, and the comb-like structure of the comb-like structure of the first sub-electrode and the comb-like structure of the second sub-electrode
  • the third sub-electrode and the fourth sub-electrode both have a comb-like structure, and the comb-like teeth of the third sub-electrode and the comb-like structure of the fourth sub-electrode
  • the structure of the comb teeth are set crosswise.
  • the area of the first sub-electrode is equal to the area of the second sub-electrode, and the area of the third sub-electrode is equal to The areas of the fourth sub-electrodes are equal.
  • a display device including: a plurality of pixel circuits as described above.
  • the display device further includes a timing controller configured to provide the mode selection signal to the plurality of pixel circuits.
  • a control method for a pixel circuit wherein the pixel circuit includes a pixel drive circuit, a mode selection circuit, and a light emitting device, and the control method includes: the pixel drive The circuit outputs a driving current according to the data signal; the mode selection circuit selects different light-emitting modes according to different mode selection signals; and the light-emitting device is driven by the driving current to emit different brightness according to the different light-emitting modes Light.
  • the light emitting mode includes a first light emitting mode, a second light emitting mode, and a third light emitting mode; wherein, when the pixel driving circuit is input with the same gray scale data, the light emitting device is The light-emitting brightness in the first light-emitting mode is less than the light-emitting brightness of the light-emitting device in the second light-emitting mode, and the light-emitting brightness of the light-emitting device in the second light-emitting mode is less than that of the light-emitting device in the first light-emitting mode. Luminous brightness in three-emission mode.
  • the light emitting device includes: a plurality of spaced apart first electrodes, a spaced apart plurality of second electrodes, and a function between the plurality of first electrodes and the plurality of second electrodes
  • the functional layer includes at least a light-emitting layer, the light-emitting device is disposed on the initial structure layer, the plurality of first electrodes includes a first sub-electrode and a second sub-electrode, and the plurality of second electrodes includes a third A sub-electrode and a fourth sub-electrode, the orthographic projection of the first sub-electrode on the initial structure layer at least partially overlaps with the orthographic projection of the third sub-electrode on the initial structure layer, and the second sub-electrode
  • the orthographic projection of the electrode on the initial structure layer and the orthographic projection of the fourth sub-electrode on the initial structure layer at least partially overlap; wherein the mode selection circuit selects different light emitting modes according to different mode selection signals
  • the first switching sub-circuit includes a first switching device and at least one first switching transistor
  • the second switching sub-circuit includes a second switching device and at least one second switching transistor
  • the mode selection The signal includes a first control signal for controlling the first switching device, a second control signal for controlling the second switching device, a third control signal for controlling the at least one first switching transistor, and a For controlling the fourth control signal of the at least one second switching transistor
  • the first connection terminal of the first switching device is electrically connected to the pixel driving circuit
  • the plurality of second connection terminals of the first switching device are electrically connected to
  • the plurality of first electrodes of the light emitting device are electrically connected in one-to-one correspondence
  • the first switching device is configured to connect the first connection terminal of the first switching device to the first control signal in response to the first control signal.
  • One of the plurality of second connection terminals of the first switching device is connected; a first switching transistor is provided between any two adjacent first electrodes of the plurality of first electrodes, wherein the first switching transistor The first electrode of the switching transistor is electrically connected to one of the two adjacent first electrodes, and the second electrode of the first switching transistor is electrically connected to the one of the two adjacent first electrodes.
  • Another first electrode, the gate of the first switching transistor is configured to receive the third control signal;
  • the first connection terminal of the second switching device is electrically connected to the first voltage terminal, and the second The plurality of second connection terminals of the switching device are electrically connected to the plurality of second electrodes of the light emitting device in a one-to-one correspondence, and the second switching device is configured to respond to the second control signal to connect the second
  • the first connection terminal of the switching device is connected to one of the plurality of second connection terminals of the second switching device; and between any two adjacent second electrodes of the plurality of second electrodes,
  • the mode selection circuit selects different modes according to different mode selection signals
  • the step of the light emitting mode includes:
  • the level of the second control signal connects the first connection terminal of the second switching device with the one second connection terminal of the second switching device, and applies the third control signal to the first switching transistor Turning off the first switching transistor, and applying the fourth control signal to the second switching transistor to turn off the second switching transistor; or applying the first control signal to the first switching device to turn off
  • the first connection terminal of the first switching device is connected to the second connection terminal of the first switching device, and the second control signal is applied to the second switching device to make the first connection terminal of the second switching device Connected to the second connection terminal of the second switching device, applying the third control signal to the first switching transistor to turn on the first switching transistor, and applying the first switching transistor to the second switching transistor Four control signals enable the second switch transistor to be turned on.
  • the third control signal is the same as the fourth control signal.
  • the first switching sub-circuit includes a plurality of third switching transistors
  • the second switching sub-circuit includes a plurality of fourth switching transistors
  • the mode selection signal includes a plurality of fifth control signals and multiple A sixth control signal
  • the plurality of first electrodes of the plurality of third switching transistors are electrically connected to the plurality of first electrodes of the light emitting device in one-to-one correspondence
  • the plurality of first electrodes of the plurality of third switching transistors The two electrodes are electrically connected to the pixel driving circuit
  • the gate of each third switching transistor is configured to receive a corresponding fifth control signal
  • the plurality of second electrodes of the device are electrically connected in one-to-one correspondence
  • the plurality of second electrodes of the plurality of fourth switching transistors are electrically connected to the first voltage terminal
  • the gate of each fourth switching transistor is configured as Receiving the corresponding sixth control signal; the step of the mode selection circuit selecting different
  • FIG. 1 is a structural diagram showing a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view showing a light emitting device according to an embodiment of the present disclosure
  • FIG. 3 is a top view showing a light emitting device according to an embodiment of the present disclosure
  • FIG. 4 is a structural diagram showing a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 5 is a structural diagram showing a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 6A is a timing diagram showing a control signal for a pixel circuit according to an embodiment of the present disclosure
  • 6B is a timing diagram showing control signals for a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 6C is a timing diagram showing a control signal for a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 7 is a flowchart showing a control method for a pixel circuit according to an embodiment of the present disclosure
  • FIG. 8 is a structural diagram showing a display device according to an embodiment of the present disclosure.
  • a specific device when it is described that a specific device is located between the first device and the second device, there may or may not be an intermediate device between the specific device and the first device or the second device.
  • the specific device When it is described that a specific device is connected to another device, the specific device may be directly connected to the other device without an intermediate device, or may not be directly connected to the other device but has an intermediate device.
  • the organic material layer of the organic light emitting diode has a certain thickness.
  • the inventors of the present disclosure found that since the organic material layer is formed by vapor deposition, it is difficult to control the uniformity of the thickness of the organic material layer.
  • the uneven thickness of the organic material layer will affect the uniformity of the display.
  • these thin film transistors will also have a problem of unevenness, which will also affect the uniformity of the display. In the normal high-gray-scale display, due to the high brightness, it is difficult for human eyes to find the unevenness of the display.
  • the OLED display device has a problem of uneven display.
  • the embodiments of the present disclosure provide a pixel circuit to improve the display uniformity of the display device.
  • the pixel circuit according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 1 is a structural diagram showing a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit includes a pixel driving circuit 110, a mode selection circuit 120 and a light emitting device 130.
  • the pixel driving circuit 110 is configured to output a driving current.
  • the pixel driving circuit 110 is configured to output a driving current according to a data signal.
  • the driving current may be transmitted to the light emitting device 130 through the mode selection circuit 120 to drive the light emitting device to emit light.
  • the mode selection circuit 120 is configured to select different lighting modes according to different mode selection signals S mod .
  • the light emitting device 130 is configured to be driven by the driving current output by the pixel driving circuit 110, and emits light of different brightness according to different light emitting modes.
  • the lighting mode may include a first lighting mode, a second lighting mode, and a third lighting mode.
  • the light-emitting brightness of the light-emitting device 130 in the first light-emitting mode is smaller than that of the light-emitting device 130 in the second light-emitting mode, and the light-emitting device 130 emits light in the second light-emitting mode.
  • the light-emitting brightness in the mode is smaller than that of the light-emitting device 130 in the third light-emitting mode.
  • the light emitting device may include: a first electrode structure, a second electrode structure, and a functional layer between the first electrode structure and the second electrode structure.
  • the functional layer may include a light-emitting layer.
  • the mode selection circuit may include a first switch sub-circuit 121 and a second switch sub-circuit 122.
  • the first switch sub-circuit 121 is electrically connected to the pixel driving circuit 110 and the first electrode structure, respectively.
  • the first switch sub-circuit 121 may be configured to execute different first conduction modes in response to different mode selection signals.
  • the first conduction mode is the connection state when the first switch sub-circuit is turned on.
  • the second switch sub-circuit 122 is electrically connected to the first voltage terminal and the second electrode structure (not shown in FIG. 1), respectively.
  • the second switch sub-circuit 122 may be configured to execute different second conduction modes in response to different mode selection signals.
  • the second conduction mode is a connection state when the second switch sub-circuit is turned on.
  • the mode selection circuit 120 may be configured to determine the light emission mode according to the first conduction mode and the second conduction mode. For example, the mode selection circuit determines different light emitting modes under different first conduction modes and different second conduction modes.
  • the pixel driving circuit outputs a driving current; the mode selection circuit selects different light-emitting modes according to different mode selection signals; the light-emitting device is driven by the driving current and emits light of different brightness according to different light-emitting modes.
  • the brightness is as uniform as possible, thereby improving the uniformity of the display of the display device. For example, the uniformity of low grayscale display can be improved.
  • the display panel includes a plurality of pixel circuits. At least some of the pixel circuits in the plurality of pixel circuits may receive the same mode selection signal. For example, pixel circuits in a partial area of the display panel may receive the same mode selection signal, or the plurality of pixel circuits of the display panel may receive the same mode selection signal.
  • At least one of the first electrode structure and the second electrode structure of the light emitting device includes a plurality of electrodes spaced apart.
  • the first electrode structure may include a plurality of first electrodes spaced apart.
  • the second electrode structure may include a plurality of second electrodes spaced apart.
  • FIG. 2 is a schematic cross-sectional view showing a light emitting device according to an embodiment of the present disclosure.
  • the light emitting device may include: a plurality of spaced apart first electrodes 210 (as a first electrode structure), a plurality of spaced apart second electrodes 220 (as a second electrode structure), and a plurality of The functional layer 230 between the first electrode 210 and the plurality of second electrodes 220.
  • the functional layer 230 includes at least a light-emitting layer.
  • the functional layer may also include an electron transport layer, a hole transport layer, an electron blocking layer, and a hole blocking layer.
  • the light emitting device may be disposed on the initial structure layer 240.
  • the initial structure layer 240 may include a substrate.
  • the initial structure layer may also include a structure layer for thin film transistors on the substrate.
  • the initial structure layer may also include an anode layer that is electrically connected to the thin film transistor.
  • the plurality of first electrodes 210 may include a first sub-electrode 211 and a second sub-electrode 212.
  • the plurality of second electrodes 220 may include a third sub-electrode 223 and a fourth sub-electrode 224.
  • the orthographic projection of the first sub-electrode 211 on the initial structure layer 240 and the orthographic projection of the third sub-electrode 223 on the initial structure layer 240 at least partially overlap.
  • the orthographic projection of the second sub-electrode 212 on the initial structure layer 240 and the orthographic projection of the fourth sub-electrode 224 on the initial structure layer 240 at least partially overlap.
  • the first electrode is a cathode and the second electrode is an anode.
  • Figure 2 shows a light-emitting device with dual cathodes and dual anodes.
  • the double cathodes and double anodes are uniformly distributed on the functional layer 230 respectively.
  • the first electrode structure of the light emitting device shown in FIG. 2 includes two sub-electrodes, and the second electrode structure also includes two sub-electrodes.
  • the number of sub-electrodes included in the first electrode structure and the second electrode structure of the embodiment of the present disclosure is not limited to this.
  • the first electrode structure and the second electrode structure may each include more than two sub-electrodes.
  • one of the two electrode structures includes one sub-electrode, and the other includes two or more sub-electrodes.
  • different first electrodes and different second electrodes can be selected for transmitting the driving current, so that the light emitting layer of the light emitting device emits light.
  • the area where the light emitting device is driven to emit light is different.
  • the first sub-electrode 211 and the fourth sub-electrode 224 may be selected for transmitting the driving current, or the second sub-electrode 212 and the third sub-electrode 223 may be selected for transmitting the driving current.
  • the first sub-electrode 211 and the third sub-electrode 223 may be selected for transmitting driving current, or the second sub-electrode 212 and the fourth sub-electrode 224 may be selected for transmitting driving current.
  • the first sub-electrode 211, the second sub-electrode 212, the third sub-electrode 223, and the fourth sub-electrode 224 can all be selected to transmit driving current.
  • the area where the light-emitting device is driven to emit light in different light-emitting modes can meet the condition: S1 ⁇ S2 ⁇ S3, where S1 is the area where the light-emitting device is driven to emit light in the first light-emitting mode, and S2 is the light-emitting area. The area where the device is driven to emit light in the second light emitting mode, and S3 is the area where the light emitting device is driven to emit light in the third light emitting mode.
  • the light-emitting brightness of the light-emitting device in different light-emitting modes can meet the condition: L1 ⁇ L2 ⁇ L3, where L1 is the light-emitting brightness of the light-emitting device in the first light-emitting mode, and L2 is the light-emitting device of the light-emitting device in the second light-emitting mode Brightness, L3 is the light-emitting brightness of the light-emitting device in the third light-emitting mode.
  • the light emitting device can emit light according to different light emitting areas. For example, in low grayscale display, the light emitting device can be made to select a smaller light emitting area. In this case, a larger driving current can be used to drive the light emitting device to emit low-brightness light. In this way, it is beneficial to achieve precise control of the driving current, and try to avoid the display uniformity problem caused by the low current in low gray scale display in the related art.
  • FIG. 3 is a top view showing a light emitting device according to an embodiment of the present disclosure.
  • the schematic cross-sectional view of the light emitting device shown in FIG. 2 may be a schematic cross-sectional view of the structure taken along the line AA′ in FIG. 3.
  • FIG. 3 shows exemplary shapes of the first sub-electrode 211 and the second sub-electrode 212.
  • the first sub-electrode 211 and the second sub-electrode 212 may respectively have portions that cross each other.
  • both the first sub-electrode 211 and the second sub-electrode 212 have a comb-shaped structure
  • the comb-shaped structure of the first sub-electrode 211 and the comb-shaped structure of the second sub-electrode 212 have a comb structure. Tooth cross setting. In this way, the first sub-electrodes 211 and the second sub-electrodes 212 can be more evenly distributed.
  • the area of the first sub-electrode and the area of the second sub-electrode are equal. This facilitates control of the light-emitting area of the light-emitting device.
  • the third sub-electrode 223 may have the same shape as the first sub-electrode 211, and the fourth sub-electrode 224 may have the same shape as the second sub-electrode 212.
  • the third sub-electrode 223 and the fourth sub-electrode 224 both have a comb-like structure, and the third sub-electrode 223 has a comb-like structure.
  • the comb teeth and the comb teeth of the comb-like structure of the fourth sub-electrode 224 are intersected.
  • the area of the third sub-electrode is equal to the area of the fourth sub-electrode. This facilitates control of the light-emitting area of the light-emitting device.
  • each sub-electrode shown in FIG. 3 is only schematic, and the scope of the embodiments of the present disclosure is not limited to this.
  • the shape of the sub-electrodes may also be round or square.
  • FIG. 4 is a structural diagram showing a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 4 shows specific circuit structures of the pixel driving circuit 110, the mode selection circuit 120', and the light emitting device 130 according to some embodiments.
  • the mode selection circuit 120' may include a first switch sub-circuit 121' and a second switch sub-circuit 122'.
  • a first switching sub-circuit 121 ' may include a first switching device S 1 and at least one of the first switching transistor T 1.
  • the second switching sub-circuit 122' may include a second switching device S 2 and at least one second switching transistor T 2 .
  • the mode selection signal S mod may include: a first control signal V Ctl1 for controlling the first switching device, a second control signal V Ctl2 for controlling the second switching device, and a second control signal V Ctl2 for controlling the at least one first switching transistor T V Ctl3 third control signal for controlling the at least one second switching transistor T 1 as a fourth control signal of V Ctl4 2.
  • At least one of said first switching transistor T 1 comprises a first switching transistor.
  • At least one second switching transistor T 2 comprises a second switching transistor.
  • the first switching device S is connected to a first terminal 311 in FIG. 41 the pixel driving circuit 110 is electrically connected.
  • a plurality of first switching device S 1 is connected to a second end of the plurality of the light emitting device 130 is electrically connected to a first electrode of one to one.
  • the plurality of first switching device S 1 is connected to the second end may comprise two second connection terminal 321 and 322.
  • a first switching device S 1 is connected to a second terminal 321 is electrically connected to the first sub-electrode of the light emitting device 211, the other of the first switching device S 1 is connected to a second terminal of the light emitting device 322 and the second sub- The electrode 212 is electrically connected.
  • the control terminal of the first switching device S 1 330 is configured to receive a first control signal V Ctl1.
  • the first switching device S 1 is configured to respond to a first control signal V Ctl1, the first switch connected to a first connection device 311 and the first switch is connected to a second end of the plurality of devices.
  • the first switching device S 1 is connected to a first terminal 311 connected thereto a second end 321 is connected.
  • the first switching device S 1 is connected to a first terminal 311 connected thereto a second end 322 connected to the other.
  • a first switching device S 1 may include a PMOS (P-channel Metal Oxide Semiconductor , P -channel metal oxide semiconductor) transistors (e.g., referred to as a first PMOS transistor) and a PMOS transistor is electrically connected to the An NMOS (N-channel Metal Oxide Semiconductor) transistor (for example, called the first NMOS transistor).
  • a PMOS P-channel Metal Oxide Semiconductor , P -channel metal oxide semiconductor
  • NMOS N-channel Metal Oxide Semiconductor
  • the first electrode of the first PMOS transistor and the first electrode of the first NMOS transistor are used as the first connection terminal 311 to be electrically connected to the pixel driving circuit.
  • the second electrode of the first PMOS transistor (for example, as the second connecting terminal 321) and the second electrode of the first NMOS transistor (for example, as the second connecting terminal 322) are electrically connected to different first electrodes of the light emitting device.
  • the gate of the first PMOS transistor and the gate of the first NMOS transistor together can serve as the control terminal 330 for receiving the first control signal V Ctl1 .
  • the first switching device S 1 is only exemplary, and the implementation of the first switching device S 1 adopted in the embodiment of the present disclosure is not limited to this.
  • a first switching transistor is provided between any two adjacent first electrodes of the plurality of first electrodes of the light emitting device 130.
  • the first electrode of the first switching transistor is electrically connected to one of the two adjacent first electrodes, and the second electrode of the first switching transistor is electrically connected to the two adjacent first electrodes The other first electrode.
  • a first switching transistor T 1 is provided between the first sub-electrode 211 and the second sub-electrode 212 of the light emitting device.
  • the first electrode of the first switching transistor T 1 is electrically connected to the first sub-electrode 211 of the light emitting device, and the second electrode of the first switching transistor T 1 is electrically connected to the second sub electrode 212 of the light emitting device.
  • the first gate of the switching transistor T 1 is configured to receive a third control signal V Ctl3.
  • the light emitting device 130 shown in FIG. 4 has two first electrodes, so that a first switching transistor is provided between the two first electrodes.
  • a first switching transistor may be provided between any two adjacent first electrodes, and each first electrode A switch transistor is controlled by the corresponding third control signal.
  • the second switching device S is connected to a first end 411 to the first voltage terminal (e.g., common ground terminal) 501 of FIG. 42 are electrically connected.
  • the plurality of second connection ends of the second switching device S 2 are electrically connected to the plurality of second electrodes of the light emitting device 130 in a one-to-one correspondence.
  • the plurality of second connection terminals of the second switching device S 2 may include two second connection terminals 421 and 422. Connecting a second terminal of the second switching device S 2 421 is electrically connected to the third sub-electrode of the light emitting device 223, the other of the second switching device S 2 is connected to a second terminal of the light emitting device 422 and the fourth sub-electrode 224 Electric connection.
  • the control terminal 430 of the second switching device S 2 is configured to receive the second control signal V Ctl2 .
  • the second switching device S 2 is configured to be responsive to a second control signal V Ctl2, connected to the first terminal of the second switching device 411 is connected to a plurality of the second switching device of the second connecting end.
  • a first connector terminal 2 to a second switching device S 411 connected thereto a second end 421 is connected.
  • the second switching device S 2 connects its first connection terminal 411 to its other second connection terminal 422.
  • the second switching device S 2 may include a PMOS transistor (e.g., referred to as second PMOS transistor) and a NMOS transistor is electrically connected to the PMOS transistor (e.g., referred to as second NMOS transistor).
  • the first electrode of the second PMOS transistor and the first electrode of the second NMOS transistor are used as the first connection terminal 411 to be electrically connected to the first voltage terminal.
  • the second electrode of the second PMOS transistor for example, as the second connecting terminal 421) and the second electrode of the second NMOS transistor (for example, as the second connecting terminal 422) are electrically connected to different second electrodes of the light emitting device.
  • the gate of the second PMOS transistor and the gate of the second NMOS transistor can be used together as the control terminal 430 for receiving the second control signal V Ctl2 .
  • the second switching device S 2 is only exemplary, and the implementation manner of the second switching device S 2 adopted in the embodiment of the present disclosure is not limited to this.
  • a second switching transistor is provided between any two adjacent second electrodes of the plurality of second electrodes of the light emitting device 130.
  • the first electrode of the second switching transistor is electrically connected to a second electrode of any two adjacent second electrodes, and the second electrode of the second switching transistor is electrically connected to any two adjacent second electrodes The other second electrode.
  • a second switching transistor T 2 is provided between the third sub-electrode 223 and the fourth sub-electrode 224 of the light emitting device.
  • the first electrode of the second switching transistor T 2 is electrically connected to the third sub-electrode 223 of the light emitting device, and the second electrode of the second switching transistor T 2 is electrically connected to the fourth sub electrode 224 of the light emitting device.
  • Gate of the second switching transistor T 2 is configured to receive a fourth control signal V Ctl4.
  • the light-emitting device 130 shown in FIG. 4 has two second electrodes, so that a second switch transistor is provided between the two second electrodes.
  • a second switch transistor is provided between the two second electrodes.
  • the embodiments of the present disclosure are not limited to this.
  • a second switching transistor may be provided between any two adjacent second electrodes, and each second electrode The two switching transistors are controlled by the corresponding fourth control signal.
  • the conductivity type of the first switching transistor T 1 and the conductivity type of the second switching transistor T 2 are the same.
  • the first switching transistor T 1 and the second switching transistor T 2 are both PMOS transistors or both NMOS transistors.
  • the third control signal V Ctl3 may be the same as the fourth control signal V Ctl4 . This can reduce the number of control signals.
  • the pixel driving circuit 110 may include a fifth switching transistor T 5 , a capacitor C 0 and a driving transistor T 0 .
  • T The first electrode of the fifth switching transistor 5 is connected to the data signal line L D.
  • the fifth switching transistor T 5 the second electrode connected to the gate of the driving transistor T 0.
  • the gate of the fifth switching transistor T 5 is electrically connected to the gate control line L G.
  • the first terminal of the capacitor C 0 is electrically connected to the gate of the driving transistor T 0 .
  • the second terminal of the capacitor C 0 is electrically connected to the second voltage terminal 502.
  • the voltage of the second voltage terminal 502 is different from the voltage of the first voltage terminal 501.
  • the second voltage terminal 502 may be a power supply voltage terminal.
  • the first electrode of the driving transistor T 0 is electrically connected to the second voltage terminal 502.
  • the second electrode of the driving transistor T 0 is electrically connected to the mode selection circuit 120'.
  • the second electrode of the driving transistor T 0 is electrically connected to the first connection terminal 311 of the first switching device S 1 .
  • circuit structure of the pixel driving circuit shown in FIG. 4 is only exemplary, and the embodiments of the present disclosure may also adopt pixel driving circuits with other circuit structures. Therefore, the scope of the embodiments of the present disclosure is not limited to this.
  • a first terminal connected to a first switching device S 1 311 is connected to a second connecting end 321, and having a second electrical under the control of the second control signal level V Ctl2, the second switching device S 2 is connected to a first end 411 and a second connection terminal 421 is connected.
  • the first switch sub-circuit 121' executes the first conduction mode with the first connection state
  • the second switch sub-circuit 122' executes the second conduction mode with the first connection state.
  • the driving current output by the pixel driving circuit 110 flows through the first sub-electrode 211, the functional layer, and the third sub-electrode 223 of the light-emitting device 130, so that the light-emitting device 130 emits light with medium brightness L2 in the second light-emitting mode.
  • the first connection end a first switching device S 1 311 is connected to the other end of the second connector 322, and the second having under the control of the second control signal V Ctl2 of the four-level, a second terminal connected to a first switching device S 2 and the other end 411 of the second connector 422 is connected.
  • the third level is different from the first level
  • the fourth level is different from the second level.
  • the driving current output by the pixel driving circuit 110 flows through the second sub-electrode 212, the functional layer, and the fourth sub-electrode 224 of the light-emitting device 130, so that the light-emitting device 130 emits light with medium brightness L2 in the second light-emitting mode.
  • a second terminal connected to a first switching device 411 is S 2 and the other end 422 connected to the second connection.
  • the first switch sub-circuit 121' executes the first conduction mode with the first connection state
  • the second switch sub-circuit 122' executes the second conduction mode with the second connection state.
  • the driving current output by the pixel driving circuit 110 flows through the first sub-electrode 211, the functional layer, and the fourth sub-electrode 224 of the light-emitting device 130, so that the light-emitting device 130 emits light with low luminance L1 in the first light-emitting mode.
  • the first connection end a first switching device S 1 311 is connected to the other end of the second connector 322, and in under the control of the second control signal V Ctl2 having the second level, connecting a first end of the second switching device S 2 411 and a second connecting end 421 of the connector.
  • the first switch sub-circuit 121' executes the first conduction mode with the second connection state
  • the second switch sub-circuit 122' executes the second conduction mode with the first connection state.
  • the driving current output by the pixel driving circuit 110 flows through the second sub-electrode 212, the functional layer, and the third sub-electrode 223 of the light-emitting device 130, so that the light-emitting device 130 emits light with low luminance L1 in the first light-emitting mode.
  • the first switching transistor T 1 under the control of a third control signal V Ctl3 turned off, the second switching transistor T 2 is turned off under the control of the fourth control signal V Ctl4.
  • the switching transistor T 1 is a first PMOS transistor
  • the first switching transistor T 1 is turned off under the control of a third control signal of the high level V Ctl3.
  • the first switch transistor T 1 may also be an NMOS transistor.
  • the second switching transistor T 2 is a PMOS transistor
  • the second switching transistor T 2 is turned off under the control of the high-level fourth control signal V Ctl4 .
  • the second switch transistor T 2 may also be an NMOS transistor.
  • a first control signal under the control V Ctl1 a first switching device connected to a first terminal 311 connected to S 1 and the second connection terminal 321 or 322, under the control of the second control signal V Ctl2,
  • the first connection terminal 411 of the second switching device S 2 is connected to the second connection terminal 421 or 422.
  • the first switching transistor T 1 is turned on under the control of the third control signal V Ctl3 (for example, a low-level third control signal)
  • the second switching transistor T 2 is turned on under the control of a fourth control signal V Ctl4 (for example, the low-level third control signal).
  • Four control signals are turned on under the control.
  • the driving current output by the pixel driving circuit 110 flows through the first sub-electrode 211, the second sub-electrode 212, the functional layer, the third sub-electrode 223, and the fourth sub-electrode 224 of the light-emitting device 130, so that the light-emitting device 130 is in the third In the light-emitting mode, it emits light with high brightness L3.
  • the above-mentioned pixel circuit realizes that light of different brightness is emitted according to different light emitting modes. In this way, even at low gray scales, the drive current can be made not too small, which is conducive to accurate control of the drive current, and try to avoid the display uniformity problem caused by the low current in the low gray scale display in the related technology. .
  • FIG. 5 is a structural diagram showing a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 5 shows the specific circuit structure of the pixel driving circuit 110, the mode selection circuit 120", and the light emitting device 130 according to some embodiments.
  • the circuit structure of the pixel driving circuit 110 has been described in detail above, and will not be omitted here. Repeat.
  • the mode selection circuit 120" may include a first switch sub-circuit 121" and a second switch sub-circuit 122".
  • the first switching sub-circuit 121′′ may include a plurality of third switching transistors.
  • the plurality of third switching transistors may include two third switching transistors T 31 and T 32.
  • the second switch sub-circuit 122" may include a plurality of fourth switch transistors.
  • the plurality of fourth switching transistors may include two fourth switching transistors T 41 and T 42 .
  • the third switch transistor may be a PMOS transistor or an NMOS transistor
  • the fourth switch transistor may be a PMOS transistor or an NMOS transistor.
  • the mode selection signal S mod may include multiple fifth control signals and multiple sixth control signals.
  • FIG. 5 shows a third switching transistor for controlling a T V Ctl51 and a fifth control signal for controlling the third switching transistor T further fifth control signal V 32 of the Ctl52 31, is also shown in FIG.
  • a sixth control signal V Ctl61 for controlling a fourth switching transistor T 41 and a sixth control signal V Ctl62 for controlling another fourth switching transistor T 42 are shown .
  • the plurality of first electrodes of the plurality of third switching transistors are electrically connected to the plurality of first electrodes of the light emitting device 130 in a one-to-one correspondence.
  • the first electrode of one third switching transistor T 31 is electrically connected to the first sub-electrode 211 of the light emitting device 130
  • the other third switching transistor T 32 has The first electrode is electrically connected to the second sub-electrode 212 of the light emitting device 130.
  • the plurality of second electrodes of the plurality of third switching transistors are electrically connected to the pixel driving circuit 110. For example, as shown in FIG.
  • the second electrodes of the two third switching transistors T 31 and T 32 are electrically connected to the driving transistor T 0 of the pixel driving circuit 110.
  • the gate of each third switching transistor is configured to receive a corresponding fifth control signal.
  • the gate of the one third switching transistor T 31 is configured to receive a fifth control signal V Ctl51
  • the gate of the other third switching transistor T 32 is configured to receive another A fifth control signal V Ctl52 .
  • the plurality of first electrodes of the plurality of fourth switching transistors and the plurality of second electrodes of the light emitting device 130 are electrically connected in a one-to-one correspondence.
  • the first electrode of one fourth switching transistor T 41 is electrically connected to the third sub-electrode 223 of the light emitting device 130
  • the other fourth switching transistor T 42 The first electrode is electrically connected to the fourth sub-electrode 224 of the light emitting device 130.
  • the plurality of second electrodes of the plurality of fourth switch transistors are electrically connected to the first voltage terminal 501. For example, as shown in FIG.
  • the second electrodes of the two fourth switching transistors T 41 and T 42 are electrically connected to the first voltage terminal (for example, the common ground terminal) 501.
  • the gate of each fourth switching transistor is configured to receive a corresponding sixth control signal.
  • a gate of said fourth switching transistor T 41 is configured to receive a sixth control signal V Ctl61
  • the other gate of the fourth switching transistor T 42 is configured to receive the other A sixth control signal V Ctl62 .
  • the structure of the pixel circuit is provided.
  • the first switch sub-circuit is controlled by a plurality of fifth control signals
  • the second switch sub-circuit is controlled by a plurality of sixth control signals.
  • the pixel circuit can emit light of different brightness according to different light emitting modes. In this way, for a display device that includes a plurality of pixel circuits, the light-emitting brightness of different pixel circuits in the plurality of pixel circuits can be made as uniform as possible, thereby improving the uniformity of the display of the display device, especially in low grayscale display. .
  • FIG. 6A is a timing diagram showing a control signal for a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6A shows a timing diagram of a plurality of fifth control signals and a plurality of sixth control signals for the pixel circuit in the first light emitting mode.
  • the working process of the pixel circuit under the control of a plurality of fifth control signals and a plurality of sixth control signals is described in detail below in conjunction with FIGS. 5 and 6A.
  • the third switch transistor and the fourth switch transistor are both PMOS transistors as an example for description.
  • the third switching transistor T 31 is turned on On; under the control of the other fifth control signal V Ctl52 at a high level, the other third switching transistor T 32 is turned off; under the control of the sixth control signal V Ctl61 at a high level, The one fourth switch transistor T 41 is turned off; under the control of the other sixth control signal V Ctl62 at a low level, the other fourth switch transistor T 42 is turned on.
  • the pixel driving circuit The driving current output by 110 flows through the first sub-electrode 211, the functional layer, and the fourth sub-electrode 224 of the light-emitting device 130, so that the light-emitting device 130 emits light with low brightness L1 in the first light-emitting mode.
  • the third switching transistor T 31 Off; under the control of the other fifth control signal V Ctl52 at a low level, the other third switching transistor T 32 is turned on; under the control of the one sixth control signal V Ctl61 at a low level , The one fourth switch transistor T 41 is turned on; under the control of the other sixth control signal V Ctl62 at a high level, the other fourth switch transistor T 42 is turned off.
  • the pixel driving circuit The driving current output by 110 flows through the second sub-electrode 212, the functional layer and the third sub-electrode 223 of the light-emitting device 130, so that the light-emitting device 130 emits light with low brightness L1 in the first light-emitting mode.
  • FIG. 6B is a timing diagram showing a control signal for a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 6B shows a timing diagram of a plurality of fifth control signals and a plurality of sixth control signals for the pixel circuit in the second light emission mode.
  • the working process of the pixel circuit under the control of a plurality of fifth control signals and a plurality of sixth control signals will be described in detail below with reference to FIGS. 5 and 6B.
  • the third switch transistor and the fourth switch transistor are both PMOS transistors as an example for description.
  • the third switching transistor T 31 is turned on On; under the control of the other fifth control signal V Ctl52 at a high level, the other third switching transistor T 32 is turned off; under the control of the sixth control signal V Ctl61 at a low level, The one fourth switch transistor T 41 is turned on; under the control of the other sixth control signal V Ctl62 at a high level, the other fourth switch transistor T 42 is turned off.
  • the driving current output by the pixel driving circuit 110 will flow through the first sub-electrode 211, the functional layer, and the third sub-electrode 223 of the light-emitting device 130, so that the light-emitting device 130 emits light in the second light emission mode.
  • Light with brightness L2 Light with brightness L2.
  • the third switching transistor T 31 under the control of the fifth control signal V Ctl51 at a high level, the third switching transistor T 31 off; another at a low level in said fifth control signal V Ctl52 control, the further third switching transistor T 32 is turned on; under the control of a high level of the sixth control signal V Ctl61 , The one fourth switching transistor T 41 is turned off; under the control of the other sixth control signal V Ctl62 at a low level, the other fourth switching transistor T 42 is turned on.
  • the driving current output by the pixel driving circuit 110 will flow through the second sub-electrode 212, the functional layer, and the fourth sub-electrode 224 of the light-emitting device 130, so that the light-emitting device 130 emits light in the second light emission mode.
  • Light with brightness L2 Light with brightness L2.
  • FIG. 6C is a timing diagram showing a control signal for a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 6C shows a timing chart of a plurality of fifth control signals and a plurality of sixth control signals for the pixel circuit in the third light emission mode.
  • the working process of the pixel circuit under the control of a plurality of fifth control signals and a plurality of sixth control signals will be described in detail below in conjunction with FIGS. 5 and 6C.
  • the third switch transistor and the fourth switch transistor are both PMOS transistors as an example for description.
  • the fifth control signals V Ctl51 and V Ctl52 and the sixth control signals V Ctl61 and V Ctl62 are all low-level signals. Under the control of these signals, the third switching transistors T 31 and T 32 and the fourth switching transistors T 41 and T 42 are all turned on.
  • the driving current output by the pixel driving circuit 110 flows through the first sub-electrode 211, the second sub-electrode 212, the functional layer, the third sub-electrode 223, and the fourth sub-electrode 224 of the light-emitting device 130, so that the light-emitting device 130 is In the third light emitting mode, light with high brightness L3 is emitted.
  • control signals used can all pass
  • the timing controller has unified control.
  • the timing controller can control the mode selection circuit to select the required light emitting mode after analyzing the grayscale data to be displayed.
  • the light-emitting material of the OLED (as a light-emitting device) includes organic materials
  • the organic material will rapidly attenuate, resulting in a decrease in brightness and a reduced life of the OLED.
  • the intermittent driving of the light-emitting device according to the above-mentioned control signal in the embodiment of the present disclosure can slow down the decay speed of the light-emitting device and prolong the service life.
  • the pixel circuit of the embodiment of the present disclosure can slow down the attenuation speed of the light-emitting device, thereby reducing the inconsistency of the attenuation of the light-emitting materials of the sub-pixels of different colors, thereby improving the display effect of the display device.
  • a display device may include a plurality of pixel circuits as described above (for example, the pixel circuits shown in FIG. 1, FIG. 4, or FIG. 5).
  • the display device may be any product or component with a display function, such as a display panel, a display screen, a monitor, a mobile phone, a tablet computer, a notebook computer, a television, or a navigator.
  • FIG. 8 is a structural diagram showing a display device according to an embodiment of the present disclosure. As shown in FIG. 8, the display device may include a plurality of pixel circuits 811, 812, and 813.
  • the display device may further include a timing controller 820.
  • the timing controller 820 is configured to provide a mode selection signal to the plurality of pixel circuits.
  • FIG. 7 is a flowchart showing a control method for a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit may include a pixel driving circuit, a mode selection circuit, and a light emitting device.
  • the control method may include steps S702 to S706.
  • step S702 the pixel driving circuit outputs a driving current according to the data signal.
  • step S704 the mode selection circuit selects different light emitting modes according to different mode selection signals.
  • step S706 the light emitting device is driven by the driving current to emit light of different brightness according to different light emitting modes.
  • the lighting mode may include a first lighting mode, a second lighting mode, and a third lighting mode.
  • the light-emitting brightness of the light-emitting device in the first light-emitting mode is lower than the light-emitting brightness of the light-emitting device in the second light-emitting mode, and the light-emitting device emits light in the second light-emitting mode.
  • the brightness is smaller than that of the light-emitting device in the third light-emitting mode.
  • the pixel driving circuit outputs the driving current according to the data signal
  • the mode selection circuit selects different light-emitting modes according to different mode selection signals
  • the light-emitting device emits light of different brightness according to different light-emitting modes under the drive of the driving current.
  • the brightness is as uniform as possible, thereby improving the uniformity of the display of the display device. For example, the uniformity of the display device during low grayscale display can be improved.
  • the light emitting device may include a plurality of spaced apart first electrodes, a spaced apart plurality of second electrodes, and a functional layer between the plurality of first electrodes and the plurality of second electrodes.
  • the functional layer includes at least a light-emitting layer.
  • the light emitting device is arranged on the initial structure layer.
  • the plurality of first electrodes include a first sub-electrode and a second sub-electrode
  • the plurality of second electrodes include a third sub-electrode and a fourth sub-electrode.
  • the orthographic projection of the first sub-electrode on the initial structure layer and the orthographic projection of the third sub-electrode on the initial structure layer at least partially overlap.
  • the orthographic projection of the second sub-electrode on the initial structure layer and the orthographic projection of the fourth sub-electrode on the initial structure layer at least partially overlap.
  • this step S704 may include: in response to the mode selection signal corresponding to the first light emission mode, the mode selection circuit controls the driving current to flow through the first sub-electrode, the functional layer and the fourth sub-electrode, or controls the driving current Flow through the second sub-electrode, the functional layer and the third sub-electrode.
  • this step S704 may include: the mode selection circuit controls the driving current to flow through the first sub-electrode, the functional layer and the third sub-electrode in response to the mode selection signal corresponding to the second light-emitting mode, or controls the driving The current flows through the second sub-electrode, the functional layer and the fourth sub-electrode.
  • this step S704 may include: the mode selection circuit responds to the mode selection signal corresponding to the third light emission mode, controlling the driving current to flow through the first sub-electrode, the second sub-electrode, the functional layer, and the third sub-electrode. Electrodes and the fourth sub-electrode.
  • the first switching sub-circuit includes a first switching device and at least one first switching transistor
  • the second switching sub-circuit includes a second switching device and at least one second switching transistor.
  • the mode selection signal includes a first control signal for controlling the first switching device, a second control signal for controlling the second switching device, a third control signal for controlling the at least one first switching transistor, and a third control signal for controlling the at least one first switching transistor.
  • the fourth control signal of the at least one second switching transistor includes a first switching device and at least one first switching transistor
  • the mode selection signal includes a first control signal for controlling the first switching device, a second control signal for controlling the second switching device, a third control signal for controlling the at least one first switching transistor, and a third control signal for controlling the at least one first switching transistor.
  • the first connection terminal of the first switching device is electrically connected to the pixel driving circuit
  • the plurality of second connection terminals of the first switching device are electrically connected to the plurality of first electrodes of the light emitting device in one-to-one correspondence
  • the first switching device is configured as In response to the first control signal, the first connection terminal of the first switching device is connected to one of the plurality of second connection terminals of the first switching device.
  • a first switch transistor is provided between any two adjacent first electrodes of the plurality of first electrodes. The first electrode of the first switching transistor is electrically connected to one of the two adjacent first electrodes, and the second electrode of the first switching transistor is electrically connected to the two adjacent first electrodes.
  • the other first electrode of one electrode, and the gate of the first switching transistor is configured to receive the third control signal.
  • the first connection terminal of the second switching device is electrically connected to the first voltage terminal
  • the plurality of second connection terminals of the second switching device are electrically connected with the plurality of second electrodes of the light emitting device in a one-to-one correspondence
  • the second switching device is configured In response to the second control signal, the first connection terminal of the second switching device is connected to one of the second connection terminals of the second switching device.
  • a second switch transistor is provided between any two adjacent second electrodes of the plurality of second electrodes.
  • the first electrode of the second switching transistor is electrically connected to one of the two adjacent second electrodes
  • the second electrode of the second switching transistor is electrically connected to the two adjacent second electrodes.
  • the other second electrode of the two electrodes, and the gate of the second switch transistor is configured to receive the fourth control signal.
  • this step S704 may include: applying a first control signal having a first level to the first switching device so that the first connection terminal of the first switching device is connected to a second connection terminal of the first switching device,
  • the switching device applies a second control signal having a second level so that the first connection terminal of the second switching device is connected to a second connection terminal of the second switching device, and the third control signal is applied to the first switching transistor to make the first switch The transistor is turned off, and the fourth control signal is applied to the second switching transistor to turn off the second switching transistor.
  • this step S704 may include: applying a first control signal having a third level to the first switching device so that the first connection terminal of the first switching device is connected to another second connection terminal of the first switching device, The second switching device applies a second control signal having a fourth level so that the first connection terminal of the second switching device is connected to the other second connection terminal of the second switching device, and the third control signal is applied to the first switching transistor so that The first switching transistor is turned off, and the fourth control signal is applied to the second switching transistor to turn off the second switching transistor.
  • this step S704 may include: applying a first control signal having a first level to the first switching device so that the first connection terminal of the first switching device is connected to the one second connection terminal of the first switching device Connected, applying a second control signal having the fourth level to the second switching device so that the first connection terminal of the second switching device is connected to the other second connection terminal of the second switching device Connected, applying the third control signal to the first switching transistor to turn off the first switching transistor, and applying the fourth control signal to the second switching transistor to turn off the second switching transistor.
  • this step S704 may include: applying a first control signal having the third level to the first switching device so that the first connection end of the first switching device is connected to the all of the first switching device.
  • the other second connection terminal is connected, and a second control signal having the second level is applied to the second switching device so that the first connection terminal of the second switching device is connected to the all of the second switching device.
  • the one second connection terminal is connected, the third control signal is applied to the first switching transistor to turn off the first switching transistor, and the fourth control signal is applied to the second switching transistor to turn off the first switching transistor.
  • the second switching transistor is off.
  • this step S704 may include: applying the first control signal to the first switching device so that the first connection terminal of the first switching device is connected to the second connection terminal of the first switching device, The second switching device applies the second control signal so that the first connection terminal of the second switching device is connected to the second connection terminal of the second switching device, and the first switching device is applied to the first switching transistor.
  • Three control signals enable the first switching transistor to turn on, and applying the fourth control signal to the second switching transistor turns on the second switching transistor.
  • the third control signal is the same as the fourth control signal.
  • the first switching sub-circuit includes a plurality of third switching transistors
  • the second switching sub-circuit includes a plurality of fourth switching transistors.
  • the mode selection signal includes a plurality of fifth control signals and a plurality of sixth control signals.
  • the plurality of first electrodes of the plurality of third switching transistors are electrically connected to the plurality of first electrodes of the light emitting device in one-to-one correspondence, and the plurality of second electrodes of the plurality of third switching transistors are electrically connected to all The pixel drive circuit.
  • the gate of each third switching transistor is configured to receive a corresponding fifth control signal.
  • the plurality of first electrodes of the plurality of fourth switching transistors are electrically connected to the plurality of second electrodes of the light emitting device in one-to-one correspondence, and the plurality of second electrodes of the plurality of fourth switching transistors are electrically connected to all The first voltage terminal.
  • the gate of each fourth switching transistor is configured to receive a corresponding sixth control signal.
  • this step S704 may include: applying a low-level fifth control signal to a third switching transistor of the plurality of third switching transistors to turn on the one third switching transistor, and The other third switching transistor in the third switching transistor applies a high-level another fifth control signal to turn off the other third switching transistor, and to a fourth switching transistor among the plurality of fourth switching transistors. Applying a sixth control signal of a high level to turn off the one fourth switching transistor, and applying another sixth control signal of a low level to the other fourth switching transistor of the plurality of fourth switching transistors makes The other fourth switching transistor is turned on.
  • this step S704 may include: applying a high-level fifth control signal to a third switching transistor of the plurality of third switching transistors to turn off the one third switching transistor T 31 ,
  • the other third switching transistor of the plurality of third switching transistors applies another fifth control signal of a low level to make the other third switching transistor turn on, and to the first one of the plurality of fourth switching transistors.
  • the four switching transistors apply a low level sixth control signal to turn on the one fourth switching transistor, and apply a high level to another fourth switching transistor of the plurality of fourth switching transistors.
  • the sixth control signal turns off the other fourth switching transistor.
  • this step S704 may include: applying a low-level fifth control signal to a third switching transistor of the plurality of third switching transistors so that the one third switching transistor is turned on.
  • the other third switching transistor of the three third switching transistors applies another fifth control signal of a high level to turn off the other third switching transistor, and the fourth switching transistor of the plurality of fourth switching transistors is switched off.
  • a sixth control signal of a low level is applied to the transistor to turn on the one fourth switching transistor, and another sixth control signal of a high level is applied to the other fourth switching transistor of the plurality of fourth switching transistors The signal turns off the other fourth switching transistor.
  • the step S704 may include: applying a high-level fifth control signal to a third switching transistor of the plurality of third switching transistors to turn off the one third switching transistor, and The other third switching transistor in the third switching transistor applies another fifth control signal with a low level to turn on the other third switching transistor, and the fourth switching transistor among the plurality of fourth switching transistors is switched on.
  • a sixth control signal of a high level is applied to the transistor to turn off the one fourth switching transistor, and another sixth control signal of a low level is applied to the other fourth switching transistor of the plurality of fourth switching transistors The other fourth switching transistor is turned on.
  • this step S704 may include: applying a low-level fifth control signal to the plurality of third switching transistors to make the plurality of third switching transistors turn on, and applying a low-level fifth control signal to the plurality of fourth switching transistors. Applying a low-level sixth control signal turns on the plurality of fourth switching transistors.

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Abstract

一种像素电路及其控制方法、显示装置。像素电路包括像素驱动电路（110）、模式选择电路（120、120'、120''）和发光器件（130）。像素驱动电路（110）被配置为输出驱动电流。模式选择电路（120、120'、120''）用于根据不同的模式选择信号（Smod）选择不同的发光模式。发光器件（130）用于根据不同的发光模式发出不同亮度的光。发光器件（130）包括第一电极结构（210）、第二电极结构（220）和在第一电极结构（210）与第二电极结构（220）之间的功能层（230）。模式选择电路（120、120'、120''）包括第一开关子电路（121、121'、121''）和第二开关子电路（122、122'、122''）。第一开关子电路（121、121'、121''）被配置为响应于不同的模式选择信号（Smod）执行不同的第一导通模式。第二开关子电路（122、122'、122''）被配置为响应于不同的模式选择信号（Smod）执行不同的第二导通模式。模式选择电路（120、120'、120''）被配置为根据第一导通模式和第二导通模式确定发光模式。

Description

像素电路及其控制方法、显示装置
相关申请的交叉引用
本申请是以CN申请号为201910541367.7，申请日为2019年6月21日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其控制方法、显示装置。
背景技术
目前，AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极管)显示技术越来越受到广泛应用。例如，在相关技术的像素电路结构中，当数据信号输入到像素电路后，驱动晶体管就会输出驱动电流。该驱动电流能够驱动发光器件(例如OLED(Organic Light Emitting Diode，有机发光二极管))发光。可以通过控制数据信号与电源电压的压差来控制驱动电流的大小，进而控制发光器件的显示的亮度。
发明内容
根据本公开实施例的一个方面，提供了一种像素电路，包括：像素驱动电路，被配置为输出驱动电流；发光器件，被配置为在所述驱动电流的驱动下，根据不同的发光模式发出不同亮度的光，所述发光器件包括第一电极结构、第二电极结构和在所述第一电极结构与所述第二电极结构之间的功能层；以及模式选择电路，被配置为根据不同的模式选择信号选择不同的发光模式，所述模式选择电路包括：第一开关子电路，分别与所述像素驱动电路和所述第一电极结构电连接，被配置为响应于不同的模式选择信号执行不同的第一导通模式；以及第二开关子电路，分别与第一电压端和所述第二电极结构电连接，被配置为响应于不同的模式选择信号执行不同的第二导通模式；其中，所述模式选择电路被配置为根据所述第一导通模式和所述第二导通模式确定所述发光模式。
在一些实施例中，所述功能层包括发光层；以及所述第一电极结构和所述第二电极结构中的至少一个包括间隔开的多个电极。
在一些实施例中，所述第一电极结构包括间隔开的多个第一电极；以及所述第二电极结构包括间隔开的多个第二电极。
在一些实施例中，所述发光器件设置在初始结构层上；以及所述多个第一电极包括第一子电极和第二子电极，所述多个第二电极包括第三子电极和第四子电极，所述第一子电极在所述初始结构层上的正投影与所述第三子电极在所述初始结构层上的正投影至少部分重合，所述第二子电极在所述初始结构层上的正投影与所述第四子电极在所述初始结构层上的正投影至少部分重合。
在一些实施例中，所述第一开关子电路包括第一开关器件和至少一个第一开关晶体管，所述第二开关子电路包括第二开关器件和至少一个第二开关晶体管；以及所述模式选择信号包括：用于控制所述第一开关器件的第一控制信号、用于控制所述第二开关器件的第二控制信号、用于控制所述至少一个第一开关晶体管的第三控制信号和用于控制所述至少一个第二开关晶体管的第四控制信号。
在一些实施例中，所述第一开关器件的第一连接端与所述像素驱动电路电连接，所述第一开关器件的多个第二连接端与所述发光器件的多个第一电极一一对应地电连接，所述第一开关器件被配置为响应于所述第一控制信号，将所述第一开关器件的第一连接端与所述第一开关器件的多个第二连接端中的一个连接；在所述多个第一电极的任意相邻的两个第一电极之间均设置有一个第一开关晶体管，其中，该第一开关晶体管的第一电极电连接至所述任意相邻的两个第一电极的一个第一电极，该第一开关晶体管的第二电极电连接至所述任意相邻的两个第一电极的另一个第一电极，该第一开关晶体管的栅极被配置为接收所述第三控制信号；所述第二开关器件的第一连接端与所述第一电压端电连接，所述第二开关器件的多个第二连接端与所述发光器件的多个第二电极一一对应地电连接，所述第二开关器件被配置为响应于所述第二控制信号，将所述第二开关器件的第一连接端与所述第二开关器件的多个第二连接端中的一个连接；以及在所述多个第二电极的任意相邻的两个第二电极之间均设置有一个第二开关晶体管，其中，该第二开关晶体管的第一电极电连接至所述任意相邻的两个第二电极的一个第二电极，该第二开关晶体管的第二电极电连接至所述任意相邻的两个第二电极的另一个第二电极，该第二开关晶体管的栅极被配置为接收所述第四控制信号。
在一些实施例中，所述第一开关器件包括第一PMOS晶体管和与所述第一PMOS晶体管电连接的第一NMOS晶体管；以及所述第二开关器件包括第二PMOS晶体管和与所述第二PMOS晶体管电连接的第二NMOS晶体管。
在一些实施例中所述第一开关器件的多个第二连接端包括两个第二连接端，所述第二开关器件的多个第二连接端包括两个第二连接端；所述至少一个第一开关晶体管包括一个第一开关晶体管；以及所述至少一个第二开关晶体管包括一个第二开关晶体管。
在一些实施例中，所述第一开关子电路包括多个第三开关晶体管，所述第二开关子电路包括多个第四开关晶体管；所述模式选择信号包括多个第五控制信号和多个第六控制信号；所述多个第三开关晶体管的多个第一电极与所述发光器件的多个第一电极一一对应地电连接，所述多个第三开关晶体管的多个第二电极电连接至所述像素驱动电路，每个第三开关晶体管的栅极被配置为接收对应的第五控制信号；以及所述多个第四开关晶体管的多个第一电极与所述发光器件的多个第二电极一一对应地电连接，所述多个第四开关晶体管的多个第二电极电连接至所述第一电压端，每个第四开关晶体管的栅极被配置为接收对应的第六控制信号。
在一些实施例中，所述多个第三开关晶体管包括两个第三开关晶体管；所述多个第四开关晶体管包括两个第四开关晶体管。
在一些实施例中，所述发光模式包括第一发光模式、第二发光模式和第三发光模式；其中，在所述像素驱动电路被输入相同灰阶数据的情况下，所述发光器件在所述第一发光模式下的发光亮度小于所述发光器件在所述第二发光模式下的发光亮度，所述发光器件在所述第二发光模式下的发光亮度小于所述发光器件在所述第三发光模式下的发光亮度。
在一些实施例中，所述像素驱动电路包括：第五开关晶体管、电容器和驱动晶体管，其中，所述第五开关晶体管的第一电极电连接至数据信号线，所述第五开关晶体管的第二电极电连接至所述驱动晶体管的栅极，所述第五开关晶体管的栅极电连接至栅极控制线，所述电容器的第一端电连接至所述驱动晶体管的栅极，所述电容器的第二端电连接至第二电压端，所述驱动晶体管的第一电极电连接至所述第二电压端，所述驱动晶体管的第二电极电连接至所述模式选择电路。
在一些实施例中，所述第一子电极和所述第二子电极均具有梳状结构，且所述第一子电极的梳状结构的梳齿与所述第二子电极的梳状结构的梳齿交叉设置；以及所述第三子电极和所述第四子电极均具有梳状结构，且所述第三子电极的梳状结构的梳齿与所述第四子电极的梳状结构的梳齿交叉设置。
在一些实施例中，在与所述功能层的延展方向相平行的方向上，所述第一子电极 的面积和所述第二子电极的面积相等，且所述第三子电极的面积和所述第四子电极的面积相等。
根据本公开实施例的另一个方面，提供了一种显示装置，包括：多个如前所述的像素电路。
在一些实施例中，所述显示装置还包括：时序控制器，被配置向所述多个像素电路提供所述模式选择信号。
根据本公开实施例的另一个方面，提供了一种用于像素电路的控制方法，其中，所述像素电路包括像素驱动电路、模式选择电路和发光器件，所述控制方法包括：所述像素驱动电路根据数据信号输出驱动电流；所述模式选择电路根据不同的模式选择信号选择不同的发光模式；以及所述发光器件在所述驱动电流的驱动下，根据不同的所述发光模式发出不同亮度的光。
在一些实施例中，所述发光模式包括第一发光模式、第二发光模式和第三发光模式；其中，在所述像素驱动电路被输入相同灰阶数据的情况下，所述发光器件在所述第一发光模式下的发光亮度小于所述发光器件在所述第二发光模式下的发光亮度，所述发光器件在所述第二发光模式下的发光亮度小于所述发光器件在所述第三发光模式下的发光亮度。
在一些实施例中，所述发光器件包括：间隔开的多个第一电极、间隔开的多个第二电极和在所述多个第一电极和所述多个第二电极之间的功能层，所述功能层至少包括发光层，所述发光器件设置在初始结构层上，所述多个第一电极包括第一子电极和第二子电极，所述多个第二电极包括第三子电极和第四子电极，所述第一子电极在所述初始结构层上的正投影与所述第三子电极在所述初始结构层上的正投影至少部分重合，所述第二子电极在所述初始结构层上的正投影与所述第四子电极在所述初始结构层上的正投影至少部分重合；其中，所述模式选择电路根据不同的模式选择信号选择不同的发光模式的步骤包括：所述模式选择电路响应于与所述第一发光模式对应的模式选择信号，控制所述驱动电流流过所述第一子电极、所述功能层和所述第四子电极，或者控制所述驱动电流流过所述第二子电极、所述功能层和所述第三子电极；所述模式选择电路响应于与所述第二发光模式对应的模式选择信号，控制所述驱动电流流过所述第一子电极、所述功能层和所述第三子电极，或者控制所述驱动电流流过所述第二子电极、所述功能层和所述第四子电极；或者所述模式选择电路响应于与所述第三发光模式对应的模式选择信号，控制所述驱动电流流过所述第一子电极、所述第 二子电极、所述功能层、所述第三子电极和所述第四子电极。
在一些实施例中，所述第一开关子电路包括第一开关器件和至少一个第一开关晶体管，所述第二开关子电路包括第二开关器件和至少一个第二开关晶体管；所述模式选择信号包括用于控制所述第一开关器件的第一控制信号、用于控制所述第二开关器件的第二控制信号、用于控制所述至少一个第一开关晶体管的第三控制信号和用于控制所述至少一个第二开关晶体管的第四控制信号；所述第一开关器件的第一连接端与所述像素驱动电路电连接，所述第一开关器件的多个第二连接端与所述发光器件的多个第一电极一一对应地电连接，所述第一开关器件被配置为响应于所述第一控制信号，将所述第一开关器件的第一连接端与所述第一开关器件的多个第二连接端中的一个连接；在所述多个第一电极的任意相邻的两个第一电极之间均设置有一个第一开关晶体管，其中，该第一开关晶体管的第一电极电连接至所述任意相邻的两个第一电极的一个第一电极，该第一开关晶体管的第二电极电连接至所述任意相邻的两个第一电极的另一个第一电极，该第一开关晶体管的栅极被配置为接收所述第三控制信号；所述第二开关器件的第一连接端与所述第一电压端电连接，所述第二开关器件的多个第二连接端与所述发光器件的多个第二电极一一对应地电连接，所述第二开关器件被配置为响应于所述第二控制信号，将所述第二开关器件的第一连接端与所述第二开关器件的多个第二连接端中的一个连接；以及在所述多个第二电极的任意相邻的两个第二电极之间均设置有一个第二开关晶体管，其中，该第二开关晶体管的第一电极电连接至所述任意相邻的两个第二电极的一个第二电极，该第二开关晶体管的第二电极电连接至所述任意相邻的两个第二电极的另一个第二电极，该第二开关晶体管的栅极被配置为接收所述第四控制信号；所述模式选择电路根据不同的模式选择信号选择不同的发光模式的步骤包括：对所述第一开关器件施加具有第一电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的一个第二连接端连接，对所述第二开关器件施加具有第二电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；对所述第一开关器件施加具有第三电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的另一个第二连接端连接，对所述第二开关器件施加具有第四电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的另一个第二连接端连接，对所述第一开关晶体管 施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；对所述第一开关器件施加具有所述第一电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的所述一个第二连接端连接，对所述第二开关器件施加具有所述第四电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的所述另一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；对所述第一开关器件施加具有所述第三电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的所述另一个第二连接端连接，对所述第二开关器件施加具有所述第二电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的所述一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；或者对所述第一开关器件施加所述第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的第二连接端连接，对所述第二开关器件施加所述第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管导通，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管导通。
在一些实施例中，所述第三控制信号与所述第四控制信号相同。
在一些实施例中，所述第一开关子电路包括多个第三开关晶体管，所述第二开关子电路包括多个第四开关晶体管，所述模式选择信号包括多个第五控制信号和多个第六控制信号，所述多个第三开关晶体管的多个第一电极与所述发光器件的多个第一电极一一对应地电连接，所述多个第三开关晶体管的多个第二电极电连接至所述像素驱动电路，每个第三开关晶体管的栅极被配置为接收对应的第五控制信号，以及所述多个第四开关晶体管的多个第一电极与所述发光器件的多个第二电极一一对应地电连接，所述多个第四开关晶体管的多个第二电极电连接至所述第一电压端，每个第四开关晶体管的栅极被配置为接收对应的第六控制信号；所述模式选择电路根据不同的模式选择信号选择不同的发光模式的步骤包括：对所述多个第三开关晶体管中的一个第三开关晶体管施加低电平的一个第五控制信号使得所述一个第三开关晶体管导通，对所述多个第三开关晶体管中的另一个第三开关晶体管施加高电平的另一个第五控制 信号使得所述另一个第三开关晶体管截止，对所述多个第四开关晶体管中的一个第四开关晶体管施加高电平的一个第六控制信号使得所述一个第四开关晶体管截止，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加低电平的另一个第六控制信号使得所述另一个第四开关晶体管导通；对所述多个第三开关晶体管中的一个第三开关晶体管施加高电平的一个第五控制信号使得所述一个第三开关晶体管T 31截止，对所述多个第三开关晶体管中的另一个第三开关晶体管施加低电平的另一个第五控制信号使得所述另一个第三开关晶体管导通，对所述多个第四开关晶体管中的一个第四开关晶体管施加低电平的一个第六控制信号使得所述一个第四开关晶体管导通，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加高电平的另一个第六控制信号使得所述另一个第四开关晶体管截止；对所述多个第三开关晶体管中的一个第三开关晶体管施加低电平的一个第五控制信号使得所述一个第三开关晶体管导通，对所述多个第三开关晶体管中的另一个第三开关晶体管施加高电平的另一个第五控制信号使得所述另一个第三开关晶体管截止，对所述多个第四开关晶体管中的一个第四开关晶体管施加低电平的一个第六控制信号使得所述一个第四开关晶体管导通，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加高电平的另一个第六控制信号使得所述另一个第四开关晶体管截止；对所述多个第三开关晶体管中的一个第三开关晶体管施加高电平的一个第五控制信号使得所述一个第三开关晶体管截止，对所述多个第三开关晶体管中的另一个第三开关晶体管施加低电平的另一个第五控制信号使得所述另一个第三开关晶体管导通，对所述多个第四开关晶体管中的一个第四开关晶体管施加高电平的一个第六控制信号使得所述一个第四开关晶体管截止，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加低电平的另一个第六控制信号使得所述另一个第四开关晶体管导通；或者对所述多个第三开关晶体管施加低电平的第五控制信号使得所述多个第三开关晶体管均导通，以及对所述多个第四开关晶体管施加低电平的第六控制信号使得所述多个第四开关晶体管均导通。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是示出根据本公开一个实施例的像素电路的结构图；
图2是示出根据本公开一个实施例的发光器件的截面示意图；
图3是示出根据本公开一个实施例的发光器件的俯视图；
图4是示出根据本公开另一个实施例的像素电路的结构图；
图5是示出根据本公开另一个实施例的像素电路的结构图；
图6A是示出根据本公开一个实施例的用于像素电路的控制信号的时序图；
图6B是示出根据本公开另一个实施例的用于像素电路的控制信号的时序图；
图6C是示出根据本公开另一个实施例的用于像素电路的控制信号的时序图。
图7是示出根据本公开一个实施例的用于像素电路的控制方法的流程图；
图8是示出根据本公开一个实施例的显示装置的结构图。
应当明白，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定器件位于第一器件和第二器件之间时，在该特定器件与第一器件或第二器件之间可以存在居间器件，也可以不存在居间器件。当描述到特定器件连接其它器件时，该特定器件可以与所述其它器件直接连接而不具有居间器件，也可以不与所述其它器件直接连接而具有居间器件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
在相关技术中，有机发光二极管的有机材料层具有一定的厚度。本公开的发明人发现，由于该有机材料层是通过蒸镀形成的，因此很难控制该有机材料层厚度的均匀性。而有机材料层的厚度不均匀将会影响显示的均匀性。另外，在制造用于显示屏的薄膜晶体管的过程中，这些薄膜晶体管也会有不均匀的问题，这也会影响显示的均匀性。在正常高灰阶显示时，由于亮度高，人眼比较难地发现显示不均匀的现象。但是在低灰阶显示时，由于显示的驱动电流比较小，有机材料层厚度的不均匀和薄膜晶体管的不均匀等就会影响显示的均匀性。因此，在相关技术中，OLED显示装置存在显示不均匀的问题。
鉴于此，本公开的实施例提供了一种像素电路，以提高显示装置显示的均匀性。下面结合附图详细描述根据本公开一些实施例的像素电路。
图1是示出根据本公开一个实施例的像素电路的结构图。如图1所示，该像素电路包括像素驱动电路110、模式选择电路120和发光器件130。
该像素驱动电路110被配置为输出驱动电流。例如该像素驱动电路110被配置为根据数据信号输出驱动电流。例如，该驱动电流可以通过模式选择电路120传输到发光器件130以驱动发光器件发光。
该模式选择电路120被配置为根据不同的模式选择信号S mod选择不同的发光模式。
该发光器件130被配置在像素驱动电路110输出的驱动电流的驱动下，根据不同的发光模式发出不同亮度的光。
在一些实施例中，发光模式可以包括第一发光模式、第二发光模式和第三发光模式。在像素驱动电路110被输入相同灰阶数据的情况下，发光器件130在第一发光模式下的发光亮度小于该发光器件130在第二发光模式下的发光亮度，该发光器件130在第二发光模式下的发光亮度小于该发光器件130在第三发光模式下的发光亮度。
在一些实施例中，发光器件可以包括：第一电极结构、第二电极结构和在第一电极结构与第二电极结构之间的功能层。例如，该功能层可以包括发光层。
在一些实施例中，如图1所示，模式选择电路可以包括第一开关子电路121和第二开关子电路122。该第一开关子电路121分别与像素驱动电路110和第一电极结构电连接。该第一开关子电路121可以被配置为响应于不同的模式选择信号执行不同的第一导通模式。这里，第一导通模式为第一开关子电路导通时的连接状态。该第二开关子电路122分别与第一电压端和第二电极结构(图1中未示出)电连接。该第二开关子电路122可以被配置为响应于不同的模式选择信号执行不同的第二导通模式。这里，第二导通模式为第二开关子电路导通时的连接状态。模式选择电路120可以被配置为根据第一导通模式和第二导通模式确定发光模式。例如，模式选择电路在不同的第一导通模式和不同的第二导通模式下确定不同的发光模式。
至此，提供了根据本公开一些实施例的像素电路。在该像素电路中，像素驱动电路输出驱动电流；模式选择电路根据不同的模式选择信号选择不同的发光模式；发光器件在驱动电流的驱动下，根据不同的发光模式发出不同亮度的光。这样，虽然在显示装置的不同的像素电路中可能存在有机材料层厚度不均匀和薄膜晶体管不均匀的问题，但是由于不同的像素电路可以按照不同的发光模式发光，因此可以使得不同像素电路的发光亮度尽量均匀，从而提高显示装置显示的均匀性。例如，可以提高低灰阶显示的均匀性。
在一些实施例中，显示面板包括多个像素电路。所述多个像素电路中的至少部分像素电路可以接收同一模式选择信号。例如，在该显示面板的部分区域中的像素电路可以接收同一模式选择信号，或者，该显示面板的所述多个像素电路可以接收同一模式选择信号。
在一些实施例中，发光器件的第一电极结构和第二电极结构中的至少一个包括间隔开的多个电极。例如，该第一电极结构可以包括间隔开的多个第一电极。例如，该第二电极结构可以包括间隔开的多个第二电极。
图2是示出根据本公开一个实施例的发光器件的截面示意图。
如图2所示，该发光器件可以包括：间隔开的多个第一电极210(作为第一电极结构)、间隔开的多个第二电极220(作为第二电极结构)和在该多个第一电极210和该多个第二电极220之间的功能层230。该功能层230至少包括发光层。例如，该功能层还可以包括电子传输层、空穴传输层、电子阻挡层和空穴阻挡层等。
如图2所示，该发光器件可以设置在初始结构层240上。例如，该初始结构层240可以包括基板。又例如，该初始结构层还可以包括在基板上的用于薄膜晶体管的结构 层等。又例如，该初始结构层还可以包括与薄膜晶体管电连接的阳极层等。
在一些实施例中，如图2所示，所述多个第一电极210可以包括第一子电极211和第二子电极212。所述多个第二电极220可以包括第三子电极223和第四子电极224。第一子电极211在初始结构层240上的正投影与第三子电极223在该初始结构层240上的正投影至少部分重合。第二子电极212在初始结构层240上的正投影与第四子电极224在该初始结构层240上的正投影至少部分重合。例如，第一电极为阴极，第二电极为阳极。这样，图2示出了具有双阴极和双阳极的发光器件。该双阴极和双阳极分别均匀地分布在功能层230上。
需要说明的是，图2所示的发光器件的第一电极结构包括两个子电极，第二电极结构也包括两个子电极。但是，本公开实施例的第一电极结构和第二电极结构所分别包括的子电极的数量并不仅限于此。例如，第一电极结构和第二电极结构可以分别包括多于两个的子电极。又例如，这两个电极结构中的一个包括一个子电极，另一个包括两个或更多个子电极。
在一些实施例中，对于不同的发光模式，可以选择不同的第一电极和不同的第二电极用于传输驱动电流，从而使得发光器件的发光层发光。对于不同的发光模式，发光器件被驱动发光的面积是不同的。
例如，对于第一发光模式，可以选择第一子电极211和第四子电极224用于传输驱动电流，或者选择第二子电极212和第三子电极223用于传输驱动电流。对于第二发光模式，可以选择第一子电极211和第三子电极223用于传输驱动电流，或者选择第二子电极212和第四子电极224用于传输驱动电流。对于第三发光模式，可以选择第一子电极211、第二子电极212、第三子电极223和第四子电极224均用于传输驱动电流。
在这样的情况下，可以使得发光器件在不同发光模式下被驱动发光的面积满足条件：S1<S2<S3，其中，S1为发光器件在第一发光模式下被驱动发光的面积，S2为发光器件在第二发光模式下被驱动发光的面积，S3为发光器件在第三发光模式下被驱动发光的面积。这样可以使得发光器件在不同发光模式下的发光亮度满足条件：L1<L2<L3，其中，L1为发光器件在第一发光模式下的发光亮度，L2为发光器件在第二发光模式下的发光亮度，L3为发光器件在第三发光模式下的发光亮度。
在上述实施例中，通过选择不同的发光模式可以使得发光器件按照不同的发光面积进行发光。例如，在低灰阶显示时，可以使得发光器件选择较小的发光面积。在这 样的情况下，可以使用较大的驱动电流来驱动发光器件发出低亮度的光。这样，有利于对驱动电流实现精确控制，尽量避免在相关技术中由于低灰阶显示时电流较小而导致的显示均匀性问题。
图3是示出根据本公开一个实施例的发光器件的俯视图。其中，图2所示的发光器件的截面示意图可以是沿着图3中的线A-A'截取的结构的截面示意图。
图3示出了第一子电极211和第二子电极212的示例性的形状。该第一子电极211和第二子电极212可以分别具有互相交叉的部分。例如，如图3所示，第一子电极211和第二子电极212均具有梳状结构，且第一子电极211的梳状结构的梳齿与第二子电极212的梳状结构的梳齿交叉设置。这样可以使得第一子电极211和第二子电极212分布地更加均匀。在一些实施例中，在与功能层的延展方向相平行的方向上，第一子电极的面积和第二子电极的面积相等。这样方便控制发光器件的发光面积。
在一些实施例中，第三子电极223可以具有与第一子电极211相同的形状，第四子电极224可以具有与第二子电极212相同的形状。例如，与图3所示的第一子电极211和第二子电极212类似地，第三子电极223和第四子电极224均具有梳状结构，且第三子电极223的梳状结构的梳齿与第四子电极224的梳状结构的梳齿交叉设置。在一些实施例中，在与功能层的延展方向相平行的方向上，第三子电极的面积和第四子电极的面积相等。这样方便控制发光器件的发光面积。
需要说明的是，图3所示的各个子电极的形状仅是示意性的，本公开实施例的范围并不仅限于此。例如，子电极的形状也可以是圆形或方形等。
图4是示出根据本公开另一个实施例的像素电路的结构图。例如，图4中示出了根据一些实施例的像素驱动电路110、模式选择电路120'和发光器件130的具体电路结构。
在一些实施例中，如图4所示，模式选择电路120'可以包括第一开关子电路121'和第二开关子电路122'。
在一些实施例中，如图4所示，第一开关子电路121'可以包括第一开关器件S 1和至少一个第一开关晶体管T 1。第二开关子电路122'可以包括第二开关器件S 2和至少一个第二开关晶体管T 2。模式选择信号S mod可以包括：用于控制第一开关器件的第一控制信号V Ctl1、用于控制第二开关器件的第二控制信号V Ctl2、用于控制所述至少一个第一开关晶体管T 1的第三控制信号V Ctl3和用于控制所述至少一个第二开关晶体管T 2的第四控制信号V Ctl4。
在一些实施例中，如图4所示，所述至少一个第一开关晶体管T 1包括一个第一开关晶体管。所述至少一个第二开关晶体管T 2包括一个第二开关晶体管。
如图4所示，第一开关器件S 1的第一连接端311与像素驱动电路110电连接。第一开关器件S 1的多个第二连接端与发光器件130的多个第一电极一一对应地电连接。例如，该第一开关器件S 1的多个第二连接端可以包括两个第二连接端321和322。该第一开关器件S 1中的一个第二连接端321与发光器件的第一子电极211电连接，该第一开关器件S 1中的另一个第二连接端322与发光器件的第二子电极212电连接。第一开关器件S 1的控制端330被配置为接收第一控制信号V Ctl1。该第一开关器件S 1被配置为响应于第一控制信号V Ctl1，将该第一开关器件的第一连接端311与该第一开关器件的多个第二连接端中的一个连接。例如，该第一开关器件S 1将其第一连接端311与其一个第二连接端321连接。又例如，该第一开关器件S 1将其第一连接端311与其另一个第二连接端322连接。
在一些实施例中，第一开关器件S 1可以包括一个PMOS(P-channel Metal Oxide Semiconductor，P沟道金属氧化物半导体)晶体管(例如称为第一PMOS晶体管)和与该PMOS晶体管电连接的一个NMOS(N-channel Metal Oxide Semiconductor，N沟道金属氧化物半导体)晶体管(例如称为第一NMOS晶体管)。例如，该第一PMOS晶体管的第一电极与该第一NMOS晶体管的第一电极一起作为第一连接端311电连接至像素驱动电路。该第一PMOS晶体管的第二电极(例如作为第二连接端321)和该第一NMOS晶体管的第二电极(例如作为第二连接端322)分别电连接至发光器件的不同的第一电极。该第一PMOS晶体管的栅极和该第一NMOS晶体管的栅极可以一起作为控制端330用于接收第一控制信号V Ctl1。当然，该第一开关器件S 1仅是示例性的，本公开实施例所采用的第一开关器件S 1的实现方式并不仅限于此。
在一些实施例中，在发光器件130多个第一电极的任意相邻的两个第一电极之间均设置有一个第一开关晶体管。该第一开关晶体管的第一电极电连接至该任意相邻的两个第一电极的一个第一电极，该第一开关晶体管的第二电极电连接至该任意相邻的两个第一电极的另一个第一电极。例如，如图4所示，在发光器件的第一子电极211和第二子电极212之间设置有一个第一开关晶体管T 1。该第一开关晶体管T 1的第一电极与发光器件的第一子电极211电连接，该第一开关晶体管T 1的第二电极与发光器件的第二子电极212电连接。第一开关晶体管T 1的栅极被配置为接收第三控制信号V Ctl3。
需要说明的是，图4所示的发光器件130具有两个第一电极，这样在这两个第一电极之间设置有一个第一开关晶体管即可。但是，本公开的实施例并不仅限于此。例如，在发光器件具有多于两个第一电极(例如三个第一电极)的情况下，可以在任意相邻的两个第一电极之间均设置有一个第一开关晶体管，每个第一开关晶体管受相应的第三控制信号的控制。
如图4所示，第二开关器件S 2的第一连接端411与第一电压端(例如公共接地端)501电连接。该第二开关器件S 2的多个第二连接端与发光器件130的多个第二电极一一对应地电连接。例如，该第二开关器件S 2的多个第二连接端可以包括两个第二连接端421和422。该第二开关器件S 2的一个第二连接端421与发光器件的第三子电极223电连接，该第二开关器件S 2的另一个第二连接端422与发光器件的第四子电极224电连接。该第二开关器件S 2的控制端430被配置为接收第二控制信号V Ctl2。该第二开关器件S 2被配置为响应于第二控制信号V Ctl2，将该第二开关器件的第一连接端411与该第二开关器件的多个第二连接端中的一个连接。例如，第二开关器件S 2将其第一连接端411与其一个第二连接端421连接。又例如，第二开关器件S 2将其第一连接端411与其另一个第二连接端422连接。
在一些实施例中，第二开关器件S 2可以包括一个PMOS晶体管(例如称为第二PMOS晶体管)和与该PMOS晶体管电连接的一个NMOS晶体管(例如称为第二NMOS晶体管)。例如，该第二PMOS晶体管的第一电极与该第二NMOS晶体管的第一电极一起作为第一连接端411电连接至第一电压端。该第二PMOS晶体管的第二电极(例如作为第二连接端421)和该第二NMOS晶体管的第二电极(例如作为第二连接端422)分别电连接至发光器件的不同的第二电极。该第二PMOS晶体管的栅极和该第二NMOS晶体管的栅极可以一起作为控制端430用于接收第二控制信号V Ctl2。当然，该第二开关器件S 2仅是示例性的，本公开实施例所采用的第二开关器件S 2的实现方式并不仅限于此。
在一些实施例中，在发光器件130的多个第二电极的任意相邻的两个第二电极之间均设置有一个第二开关晶体管。该第二开关晶体管的第一电极电连接至该任意相邻的两个第二电极的一个第二电极，该第二开关晶体管的第二电极电连接至该任意相邻的两个第二电极的另一个第二电极。如图4所示，在发光器件的第三子电极223和第四子电极224之间设置有一个第二开关晶体管T 2。该第二开关晶体管T 2的第一电极与发光器件的第三子电极223电连接，该第二开关晶体管T 2的第二电极与发光器件的 第四子电极224电连接。第二开关晶体管T 2的栅极被配置为接收第四控制信号V Ctl4。
需要说明的是，图4所示的发光器件130具有两个第二电极，这样在这两个第二电极之间设置有一个第二开关晶体管即可。但是，本公开的实施例并不仅限于此。例如，在发光器件具有多于两个第二电极(例如三个第二电极)的情况下，可以在任意相邻的两个第二电极之间均设置有一个第二开关晶体管，每个第二开关晶体管受相应的第四控制信号的控制。
在一些实施例中，第一开关晶体管T 1的导电类型和第二开关晶体管T 2的导电类型相同。例如，第一开关晶体管T 1和第二开关晶体管T 2均为PMOS晶体管或均为NMOS晶体管。在这样的情况下，第三控制信号V Ctl3可以与第四控制信号V Ctl4相同。这样可以减少控制信号的数量。
在一些实施例中，像素驱动电路110可以包括第五开关晶体管T 5、电容器C 0和驱动晶体管T 0。该第五开关晶体管T 5的第一电极电连接至数据信号线L D。该第五开关晶体管T 5的第二电极电连接至驱动晶体管T 0的栅极。该第五开关晶体管T 5的栅极电连接至栅极控制线L G。电容器C 0的第一端电连接至驱动晶体管T 0的栅极。该电容器C 0的第二端电连接至第二电压端502。第二电压端502的电压与第一电压端501的电压不同。例如，该第二电压端502可以为电源电压端。驱动晶体管T 0的第一电极电连接至该第二电压端502。驱动晶体管T 0的第二电极电连接至模式选择电路120'。例如，该驱动晶体管T 0的第二电极电连接至第一开关器件S 1的第一连接端311。
需要说明的是，图4所示的像素驱动电路的电路结构仅是示例性的，本公开的实施例还可以采用其他电路结构的像素驱动电路。因此，本公开实施例的范围并不仅限于此。
下面结合图4详细描述根据本公开一些实施例的像素电路的工作过程。
在一些实施例中，在具有第一电平的第一控制信号V Ctl1的控制下，第一开关器件S 1的第一连接端311与一个第二连接端321连接，以及在具有第二电平的第二控制信号V Ctl2的控制下，第二开关器件S 2的第一连接端411与一个第二连接端421连接。这样，第一开关子电路121'执行具有第一种连接状态的第一导通模式，第二开关子电路122'执行具有第一种连接状态的第二导通模式。像素驱动电路110输出的驱动电流会流过发光器件130的第一子电极211、功能层和第三子电极223，从而使得发光器件130在第二发光模式下发出具有中等亮度L2的光。
在另一些实施例中，在具有第三电平的第一控制信号V Ctl1的控制下，第一开关器 件S 1的第一连接端311与另一个第二连接端322连接，以及在具有第四电平的第二控制信号V Ctl2的控制下，第二开关器件S 2的第一连接端411与另一个第二连接端422连接。这里，第三电平与第一电平不同，第四电平与第二电平不同。这样，第一开关子电路121'执行具有第二种连接状态的第一导通模式，第二开关子电路122'执行具有第二种连接状态的第二导通模式。像素驱动电路110输出的驱动电流会流过发光器件130的第二子电极212、功能层和第四子电极224，从而使得发光器件130在第二发光模式下发出具有中等亮度L2的光。
在另一些实施例中，在具有第一电平的第一控制信号V Ctl1的控制下，第一开关器件S 1的第一连接端311与所述一个第二连接端321连接，以及在具有第四电平的第二控制信号V Ctl2的控制下，第二开关器件S 2的第一连接端411与所述另一个第二连接端422连接。这样，第一开关子电路121'执行具有第一种连接状态的第一导通模式，第二开关子电路122'执行具有第二种连接状态的第二导通模式。像素驱动电路110输出的驱动电流会流过发光器件130的第一子电极211、功能层和第四子电极224，从而使得发光器件130在第一发光模式下发出具有低亮度L1的光。
在另一些实施例中，在具有第三电平的第一控制信号V Ctl1的控制下，第一开关器件S 1的第一连接端311与所述另一个第二连接端322连接，以及在具有第二电平的第二控制信号V Ctl2的控制下，第二开关器件S 2的第一连接端411与所述一个第二连接端421连接。这样，第一开关子电路121'执行具有第二种连接状态的第一导通模式，第二开关子电路122'执行具有第一种连接状态的第二导通模式。像素驱动电路110输出的驱动电流会流过发光器件130的第二子电极212、功能层和第三子电极223，从而使得发光器件130在第一发光模式下发出具有低亮度L1的光。
需要说明的是，在上述四种情况下，第一开关晶体管T 1在第三控制信号V Ctl3的控制下截止，第二开关晶体管T 2在第四控制信号V Ctl4的控制下截止。例如，在第一开关晶体管T 1为PMOS晶体管的情况下，该第一开关晶体管T 1在高电平的第三控制信号V Ctl3的控制下截止。当然，本领域技术人员可以理解，第一开关晶体管T 1也可以为NMOS晶体管。又例如，在第二开关晶体管T 2为PMOS晶体管的情况下，该第二开关晶体管T 2在高电平的第四控制信号V Ctl4的控制下截止。当然，本领域技术人员可以理解，第二开关晶体管T 2也可以为NMOS晶体管。
在另一些实施例中，在第一控制信号V Ctl1控制下，第一开关器件S 1的第一连接端311与第二连接端321或322连接，在第二控制信号V Ctl2的控制下，第二开关器件 S 2的第一连接端411与第二连接端421或422连接。第一开关晶体管T 1在第三控制信号V Ctl3(例如低电平的第三控制信号)的控制下导通，第二开关晶体管T 2在第四控制信号V Ctl4(例如低电平的第四控制信号)的控制下导通。像素驱动电路110输出的驱动电流会流过发光器件130的第一子电极211、第二子电极212、功能层、第三子电极223和第四子电极224，从而使得发光器件130在第三发光模式下发出具有高亮度L3的光。
至此，上述像素电路实现了根据不同的发光模式发出不同亮度的光。这样即使在低灰阶下，也可以使得驱动电流不会很小，从而有利于对驱动电流实现精确控制，尽量避免在相关技术中由于低灰阶显示时电流较小而导致的显示均匀性问题。
图5是示出根据本公开另一个实施例的像素电路的结构图。例如，图5中示出了根据一些实施例的像素驱动电路110、模式选择电路120"和发光器件130的具体电路结构。这里，前面已经详细描述了像素驱动电路110的电路结构，这里不再赘述。
在一些实施例中，如图5所示，模式选择电路120"可以包括第一开关子电路121"和第二开关子电路122"。
在一些实施例中，第一开关子电路121"可以包括多个第三开关晶体管。例如，该多个第三开关晶体管可以包括两个第三开关晶体管T 31和T 32。在一些实施例中，第二开关子电路122"可以包括多个第四开关晶体管。例如，该多个第四开关晶体管可以包括两个第四开关晶体管T 41和T 42。在一些实施例中，第三开关晶体管可以为PMOS晶体管或NMOS晶体管，第四开关晶体管可以为PMOS晶体管或NMOS晶体管。
在一些实施例中，模式选择信号S mod可以包括多个第五控制信号和多个第六控制信号。例如，图5中示出了用于控制一个第三开关晶体管T 31的第五控制信号V Ctl51和用于控制另一个第三开关晶体管T 32的第五控制信号V Ctl52，图5中还示出了用于控制一个第四开关晶体T 41的第六控制信号V Ctl61和用于控制另一个第四开关晶体管T 42的第六控制信号V Ctl62。
在一些实施例中，所述多个第三开关晶体管的多个第一电极与发光器件130的多个第一电极一一对应地电连接。例如，如图5所示，在两个第三开关晶体管中，一个第三开关晶体管T 31的第一电极与发光器件130的第一子电极211电连接，另一个第三开关晶体管T 32的第一电极与发光器件130的第二子电极212电连接。所述多个第三开关晶体管的多个第二电极电连接至像素驱动电路110。例如，如图5所示，两个第三开关晶体管T 31和T 32的第二电极均电连接至像素驱动电路110的驱动晶体管T 0。 每个第三开关晶体管的栅极被配置为接收对应的第五控制信号。例如，如图5所示，所述一个第三开关晶体管T 31的栅极被配置为接收一个第五控制信号V Ctl51，所述另一个第三开关晶体管T 32的栅极被配置为接收另一个第五控制信号V Ctl52。
在一些实施例中，所述多个第四开关晶体管的多个第一电极与发光器件130的多个第二电极一一对应地电连接。例如，如图5所示，在两个第四开关晶体管中，一个第四开关晶体管T 41的第一电极与发光器件130的第三子电极223电连接，另一个第四开关晶体管T 42的第一电极与发光器件130的第四子电极224电连接。所述多个第四开关晶体管的多个第二电极电连接至第一电压端501。例如，如图5所示，两个第四开关晶体管T 41和T 42的第二电极均电连接至第一电压端(例如公共接地端)501。每个第四开关晶体管的栅极被配置为接收对应的第六控制信号。例如，如图5所示，所述一个第四开关晶体管T 41的栅极被配置为接收一个第六控制信号V Ctl61，所述另一个第四开关晶体管T 42的栅极被配置为接收另一个第六控制信号V Ctl62。
至此，提供了根据本公开另一些实施例的像素电路的结构。在该像素电路中，第一开关子电路受到多个第五控制信号的控制，第二开关子电路受到多个第六控制信号的控制。在这些第五控制信号和第六控制信号端的控制下，像素电路可以按照不同的发光模式发出不同亮度的光。这样，对于包括多个像素电路的显示装置，可以使得该多个像素电路中的不同像素电路的发光亮度尽量均匀，从而提高显示装置显示的均匀性，尤其是在低灰阶显示时的均匀性。
图6A是示出根据本公开一个实施例的用于像素电路的控制信号的时序图。图6A示出了在第一发光模式下的用于像素电路的多个第五控制信号和多个第六控制信号的时序图。下面结合图5和图6A详细描述像素电路在多个第五控制信号和多个第六控制信号的控制下按照第一发光模式发光的工作过程。这里，以第三开关晶体管和第四开关晶体管均为PMOS晶体管为例进行描述。
在一些实施例中，如图5和图6A所示，在第一阶段t 1，在低电平的所述一个第五控制信号V Ctl51的控制下，所述一个第三开关晶体管T 31导通；在高电平的所述另一个第五控制信号V Ctl52控制下，所述另一个第三开关晶体管T 32截止；在高电平的所述一个第六控制信号V Ctl61的控制下，所述一个第四开关晶体管T 41截止；在低电平的所述另一个第六控制信号V Ctl62控制下，所述另一个第四开关晶体管T 42导通。由于所述一个第三开关晶体管T 31与发光器件130的第一子电极211电连接且所述另一个第四开关晶体管T 42与发光器件130的第四子电极224电连接，因此像素驱动电路110输 出的驱动电流会流过发光器件130的第一子电极211、功能层和第四子电极224，从而使得发光器件130在第一发光模式下发出具有低亮度L1的光。
在另一些实施例中，如图5和图6A所示，在第二阶段t 2，在高电平的所述一个第五控制信号V Ctl51的控制下，所述一个第三开关晶体管T 31截止；在低电平的所述另一个第五控制信号V Ctl52控制下，所述另一个第三开关晶体管T 32导通；在低电平的所述一个第六控制信号V Ctl61的控制下，所述一个第四开关晶体管T 41导通；在高电平的所述另一个第六控制信号V Ctl62控制下，所述另一个第四开关晶体管T 42截止。由于所述另一个第三开关晶体管T 32与发光器件130的第二子电极212电连接且所述一个第四开关晶体管T 41与发光器件130的第三子电极223电连接，因此像素驱动电路110输出的驱动电流会流过发光器件130的第二子电极212、功能层和第三子电极223，从而使得发光器件130在第一发光模式下发出具有低亮度L1的光。
至此，详细描述了图5所示的像素电路按照第一发光模式发光的工作过程。
图6B是示出根据本公开另一个实施例的用于像素电路的控制信号的时序图。图6B示出了在第二发光模式下的用于像素电路的多个第五控制信号和多个第六控制信号的时序图。下面结合图5和图6B详细描述像素电路在多个第五控制信号和多个第六控制信号的控制下按照第二发光模式发光的工作过程。这里，以第三开关晶体管和第四开关晶体管均为PMOS晶体管为例进行描述。
在一些实施例中，如图5和图6B所示，在第三阶段t 3，在低电平的所述一个第五控制信号V Ctl51的控制下，所述一个第三开关晶体管T 31导通；在高电平的所述另一个第五控制信号V Ctl52控制下，所述另一个第三开关晶体管T 32截止；在低电平的所述一个第六控制信号V Ctl61的控制下，所述一个第四开关晶体管T 41导通；在高电平的所述另一个第六控制信号V Ctl62控制下，所述另一个第四开关晶体管T 42截止。在这样的情况下，像素驱动电路110输出的驱动电流会流过发光器件130的第一子电极211、功能层和第三子电极223，从而使得发光器件130在第二发光模式下发出具有中等亮度L2的光。
在另一些实施例中，如图5和图6B所示，在第四阶段t 4，在高电平的所述一个第五控制信号V Ctl51的控制下，所述一个第三开关晶体管T 31截止；在低电平的所述另一个第五控制信号V Ctl52控制下，所述另一个第三开关晶体管T 32导通；在高电平的所述一个第六控制信号V Ctl61的控制下，所述一个第四开关晶体管T 41截止；在低电平的所述另一个第六控制信号V Ctl62控制下，所述另一个第四开关晶体管T 42导通。在这样 的情况下，像素驱动电路110输出的驱动电流会流过发光器件130的第二子电极212、功能层和第四子电极224，从而使得发光器件130在第二发光模式下发出具有中等亮度L2的光。
至此，详细描述了图5所示的像素电路按照第二发光模式发光的工作过程。
图6C是示出根据本公开另一个实施例的用于像素电路的控制信号的时序图。图6C示出了在第三发光模式下的用于像素电路的多个第五控制信号和多个第六控制信号的时序图。下面结合图5和图6C详细描述像素电路在多个第五控制信号和多个第六控制信号的控制下按照第三发光模式发光的工作过程。这里，以第三开关晶体管和第四开关晶体管均为PMOS晶体管为例进行描述。
在一些实施例中，如图5和图6C所示，在第五阶段t 5，第五控制信号V Ctl51和V Ctl52、第六控制信号V Ctl61和V Ctl62均为低电平信号。在这些信号的控制下，第三开关晶体管T 31和T 32、以及第四开关晶体管T 41和T 42均导通。因此，像素驱动电路110输出的驱动电流会流过发光器件130的第一子电极211、第二子电极212、功能层、第三子电极223和第四子电极224，从而使得发光器件130在第三发光模式下发出具有高亮度L3的光。
至此，详细描述了图5所示的像素电路按照第三发光模式发光的工作过程。
在本公开的一些实施例中，所使用的控制信号(例如，第一控制信号、第二控制信号、第三控制信号、第四控制信号、第五控制信号和第六控制信号)都可以通过时序控制器统一控制。该时序控制器可以在分析需要显示的灰阶数据后控制模式选择电路选择所需要的发光模式。
在相关技术中，由于OLED(作为发光器件)的发光材料包括有机材料，OLED在被驱动电流长时间驱动发光的情况下，有机材料会迅速衰减，导致亮度下降，OLED的寿命也减小。但是按照本公开实施例的上述控制信号对发光器件实现间歇式驱动，则可以减缓发光器件的衰减速度，延长使用寿命。
另外，在相关技术中，由于驱动晶体管的阈值电压的漂移和不同RGB(红色、绿色、蓝色)子像素(每个子像素包括一个像素电路)的有机材料的衰减速率不同，不同的像素电路在使用一段时间后，很容易出现亮度不一致的问题。显示装置在长时间固定显示一个画面的情况下，由于在显示该画面的不同部分时像素电路的驱动电流不同，而且不同OLED的衰减速率也不同，因此可能会出现显示不均或图像残留的问题。而本公开实施例的像素电路可以减缓发光器件的衰减速度，从而减弱了不同颜色子像 素的发光材料衰减的不一致性，进而可以改善显示装置的显示效果。
在本公开的一些实施例中，还提供了一种显示装置。该显示装置可以包括多个如前所述的像素电路(例如如图1、图4或图5所示的像素电路)。例如，该显示装置可以为：显示面板、显示屏、显示器、手机、平板电脑、笔记本电脑、电视机或导航仪等任何具有显示功能的产品或部件。
图8是示出根据本公开一个实施例的显示装置的结构图。如图8所示，该显示装置可以包括多个像素电路811、812和813。
在一些实施例中，如图8所示，该显示装置还可以包括时序控制器820。该时序控制器820被配置向所述多个像素电路提供模式选择信号。
图7是示出根据本公开一个实施例的用于像素电路的控制方法的流程图。该像素电路可以包括像素驱动电路、模式选择电路和发光器件。如图7所示，该控制方法可以包括步骤S702至S706。
在步骤S702，像素驱动电路根据数据信号输出驱动电流。
在步骤S704，模式选择电路根据不同的模式选择信号选择不同的发光模式。
在步骤S706，发光器件在驱动电流的驱动下，根据不同的发光模式发出不同亮度的光。
在一些实施例中，发光模式可以包括第一发光模式、第二发光模式和第三发光模式。在像素驱动电路被输入相同灰阶数据的情况下，发光器件在第一发光模式下的发光亮度小于该发光器件在第二发光模式下的发光亮度，该发光器件在第二发光模式下的发光亮度小于该发光器件在第三发光模式下的发光亮度。
至此，提供了根据本公开一些实施例的用于像素电路的控制方法。在该控制方法中，像素驱动电路根据数据信号输出驱动电流，模式选择电路根据不同的模式选择信号选择不同的发光模式，以及发光器件在驱动电流的驱动下根据不同的发光模式发出不同亮度的光。这样，虽然在显示装置的不同的像素电路中可能存在有机材料层厚度不均匀和薄膜晶体管不均匀的问题，但是由于不同的像素电路可以按照不同的发光模式发光，因此可以使得不同像素电路的发光亮度尽量均匀，从而提高显示装置显示的均匀性。例如，可以提高显示装置在低灰阶显示时的均匀性。
在一些实施例中，发光器件可以包括：间隔开的多个第一电极、间隔开的多个第二电极和在该多个第一电极和该多个第二电极之间的功能层。该功能层至少包括发光层。该发光器件设置在初始结构层上。
例如，该多个第一电极包括第一子电极和第二子电极，该多个第二电极包括第三子电极和第四子电极。第一子电极在初始结构层上的正投影与第三子电极在初始结构层上的正投影至少部分重合。第二子电极在初始结构层上的正投影与第四子电极在初始结构层上的正投影至少部分重合。
在一些实施例中，该步骤S704可以包括：模式选择电路响应于与第一发光模式对应的模式选择信号，控制驱动电流流过第一子电极、功能层和第四子电极，或者控制驱动电流流过第二子电极、功能层和第三子电极。
在另一些实施例中，该步骤S704可以包括：模式选择电路响应于与第二发光模式对应的模式选择信号，控制驱动电流流过第一子电极、功能层和第三子电极，或者控制驱动电流流过第二子电极、功能层和第四子电极。
在另一些实施例中，该步骤S704可以包括：模式选择电路响应于与第三发光模式对应的模式选择信号，控制驱动电流流过第一子电极、第二子电极、功能层、第三子电极和第四子电极。
在一些实施例中，第一开关子电路包括第一开关器件和至少一个第一开关晶体管，第二开关子电路包括第二开关器件和至少一个第二开关晶体管。模式选择信号包括用于控制第一开关器件的第一控制信号、用于控制第二开关器件的第二控制信号、用于控制所述至少一个第一开关晶体管的第三控制信号和用于控制所述至少一个第二开关晶体管的第四控制信号。第一开关器件的第一连接端与像素驱动电路电连接，第一开关器件的多个第二连接端与发光器件的多个第一电极一一对应地电连接，第一开关器件被配置为响应于第一控制信号，将第一开关器件的第一连接端与第一开关器件的多个第二连接端中的一个连接。在所述多个第一电极的任意相邻的两个第一电极之间均设置有一个第一开关晶体管。该第一开关晶体管的第一电极电连接至所述任意相邻的两个第一电极的一个第一电极，该第一开关晶体管的第二电极电连接至所述任意相邻的两个第一电极的另一个第一电极，该第一开关晶体管的栅极被配置为接收第三控制信号。第二开关器件的第一连接端与第一电压端电连接，第二开关器件的多个第二连接端与发光器件的多个第二电极一一对应地电连接，第二开关器件被配置为响应于第二控制信号，将第二开关器件的第一连接端与第二开关器件的多个第二连接端中的一个连接。在所述多个第二电极的任意相邻的两个第二电极之间均设置有一个第二开关晶体管。该第二开关晶体管的第一电极电连接至所述任意相邻的两个第二电极的一个第二电极，该第二开关晶体管的第二电极电连接至所述任意相邻的两个第二电极的 另一个第二电极，该第二开关晶体管的栅极被配置为接收第四控制信号。
例如，该步骤S704可以包括：对第一开关器件施加具有第一电平的第一控制信号使得第一开关器件的第一连接端与第一开关器件的一个第二连接端连接，对第二开关器件施加具有第二电平的第二控制信号使得第二开关器件的第一连接端与第二开关器件的一个第二连接端连接，对第一开关晶体管施加第三控制信号使得第一开关晶体管截止，以及对第二开关晶体管施加第四控制信号使得第二开关晶体管截止。
又例如，该步骤S704可以包括：对第一开关器件施加具有第三电平的第一控制信号使得第一开关器件的第一连接端与第一开关器件的另一个第二连接端连接，对第二开关器件施加具有第四电平的第二控制信号使得第二开关器件的第一连接端与第二开关器件的另一个第二连接端连接，对第一开关晶体管施加第三控制信号使得第一开关晶体管截止，以及对第二开关晶体管施加第四控制信号使得第二开关晶体管截止。
又例如，该步骤S704可以包括：对所述第一开关器件施加具有第一电平的第一控制信号使得第一开关器件的第一连接端与第一开关器件的所述一个第二连接端连接，对所述第二开关器件施加具有所述第四电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的所述另一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止。
又例如，该步骤S704可以包括：对所述第一开关器件施加具有所述第三电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的所述另一个第二连接端连接，对所述第二开关器件施加具有所述第二电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的所述一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止。
又例如，该步骤S704可以包括：对所述第一开关器件施加所述第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的第二连接端连接，对所述第二开关器件施加所述第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管导通，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管导通。
在一些实施例中，第三控制信号与第四控制信号相同。
在一些实施例中，第一开关子电路包括多个第三开关晶体管，第二开关子电路包括多个第四开关晶体管。模式选择信号包括多个第五控制信号和多个第六控制信号。所述多个第三开关晶体管的多个第一电极与所述发光器件的多个第一电极一一对应地电连接，所述多个第三开关晶体管的多个第二电极电连接至所述像素驱动电路。每个第三开关晶体管的栅极被配置为接收对应的第五控制信号。所述多个第四开关晶体管的多个第一电极与所述发光器件的多个第二电极一一对应地电连接，所述多个第四开关晶体管的多个第二电极电连接至所述第一电压端。每个第四开关晶体管的栅极被配置为接收对应的第六控制信号。
例如，该步骤S704可以包括：对所述多个第三开关晶体管中的一个第三开关晶体管施加低电平的一个第五控制信号使得所述一个第三开关晶体管导通，对所述多个第三开关晶体管中的另一个第三开关晶体管施加高电平的另一个第五控制信号使得所述另一个第三开关晶体管截止，对所述多个第四开关晶体管中的一个第四开关晶体管施加高电平的一个第六控制信号使得所述一个第四开关晶体管截止，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加低电平的另一个第六控制信号使得所述另一个第四开关晶体管导通。
又例如，该步骤S704可以包括：对所述多个第三开关晶体管中的一个第三开关晶体管施加高电平的一个第五控制信号使得所述一个第三开关晶体管T 31截止，对所述多个第三开关晶体管中的另一个第三开关晶体管施加低电平的另一个第五控制信号使得所述另一个第三开关晶体管导通，对所述多个第四开关晶体管中的一个第四开关晶体管施加低电平的一个第六控制信号使得所述一个第四开关晶体管导通，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加高电平的另一个第六控制信号使得所述另一个第四开关晶体管截止。
又例如，该步骤S704可以包括：对所述多个第三开关晶体管中的一个第三开关晶体管施加低电平的一个第五控制信号使得所述一个第三开关晶体管导通，对所述多个第三开关晶体管中的另一个第三开关晶体管施加高电平的另一个第五控制信号使得所述另一个第三开关晶体管截止，对所述多个第四开关晶体管中的一个第四开关晶体管施加低电平的一个第六控制信号使得所述一个第四开关晶体管导通，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加高电平的另一个第六控制信号使得所述另一个第四开关晶体管截止。
又例如，该步骤S704可以包括：对所述多个第三开关晶体管中的一个第三开关 晶体管施加高电平的一个第五控制信号使得所述一个第三开关晶体管截止，对所述多个第三开关晶体管中的另一个第三开关晶体管施加低电平的另一个第五控制信号使得所述另一个第三开关晶体管导通，对所述多个第四开关晶体管中的一个第四开关晶体管施加高电平的一个第六控制信号使得所述一个第四开关晶体管截止，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加低电平的另一个第六控制信号使得所述另一个第四开关晶体管导通。
又例如，该步骤S704可以包括：对所述多个第三开关晶体管施加低电平的第五控制信号使得所述多个第三开关晶体管均导通，以及对所述多个第四开关晶体管施加低电平的第六控制信号使得所述多个第四开关晶体管均导通。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (22)

  1. 一种像素电路，包括：
    像素驱动电路，被配置为输出驱动电流；
    发光器件，被配置为在所述驱动电流的驱动下，根据不同的发光模式发出不同亮度的光，所述发光器件包括第一电极结构、第二电极结构和在所述第一电极结构与所述第二电极结构之间的功能层；以及
    模式选择电路，被配置为根据不同的模式选择信号选择不同的发光模式，所述模式选择电路包括：
    第一开关子电路，分别与所述像素驱动电路和所述第一电极结构电连接，被配置为响应于不同的模式选择信号执行不同的第一导通模式；以及
    第二开关子电路，分别与第一电压端和所述第二电极结构电连接，被配置为响应于不同的模式选择信号执行不同的第二导通模式；
    其中，所述模式选择电路被配置为根据所述第一导通模式和所述第二导通模式确定所述发光模式。
  2. 根据权利要求1所述的像素电路，其中：
    所述功能层包括发光层；以及
    所述第一电极结构和所述第二电极结构中的至少一个包括间隔开的多个电极。
  3. 根据权利要求2所述的像素电路，其中：
    所述第一电极结构包括间隔开的多个第一电极；以及
    所述第二电极结构包括间隔开的多个第二电极。
  4. 根据权利要求3所述的像素电路，其中：
    所述发光器件设置在初始结构层上；以及
    所述多个第一电极包括第一子电极和第二子电极，所述多个第二电极包括第三子电极和第四子电极，所述第一子电极在所述初始结构层上的正投影与所述第三子电极在所述初始结构层上的正投影至少部分重合，所述第二子电极在所述初始结构层上的正投影与所述第四子电极在所述初始结构层上的正投影至少部分重合。
  5. 根据权利要求3所述的像素电路，其中：
    所述第一开关子电路包括第一开关器件和至少一个第一开关晶体管，所述第二开关子电路包括第二开关器件和至少一个第二开关晶体管；以及
    所述模式选择信号包括用于控制所述第一开关器件的第一控制信号、用于控制所述第二开关器件的第二控制信号、用于控制所述至少一个第一开关晶体管的第三控制信号和用于控制所述至少一个第二开关晶体管的第四控制信号。
  6. 根据权利要求5所述的像素电路，其中：
    所述第一开关器件的第一连接端与所述像素驱动电路电连接，所述第一开关器件的多个第二连接端与所述发光器件的多个第一电极一一对应地电连接，所述第一开关器件被配置为响应于所述第一控制信号，将所述第一开关器件的第一连接端与所述第一开关器件的多个第二连接端中的一个连接；
    在所述多个第一电极的任意相邻的两个第一电极之间均设置有一个第一开关晶体管，其中，该第一开关晶体管的第一电极电连接至所述任意相邻的两个第一电极的一个第一电极，该第一开关晶体管的第二电极电连接至所述任意相邻的两个第一电极的另一个第一电极，该第一开关晶体管的栅极被配置为接收所述第三控制信号；
    所述第二开关器件的第一连接端与所述第一电压端电连接，所述第二开关器件的多个第二连接端与所述发光器件的多个第二电极一一对应地电连接，所述第二开关器件被配置为响应于所述第二控制信号，将所述第二开关器件的第一连接端与所述第二开关器件的多个第二连接端中的一个连接；以及
    在所述多个第二电极的任意相邻的两个第二电极之间均设置有一个第二开关晶体管，其中，该第二开关晶体管的第一电极电连接至所述任意相邻的两个第二电极的一个第二电极，该第二开关晶体管的第二电极电连接至所述任意相邻的两个第二电极的另一个第二电极，该第二开关晶体管的栅极被配置为接收所述第四控制信号。
  7. 根据权利要求5或6所述的像素电路，其中：
    所述第一开关器件包括第一PMOS晶体管和与所述第一PMOS晶体管电连接的第一NMOS晶体管；以及
    所述第二开关器件包括第二PMOS晶体管和与所述第二PMOS晶体管电连接的第二NMOS晶体管。
  8. 根据权利要求6所述的像素电路，其中：
    所述第一开关器件的多个第二连接端包括两个第二连接端，所述第二开关器件的多个第二连接端包括两个第二连接端；
    所述至少一个第一开关晶体管包括一个第一开关晶体管；以及
    所述至少一个第二开关晶体管包括一个第二开关晶体管。
  9. 根据权利要求3所述的像素电路，其中：
    所述第一开关子电路包括多个第三开关晶体管，所述第二开关子电路包括多个第四开关晶体管；
    所述模式选择信号包括多个第五控制信号和多个第六控制信号；
    所述多个第三开关晶体管的多个第一电极与所述发光器件的多个第一电极一一对应地电连接，所述多个第三开关晶体管的多个第二电极电连接至所述像素驱动电路，每个第三开关晶体管的栅极被配置为接收对应的第五控制信号；以及
    所述多个第四开关晶体管的多个第一电极与所述发光器件的多个第二电极一一对应地电连接，所述多个第四开关晶体管的多个第二电极电连接至所述第一电压端，每个第四开关晶体管的栅极被配置为接收对应的第六控制信号。
  10. 根据权利要求9所述的像素电路，其中：
    所述多个第三开关晶体管包括两个第三开关晶体管；以及
    所述多个第四开关晶体管包括两个第四开关晶体管。
  11. 根据权利要求1所述的像素电路，其中，
    所述发光模式包括第一发光模式、第二发光模式和第三发光模式；
    其中，在所述像素驱动电路被输入相同灰阶数据的情况下，所述发光器件在所述第一发光模式下的发光亮度小于所述发光器件在所述第二发光模式下的发光亮度，所述发光器件在所述第二发光模式下的发光亮度小于所述发光器件在所述第三发光模式下的发光亮度。
  12. 根据权利要求1所述的像素电路，其中，
    所述像素驱动电路包括：第五开关晶体管、电容器和驱动晶体管，
    其中，所述第五开关晶体管的第一电极电连接至数据信号线，所述第五开关晶体管的第二电极电连接至所述驱动晶体管的栅极，所述第五开关晶体管的栅极电连接至栅极控制线，所述电容器的第一端电连接至所述驱动晶体管的栅极，所述电容器的第二端电连接至第二电压端，所述驱动晶体管的第一电极电连接至所述第二电压端，所述驱动晶体管的第二电极电连接至所述模式选择电路。
  13. 根据权利要求4所述的像素电路，其中：
    所述第一子电极和所述第二子电极均具有梳状结构，且所述第一子电极的梳状结构的梳齿与所述第二子电极的梳状结构的梳齿交叉设置；以及
    所述第三子电极和所述第四子电极均具有梳状结构，且所述第三子电极的梳状结构的梳齿与所述第四子电极的梳状结构的梳齿交叉设置。
  14. 根据权利要求4所述的像素电路，其中，
    在与所述功能层的延展方向相平行的方向上，所述第一子电极的面积和所述第二子电极的面积相等，且所述第三子电极的面积和所述第四子电极的面积相等。
  15. 一种显示装置，包括：多个如权利要求1至14任意一项所述的像素电路。
  16. 根据权利要求15所述的显示装置，还包括：
    时序控制器，被配置向所述多个像素电路提供所述模式选择信号。
  17. 一种用于像素电路的控制方法，其中，所述像素电路包括像素驱动电路、模式选择电路和发光器件，
    所述控制方法包括：
    所述像素驱动电路根据数据信号输出驱动电流；
    所述模式选择电路根据不同的模式选择信号选择不同的发光模式；以及
    所述发光器件在所述驱动电流的驱动下，根据不同的所述发光模式发出不同亮度的光。
  18. 根据权利要求17所述的控制方法，其中，
    所述发光模式包括第一发光模式、第二发光模式和第三发光模式；
    其中，在所述像素驱动电路被输入相同灰阶数据的情况下，所述发光器件在所述第一发光模式下的发光亮度小于所述发光器件在所述第二发光模式下的发光亮度，所述发光器件在所述第二发光模式下的发光亮度小于所述发光器件在所述第三发光模式下的发光亮度。
  19. 根据权利要求18所述的控制方法，其中，
    所述发光器件包括：间隔开的多个第一电极、间隔开的多个第二电极和在所述多个第一电极和所述多个第二电极之间的功能层，所述功能层至少包括发光层，所述发光器件设置在初始结构层上，
    所述多个第一电极包括第一子电极和第二子电极，所述多个第二电极包括第三子电极和第四子电极，所述第一子电极在所述初始结构层上的正投影与所述第三子电极在所述初始结构层上的正投影至少部分重合，所述第二子电极在所述初始结构层上的正投影与所述第四子电极在所述初始结构层上的正投影至少部分重合；
    其中，所述模式选择电路根据不同的模式选择信号选择不同的发光模式的步骤包括：
    所述模式选择电路响应于与所述第一发光模式对应的模式选择信号，控制所述驱动电流流过所述第一子电极、所述功能层和所述第四子电极，或者控制所述驱动电流流过所述第二子电极、所述功能层和所述第三子电极；
    所述模式选择电路响应于与所述第二发光模式对应的模式选择信号，控制所述驱动电流流过所述第一子电极、所述功能层和所述第三子电极，或者控制所述驱动电流流过所述第二子电极、所述功能层和所述第四子电极；或者
    所述模式选择电路响应于与所述第三发光模式对应的模式选择信号，控制所述驱动电流流过所述第一子电极、所述第二子电极、所述功能层、所述第三子电极和所述第四子电极。
  20. 根据权利要求19所述的控制方法，其中，
    所述第一开关子电路包括第一开关器件和至少一个第一开关晶体管，所述第二开关子电路包括第二开关器件和至少一个第二开关晶体管；所述模式选择信号包括用于控制所述第一开关器件的第一控制信号、用于控制所述第二开关器件的第二控制信号、 用于控制所述至少一个第一开关晶体管的第三控制信号和用于控制所述至少一个第二开关晶体管的第四控制信号；所述第一开关器件的第一连接端与所述像素驱动电路电连接，所述第一开关器件的多个第二连接端与所述发光器件的多个第一电极一一对应地电连接，所述第一开关器件被配置为响应于所述第一控制信号，将所述第一开关器件的第一连接端与所述第一开关器件的多个第二连接端中的一个连接；在所述多个第一电极的任意相邻的两个第一电极之间均设置有一个第一开关晶体管，其中，该第一开关晶体管的第一电极电连接至所述任意相邻的两个第一电极的一个第一电极，该第一开关晶体管的第二电极电连接至所述任意相邻的两个第一电极的另一个第一电极，该第一开关晶体管的栅极被配置为接收所述第三控制信号；所述第二开关器件的第一连接端与所述第一电压端电连接，所述第二开关器件的多个第二连接端与所述发光器件的多个第二电极一一对应地电连接，所述第二开关器件被配置为响应于所述第二控制信号，将所述第二开关器件的第一连接端与所述第二开关器件的多个第二连接端中的一个连接；以及在所述多个第二电极的任意相邻的两个第二电极之间均设置有一个第二开关晶体管，其中，该第二开关晶体管的第一电极电连接至所述任意相邻的两个第二电极的一个第二电极，该第二开关晶体管的第二电极电连接至所述任意相邻的两个第二电极的另一个第二电极，该第二开关晶体管的栅极被配置为接收所述第四控制信号；
    所述模式选择电路根据不同的模式选择信号选择不同的发光模式的步骤包括：
    对所述第一开关器件施加具有第一电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的一个第二连接端连接，对所述第二开关器件施加具有第二电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；
    对所述第一开关器件施加具有第三电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的另一个第二连接端连接，对所述第二开关器件施加具有第四电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的另一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；
    对所述第一开关器件施加具有所述第一电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的所述一个第二连接端连接，对所述第二开关器件施加具有所述第四电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的所述另一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；
    对所述第一开关器件施加具有所述第三电平的第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的所述另一个第二连接端连接，对所述第二开关器件施加具有所述第二电平的第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的所述一个第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管截止，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管截止；或者
    对所述第一开关器件施加所述第一控制信号使得所述第一开关器件的第一连接端与所述第一开关器件的第二连接端连接，对所述第二开关器件施加所述第二控制信号使得所述第二开关器件的第一连接端与所述第二开关器件的第二连接端连接，对所述第一开关晶体管施加所述第三控制信号使得所述第一开关晶体管导通，以及对所述第二开关晶体管施加所述第四控制信号使得所述第二开关晶体管导通。
  21. 根据权利要求20所述的控制方法，其中，
    所述第三控制信号与所述第四控制信号相同。
  22. 根据权利要求19所述的控制方法，其中，
    所述第一开关子电路包括多个第三开关晶体管，所述第二开关子电路包括多个第四开关晶体管，所述模式选择信号包括多个第五控制信号和多个第六控制信号，所述多个第三开关晶体管的多个第一电极与所述发光器件的多个第一电极一一对应地电连接，所述多个第三开关晶体管的多个第二电极电连接至所述像素驱动电路，每个第三开关晶体管的栅极被配置为接收对应的第五控制信号，以及所述多个第四开关晶体管的多个第一电极与所述发光器件的多个第二电极一一对应地电连接，所述多个第四开关晶体管的多个第二电极电连接至所述第一电压端，每个第四开关晶体管的栅极被配置为接收对应的第六控制信号；
    所述模式选择电路根据不同的模式选择信号选择不同的发光模式的步骤包括：
    对所述多个第三开关晶体管中的一个第三开关晶体管施加低电平的一个第五控制信号使得所述一个第三开关晶体管导通，对所述多个第三开关晶体管中的另一个第三开关晶体管施加高电平的另一个第五控制信号使得所述另一个第三开关晶体管截止，对所述多个第四开关晶体管中的一个第四开关晶体管施加高电平的一个第六控制信号使得所述一个第四开关晶体管截止，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加低电平的另一个第六控制信号使得所述另一个第四开关晶体管导通；
    对所述多个第三开关晶体管中的一个第三开关晶体管施加高电平的一个第五控制信号使得所述一个第三开关晶体管T 31截止，对所述多个第三开关晶体管中的另一个第三开关晶体管施加低电平的另一个第五控制信号使得所述另一个第三开关晶体管导通，对所述多个第四开关晶体管中的一个第四开关晶体管施加低电平的一个第六控制信号使得所述一个第四开关晶体管导通，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加高电平的另一个第六控制信号使得所述另一个第四开关晶体管截止；
    对所述多个第三开关晶体管中的一个第三开关晶体管施加低电平的一个第五控制信号使得所述一个第三开关晶体管导通，对所述多个第三开关晶体管中的另一个第三开关晶体管施加高电平的另一个第五控制信号使得所述另一个第三开关晶体管截止，对所述多个第四开关晶体管中的一个第四开关晶体管施加低电平的一个第六控制信号使得所述一个第四开关晶体管导通，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加高电平的另一个第六控制信号使得所述另一个第四开关晶体管截止；
    对所述多个第三开关晶体管中的一个第三开关晶体管施加高电平的一个第五控制信号使得所述一个第三开关晶体管截止，对所述多个第三开关晶体管中的另一个第三开关晶体管施加低电平的另一个第五控制信号使得所述另一个第三开关晶体管导通，对所述多个第四开关晶体管中的一个第四开关晶体管施加高电平的一个第六控制信号使得所述一个第四开关晶体管截止，以及对所述多个第四开关晶体管中的另一个第四开关晶体管施加低电平的另一个第六控制信号使得所述另一个第四开关晶体管导通；或者
    对所述多个第三开关晶体管施加低电平的第五控制信号使得所述多个第三开关 晶体管均导通，以及对所述多个第四开关晶体管施加低电平的第六控制信号使得所述多个第四开关晶体管均导通。
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