WO2020253412A1 - 激光投影设备 - Google Patents

激光投影设备 Download PDF

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Publication number
WO2020253412A1
WO2020253412A1 PCT/CN2020/089089 CN2020089089W WO2020253412A1 WO 2020253412 A1 WO2020253412 A1 WO 2020253412A1 CN 2020089089 W CN2020089089 W CN 2020089089W WO 2020253412 A1 WO2020253412 A1 WO 2020253412A1
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WIPO (PCT)
Prior art keywords
current control
light source
pin
laser
resistor
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PCT/CN2020/089089
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English (en)
French (fr)
Inventor
吴凯
王振
Original Assignee
青岛海信激光显示股份有限公司
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Application filed by 青岛海信激光显示股份有限公司 filed Critical 青岛海信激光显示股份有限公司
Publication of WO2020253412A1 publication Critical patent/WO2020253412A1/zh
Priority to US17/381,760 priority Critical patent/US11762270B2/en
Priority to US18/446,321 priority patent/US20230384659A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H04N9/3102—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM] using two-dimensional electronic spatial light modulators
    • H04N9/3111—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM] using two-dimensional electronic spatial light modulators for displaying the colours sequentially, e.g. by using sequentially activated light sources
    • H04N9/3114—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM] using two-dimensional electronic spatial light modulators for displaying the colours sequentially, e.g. by using sequentially activated light sources by using a sequential colour filter producing one colour at a time
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B21/00—Projectors or projection-type viewers; Accessories therefor
    • G03B21/14—Details
    • G03B21/20—Lamp housings
    • G03B21/2053—Intensity control of illuminating light
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B21/00—Projectors or projection-type viewers; Accessories therefor
    • G03B21/14—Details
    • G03B21/20—Lamp housings
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
    • G03B21/00—Projectors or projection-type viewers; Accessories therefor
    • G03B21/14—Details
    • G03B21/20—Lamp housings
    • G03B21/2006—Lamp housings characterised by the light source
    • G03B21/2033—LED or laser light sources
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H04N9/3141—Constructional details thereof
    • H04N9/315—Modulator illumination systems
    • H04N9/3155—Modulator illumination systems for controlling the light source
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H04N9/3141—Constructional details thereof
    • H04N9/315—Modulator illumination systems
    • H04N9/3158—Modulator illumination systems for controlling the spectrum
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/12—Picture reproducers
    • H04N9/31—Projection devices for colour picture display, e.g. using electronic spatial light modulators [ESLM]
    • H04N9/3141—Constructional details thereof
    • H04N9/315—Modulator illumination systems
    • H04N9/3161—Modulator illumination systems using laser light sources
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/64—Constructional details of receivers, e.g. cabinets or dust covers

Definitions

  • This application belongs to the field of projection display, and particularly relates to a laser projection device.
  • Laser projection equipment such as ultra-short-focus laser TVs are widely used in the display field because of their advantages of high color purity, large color gamut, and high brightness.
  • the light source system of the current laser TV usually includes a laser light source, a fluorescent wheel and a color filter wheel.
  • the laser light source is usually a blue laser for emitting blue laser light.
  • the blue laser is irradiated on three different areas of the fluorescent wheel sequentially to generate three-color light, and the three-color light is filtered through the color filter wheel in order to obtain three-color light with higher purity.
  • the laser light source of the current laser projection equipment usually can only provide laser with a fixed brightness. Therefore, the final display effect of the laser projection equipment is poor.
  • the embodiment of the present application provides a laser projection device, including:
  • Display control module light source drive circuit, and laser light source connected in sequence;
  • the display control module is used to generate N first current control signals corresponding to each frame of the multi-frame display image, and select a valid second current control signal from the N first current control signals,
  • the second current control signal is transmitted to the light source driving circuit, and the N first current control signals include monochromatic current control signals corresponding to the M primary colors of each frame of image, and color mixing currents.
  • Control signal, N is an integer greater than 2, and M is a positive integer;
  • the light source driving circuit is configured to control the laser light source to emit light based on the received second current control signal
  • the magnitude of the second current control signal corresponding to at least two frames of the display image is different.
  • Figure 1 is a schematic diagram of an implementation environment provided by some embodiments of the present application.
  • FIG. 2 is a schematic structural diagram of a projection light source provided by some embodiments of the present application.
  • FIG. 3 is a schematic structural diagram of a laser projection device provided by some embodiments of the present application.
  • FIG. 4 is a schematic structural diagram of a display control module provided by some embodiments of the present application.
  • FIG. 5 is a schematic structural diagram of a display control module provided by some embodiments of the present application.
  • FIG. 6 is a schematic structural diagram of a signal generator provided by some embodiments of the present application.
  • FIG. 7 is a schematic structural diagram of a signal output circuit provided by some embodiments of the present application.
  • FIG. 8 is a schematic structural diagram of a buffer circuit provided by some embodiments of the present application.
  • FIG. 9 is a schematic structural diagram of a signal selector provided by some embodiments of the present application.
  • FIG. 10 is a schematic structural diagram of a control chip provided by some embodiments of the present application.
  • FIG. 11 is a schematic structural diagram of a light source driving circuit provided by some embodiments of the present application.
  • FIG. 12 is a schematic structural diagram of a bank laser provided by some embodiments of the present application.
  • FIG. 13 is a schematic diagram of the internal structure of a processing module provided by some embodiments of the present application.
  • FIG. 14 is a schematic structural diagram of a light source driving circuit provided by some embodiments of the present application.
  • FIG. 15 is a schematic structural diagram of a step-down circuit provided by some embodiments of the present application.
  • FIG. 16 is a schematic structural diagram of an MCL provided by some embodiments of the present application.
  • FIG. 17 is a schematic structural diagram of a laser serial connection circuit provided by some embodiments of the present application.
  • FIG. 18 is an equivalent circuit diagram of an MCL provided by some embodiments of the present application.
  • FIG. 19 is a schematic structural diagram of a control chip provided by some embodiments of the present application.
  • 20 is a schematic structural diagram of a light source driving circuit provided by some embodiments of the present application.
  • FIG. 21 is a schematic structural diagram of a buck-boost circuit provided by some embodiments of the present application.
  • FIG. 22 is a schematic structural diagram of a display control module provided by some embodiments of the present application.
  • FIG. 23 is a graph of the relationship between the grayscale value of the input signal and the screen brightness provided by some embodiments of the present application.
  • 25 is a graph of the relationship between the gray scale value of the input signal and the screen brightness provided by some embodiments of the present application.
  • FIG. 26 is a schematic structural diagram of a laser projection device provided by some embodiments of the present application.
  • FIG. 27 is a schematic structural diagram of a laser projection device provided by some embodiments of the present application.
  • FIG. 28 is a schematic structural diagram of a laser projection device provided by some embodiments of the present application.
  • FIG. 1 shows a schematic diagram of an implementation environment involved in some embodiments of the present application.
  • the implementation environment may include: a projection light source 10, an optical engine 20, and a projection lens 30, and the projection light source 10, an optical engine 20, and a projection lens 30 are arranged in sequence along the light beam transmission direction.
  • the projection light source 10 is used to emit a light beam
  • the optical machine 20 is used to modulate the light beam to generate an image light beam when illuminated by the light beam from the projection light source 10
  • the projection lens 30 is used to project the image light beam onto the projection screen 40.
  • the above-mentioned projection light source 10, optical machine 20, and projection lens 30 may be applied to laser projection equipment such as laser televisions.
  • the projection light source may include: at least one laser, and the projection light source is used to emit laser light of at least one color.
  • the projection light source may be a monochromatic projection light source (that is, it includes one laser and the laser emits one color laser), or it may be a dual-color projection light source (that is, it includes multiple lasers and the laser emits two colors of laser light) .
  • the projection light source 10 includes at least a fluorescent wheel 110, a color filter wheel 120, a blue laser light source 130, a light combining component 140, a beam shaping component 150 and a light collecting component 160.
  • the blue laser light source 130, the beam shaping member 150, the light combining member 140, the fluorescent wheel 110, the color filter wheel 120, and the light collecting member 160 are arranged in sequence along the transmission direction of the blue laser.
  • the blue laser light source 130 is used to emit blue laser light.
  • the beam shaping component 150 is used to perform diameter reduction processing on the blue laser light emitted by the blue laser light source 130 to obtain a collimated blue laser beam after the diameter reduction, and transmit the collimated blue laser light to the light combining component 140.
  • the light combining component 140 is used to transmit the received blue laser light to the fluorescent wheel 110, and the light combining component 140 is also used to transmit the blue laser light transmitted by the fluorescent wheel 110 to the color filter wheel 120. After the blue laser is irradiated to the transmission area Through the transmission area, the light combining component 140 is also used to transmit the fluorescence emitted by the fluorescence wheel 110 to the color filter wheel 120, and the fluorescence is generated by the blue laser irradiating the fluorescence area.
  • the color filter wheel 120 is used to output red, blue, and green light sequentially when rotating. The red and green lights are obtained by filtering the fluorescence by the color filter wheel 120, and the blue light is transmitted through the color filter wheel 120. Laser get.
  • the light collecting part 160 is used for homogenizing red light, blue light and green light.
  • the light emission process of the projection light source is: the blue laser light emitted by the blue laser light source 130 is shaped by the beam shaping device 150, and then emitted to the light combining component 140, and then transmitted to the fluorescent wheel 110; timing sequence of the fluorescent wheel 110
  • the blue laser is transmitted from the fluorescent wheel 110 and passes through the optical path of the blue laser relay circuit (referring to the blue laser transmitted from the fluorescent wheel 110 in Figure 2
  • the light path loop to the light combining part 140) passes through the light combining part 140 again, passes through the filter color wheel 120 and then enters the light collecting part 160; when the blue laser irradiates the fluorescent area on the fluorescent wheel 110, the fluorescent area is excited
  • the phosphor emits at least one color of fluorescence (such as yellow fluorescence and/or green fluorescence in FIG.
  • the excited fluorescence is transmitted in the reverse direction, reflected by the light combining part 140 to the filter wheel 120, and then enters the light collecting part 160.
  • the light collecting component 160 After the light of the above three colors (tricolor light for short) passes through the light collecting component 160, it is modulated by the optical engine 20 to generate an image beam, and the image beam is transmitted to the projection lens 30 to finally realize the image output of the three color light.
  • the laser light source of the current laser projection equipment generally can only provide laser with a fixed brightness, and therefore, the final display effect of the laser projection equipment is poor.
  • FIG. 3 provides a laser projection device according to some embodiments of the application, including:
  • the display control module 21, the light source drive circuit 22, and the laser light source 23 are connected in sequence.
  • the laser light source 23 may be a monochromatic laser light source, such as a red laser light source or a blue laser light source 130 as shown in FIG. 2.
  • the display control module 21 is used to generate N first current control signals corresponding to each frame of the multi-frame display image, and select a valid second current control signal from the N first current control signals, and set the second
  • the current control signal is transmitted to the light source driving circuit 22, and the N first current control signals include a single color current control signal corresponding to the M primary colors of each frame image and a color mixing current control signal.
  • N is an integer greater than 2
  • M is a positive integer
  • each single-color current control signal is used to control the current of the corresponding primary color display stage
  • the mixed color current control signal is used to control at least two primary colors (usually to control two primary colors in the embodiment of the application) to display simultaneously (At least two primary colors displayed at the same time will produce mixed color current).
  • the four first current control signals are red current control signal, green current control signal, blue current control signal and color mixing current control signal, respectively.
  • the red current control signal is used to control the current in the red display stage
  • the green current control signal is used to control the current in the green display stage
  • the blue current control signal is used to control the current in the blue display stage
  • the color mixing current control signal is used Controls the current in the phase when at least two primary colors of red, green and blue are simultaneously displayed.
  • the light source driving circuit 22 is configured to control the laser light source 23 to emit light based on the received second current control signal.
  • the magnitudes of the second current control signals corresponding to at least two frames of display images are different.
  • the display control module can generate N first current control signals corresponding to each frame of the multi-frame display image, and the N first current control signals Select a valid second current control signal in the, and transmit the second current control signal to the light source drive circuit, so that the light source drive circuit controls the laser light source to emit light. Since at least two frames of display images correspond to different second current control signals, where The above-mentioned at least two frames of display images can be two frames of images that are adjacent in display timing, or can be displayed images with multiple frames in between. Since the corresponding laser light currents are different when displaying at least two frames of display images, The dynamic dimming of the laser light source, therefore, the laser projection device can support a laser light source with variable brightness, and effectively improve the display effect of the laser projection device.
  • the display control module 21 includes a processing module 211, a signal generator 212 and a data selector 213, and the processing module 211 is connected to the data selector 213. It is worth noting that the processing module 211 can generally also control the signal generation of the signal generator 212, and therefore can also be connected to the signal generator 212.
  • the processing module 211 is configured to generate N first current control signals and M enable signals corresponding to each frame of the multi-frame display image, and transmit the N first current control signals and M enable signals to Data selector 213.
  • both the monochrome current control signal and the color mixing current control signal are pulse width modulation (PWM, Pulse Width Modulation) signals.
  • the four first current control signals are the red PWM signal R_PWM, the green PWM signal G_PWM, the blue PWM signal B_PWM, and the color mixing PWM signal Y_PWM.
  • the M enable signals are the red enable signal R_EN, the green enable signal G_EN, and the blue enable signal B_EN.
  • the amplitude voltage of the color mixing PWM signal Y_PWM is 3.3V
  • the frequency is 18.3kHz
  • the duty cycle is 50%.
  • the signal generator 212 is used to generate a duty cycle control signal LD_duty, and output it to the light source driving circuit 22.
  • the duty cycle control signal LD_duty is used to control the on and off of the laser light source. For example, when the duty cycle control signal LD_duty is at a high level, the laser light source is turned on; when the duty cycle control signal LD_duty is at a low level, the laser light source is turned off.
  • the duty cycle control signal LD_duty is usually It is a continuous high level signal.
  • the data selector 213 is configured to select the second current control signal T_PWM from the N first current control signals based on the M enable signals, and transmit the second current control signal T_PWM to the light source driving circuit 22.
  • the second current control signal T_PWM matches the signal at the effective potential among the M enable signals.
  • the light source driving circuit 22 is configured to adjust the current of the laser light source 23 based on the received second current control signal T_PWM, and control the turning on and off of the laser light source 23 based on the duty cycle control signal LD_duty.
  • the signal generator 212 may generate the duty cycle control signal LD_duty in various ways. In an optional implementation manner, the signal generator 212 directly generates a continuous high-level duty cycle control signal LD_duty; in another optional implementation manner, the signal generator 212 is based on M enable signals , Synthesize the duty cycle control signal LD_duty. As shown in FIG. 5, the processing module 211 is also connected to the signal generator 212. The processing module 211 is also used to transmit the M enable signals to the signal generator 212; the signal generator 212 is used to synthesize the duty cycle control signals based on the M enable signals.
  • the signal generator 212 includes: a first OR gate N99 and a second OR gate N99 Gate N100.
  • OR gate (AND gate) is also called “or circuit", logic “and” circuit.
  • the OR gate has multiple input terminals and one output terminal. As long as the input has a high level (logic 1), the output is high, otherwise the output is low (logic 0).
  • the two input terminals of the first OR gate N99 are used to respectively receive two enable signals of the three enable signals
  • one input terminal of the second OR gate N100 is connected to the output terminal of the first OR gate N99
  • the other One input terminal is used to receive the other enable signals except the two enable signals among the three enable signals
  • the output terminal of the second OR gate N100 is used to output the duty cycle control signal LD_duty.
  • the processing module 211 may include a signal output circuit.
  • the signal output circuit is used to output the aforementioned N first current control signals and M enable signals.
  • FIG. 7 is a schematic structural diagram of the signal output circuit.
  • the signal output circuit includes: a control chip 2111 and a buffer circuit 2112 connected in sequence.
  • the buffer circuit 2112 is connected to the control chip 2111, the signal generator 212 and the data selector 213;
  • the control chip 2111 is used to generate N first current control signals and M enable signals corresponding to each frame of the multi-frame display image, and transmit the N first current control signals and M enable signals to Buffer circuit 2112;
  • the buffer circuit (Snubber Circuit) 2112 is used to buffer each received first current control signal and each enable signal respectively, and output each first current control signal after the buffer processing to the data selector 213 , And output each of the buffered enable signals to the data selector 213 and the signal generator 212 respectively.
  • Snubber circuit is also called absorption circuit, which is a kind of protection circuit.
  • the buffer circuit provided by the embodiments of the present application may be a three-state buffer (three-state buffer), also known as a three-state gate or a three-state driver.
  • the three-state buffer has a three-state output terminal and an enable input terminal, and a three-state output terminal Under the control of the enable input, when the potential of the enable input is an effective potential, the three-state output is used for normal logic state output (logic 0 or logic 1). When the potential of the enable input is an invalid potential, the three-state output The output of the terminal is in a high impedance state, which is equivalent to disconnecting the three-state output terminal from the circuit to which it is connected.
  • the buffer circuit 2112 may include a buffer chip U1.
  • the control chip 2111 may include a GPIO-04 pin for outputting a red PWM signal R_PWM, a GPIO-05 pin for outputting a green PWM signal G_PWM, a GPIO-06 pin for outputting a blue PWM signal B_PWM, GPIO-10 pin for output mixed color PWM signal Y_PWM, GPIO-24 pin for outputting red enable signal R_EN, GPIO-25 pin for outputting green enable signal G_EN and blue enable signal GPIO-26 pin of B_EN.
  • the Buffer chip U1 may include a total of seven input pins from pins A1 to A7, and a total of seven output pins from pins Y1 to Y7.
  • the Buffer chip U1 also includes Pin, GND pin, VCC pin and Pin.
  • the A1 pin is respectively connected to the GPIO-04 pin and one end of the resistor R4 to receive the red PWM signal R_PWM provided by the control chip 2111.
  • the A2 pin is respectively connected to the GPIO-05 pin and one end of the resistor R5 to receive the green PWM signal G_PWM provided by the control chip 2111.
  • the A3 pin is respectively connected to the GPIO-06 pin and one end of the resistor R6 to receive the blue PWM signal B_PWM provided by the control chip 2111.
  • the A4 pin is respectively connected to the GPIO-10 pin and one end of the resistor R10 to receive the color mixing PWM signal Y_PWM provided by the control chip 2111.
  • the A5 pin is respectively connected to the GPIO-24 pin and one end of the resistor R9 to receive the enable signal R_EN provided by the control chip 2111.
  • the A6 pin is respectively connected to the GPIO-25 pin and one end of the resistor R8 to receive the enable signal G_EN provided by the control chip 2111.
  • the A7 pin is respectively connected to the GPIO-26 pin and one end of the resistor R7 to receive the enable signal B_EN provided by the control chip 2111.
  • the VCC pin is connected to one end of the inductor L1 and one end of the capacitor C8, the other end of the inductor L1 is connected to the power terminal VCC6, and the other end of the capacitor C8 is grounded.
  • One end of the inductor L1 and the capacitor C8 form a filter circuit to filter out high-frequency components and clutter in the circuit.
  • the VCC pin may also be directly connected to the power terminal VCC6.
  • the Y1 pin is used to provide the red PWM signal R_PWM after buffering.
  • the Y2 pin is used to provide the green PWM signal G_PWM after buffering.
  • the Y3 pin is used to provide the blue PWM signal B_PWM after buffering.
  • the Y4 pin is used to provide the color mixing PWM signal Y_PWM after buffering.
  • the Y1 pin to the Y4 pin can be directly or indirectly connected to the data selector 13.
  • the Y5 pin is used to provide the enable signal R_EN after buffering.
  • the Y6 pin is used to provide the enable signal G_EN after buffering.
  • the Y7 pin is used to provide the enable signal B_EN after buffering.
  • the Y5 pins to Y7 pins may be directly or indirectly connected to the data selector 213, and may also be directly or indirectly connected to the signal generator 212.
  • the voltage provided by the power terminal VCC6 may be 3V.
  • the resistance value of the resistor R4 to the resistor R10 can all be 10k ⁇ .
  • the parameter of the capacitor C8 can be 100n/16v.
  • the model of the inductor L1 can be BLM15AG121SN1D.
  • the PWM signal and the enable signal transmitted by the control chip 2111 are transmitted to the subsequent circuit through the buffer circuit, the driving capability of the PWM signal and the enable signal transmitted to the subsequent circuit is enhanced, and the stable and efficient operation of the subsequent circuit is ensured.
  • control chip 2111 may be a digital light processing (DLP, Digital Light Processing) chip
  • DLP Digital Light Processing
  • the DLP chip may be a DLPC6421 chip or a DDP4422 chip.
  • the data selector 213 can be an 8-to-1 selector, assuming that the four first current control signals are red PWM signal R_PWM, green PWM signal G_PWM, and blue PWM signal.
  • the M enable signals are the red enable signal R_EN, the green enable signal G_EN, and the blue enable signal B_EN.
  • the data selector 213 has data input terminals for receiving four first current control signals, which are respectively the pin S5 for receiving the red PWM signal R_PWM (for example, the same as the buffer circuit 2112 shown in FIG.
  • the pin S3 used to receive the green PWM signal G_PWM (for example, connected to the Y2 pin in the buffer circuit 2112 shown in Fig. 8), and the pin S1 used to receive the blue PWM signal B_PWM (For example, it is connected to the Y3 pin in the buffer circuit 2112 shown in FIG. 8) and the pin S7 for receiving the color mixing PWM signal Y_PWM (for example, it is connected to the Y4 pin in the buffer circuit 2112 shown in FIG. 8);
  • the selector 213 also has logic pins for receiving three enable signals, which are pins A2 for receiving the red enable signal R_EN (for example, connected to the Y5 pin in the buffer circuit 2112 shown in FIG.
  • the pin A1 used to receive the green enable signal G_EN (for example, connected to the Y6 pin in the buffer circuit 2112 shown in FIG. 8) and the pin A0 used to receive the blue enable signal B_EN (for example, as shown in FIG. 8
  • the Y7 pin in the buffer circuit 2112 shown is connected; the data selector 213 also has an output pin D for outputting the second current control signal T_PWM.
  • the data selector 213 is used to set the first current control signal corresponding to a certain primary color (that is, the first current control signal) when the enable signal corresponding to a certain primary color is at an effective potential and the enable signal corresponding to other primary colors is not at an effective potential.
  • the control signal is an effective control signal) as the second current control signal output from the output pin; when the enable signals corresponding to at least two primary colors are at effective potentials, the color mixing current control signal is used as the second current control signal from the output pin D output.
  • the second current control signal T_PWM output by the output pin meets Table 1. Please refer to Table 1.
  • the potentials of the enable signals R_EN, G_EN, and B_EN are 0, 1, and 0 respectively, then the green enable signal G_EN is the effective potential, and the red enable signal R_EN and the blue-green enable signal B_EN are not.
  • the second current control signal T_PWM is G_PWM; the potentials of the enable signals R_EN, G_EN, and B_EN are 1, 1, 0, respectively, then the red enable signal R_EN and the green enable signal G_EN are effective potentials, and the blue enable signal B_EN If it is not a valid potential, the second current control signal T_PWM is Y_PWM.
  • the content of Table 1 can be simplified in actual use.
  • control chip 2111 also includes other pins. As shown in FIG. 10, the control chip also includes a power pin VCC, a first ground pin GND, and a second ground pin VSS.
  • the enable pin EN, the power pin VCC is connected to the first power terminal VCC1, the enable pin EN is connected to the second power terminal VCC2, and the first ground pin GND and the second ground pin VSS are both grounded.
  • the display control module 21 further includes a first resistor R1445 and a first capacitor C1372.
  • the first resistor R1445 is connected in series between the power pin VCC and the first power terminal VCC1.
  • One end of a capacitor C1372 is connected to one end of the first resistor R1445 connected to the power pin VCC, and the other end is grounded.
  • the first resistor R1445 and the first capacitor C1372 form a filter circuit for filtering high frequency components and clutter in the circuit.
  • the VCC pin may also be directly connected to the first power terminal VCC1.
  • the display control module 21 further includes a second resistor R1287, and the second resistor R1287 is connected in series between the enable pin EN and the second power terminal VCC2; optionally, the display control module 21 further includes a third resistor R1325 , The fourth resistor R1427, the fifth resistor R1272 and the second capacitor C1430, wherein the third resistor R1325, the fourth resistor R1427 are connected in series, and one end of the series connected third resistor R1325 and fourth resistor R1427 is connected to the output pin D, and the other One end is used to output the modulated T_PWM.
  • the other end is connected to the data selector 213, the fifth resistor R1272 and the second capacitor C1430 are connected in parallel, and one end of the fifth resistor R1272 and the second capacitor C1430 connected in parallel is connected to the third resistor R1325 and the second capacitor.
  • the node between the four resistors R1427 is connected, and the other end is grounded.
  • the fifth resistor R1272 is a pull-down resistor, used to pull down the potential of the output terminal D to a low level when the output terminal D does not output a signal, so as to ensure that when the output terminal D does not output a signal, the color mixing PWM signal T_PWM is low level ;
  • the second capacitor C1430 is a filter capacitor, used to filter out the spikes and ripples of the mixed color PWM signal T_PWM;
  • the first resistor R1445, the third resistor R1325 and the fourth resistor R1427 are usually 0 ohm resistors, the first resistor R1445,
  • the three resistors R1325 and the fourth resistor R1427 are optional resistors. When some nodes of the data selector 213 require testing, connect the first resistor R1445, the third resistor R1325, and the fourth resistor R1427 in series at the corresponding positions. Convenient for testing.
  • the data selector 213 in FIG. 10 also includes other pins.
  • the data selector 213 has a total of 16 pins. All pins except the aforementioned pins are idle pins or used for other functions. The embodiments of this application do not limit this.
  • the resistance of the resistor R1287 can be 3.3kW
  • the resistance of the resistor R1272 can be 10kW
  • the capacitance of the C1372 is 100nF (nanofarad)
  • the working voltage is 16V
  • the voltage of the second power terminal VCC2 is 5V.
  • the light source driving circuit 22 includes: a voltage output circuit 221, a driving chip 222, and a peripheral circuit 223;
  • the voltage output circuit 221 is used to provide the peripheral circuit 223 with the rated voltage of the laser light source 23;
  • the driving chip 222 is used to receive the second current control signal, and provide the current corresponding to the second current control signal to the peripheral circuit 223, and receive the duty cycle control signal, and control the conduction of the peripheral circuit 223 based on the duty cycle control signal. On and off
  • the peripheral circuit 223 is respectively connected to the driving chip 222 and the laser light source 23, and is used to provide the laser light source 23 with a current corresponding to the second current control signal under a rated voltage when the drive chip 222 and the laser light source 23 are turned on.
  • the aforementioned light source drive circuit 22 is suitable for various monochromatic laser light sources.
  • the current voltage output circuit is divided into two types: boost and buck according to the working mode.
  • a step-up circuit is a circuit that raises the input voltage Vi to the rated voltage Vo of the laser light source, Vi ⁇ Vo
  • a step-down circuit is a circuit that lowers the input voltage Vi to the rated voltage Vo of the laser light source, Vi>Vo.
  • the embodiment of the present application takes the following two laser light sources respectively involving a boost circuit and a buck circuit as examples for description.
  • the laser light source 23 is a laser component, also called a bank light source (bank is a packaging method), and the voltage output circuit is a step-down circuit.
  • the bank light source may include one or more bank lasers. When the bank light source includes multiple bank lasers, the multiple bank lasers are connected in series, and when the bank light source includes multiple bank lasers, the multiple bank lasers are connected in series. As shown in FIG. 12, each bank laser may include a plurality of transistor outlines (TO, Transistor Outline) 231 connected in series.
  • one bank laser can encapsulate 8 TOs.
  • the number of bank lasers required is different, such as 1, 2, or more.
  • the driving chip 222 may include one or more processing modules, and each processing module may be used to control one laser.
  • the structure of each processing module is the same.
  • the structure of each processing module may be as shown in FIG. 13, which is an internal structure of a processing module provided by an embodiment of the present application. Schematic.
  • the processing module may include: a divider x1, a switching frequency square wave generator H, a voltage filter M, a comparator lm1, a comparator lm2, a comparator lm3, a buffer m1, a resistor r21, and a capacitor c21.
  • FIG. 13 assumes that the processing module has a first pin ADIM for receiving the second current control signal T_PWM, and a second pin RT for receiving the duty cycle control signal LD_Duty.
  • the processing module also has a third pin DRV, a fourth pin PWM and a fifth pin ISEN.
  • the first pin ADIM of the processing module can be connected to one end of the divider x1.
  • the divider x1 is used to connect the signal transmitted by the first pin ADIM (for example, the first pin ADIM is connected to the output pin D of the data selector shown in FIG. 9, and the first pin ADIM is the aforementioned second
  • the current control signal T_PWM is divided by 10.
  • the other end of the divider x1 is connected to one end of the voltage filter M, and the voltage filter M is connected to determine the positive input signal ADJ according to the voltage of the signal output by the divider x1.
  • the voltage filter M is used to limit the voltage of the positive input signal ADJ so that the voltage is less than or equal to the preset upper limit voltage.
  • the positive input signal ADJ output by the voltage filter M is the signal output by the divider x1;
  • the voltage of the positive input signal ADJ output by the voltage filter M is the upper limit voltage. This can ensure that the voltage of the positive input signal ADJ is less than or equal to the upper limit voltage, and avoid excessively high voltage of the positive input signal ADJ from causing damage to subsequent circuits (such as the comparator lm1).
  • Each of the comparators lm1 and lm3 has two input terminals, a positive input terminal and a negative input terminal, and one output terminal.
  • the comparator lm2 has a total of 3 input terminals, a positive input terminal, a negative input terminal, and an enable input terminal, and one output terminal.
  • the positive input terminal of the comparator lm1 is connected to the other terminal of the voltage filter M.
  • the negative input end of the comparator lm1 is respectively connected to one end of the resistor R932 and one end of the capacitor c21, and the other end of the resistor R932 is connected to the fifth pin ISEN.
  • the output end of the comparator lm1 can be connected to the other end of the capacitor c21.
  • the comparator lm1 is used to compare the voltage of the positive input terminal and the negative input terminal.
  • the logical value of the output of the comparator lm1 is 1.
  • the logical value of the output of the comparator lm1 is 0.
  • the positive input terminal of the comparator lm2 is connected to the output terminal of the comparator lm1.
  • the negative input terminal of the comparator lm2 is connected to one end of the switching frequency square wave generator H, and the other end of the switching frequency square wave generator H is connected to the second pin RT.
  • the enable input terminal of the comparator lm2 is connected to the output terminal of the comparator lm3.
  • the output terminal of the comparator lm2 is connected to one end of the buffer m1, and the other end of the buffer m1 is connected to the third pin DRV.
  • the switching frequency square wave generator H is used to generate a square wave with a specified switching frequency.
  • the square wave is transmitted to the third pin DRV through the comparator lm1 and the comparator lm2, and is output by the third pin DRV.
  • the square wave output by the third pin DRV is also called a driver (DRV) square wave.
  • the DRV square wave output by the third pin DRV is relative to the switching frequency of the square wave generated by the switching frequency square wave generator H constant.
  • the switching frequency of the switching frequency square wave generator H can be related by the resistance value of its external resistor. For example, in FIG. 14, the switching frequency square wave generator H is connected to the resistor R904, and the switching frequency of the switching frequency square wave generator H can be calculated based on the resistance value of the resistor R904.
  • the comparator lm2 is used to compare the voltage of the positive input terminal and the negative input terminal when the enable input terminal is at a valid level. When the voltage at the positive input terminal of the comparator lm2 is greater than the voltage at the negative input terminal, the output logic value of the comparator lm2 is 1; when the voltage at the positive input terminal of the comparator lm2 is less than the voltage at the negative input terminal, the logic value output by the comparator lm2 0.
  • the positive input terminal of the comparator lm3 is connected to the fourth pin PWM, and the negative input terminal of the comparator lm3 is connected to the DC power terminal.
  • the voltage of the DC power terminal may be 1V.
  • the comparator lm3 is used for the voltage of its positive input terminal and negative input terminal. When the voltage of the positive input terminal of the comparator lm3 is greater than the voltage of the negative input terminal, the logic value of the comparator lm3 output is 1; when the voltage of the positive input terminal of the comparator lm3 is less than the voltage of the negative input terminal, the logic value of the comparator lm3 output 0.
  • each electronic component connected to the processing module may be a component in the peripheral circuit 223.
  • each processing module may be as shown in FIG. 13, including: the first pin ADIM, the second pin RT, the third pin DRV, and the fourth pin. Pin PWM and fifth pin ISEN. Among them, multiple processing modules can share the first pin ADIM and the second pin RT. Please refer to FIG. 14. Assuming that the driving chip 222 is used to control two lasers, the first laser and the second laser, the driving chip 222 includes two processing modules, which are the first processing corresponding to the first laser. Module and a second processing module corresponding to the second laser.
  • the first laser and the second laser can be implemented in multiple ways. For example, in one implementation, the first laser and the second laser can be a bank laser respectively, and in another implementation, the first laser and the second laser One of the two lasers is a bank laser, and the other is two bank lasers connected in series.
  • the two processing modules share the first pin ADIM and the second pin RT.
  • the first processing module of the two processing modules has a third pin DRV1, a fourth pin PWM1 and a fifth pin ISEN1; the second processing module The module has a third pin DRV2, a fourth pin PWM2 and a fifth pin ISEN2.
  • the driver chip 222 also includes a power pin VCC, a sixth pin BLON, a seventh pin VREF, and a ground pin GND.
  • the power pin VCC is used to power the driver chip 222, and the power supply voltage is usually 12V;
  • the sixth pin BLON is used to control the opening and closing of the driving chip;
  • the seventh pin VREF is used to provide a reference voltage generated inside the driving chip 222, the reference voltage is usually 6V;
  • the ground pin GND is grounded.
  • the peripheral circuit may include a positive output port LD1+ and a negative output port LD1- corresponding to the first processing module, and a positive output port LD2+ and a negative output port LD2- corresponding to the second processing module.
  • the first pin ADIM of the driving chip 222 can be connected to the data selector 213 through a voltage divider resistor, for example, can be connected to the output pin D of the data selector 213 shown in FIG. 9 or FIG. 10 for receiving the data
  • the second current control signal T_PWM provided by the selector 213.
  • the first pin ADIM of the driving chip 222 can be connected to one end of the resistor R987 and one end of the resistor R986, the other end of the resistor R987 is grounded, and the capacitor C925 is connected in parallel with the resistor R987, and the resistor R986
  • the other end of the resistor R974 is connected to one end of the resistor R974, and the other end of the resistor R974 is connected to the data selector 213 (such as the output pin D) for receiving the second current control signal T_PWM provided by the data selector 213.
  • the other end of the resistor R974 is also connected to one end of the resistor R961, and the other end of the resistor R961 is grounded.
  • R961 is a pull-down resistor
  • resistors R986, R974, and R987 are voltage divider resistors.
  • Capacitor C925 is a filter capacitor used for high-frequency filtering and blocking high-frequency clutter in the circuit.
  • the fifth pin ISEN of each processing module can be connected to a sampling resistor.
  • the fifth pin ISEN1 of the first processing module can be connected to one end of the first sampling resistor (not shown in FIG. 14) through the resistor R919, and one end of the first sampling resistor is also connected to the negative output port LD1, and
  • the fifth pin ISEN1 of the first processing module can be connected to the other end of the first sampling resistor through a capacitor C918, and the other end of the first sampling resistor is grounded.
  • the first sampling resistor may include one or more resistors. When it includes multiple resistors, the multiple resistors are connected in parallel, and the required resistance value can be achieved by connecting multiple resistors in parallel, so as to achieve current regulation of the light source driving circuit.
  • the first sampling resistor may include a resistor R977, a resistor R978, a resistor R927, and a resistor R979 connected in parallel.
  • the first processing module can detect the driving current of the corresponding laser through the first sampling resistor.
  • the fifth pin ISEN2 of the second processing module can be connected to one end of a second sampling resistor (not shown in FIG. 14) through a resistor R926, and one end of the second sampling resistor is also connected to the negative output port LD2 -, and
  • the fifth pin ISEN2 of the second processing module can be connected to the other end of the second sampling resistor through a capacitor C917, and the other end of the second sampling resistor is grounded.
  • the second sampling resistor may include one or more resistors. When it includes multiple resistors, the multiple resistors are connected in parallel, and the required resistance value can be achieved by connecting multiple resistors in parallel, so as to achieve current regulation of the light source driving circuit.
  • the second sampling resistor may include a resistor R925, a resistor R976, a resistor R975, and a resistor R920 connected in parallel.
  • the second processing module can detect the driving current of the corresponding laser through the second sampling resistor.
  • the third pin DRV1 of the first processing module can be connected to the switching transistor V827.
  • the third pin DRV1 of the first processing module may be connected to the gate of the switching transistor V827.
  • the source of the switching transistor V827 is respectively connected to one end of the first sampling resistor and one end of the transformer L810, and the other end of the transformer L810 is connected to the negative output port LD1 ⁇ .
  • the drain of the switching transistor V827 is connected to the power supply terminal VDD1.
  • the signal output by the third pin DRV1 of the first processing module can control the switching state of the switching transistor V827, so that when the switching transistor V827 is in the conducting state, the power supply terminal VDD1 is connected to one end of the transformer L810, thereby changing the negative pole through the transformer L810 For the output voltage of the output port LD1-, the other end of the transformer L810 is not connected to other ports.
  • the switching transistor may be a metal oxide semiconductor (MOS, Metal Oxide Semiconductor) field effect transistor.
  • the third pin DRV1 of the first processing module can be connected to one end of the diode VD901 and one end of the resistor R922, the other end of the diode VD901 is connected to one end of the resistor R923, and the other end of the resistor R922 is connected to the other end of the resistor R923. Both are connected to the gate of the switching transistor V827, and the other end of the resistor R922 and the other end of the resistor R923 are also connected to one end of the first sampling resistor through the resistor R932.
  • the drain of the switching transistor V827 can be connected to the power supply terminal VDD1 through two parallel diodes VD908.
  • the source of the switching transistor V827 can be connected to the transformer L810 through a capacitor C923.
  • a capacitor C16 is also connected in series between the positive output port LD1+ and the negative output port LD1 ⁇ corresponding to the first processing module.
  • the capacitor C16 is a step-down capacitor. When the power terminal VDD1 is turned on, the capacitor C16 is continuously charged, and when the power terminal VDD1 is turned off, the capacitor C16 is continuously discharged.
  • the capacitor C16 can be one or more capacitors. When it includes multiple capacitors, the multiple capacitors are connected in parallel. By connecting multiple capacitors in parallel, the required capacitance value can be achieved, so as to meet the current regulation requirements of the light source driving circuit and ensure Accurate adjustment of the current of the light source drive circuit.
  • the capacitor C16 may be 4 capacitors connected in parallel.
  • the third pin DRV2 of the second processing module can be connected to the switching transistor V937.
  • the second output pin DRV2 of the second processing module may be connected to the gate of the switching transistor V937.
  • the source of the switching transistor V937 is respectively connected to one end of the second sampling resistor and one end of the transformer L812, and the other end of the transformer L812 is connected to the negative output port LD2 ⁇ .
  • the drain of the switching transistor V937 is connected to the power supply terminal VDD2.
  • the signal output from the third pin DRV1 of the second processing module can control the switching state of the switching transistor V937, so that when the switching transistor V937 is in the on state, the power terminal VDD2 is connected to one end of the transformer L812, thereby changing the negative pole through the transformer L812
  • the output voltage of the output port LD2- may be a MOS field effect transistor.
  • the third pin DRV2 of the second processing module can be connected to one end of the diode VD902 and one end of the resistor R921, the other end of the diode VD902 is connected to one end of the resistor R924, and the other end of the resistor R924 and the other end of the resistor R921 Both are connected to the gate of the switching transistor V937, and the other end of the resistor R921 and the other end of the resistor R924 are also connected to one end of the second sampling resistor through the resistor R931.
  • the drain of the switching transistor V937 can be connected to the power supply terminal VDD2 through two parallel diodes VD909.
  • the source of the switching transistor V937 can be connected to the transformer L812 through a capacitor C924.
  • a resistor C17 is also connected in series between the positive output port LD2+ and the negative output port LD2- corresponding to the second processing module.
  • the capacitor C17 is a step-down capacitor. When the power terminal VDD2 is turned on, the capacitor C17 is continuously charged, and when the power terminal VDD2 is turned off, the capacitor C17 is continuously discharged.
  • the resistor C17 can be one or more resistors. When it includes multiple capacitors, the multiple capacitors are connected in parallel. By connecting multiple capacitors in parallel, the required capacitance value can be achieved, so as to meet the current regulation requirements of the light source driving circuit and ensure Accurate adjustment of the current of the light source drive circuit.
  • the capacitor C17 can be 4 resistors connected in parallel.
  • the fourth pin PWM1 of the first processing module is respectively connected to one end of the resistor R908 and one end of the resistor R959, and the other end of the resistor R908 is respectively connected to one end of the resistor R980 and the source of the switching transistor V936; the fourth pin of the second processing module
  • the PWM2 pin is connected to one end of the resistor R937 and the other end of the resistor R959.
  • the capacitor C920 is connected in parallel with the resistor R907. One end of the parallel capacitor C920 and the resistor R907 is connected to one end of the resistor R908, and the other end is connected to the other end of the resistor R937.
  • R980 is connected to the seventh pin VREF for receiving the reference voltage; the gate of the switching transistor V936 is connected to the first pin ADIM through a resistor R981, one end of the resistor R982 is connected to the gate of the switching transistor V936, and the other end is grounded .
  • the seventh pin VREF is connected to one end of the capacitor C915, and the other end of the capacitor C915 is grounded.
  • the resistor R907 and the resistor R937 are pull-down resistors, which are used to pull down the levels of the fourth pins PWM1 and PWM2 when there is no signal on the first pin ADIM to ensure that the fourth pin will be used when there is no signal on the first pin ADIM.
  • the second current control signal T_PWM of the pins PWM1 and PWM2 are both low level; resistor R959 is a 0 ohm resistor, which is a resistor that can be optionally set. When there is a test requirement in the circuit, the resistor can be connected in series in Figure 14 To facilitate debugging, the resistor R959 can connect the fourth pin PWM1 and PWM2 together, and is controlled by the first pin ADIM; the resistor R982 is a pull-down resistor, used when there is no signal on the first pin ADIM, Pull down the level of the first pin ADIM to ensure that when there is no signal on the first pin ADIM, the second current control signal T_PWM is low; when the first pin ADIM is high, the switching transistor V936 is turned on and Ground, the signals entering the fourth pins PWM1 and PWM2 are low at this time; when the first pin ADIM is low, the switching transistor V936 is turned off, and the seventh pin VREF is connected to the fourth pin through a resist
  • the second pin RT of the driving chip 222 can be connected to one end of the resistor R904, and the other end of the resistor R904 is grounded.
  • resistor R903 One end of the resistor R903 is connected to the power supply terminal VCC3, the other end is connected to the power supply pin VCC of the driving chip 222, one end of the capacitor C914 is connected to the power supply pin VCC, and the other end is grounded.
  • the resistor R903 and the capacitor C914 form a low-pass filter for low-frequency filtering and blocking high-frequency clutter in the circuit.
  • the driving chip 222 may also include an eighth pin ST.
  • the eighth pin ST of the driving chip 222 may be connected to one end of a resistor R902, and the other end of the resistor R902 is respectively connected to one end of the resistor R901 and the base of the transistor V901. Connect, the other end of the resistor R901 is connected to the emitter of the transistor V901, and the collector of the transistor V901 is grounded.
  • the circuit connected to the eighth pin ST is a protection circuit. When the light source drive circuit works abnormally, the eighth pin ST can output an error signal to trigger the protection mechanism of the light source drive circuit. For example, the laser light source or the overall power supply can be turned off to implement the protection mechanism.
  • the sixth pin BLON is respectively connected to one end of the resistor R905 and one end of the resistor R905, the other end of the resistor R905 is grounded, and the other end of the resistor R905 is respectively connected to one end of the resistor R962 and the source of the switching transistor V938.
  • the gate is respectively connected to one end of the resistor R963 and one end of the resistor R964.
  • the other end of the resistor R963 is connected to receive the lighting enable signal ENA, and the other end of the resistor R964 is connected to the drain of the switching transistor V938.
  • the sixth pin BLON is connected to the peripheral sub-circuit including the switching transistor V938 to realize the inversion of ENA.
  • the lighting enable signal ENA is a signal used to control whether the driving chip 222 works.
  • the lighting enable signal ENA is generated by chips other than the driving chip 222.
  • the control chip 2111 shown in FIG. 8 also has a lighting pin LEDEN (not marked in the figure), and the lighting enable signal ENA can be generated by The control chip 2111 shown is generated and output through the lighting pin LEDEN of the control chip 2111.
  • switching transistor V936 and switching transistor V938) for signal reversal are optional components based on actual design logic, which are selected according to the matching of the front-end design logic and the back-end design in the circuit. Set up. For example, the signal output by the display control module 21 is input to the back end after being inverted, and needs to be inverted and adjusted to the actual output signal of the display control module 21 before entering the driving chip 222.
  • FIG. 15 is a schematic diagram of the structure of a schematic step-down circuit provided by an embodiment of the application.
  • FIG. 15 takes the first processing module and the step-down circuit connected to it as an example for description.
  • the functions of each pin and component in FIG. 15 can refer to the specific description in the foregoing FIG. 14, which will not be repeated in this embodiment of the application. .
  • the aforementioned resistor R987, resistor R986, and resistor R974 are voltage dividing resistors, which can divide the second current control signal T_PWM provided by the data selector 213, so that the voltage of the divided analog signal is input
  • the first pin ADIM of the driving chip 222, the driving chip 222 adjusts the driving current of the laser light source according to the input voltage U ADIM of the first pin ADIM. Taking any laser in the laser light source as an example, the driving current of the laser L Laser The size calculation formula is as follows:
  • T_PWM represents the average voltage amplitude of the T_PWM signal
  • U ADIM is the input voltage of the first pin ADIM
  • R ISEN is the resistance of the sampling resistor of any laser.
  • R ISEN is the resistance of the first sampling resistor
  • the first processing module can detect the actual driving current of the corresponding first laser through the first sampling resistor, and feed it back to the negative input terminal of the comparator lm1 through the fifth pin ISEN1, and use the comparison result to pass
  • the third pin DRV1 adjusts the duty cycle of the DRV square wave to control the switching action of the switching transistor V827 to adjust the voltage of the negative output port LD1-and then adjust the voltage across the positive and negative terminals of the first laser to make the first laser actually drive current Reach the required set current value, that is, the current value of the aforementioned drive current L Laser .
  • the duty cycle of the DRV square wave is increased, and when the detection current is greater than the set current value, the duty cycle of the DRV square wave is reduced. ratio.
  • the second processing module can detect the actual driving current of the corresponding second laser through the second sampling resistor, and feed it back to the negative input terminal of the comparator lm1 through the fifth pin ISEN2, and use the comparison result to pass the third pin DRV2 Adjust the duty cycle of the DRV square wave to control the switching action of the switching transistor V937 to adjust the voltage of the negative output port LD1-and then adjust the voltage across the positive and negative electrodes of the second laser so that the actual driving current of the second laser reaches the required setting.
  • the constant current value is the current value of the aforementioned drive current L Laser .
  • the adjustment principle refer to the adjustment principle of the aforementioned first processing module, which will not be repeated here.
  • the switching frequency of the switching transistors V827 and V927 can be determined by the DRV square wave output by the third pin DRV.
  • the switching frequency of the DRV square wave is the switching frequency of the square wave generator H calculated based on the resistance of the resistor R904 Therefore, the switching frequency of the switching transistors V827 and V927 is determined by the resistance of the resistor R904. Among them, the switching frequency of the switching transistors V827 and V927
  • the signals output by the fourth pins PWM1 and PWM2 of the drive chip can be understood as the enable signals for the drive chip to work. When the signal is high, the drive chip works normally, and when the signal is low, the drive chip stops working. Normally, the signals output by the fourth pins PWM1 and PWM2 are continuously high to ensure the continuous operation of the driving chip.
  • the laser light source 23 is a multichip laser (MCL, Multichiped Laser), and the voltage output circuit is a booster circuit. Since the initial input voltage Vi of the boost circuit is lower than that of the buck circuit, if the boost circuit has a short circuit and other faults, the lower initial input voltage Vi does not exceed the rated voltage Vo of the laser and will not cause damage to the laser. It will not cause the risk of electric shock to the human body. Therefore, compared with the step-down circuit, the booster circuit is less likely to damage the equipment, and the safety is higher.
  • MCL Multichiped Laser
  • FIG. 16 is a schematic structural diagram of an MCL provided by an embodiment of the present application.
  • the MCL usually includes 4 laser units 232, and each laser unit 232 includes multiple TOs connected in series.
  • the multiple laser units can be connected in series in two ways: wired series and board series.
  • Wire series connection refers to connecting multiple laser units end to end in sequence through wires.
  • the board series connection means that in the process of drawing the layout of the light source driving circuit, the multiple laser units are connected end to end in sequence through the layout wiring.
  • the number of TOs connected in series can be set according to the brightness of the laser power supply.
  • each laser unit 232 may include 5 TOs connected in series. That is, the MCL can adopt a 4 ⁇ 5 layout, and the MCL includes 20 TOs in total. Or each laser unit 232 may include 6 TOs connected in series. That is, the MCL can adopt a 4 ⁇ 6 layout, and the MCL includes a total of 24 TOs. Or each laser unit 232 may include 7 TOs connected in series. That is, the MCL can adopt a 4 ⁇ 7 layout, and the MCL includes 28 TOs in total.
  • the MCL may also include 3 laser units, each laser unit includes 5 serially connected TOs, that is, the MCL can adopt a 3 ⁇ 5 layout, and the MCL includes 15 TOs in total. .
  • the MCL may also include 2 laser units, and each laser unit includes 7 TOs connected in series, that is, the MCL may adopt a 2 ⁇ 7 layout, and the MCL includes 14 TOs in total.
  • the MCL includes 4 laser units, and each laser unit includes 6 serial TOs as an example for illustration, and the layout of the MCL is not limited.
  • FIG. 17 is a schematic structural diagram of a laser series connection circuit provided by an embodiment of the present application.
  • the laser series connection circuit may be an XP socket.
  • the output signal of the light source driving circuit reaches the laser serial connection board through the XP socket, thereby lighting the laser.
  • the XP socket can include a total of 8 pins from pin 1 to pin 8.
  • pin 1 can be connected to the negative output port of the light source driving circuit 22
  • pin 7 can be connected to the positive output port of the light source driving circuit 22.
  • Pin 2 is used to connect to the negative pole of the laser
  • pin 8 is used to connect to the positive pole of the laser.
  • FIG. 18 is an equivalent circuit diagram of an MCL provided by an embodiment of the present application.
  • the blue MCL includes 4 laser units 101, and each laser unit 101 includes 2 ports, then the 4 laser units include port 0 to port 7.
  • Port 0, port 2, port 4, and port 6 are positive, and port 1, port 3, port 5, and port 7 are negative.
  • port 5 can be connected to port 6
  • port 7 can be connected to port 2
  • port 3 can be connected to port
  • port 4 can be connected to pin 8 of the blue MCL laser serial circuit
  • port 1 can be connected to The pin 2 of the blue MCL laser serial circuit is connected.
  • the 140V voltage transmitted by the power drive circuit 02 can be transmitted to the third laser unit through the laser series circuit, and the third laser unit is reduced to 108.5V, and then transmitted to the fourth laser unit, and The fourth laser unit is stepped down to 77V, and then transmitted to the second laser unit, and the second laser unit is stepped down to 45.5V, and finally transmitted to the first laser unit, and then transmitted to the first laser unit.
  • the cell is stepped down to 14V, which makes the MCL emit light.
  • the light source driving circuit may be as shown in FIG. 19.
  • the driving chip has a control pin CTRL for receiving the second current control signal T_PWM, and a duty cycle adjustment pin PWM for receiving the duty cycle control signal LD_duty.
  • the processing module also has a PWM output pin PWMOUT, a setting pin RT, a switch pin GATE, a first current control pin ISP and a second current control pin ISN, and an adjustment pin FB.
  • the control pin CTRL is connected to one end of the resistor R812 and one end of the resistor R813, and the other end of the resistor R812 is connected to the node ADIM that provides the second current control signal T_PWM through R811, for example, to the other end of the resistor R1427 in FIG. connection.
  • the other end of the resistor R813 is grounded.
  • the node ADIM is used to receive the second current control signal T_PWM, which is input to the control pin CTRL through a voltage divider circuit composed of resistors R811, R812, and R813.
  • the setting pin RT is grounded through a resistor R818.
  • a current detection resistor is connected in series between the first current control pin ISP and the second current control pin ISN.
  • the current detection resistor may include a resistor R825 and a resistor R855 connected in parallel.
  • the adjustment pin FB is respectively connected to one end of the resistor R823 and one end of the resistor R880.
  • the other end of the resistor R823 is connected to the positive output port LD+ (ie, the positive electrode of the laser) through the series resistor R822, and the other end of the resistor R880 is grounded.
  • the PWM output pin PWMOUT is connected to the negative output port LD- (ie, the negative electrode of the laser), and the switch pin GATE is connected to a switching transistor, which can be NMOS.
  • the LD+ of the positive output port and the LD- of the negative output port can be respectively connected to the aforementioned laser series circuit.
  • FIG. 20 is a schematic diagram of a specific structure of the aforementioned light source driving circuit.
  • the driver chip also includes power supply pin VC, function pin SENSE, ground pin GND, pin VIN, pin INTVCC, pin OPENLED, pin VERF and pin SS.
  • the control pin CTRL is connected to the node k, the resistor R813 and the capacitor C803 are connected in parallel. One end of the parallel resistor R813 and the capacitor C803 is connected to the node k, and the other end is grounded.
  • the node k is also connected to one end of the series resistors R811 and R822.
  • the other ends of the resistor R811 and the resistor R822 are respectively connected to the ADIM port and one end of the resistor R802, and the other end of the resistor R802 is grounded.
  • the ADIM port is used to receive the duty cycle control signal LD_duty.
  • the capacitor C803 is an optional resistor. Setting the capacitor C803 can suppress the current overcharge of the laser and realize the function of the filter circuit.
  • a resistor R821 and a capacitor C808 are connected in series between the power pin VC and ground.
  • the power supply pin VC is also called the output pin of the transconductance error amplifier. It forms a stable voltage loop with the external resistor R821 and the capacitor C808 to stabilize the circuit.
  • the first current control pin ISP is connected to the node f
  • the second current control pin ISN is connected to the laser anode LD+
  • the resistor R825 is connected in parallel with the resistor R855
  • the parallel resistor R825 and resistor R855 are connected in series between the laser anode LD+ and the node f.
  • the function pin SENSE is used to detect the size of the drive current in the peripheral circuit.
  • the function pin SENSE is connected to one end of the resistor R826, and the other end of the resistor R826 is grounded through the capacitor C818.
  • One end of the resistor R826 is also connected to one end of the resistor R828 and one end of the resistor R856, and the other end of the resistor R856 is grounded.
  • the other end of the resistor R828 is connected to one end of the resistor R827, the anode of the diode VD805, and the gate of the switching transistor V928.
  • the cathode of the diode VD805 is connected to one end of the resistor R984.
  • the other end of the resistor R984 and the other end of the resistor R827 are connected to the switch. Pin GATE is connected.
  • the drain of the switching transistor V928 is connected to one end of the resistor R856.
  • the capacitor C821 and the capacitor C822 are in parallel, the resistor R832 and the resistor R830 are in parallel, and the parallel capacitor C821 and the capacitor C822 are connected in series with the parallel resistor R832 and the resistor R830 between the source of the switching transistor V928 and the ground.
  • the source of the switching transistor V928 is also connected to one end of the capacitor C1003, the anode of the two parallel diodes VD802, and one end of the inductor L903.
  • the other end of the inductor L903 is connected to the power supply terminal VCC5, and one end of the parallel capacitors C809 and C810. Connect, the other end of the parallel capacitors C809 and C810 is grounded.
  • the other end of the capacitor C1003 is connected to one end of the resistor R986, and the other end of the resistor R986 is respectively connected to the negative poles of the two parallel diodes VD802 and node f.
  • the node f and ground are also connected to parallel resistors C812, C813, C814, C815 and C816.
  • the adjustment pin FB is respectively connected to one end of the resistor R822 and one end of the resistor R880, the other end of the resistor R880 is grounded, and the other end of the resistor R822 is connected to the node f through the resistor R823.
  • the PWM output pin PWMOUT is connected to one end of the resistor R835.
  • the other end of the resistor R835 is connected to the gate of the switching transistor V803 and one end of the resistor R836.
  • the other end of the resistor R836 and the drain of the switching transistor V803 are both grounded.
  • the switching transistor V803 The source of the laser is connected to the negative pole LD- of the laser.
  • the ground pin GND is grounded.
  • Pin VIN is the power supply pin of the drive chip. Pin VIN is connected to one end of capacitor C806, one end of C807, one end of resistor R819, and one end of resistor R820. The other end of capacitor C806 and the other end of C807 are grounded. The other end of R819 and the other end of resistor R820 are connected to the power supply terminal VDD3.
  • the pin INTVCC is used to provide a regulated power supply.
  • the pin INTVCC is respectively connected to one end of the capacitor C805 and one end of the resistor R816, and the other end of the capacitor C805 is grounded.
  • the other end of the resistor R816 is respectively connected to the pin OPENLED and the cathode of the diode VD801, and the anode of the diode VD801 is connected to the pin SS.
  • This pin INTVCC provides power for internal loads, such as the driver of pin GATE and the driver of pin PWMOUT.
  • the voltage of the pin INTVCC is usually 7.15V.
  • the OPENLED pin is used to detect whether the load of the peripheral circuit is open, and when the load of the peripheral circuit is open, it outputs a low-level signal indicating an open circuit.
  • the pin SS is a soft-start pin, used to control the time of software startup, the soft-start time is set by the capacitor C804 connected to the pin SS.
  • Pin UVLO is connected to one end of C825, one end of resistor R842, one end of resistor R987, one end of resistor R841 and the source of switching transistor V805, the other end of C825 and resistor R842 is grounded, and the other end of resistor R987 is connected to power supply terminal VDD4 , The other end of the resistor R841 is connected to the power supply terminal VDD5.
  • the gate of the switching transistor V805 is respectively connected to one end of the resistor R838 and one end of the resistor R849, the other end of the resistor R838 is connected to ENA, and the other end of the resistor R840 and the drain of the switching transistor V805 are both grounded.
  • the setting pin RT is grounded through a resistor R818.
  • the duty cycle adjustment pin PWM is respectively connected to one end of the resistor R809, one end of the resistor R808 and the source of the switching transistor V801, the other end of the resistor R808 is connected to the power supply terminal VDD6, and the gate of the switching transistor V805 is respectively connected to one end of the resistor R801
  • One end of the resistor R807 is connected, one end of the resistor R805 is connected to the PDIM, and the other end of the resistor R807 and the drain of the switching transistor V801 are both grounded.
  • the pin VREF is the reference voltage output pin, and the output reference voltage can be 2V.
  • This pin VRF can be connected to the test point TP3 used to test the reference voltage, or it can be an idle pin.
  • the current of the MCL shown in FIG. 20 is 3A, and the voltage consumed across the MCL is 82V. You can choose to start boosting from 60V.
  • the resistor R811, the resistor R812, and the resistor R813 are voltage dividing resistors, which can divide the second current control signal T_PWM provided by the data selector 213. The voltage of the divided second current control signal T_PWM is divided by the resistor R811, the resistor R812, and the resistor R813 and then input to the control pin CTRL of the driving chip 222.
  • the driving chip 222 adjusts the driving current of the MCL according to the input voltage of the control pin CTRL.
  • I LD the formula for calculating the magnitude of the driving current I LD is as follows:
  • ADIM represents the average voltage amplitude of the T_PWM signal
  • V CTRL is the input voltage of the pin CTRL
  • R LD is the resistance of the sampling resistor.
  • Pin PWM is connected to LD_Duty (corresponding to PDIM port).
  • LD_Duty corresponding to PDIM port.
  • Pin RT is used to set the switching frequency of the switching transistor V928 (pin RT sets the switching frequency of the switching transistor V928 by directly or indirectly connecting to the pin GATE inside the chip), which is grounded through the resistor R818, and the pin FB It is used to set the maximum output voltage of the boost circuit so that the voltage at both ends of the MCL will not exceed this limit and play a role in protecting the MCL.
  • the voltage of the aforementioned power terminal VCC5 may be 48V
  • the voltage of the power terminal VDD5 may be 48V
  • the voltage of the power terminal VDD6 may be 5V.
  • FIG. 21 is a schematic structural diagram of a schematic boost circuit provided by an embodiment of the application.
  • the functions of each pin and component in FIG. 21 can be referred to the specific description in FIG. 14, which is not repeated in the embodiment of the present application.
  • the display control module 21 further includes a digital-to-analog converter 214 between the processing module and the data selector 213.
  • the digital-to-analog converter 214 may be a digital-to-analog converter (DAC) chip.
  • DAC digital-to-analog converter
  • the digital-to-analog converter 214 is configured to receive N first current control signals in the form of digital signals, respectively convert the received N first current control signals into N first current control signals in the form of analog signals, and convert The subsequent N first current control signals are transmitted to the data selector 213.
  • the converted N first current control signals are DC voltage signals.
  • FIG. 22 assumes that the N first current control signals in the form of digital signals include 4 digital signals R_PWM1, G_PWM1, B_PWM1, and Y_PWM1.
  • the N first current control signals obtained by corresponding conversion include 4 analog signals R_PWM2, G_PWM2, B_PWM2, and Y_PWM2.
  • each switch transistor may be a MOS tube, such as an NMOS tube or a PMOS tube, when the on-off time of the peripheral circuit reaches the ns (nanosecond) level, the light source driving circuit
  • the on-off time of the laser light source reaches the ⁇ s (microsecond) level, so that the current response speed of the laser light source is fast, the accuracy is high, high current and low ripple, and the brightness of the laser light source can be adjusted quickly.
  • the aforementioned light source drive circuit adopts fast response devices (such as MOS tubes) and drive chips to ensure that the current turn-on and turn-off response delay time is within 1us, the current rise and fall times are within 20us, the current ripple frequency is 400kHz, and the amplitude Within ⁇ 5%.
  • the current turn-on response delay is small, the current rise time is fast, the current turn-off response delay is small, the current fall time is fast, the ripple frequency is large, and the amplitude is small.
  • the above rapid control of the current of the laser light source ensures that the current of the laser light source under the ultra-high contrast function can quickly follow the requirements of the image display for the laser source control, ensuring the real-time modulation of the current and the strict synchronization of the image display, so as to achieve the subsequent high Contrast image display algorithm.
  • the contrast of laser projection equipment is usually divided into static contrast and dynamic contrast.
  • Static contrast usually refers to the contrast calculated by the contrast algorithm formulated by the American National Standards Institute (ANSI), which refers to the brightness of the white area and the black area in a picture (that is, the same frame of image) ratio.
  • ANSI American National Standards Institute
  • Dynamic contrast refers to the light-dark ratio of the same frame of image during the display process, which is related to the brightness of the laser light source during the display process, that is, the brightest white area and the darkest black area of the image during the display process. Brightness ratio.
  • the dynamic contrast C satisfies:
  • L w luminance for one frame of image during the display of the brightest white region L B luminance for an image display during the black region darkest.
  • the dynamic contrast formula when L w reaches the maximum value, the dynamic contrast can be improved by reducing the value of L B.
  • the actual display brightness of the image of the laser projection device is usually determined by two factors. One factor is the brightness of the laser light source, and the other factor is the grayscale value of the image (that is, the brightness of the image itself).
  • the superposition can finally determine the actual display brightness of a frame of image. Therefore, the display effect can be optimized by adjusting the ratio of the two factors.
  • the brightness of the image itself in the video displayed by the laser projection device is constantly changing based on its content.
  • the laser light source can be adjusted according to the brightness of the image itself to adjust the actual display brightness of the image.
  • the brightness of the laser light source can be reduced to make the actual display brightness of the frame of image lower than its own brightness.
  • the lower limit of the actual display brightness of the laser projection device when displaying images that is, the lowest actual display brightness (L B )
  • L B lowest actual display brightness
  • the power consumption of the laser projection device is also reduced.
  • the laser projection device provided by the embodiment of the present application can improve the dynamic contrast of the laser projection device without changing the actual display brightness of the image.
  • the image display algorithm is as follows: the brightness of the laser light source and the grayscale value of each frame of image are processed separately to enhance the detail expression of the image, and then under the premise of ensuring the brightness of the displayed image, reduce the brightness of the light source and increase the laser The dynamic contrast of the projection device.
  • FIGS. 23 to 25 as examples to illustrate the image display principles involved in the embodiments of the present application:
  • Fig. 23 to Fig. 25 show the relationship between the input signal gray scale value (also called display gray scale value or image brightness) and screen brightness (that is, actual display brightness).
  • the abscissa is the grayscale value of the input signal
  • the ordinate is the screen brightness.
  • the power of the laser light source (because the power of the laser light source is proportional to the brightness of the laser light source, in the embodiment of this application, it is assumed that the power of the laser light source is equivalent to the laser light source).
  • the brightness of the light source is a standard quantity (that is, a reference quantity).
  • the unit is one.
  • the curve of the gray scale value of the input signal of the laser projection device and the screen brightness (that is, the Horse curve) is the solid line in Figure 23.
  • the input signal grayscale value of a frame of image A currently displayed is 160
  • the corresponding screen brightness is 96.
  • the input signal grayscale value of this frame of image A is increased by D times.
  • Image A is transformed into image A', and the screen brightness corresponding to this image A'is 192.
  • the screen brightness can be reduced to 96 by reducing the power of the laser light source, thereby converting image A'into image A.
  • the laser projection device provided by the embodiment of the present application can expand the display grayscale value range of the image, that is, increase the display grayscale.
  • the upper limit of the value therefore, enhances the detailed expression of the image, and at the same time, under the premise of ensuring that the actual display brightness of the image A remains unchanged, the brightness of the laser light source is reduced, the contrast is increased, and the power consumption is reduced.
  • the laser projection device further includes a light modulation device 24, and the light modulation device 24 may be a digital micromirror device (DMD) or a liquid crystal on silicon (LCOS) ).
  • DMD digital micromirror device
  • LCOS liquid crystal on silicon
  • the processing module 211 includes an algorithm processor 211a and a control processing module 211b.
  • the algorithm processor 211a is connected to the control processing module 211b, and the control processing module 211b is also connected to the data selector 213 and the light modulation device 24, respectively.
  • the algorithm processor 211a is configured to determine the gain value ⁇ of each frame of image, ⁇ 1 according to the grayscale value of each frame of image.
  • the algorithm processor can be implemented using Field-Programmable Gate Array (FPGA).
  • the image display data of each frame of image can reflect the basic distribution and basic tone of each frame of image color.
  • the image display data is 4K data
  • the 4K data can be used as 8 channels of VBO (full name V-by-One, A digital interface standard developed for image transmission is input to the algorithm processor 211a.
  • the algorithm processor 211a is further configured to send N first current control signals, M enable signals and image display data to the control processing module 211b.
  • the algorithm processor 211a can generate N first current control signals corresponding to each frame of the multi-frame display image in a variety of ways.
  • the algorithm processor 211a determines each After the gain value ⁇ of the frame image, the brightness of each primary color is calculated, and the current control signal of the corresponding primary color and the color mixing current control signal are generated based on the brightness through the second preset algorithm; in another alternative, the algorithm The processor 211a can pre-store the corresponding relationship between the current control signal and the brightness. After determining the gain value ⁇ of each frame of image, the algorithm processor 211a calculates the brightness of each primary color, and then queries the corresponding relationship according to the calculated brightness. Relationship, the current control signal corresponding to the brightness is obtained. For example, when the current control signal is a PWM signal, the corresponding relationship between the current control signal and the current can be characterized by the corresponding relationship between the PWM value and the brightness.
  • the control processing module 211b is configured to transmit the N first current control signals and M enable signals to the data selector 213. It is also possible to transmit M enable signals to the signal generator 212.
  • the control processing module 211b is also used to send image display data to the light modulation device 24, wherein each of the aforementioned current control signals is used to indicate the adjusted brightness of the corresponding laser light source, and the adjusted brightness is 1% of the brightness before adjustment. / ⁇ , the image display data is used to indicate the grayscale value of each frame of image after adjustment, and the adjusted grayscale value is ⁇ times the grayscale value before adjustment.
  • the light modulation device 24 is used to modulate the beam of the laser light source based on the image display data to generate an image beam, and project the image beam onto the projection screen to realize the display of each frame of image.
  • the laser projection device may also include a plurality of optical lenses located between the light modulation device 24 and the projection screen, and the plurality of optical lenses are used to transmit, reflect and/or refract the image beam. Then, project to the projection screen.
  • the display control module 21 can adjust the brightness of the laser light source in real time based on the gain value ⁇ of each frame of image, that is, the change of each frame of image, so as to achieve dynamic contrast.
  • the first switch transistor is a MOS tube, such as an NMOS tube
  • the on-off time of the light source switch circuit reaches ns (nanosecond) level
  • the on-off time of the laser series circuit reaches ⁇ s (microsecond) level
  • the laser series circuit can quickly and accurately respond to the changes in the brightness of each pixel of the image, and the brightness of the laser light source can be changed from Arbitrarily adjust the brightness from 0 to the rated current value.
  • This drive circuit is the basis for achieving high dynamic contrast, that is, the hardware supports the dynamic brightness adjustment of the laser projection device.
  • the image display data of laser projection equipment becomes larger and larger.
  • the image display data is 4K data, that is, data with a pixel resolution of 4096 ⁇ 2160.
  • the display control module 21 uses only one processing
  • the processor is likely to cause low processing efficiency of the processor. Therefore, an embodiment of the present application proposes a manner in which the master and slave processors co-process image display data to improve processing efficiency.
  • the control processing module 211b includes a master control processor X1 and a slave control processor X2.
  • the algorithm processor 211a is connected to the master control processor X1 and the slave control processor X2 respectively, and the master control processor X1 is also connected to The light source driving circuit 22 and the light modulation device 24 are connected, and the slave control processor X2 is also connected with the light modulation device 24.
  • the laser projection equipment can include a display board, a power supply board, and a laser board, an algorithm processor 211a, a master control processor X1, a slave control processor X2, a data selector 213, a signal generator 212, and the aforementioned digital-to-analog conversion
  • the devices 214 are all arranged on the display board, the light source driving circuit 22 is arranged on the power board, and the laser light source 23 is arranged on the laser board.
  • the algorithm processor 211a is configured to determine the gain value ⁇ of each frame of image, ⁇ 1 according to the grayscale value of each frame of image.
  • the algorithm processor 211a is also used to send N first current control signals and first sub-data to the master control processor X1, and send second sub-data to the slave control processor.
  • the first sub-data and the second sub-data constitute The image shows the data.
  • FIG. 27 assumes that the N first current control signals include: a red PWM signal R_PWM, a green PWM signal G_PWM, a blue PWM signal B_PWM, and a mixed color PWM signal Y_PWM.
  • the first sub-data and the second sub-data are both 60bit (bit) data
  • both the first sub-data and the second sub-data may be low-voltage differential signals (Low-Voltage Differential Signaling, LVDS), where the first sub-data is two-channel west (west) LVDS, and the second sub-data can be two-channel east (east) LVDS.
  • LVDS Low-Voltage Differential Signaling
  • Each current control signal is used to indicate the adjusted brightness
  • the adjusted brightness is 1/ ⁇ of the brightness before adjustment
  • the image display data is used to indicate the grayscale value of each frame of image after adjustment
  • the adjusted grayscale The value is ⁇ times the grayscale value before adjustment.
  • the main control processor X1 is configured to receive the N first current control signals, generate M enable signals, and transmit the received N first current control signals and M enable signals to the data selector, and The M enable signals can be transmitted to the signal generator, and the first sub-data can be sent to the optical modulation device.
  • FIG. 27 assumes that the M enable signals are red enable signal R_EN, green enable signal G_EN, and blue enable signal B_EN, respectively.
  • the signal output circuit of the processing module 211 shown in FIG. 5 may be integrated in the main control processor X1.
  • the slave control processor X2 is used to send the second sub-data to the light modulation device 24.
  • the light modulation device 24 is used to modulate the beam of the laser light source based on the first sub-data and the second sub-data to generate an image beam, and project the image beam onto the projection screen to display each frame of image.
  • the laser projection device further includes: a memory 26, a galvanometer drive circuit 27, a galvanometer 28 and a power supply module 25, wherein the memory 26 is connected to the algorithm processor 211a for storing images
  • the memory is a Double Data Rate (DDR) memory
  • the galvanometer drive circuit 27 and algorithm processing respectively
  • the galvanometer 211a and the galvanometer 28 are connected to drive the galvanometer 28 to vibrate under the control of the algorithm processor 211a.
  • the galvanometer 28 may be a 4-dimensional galvanometer, that is, it can vibrate in 4 directions.
  • the galvanometer drive circuit 27 and the galvanometer 28 can be set to superimpose images, increase the expressive power of details, and increase the resolution; the power module 25 is used to provide electrical energy for the electrical components, and it is used for each of the laser projection equipment.
  • the electrical components are connected separately, and FIG. 12 is only used for schematic illustration with the algorithm processor 211a, the master processor X1 and the slave processor X2 respectively connected to each other for illustration.
  • the laser light source 23 in the laser projection device may be the blue laser light source 130 in FIG. 1. Further, the laser projection device may further include: an optical machine 20, a projection lens 30, and the aforementioned projection light source 10 For other components except the blue laser light source 130, the function of each component can be referred to FIG. 1, which will not be repeated in the embodiment of the present application.

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Abstract

一种激光投影设备，包括依次连接的显示控制模块、光源驱动电路以及激光光源；显示控制模块，用于生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号，并在N个第一电流控制信号中选择有效的第二电流控制信号，将第二电流控制信号传输至光源驱动电路，N个第一电流控制信号包括与每一帧图像的M个基色一一对应的单色电流控制信号以及混色电流控制信号，N为大于2的整数，M为正整数；光源驱动电路，用于基于接收到的第二电流控制信号，控制激光光源发光；其中，至少两帧显示图像对应的第二电流控制信号的大小不同。

Description

激光投影设备
本申请要求于2019年6月20日提交中国专利局、申请号为201910539233.1，申请名称为“激光投影设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于投影显示领域，特别涉及一种激光投影设备。
背景技术
诸如超短焦激光电视等激光投影设备因其具有色彩纯度高、色域大和亮度高等优点，被广泛应用于显示领域。
目前的激光电视的光源系统通常包括激光光源、荧光轮和滤色轮，该激光光源通常为用于出射蓝色激光的蓝色激光器。该蓝色激光时序性地照射至荧光轮的三个不同的区域上，从而产生三色光，该三种颜色的光依次通过滤色轮进行过滤处理，得到纯度更高的三色光。
但是目前的激光投影设备的激光光源通常只能提供固定亮度的激光，因此，最终激光投影设备的显示效果较差。
发明内容
本申请实施例提供了一种激光投影设备，包括：
依次连接的显示控制模块，光源驱动电路，以及激光光源；
所述显示控制模块，用于生成多帧显示图像中的每一帧图像对应的N个第 一电流控制信号，并在所述N个第一电流控制信号中选择有效的第二电流控制信号，将所述第二电流控制信号传输至所述光源驱动电路，所述N个第一电流控制信号包括与所述每一帧图像的M个基色一一对应的单色电流控制信号，以及混色电流控制信号，N为大于2的整数，M为正整数；
所述光源驱动电路，用于基于接收到的所述第二电流控制信号，控制所述激光光源发光；
其中，至少两帧所述显示图像对应的第二电流控制信号的大小不同。
附图说明
为了更清楚地说明本申请申请的实施例，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一些实施例提供的实施环境的示意图；
图2是本申请一些实施例提供的一种投影光源的结构示意图；
图3是本申请一些实施例提供的一种激光投影设备的结构示意图；
图4是本申请一些实施例提供的一种显示控制模块的结构示意图；
图5是本申请一些实施例提供的一种显示控制模块的结构示意图；
图6是本申请一些实施例提供的一种信号生成器的结构示意图；
图7是本申请一些实施例提供的一种信号输出电路的结构示意图；
图8是本申请一些实施例提供的一种缓冲电路的结构示意图；
图9是本申请一些实施例提供的一种信号选择器的结构示意图；
图10是本申请一些实施例提供的一种控制芯片的结构示意图；
图11是本申请一些实施例提供的一种光源驱动电路的结构示意图；
图12是本申请一些实施例提供的一种bank激光器的结构示意图；
图13是本申请一些实施例提供的一种处理模块的内部结构示意图；
图14是本申请一些实施例提供的一种光源驱动电路的结构示意图；
图15是本申请一些实施例提供的一种降压电路的结构示意图；
图16是本申请一些实施例提供的一种MCL的结构示意图；
图17是本申请一些实施例提供的一种激光器串接电路的结构示意图；
图18是本申请一些实施例提供的一种MCL的等效电路图；
图19是本申请一些实施例提供的一种控制芯片的结构示意图；
图20是本申请一些实施例提供的一种光源驱动电路的结构示意图；
图21是本申请一些实施例提供的一种升降压电路的结构示意图；
图22是本申请一些实施例提供的一种显示控制模块的结构示意图；
图23是本申请一些实施例提供的一种输入信号灰阶值、屏幕亮度的关系曲线图；
图24是本申请一些实施例提供的一种输入信号灰阶值、屏幕亮度的关系曲线图；
图25是本申请一些实施例提供的一种输入信号灰阶值、屏幕亮度的关系曲线图；
图26是本申请一些实施例提供的一种激光投影设备的结构示意图；
图27是本申请一些实施例提供的一种激光投影设备的结构示意图；
图28是本申请一些实施例提供的一种激光投影设备的结构示意图。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述，显然，所描述的实施例仅仅是本申请一部份实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
请参考图1，其示出了本申请一些实施例所涉及的实施环境的示意图。该实施环境可以包括：投影光源10、光机20和投影镜头30，该投影光源10、光机20和投影镜头30沿光束传输方向依次排列。其中，投影光源10用于出射光束，光机20用于在受到投影光源10出射的光束的照射时，对光束进行调制生成影像光束，投影镜头30用于将影像光束投射至投影屏幕40上。
示例的，上述投影光源10、光机20和投影镜头30可以应用于激光电视等激光投影设备中，该投影光源可以包括：至少一个激光器，投影光源用于发射至少一种颜色的激光。示例的，该投影光源可以是单色投影光源(即包括一个激光器且该激光器发射一种颜色的激光)，也可以是双色投影光源(即包括多个激光器且激光器共发射两种颜色的激光)。
示例的，如图2所示，该投影光源10至少包括荧光轮110、滤色轮120、蓝色激光光源130、合光部件140、光束整形部件150和光收集部件160。该蓝色激光光源130、光束整形部件150、合光部件140、荧光轮110、滤色轮120和 光收集部件160沿蓝色激光的传输方向依次排列。其中，蓝色激光光源130用于发出蓝色激光。光束整形部件150用于将蓝色激光光源130发出的蓝色激光进行径缩处理得到径缩后的准直的蓝色激光，并将该准直的蓝色激光传输至合光部件140。合光部件140用于将接收的蓝色激光传输至荧光轮110，合光部件140还用于将荧光轮110透射的蓝色激光传输至滤色轮120，该蓝色激光照射到透射区后经透射区，合光部件140还用于将荧光轮110发出的荧光传输至滤色轮120，荧光由蓝色激光照射荧光区所产生。滤色轮120用于在转动时，时序性地输出红光、蓝光和绿光，该红光和绿光由滤色轮120对荧光进行过滤处理得到，该蓝光由滤色轮120透射蓝色激光得到。光收集部件160用于对红光、蓝光和绿光进行匀光处理。
该投影光源的出光过程为：蓝色激光光源130发出的蓝色激光，由光束整形装置150对蓝色激光束整形后，出射至合光部件140，再透射至荧光轮110；荧光轮110时序性地转动，当蓝色激光照射到荧光轮110上的透射区时，蓝色激光从荧光轮110透射，经过蓝色激光的中继回路光路(指图2中蓝色激光从荧光轮110传输至合光部件140的光路回路)后再次透过合光部件140，并经过滤色轮120后进入光收集部件160；当蓝色激光照射到荧光轮110上的荧光区时，激发荧光区上的荧光粉发出至少一种颜色的荧光(例如图2中的黄色荧光和/或绿色荧光)，激发出的荧光反向传输，由合光部件140反射至滤色轮120，然后进入光收集部件160。上述三种颜色的光(简称三色光)经过光收集部件160后，通过光机20的调制生成影像光束，该影像光束传输至投影镜头30，最终实现三色光的图像输出。
但是目前的激光投影设备的激光光源通常只能提供固定亮度的激光，因此， 最终激光投影设备的显示效果较差。
图3为本申请一些实施例提供一种激光投影设备，包括：
依次连接的显示控制模块21，光源驱动电路22，以及激光光源23。示例的，该激光光源23可以为单色激光光源，例如红色激光光源或如图2所示的蓝色激光光源130。
显示控制模块21，用于生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号，并在N个第一电流控制信号中选择有效的第二电流控制信号，将第二电流控制信号传输至光源驱动电路22，N个第一电流控制信号包括与每一帧图像的M个基色一一对应的单色电流控制信号，以及混色电流控制信号，N为大于2的整数，M为正整数，每个单色电流控制信号用于控制对应基色显示的阶段的电流，混色电流控制信号用于控制至少两个基色(在本申请实施例中通常是控制两个基色)同时显示(至少两个基色同时显示会产生混色)的阶段的电流。
示例的，假设N＝4，M＝3，4个第一电流控制信号分别为红色电流控制信号、绿色电流控制信号，蓝色电流控制信号和混色电流控制信号。红色电流控制信号用于控制红色显示的阶段的电流，绿色电流控制信号用于控制绿色显示的阶段的电流，蓝色电流控制信号用于控制蓝色显示的阶段的电流，混色电流控制信号用于控制红色、绿色和蓝色中至少两个基色同时显示的阶段的电流。
光源驱动电路22，用于基于接收到的第二电流控制信号，控制激光光源23发光。
其中，至少两帧显示图像对应的第二电流控制信号的大小不同。
综上所述，本申请实施例提供的激光投影设备，由于显示控制模块能够生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号，并在N个第一电流控制信号中选择有效的第二电流控制信号，将第二电流控制信号传输至光源驱动电路，以使光源驱动电路控制激光光源发光，由于至少两帧显示图像对应的第二电流控制信号的大小不同，其中，上述至少两帧显示图像可以为在显示时序上相邻的两帧图像，也可以是中间间隔多帧的显示图像，由于在显示至少两帧显示图像时对应的激光器点亮电流不同，从而实现激光光源的动态调光，因此，该激光投影设备可以支持可变亮度的激光光源，有效提高激光投影设备的显示效果。
在一些实施例中，如图4所示，显示控制模块21，包括：处理模块211、信号生成器212和数据选择器213，处理模块211与数据选择器213连接。值得说明的是，该处理模块211通常也可以控制信号生成器212的信号生成，因此也可以与该信号生成器212连接。
处理模块211，用于生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号和M个使能信号，并将N个第一电流控制信号和M个使能信号传输至数据选择器213。示例的，图4中假设N＝4，M＝3，单色电流控制信号和混色电流控制信号均为脉冲宽度调制(PWM，Pulse Width Modulation)信号。4个第一电流控制信号分别为红色PWM信号R_PWM、绿色PWM信号G_PWM、蓝色PWM信号B_PWM和混色PWM信号Y_PWM。M个使能信号分别为红色使能信号R_EN、绿色使能信号G_EN和蓝色使能信号B_EN。例如，混色PWM信号Y_PWM的幅值电压是3.3V，频率是18.3kHZ，占空比为50％。
信号生成器212，用于生成占空比控制信号LD_duty，并输出至光源驱动电 路22。该占空比控制信号LD_duty用于控制激光光源的开启与关闭。示例的，占空比控制信号LD_duty为高电平时，激光光源开启；占空比控制信号LD_duty为低电平时，激光光源关闭。当激光光源为单色光源时，由于该激光投影设备在进行图像显示的过程中，需要保证该单色激光光源常开，因此，在激光投影设备工作过程中，该占空比控制信号LD_duty通常为持续的高电平信号。
数据选择器213，用于基于M个使能信号，在N个第一电流控制信号中选择第二电流控制信号T_PWM，并将第二电流控制信号T_PWM传输至光源驱动电路22。该第二电流控制信号T_PWM与M个使能信号中处于有效电位的信号匹配。
光源驱动电路22，用于基于接收到的第二电流控制信号T_PWM，调节激光光源23的电流，并基于占空比控制信号LD_duty控制激光光源23的开启与关闭。
在本申请实施例中，信号生成器212可以以多种方式生成占空比控制信号LD_duty。在一种可选的实现方式中，信号生成器212直接生成一个持续高电平的占空比控制信号LD_duty；在另一种可选的实现方式中，信号生成器212基于M个使能信号，合成占空比控制信号LD_duty。则如图5所示，处理模块211还与信号生成器212连接。处理模块211，还用于将M个使能信号传输至信号生成器212；信号生成器212，用于基于M个使能信号，合成占空比控制信号。
可选的，当占空比控制信号LD_duty是基于M个使能信号合成时，则如图6所示，当M＝3时，该信号生成器212包括：第一或门N99和第二或门N100。或门(AND gate)又称“或电路”、逻辑“和”电路。或门有多个输入端，一个输出端。只要输入存在一个高电平(逻辑1)时，输出即为高电平，否则输出为 低电平(逻辑0)。
其中，第一或门N99的两个输入端用于分别接收3个使能信号中的两个使能信号，第二或门N100的一个输入端与第一或门N99的输出端连接，另一个输入端用于接收3个使能信号中除两个使能信号之外的其他使能信号，第二或门N100的输出端用于输出占空比控制信号LD_duty。图6以第一或门N99的两个输入端分别接收红色使能信号R_EN和绿色使能信号G_EN，第二或门N100的另一个输入端接收蓝色使能信号B_EN为例进行说明，但并不对红色使能信号R_EN、绿色使能信号G_EN和蓝色使能信号B_EN的输入顺序进行限定。
示例的，图6中，当红色使能信号R_EN、绿色使能信号G_EN和蓝色使能信号B_EN的电位分别为1、0和0时，占空比控制信号LD_duty的电位为1，当红色使能信号R_EN、绿色使能信号G_EN和蓝色使能信号B_EN的电位分别为1、1和0时，占空比控制信号LD_duty的电位为1。
为了便于说明，后续实施例以占空比控制信号LD_duty由信号生成器基于M个使能信号合成为例进行说明，但是本申请实施例并不对占空比控制信号LD_duty的生成方式进行限定。
可选的，处理模块211可以包括信号输出电路。该信号输出电路用于输出前述N个第一电流控制信号和M个使能信号。如图7所示，图7为该信号输出电路的结构示意图，该信号输出电路包括：依次连接的控制芯片2111和缓冲电路2112。缓冲电路2112与控制芯片2111、信号生成器212和数据选择器213连接；
控制芯片2111，用于生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号和M个使能信号，并将N个第一电流控制信号和M个使能信号传 输至缓冲电路2112；
缓冲电路(Snubber Circuit)2112，用于对接收到的每个第一电流控制信号和每个使能信号分别进行缓冲处理，将缓冲处理后的每个第一电流控制信号输出至数据选择器213，并将缓冲处理后的每个使能信号分别输出数据选择器213和信号生成器212。缓冲电路又称吸收电路，它是一种保护电路。本申请实施例提供的缓冲电路可以为三态缓冲器(Three‐state buffer)，又称为三态门或三态驱动器，三态缓冲器具有三态输出端和使能输入端，三态输出端受到使能输入端的控制，当使能输入端的电位为有效电位时，三态输出端用于正常逻辑状态输出(逻辑0或逻辑1)，当使能输入端的电位为无效电位时，三态输出端的输出处于高阻状态，即等效于三态输出端与其所连的电路断开。
示例的，假设4个第一电流控制信号分别为红色PWM信号R_PWM、绿色PWM信号G_PWM、蓝色PWM信号B_PWM和混色PWM信号Y_PWM。M个使能信号分别为红色使能信号R_EN、绿色使能信号G_EN和蓝色使能信号B_EN。则如图8所示，该缓冲电路2112可以包括缓冲(Buffer)芯片U1。控制芯片2111可以包括用于输出红色PWM信号R_PWM的GPIO‐04引脚、用于输出绿色PWM信号G_PWM的GPIO‐05引脚、用于输出蓝色PWM信号B_PWM的GPIO‐06引脚、用于输出混色PWM信号Y_PWM的GPIO‐10引脚、用于输出红色使能信号R_EN的GPIO‐24引脚、用于输出绿色使能信号G_EN的GPIO‐25引脚和用于输出蓝色使能信号B_EN的GPIO‐26引脚。
Buffer芯片U1可以包括A1至A7引脚共七个输入引脚，以及Y1至Y7引脚共7个输出引脚。该Buffer芯片U1还包括
Figure PCTCN2020089089-appb-000001
引脚、GND引脚、VCC引脚和
Figure PCTCN2020089089-appb-000002
引脚。
其中，A1引脚分别与GPIO‐04引脚和电阻R4的一端连接，用于接收该控制芯片2111提供的红色PWM信号R_PWM。A2引脚分别与GPIO‐05引脚和电阻R5的一端连接，用于接收该控制芯片2111提供的绿色PWM信号G_PWM。A3引脚分别与GPIO‐06引脚和电阻R6的一端连接，用于接收该控制芯片2111提供的蓝色PWM信号B_PWM。A4引脚分别与GPIO‐10引脚和电阻R10的一端连接，用于接收该控制芯片2111提供的混色PWM信号Y_PWM。
A5引脚分别与GPIO‐24引脚和电阻R9的一端连接，用于接收该控制芯片2111提供的使能信号R_EN。A6引脚分别与GPIO‐25引脚和电阻R8的一端连接，用于接收该控制芯片2111提供的使能信号G_EN。A7引脚分别与GPIO‐26引脚和电阻R7的一端连接，用于接收该控制芯片2111提供的使能信号B_EN。
电阻R4的另一端、电阻R5的另一端、电阻R6的另一端、电阻R10的另一端、电阻R7的另一端、电阻R8的另一端、电阻R9的另一端、
Figure PCTCN2020089089-appb-000003
引脚以及
Figure PCTCN2020089089-appb-000004
引脚均接地。在一种可选方式中，如图8所示，VCC引脚分别与电感L1的一端和电容C8的一端连接，且电感L1另一端与电源端VCC6连接，电容C8的另一端接地。电感L1的一端和电容C8组成滤波电路，用于滤除电路中的高频成分和杂波。在另一种可选方式中，当电源端VCC6的信号质量较好时，VCC引脚也可以与电源端VCC6直接连接。
Y1引脚用于提供经过缓冲处理后的红色PWM信号R_PWM。Y2引脚用于提供经过缓冲处理后的绿色PWM信号G_PWM。Y3引脚用于提供经过缓冲处理后的蓝色PWM信号B_PWM。Y4引脚用于提供经过缓冲处理后的混色PWM信号Y_PWM。其中，Y1引脚至Y4引脚均可以直接或间接地与数据选择器13连接。
Y5引脚用于提供经过缓冲处理后的使能信号R_EN。Y6引脚用于提供经过 缓冲处理后的使能信号G_EN。Y7引脚用于提供经过缓冲处理后的使能信号B_EN。Y5引脚至Y7引脚可以直接或间接地与数据选择器213，并且也可以直接或间接地与信号生成器212连接。
其中，电源端VCC6提供的电压可以为3V。电阻R4至电阻R10的阻值均可以为10kΩ。电容C8的参数可以为100n/16v。电感L1的型号可以为BLM15AG121SN1D。
由于控制芯片2111传输的PWM信号和使能信号通过缓冲电路传输至后续电路，因此，增强了传输至后续电路的PWM信号和使能信号的驱动能力，保障了后续电路的稳定高效运行。
可选的，该控制芯片2111可以为数字光处理(DLP，Digital Light Processing)芯片，该DLP芯片可以是DLPC6421芯片，也可以是DDP4422芯片。
可选的，当N＝4，M＝3时，该数据选择器213可以为8选1选择器，假设4个第一电流控制信号分别为红色PWM信号R_PWM、绿色PWM信号G_PWM、蓝色PWM信号B_PWM和混色PWM信号Y_PWM。M个使能信号分别为红色使能信号R_EN、绿色使能信号G_EN和蓝色使能信号B_EN。如图9所示，数据选择器213具有用于接收4个第一电流控制信号的数据输入端，分别为用于接收红色PWM信号R_PWM的引脚S5(例如与图8所示的缓冲电路2112中的Y1引脚连接)、用于接收绿色PWM信号G_PWM的引脚S3(例如与图8所示的缓冲电路2112中的Y2引脚连接)、用于接收蓝色PWM信号B_PWM的引脚S1(例如与图8所示的缓冲电路2112中的Y3引脚连接)和用于接收混色PWM信号Y_PWM的引脚S7(例如与图8所示的缓冲电路2112中的Y4引脚连接)；数据选择器213还具有用于接收3个使能信号的逻辑引脚，分别为用于接收红色使 能信号R_EN的引脚A2(例如与图8所示的缓冲电路2112中的Y5引脚连接)、用于接收绿色使能信号G_EN的引脚A1(例如与图8所示的缓冲电路2112中的Y6引脚连接)和用于接收蓝色使能信号B_EN的引脚A0(例如与图8所示的缓冲电路2112中的Y7引脚连接)；数据选择器213还具有用于输出第二电流控制信号T_PWM的输出引脚D。
数据选择器213用于在对应某一基色的使能信号为有效电位，且对应其他基色的使能信号不为有效电位时，将对应某一基色的第一电流控制信号(即该第一电流控制信号为有效的控制信号)作为第二电流控制信号从输出引脚输出；在对应至少两个基色的使能信号为有效电位时，将混色电流控制信号作为第二电流控制信号从输出引脚D输出。
示例的，假设有效电位为1，非有效电位为0，则输出引脚输出的第二电流控制信号T_PWM满足表1。请参考表1，使能信号R_EN、G_EN和B_EN的电位分别为0，1，0，则绿色使能信号G_EN为有效电位，红色使能信号R_EN和蓝绿色使能信号B_EN不为有效电位，则第二电流控制信号T_PWM为G_PWM；使能信号R_EN、G_EN和B_EN的电位分别为1，1，0，则红色使能信号R_EN和绿色使能信号G_EN为有效电位，蓝色使能信号B_EN不为有效电位，则第二电流控制信号T_PWM为Y_PWM。需要说明的是，该表1的内容在实际使用时可以简化表示，例如使能信号R_EN、G_EN和B_EN的电位分别为1，0，0，表示为EN_R：EN_G：EN_B＝1：0：0。
表1
Figure PCTCN2020089089-appb-000005
Figure PCTCN2020089089-appb-000006
需要说明的是，根据实际使用情况，该控制芯片2111还包括其他引脚，如图10所示，该控制芯片还包括电源引脚VCC，第一接地引脚GND，第二接地引脚VSS，使能引脚EN，电源引脚VCC与第一电源端VCC1连接，使能引脚EN与第二电源端VCC2连接，第一接地引脚GND和第二接地引脚VSS均接地。
在一种可选方式中，如图10所示，显示控制模块21还包括第一电阻R1445以及第一电容C1372，第一电阻R1445串联在电源引脚VCC和第一电源端VCC1之间，第一电容C1372一端与第一电阻R1445连接电源引脚VCC的一端连接，另一端接地，第一电阻R1445以及第一电容C1372组成滤波电路，用于滤除电路中的高频成分和杂波。在另一种可选方式中，当第一电源端VCC1的信号质量较好时，VCC引脚也可以与第一电源端VCC1直接连接。
可选的，显示控制模块21还包括第二电阻R1287，该第二电阻R1287串联在使能引脚EN与第二电源端VCC2之间；可选的，显示控制模块21还包括第三电阻R1325、第四电阻R1427、第五电阻R1272和第二电容C1430，其中，第三 电阻R1325、第四电阻R1427串联，且串联的第三电阻R1325和第四电阻R1427一端与输出引脚D连接，另一端用于输出调制后的T_PWM，例如该另一端与数据选择器213连接，第五电阻R1272和第二电容C1430并联，并联的第五电阻R1272和第二电容C1430一端与第三电阻R1325和第四电阻R1427之间的节点连接，另一端接地。其中，第五电阻R1272是下拉电阻，用于在输出端D未输出信号时，将输出端D的电位下拉为低电位，从而保证输出端D未输出信号时，混色PWM信号T_PWM是低电平；第二电容C1430是滤波电容，用于滤除混色PWM信号T_PWM的尖刺和纹波；第一电阻R1445、第三电阻R1325和第四电阻R1427通常为0欧电阻，第一电阻R1445、第三电阻R1325和第四电阻R1427为可以选择设置的电阻，当数据选择器213的一些节点有测试需求时，将第一电阻R1445、第三电阻R1325和第四电阻R1427串接在对应位置，可以方便测试。
需要说明的是，图10中数据选择器213还包括其他引脚，例如该数据选择器213共16个引脚，除前述引脚之外的引脚均为空闲引脚，或者用于其他功能，本申请实施例对此不做限定。其中，电阻R1287的阻值可以为3.3kW，电阻R1272的阻值可以为10kW，C1372的电容容量为100nF(纳法)，工作电压均为16V，第二电源端VCC2的电压为5V。
可选的，如图11所示，光源驱动电路22包括：电压输出电路221、驱动芯片222和外围电路223；
电压输出电路221，用于为外围电路223提供激光光源23的额定电压；
驱动芯片222，用于接收第二电流控制信号，并向外围电路223提供第二电流控制信号对应的电流，以及，接收占空比控制信号，并基于占空比控制信号控 制外围电路223的导通和断开；
外围电路223分别与驱动芯片222和激光光源23连接，用于在自身导通时，在额定电压下向激光光源23提供第二电流控制信号对应的电流。
前述光源驱动电路22适用于各种单色的激光光源，对于不同的激光光源，其驱动芯片、电压输出电路和外围电路的结构不同，目前电压输出电路按工作模式分为升压和降压两种，升压电路是把输入电压Vi升高到激光光源的额定电压Vo的电路，Vi＜Vo，降压电路是把输入电压Vi降低到激光光源的额定电压Vo的电路，Vi＞Vo。本申请实施例以以下两种分别涉及升压电路和降压电路的激光光源为例进行说明。
在一种可选实现方式中，激光光源23为激光器组件，也称bank光源(bank是一种封装方式)，电压输出电路为降压电路。bank光源可以包括一个或多个bank激光器，当bank光源包括多个bank激光器时，该多个bank激光器串联，当bank光源包括多个bank激光器时，该多个bank激光器串联。如图12所示，每个bank激光器可以包括多个串联的晶体管外壳(TO，Transistor Outline)231。
示例的，图12中，一个bank激光器可以封装8个TO，为了达到不同的投影尺寸所需要的亮度，需要的bank激光器数量不同，比如1个，2个，或者更多。
相应的，在该种可选的实现方式中，驱动芯片222可以包括1个或多个处理模块，每个处理模块可以用于控制1个激光器。当驱动芯片222包括多个处理模块时，各个处理模块的结构相同，示例的，每个处理模块的结构可以如图13所示，图13是本申请实施例提供的一种处理模块的内部结构示意图。该处理模块可以包括：除法器x1、开关频率方波发生器H、电压过滤器M、比较器lm1、 比较器lm2、比较器lm3、缓冲器m1、电阻r21和电容c21，该处理模块具有第一引脚ADIM、第二引脚RT、第三引脚DRV、第四引脚PWM和第五引脚ISEN。图13假设该处理模块具有用于接收第二电流控制信号T_PWM的第一引脚ADIM，用于接收占空比控制信号LD_Duty的第二引脚RT。该处理模块还具有第三引脚DRV，第四引脚PWM和第五引脚ISEN。
处理模块的第一引脚ADIM可以与除法器x1的一端连接。该除法器x1用于将第一引脚ADIM传输的信号(例如，该第一引脚ADIM与图9所示的数据选择器的输出引脚D连接，该第一引脚ADIM即前述第二电流控制信号T_PWM)和10相除。该除法器x1的另一端与电压过滤器M的一端连接，电压过滤器M连接能够根据除法器x1输出的信号的电压，确定正极输入信号ADJ。该电压过滤器M用于限制正极输入信号ADJ的电压，使该电压小于或等于预设的上限电压。当除法器x1输出的信号的电压小于或等于电压过滤器M中设置的上限电压，例如300mV(毫伏)时，电压过滤器M输出的正极输入信号ADJ为除法器x1输出的信号；当除法器x1输出的信号的电压大于该上限电压时，电压过滤器M输出的正极输入信号ADJ的电压为上限电压。这样可以保证正极输入信号ADJ的电压小于或等于上限电压，避免正极输入信号ADJ的电压过高引起后续电路(如比较器lm1)的损伤。
比较器lm1和比较器lm3中的每个比较器均具有正极输入端和负极输入端共2个输入端，以及1个输出端。比较器lm2具有正极输入端、负极输入端和使能输入端共3个输入端，以及1个输出端。
比较器lm1的正极输入端与电压过滤器M的另一端连接。比较器lm1的负极输入端分别与电阻R932的一端和电容c21的一端连接，电阻R932的另一端 与第五引脚ISEN连接。比较器lm1的输出端可以电容c21的另一端连接。比较器lm1用于比较其正极输入端和负极输入端的电压大小。当比较器lm1的正极输入端的电压大于负极输入端的电压(即第五引脚ISEN的驱动电流与电阻R932的乘积)时，比较器lm1的输出的逻辑值为1。当比较器lm1的正极输入端的电压小于负极输入端的电压时，比较器lm1的输出的逻辑值为0。
比较器lm2的正极输入端与比较器lm1的输出端连接。比较器lm2的负极输入端与开关频率方波发生器H的一端连接，开关频率方波发生器H的另一端与第二引脚RT连接。比较器lm2的使能输入端与比较器lm3的输出端连接。比较器lm2的输出端与缓冲器m1的一端连接，缓冲器m1的另一端与第三引脚DRV连接。开关频率方波发生器H用于生成指定开关频率的方波。该方波经过比较器lm1与比较器lm2传输至第三引脚DRV，由第三引脚DRV输出。其中，由第三引脚DRV输出的方波也称为驱动(driver，DRV)方波，第三引脚DRV输出的DRV方波相对于开关频率方波发生器H生成的方波的开关频率不变。该开关频率方波发生器H的开关频率可以通过其外连电阻的阻值相关。示例的，图14中，该开关频率方波发生器H与电阻R904连接，则开关频率方波发生器H的开关频率可以基于该电阻R904的阻值计算得到。
该比较器lm2用于在其使能输入端为有效电平时，比较其正极输入端与负极输入端的电压大小。当比较器lm2的正极输入端的电压大于负极输入端的电压时，比较器lm2输出的逻辑值为1；当比较器lm2的正极输入端的电压小于负极输入端的电压时，比较器lm2输出的逻辑值为0。
比较器lm3的正极输入端与第四引脚PWM连接，比较器lm3的负极输入端与直流电源端连接，例如该直流电源端的电压可以为1V。该比较器lm3用于 其正极输入端与负极输入端的电压大小。当比较器lm3的正极输入端的电压大于负极输入端的电压时，比较器lm3输出的逻辑值为1；当比较器lm3的正极输入端的电压小于负极输入端的电压时，比较器lm3输出的逻辑值为0。
需要说明的是，上述光源驱动电路22中，该处理模块所连接的各个电子元器件均可以为外围电路223中的元器件。
进一步的，当该驱动芯片222用于控制多个激光器时，每个处理模块可以如图13所示，包括：第一引脚ADIM、第二引脚RT、第三引脚DRV，第四引脚PWM和第五引脚ISEN。其中，多个处理模块可以共用第一引脚ADIM和第二引脚RT。请参考图14，图14假设该驱动芯片222用于控制两个激光器，分别为第一激光器和第二激光器，则驱动芯片222包括两个处理模块，分别为与第一激光器对应的第一处理模块和与第二激光器对应的第二处理模块。第一激光器和第二激光器可以有多种实现方式，例如，在一种实现方式中，第一激光器和第二激光器可以分别为一个bank激光器，在另一种实现方式中，第一激光器和第二激光器中的一个是一个bank激光器，另一个是两个串联的bank激光器。
该两个处理模块共用第一引脚ADIM和第二引脚RT，两个处理模块中的第一处理模块具有第三引脚DRV1，第四引脚PWM1和第五引脚ISEN1；第二处理模块具有第三引脚DRV2，第四引脚PWM2和第五引脚ISEN2。进一步的，该驱动芯片222还包括电源引脚VCC、第六引脚BLON和第七引脚VREF和接地引脚GND，电源引脚VCC用于为驱动芯片222供电，通常供电电压为12V；该第六引脚BLON用于控制驱动芯片的开启和关闭；第七引脚VREF用于提供驱动芯片222内部产生的参考电压，该参考电压通常为6V；该接地引脚GND接地。外围电路可以包括与第一处理模块对应的正极输出端口LD1+和负极输出端口LD1‐，以及 与第二处理模块对应的正极输出端口LD2+和负极输出端口LD2‐。
其中，驱动芯片222的第一引脚ADIM可以通过分压电阻与数据选择器213连接，例如可以与图9或图10所示的数据选择器213的输出引脚D连接，用于接收该数据选择器213提供的第二电流控制信号T_PWM。
示例地，如图14所示，驱动芯片222的第一引脚ADIM可以分别与电阻R987的一端和电阻R986的一端连接，该电阻R987的另一端接地，且电容C925与电阻R987并联，电阻R986的另一端与电阻R974的一端连接，该电阻R974的另一端与数据选择器213(如输出引脚D)连接，用于接收该数据选择器213提供的第二电流控制信号T_PWM。该电阻R974的另一端还与电阻R961的一端连接，电阻R961的另一端接地。其中，R961是下拉电阻，电阻R986、R974和R987为分压电阻。电容C925是滤波电容，用于进行高频滤波，阻隔电路中的高频杂波。
每个处理模块的第五引脚ISEN可以与采样电阻连接。示例地，第一处理模块的第五引脚ISEN1可以通过电阻R919与第一采样电阻(图14未示出)的一端连接，该第一采样电阻的一端还与负极输出端口LD1‐连接，且该第一处理模块的第五引脚ISEN1可以通过电容C918与第一采样电阻的另一端连接，该第一采样电阻的另一端接地。其中，第一采样电阻可以包括一个或多个电阻，当其包括多个电阻时，该多个电阻并联，通过将多个电阻并联可以实现所需的电阻值，从而达到光源驱动电路的电流调节需求，保证光源驱动电路的电流的准确调节，例如第一采样电阻可以包括并联的电阻R977、电阻R978、电阻R927和电阻R979。该第一处理模块可以通过第一采样电阻实现对对应激光器的驱动电流的检测。
示例地，第二处理模块的第五引脚ISEN2可以通过电阻R926与第二采样电 阻(图14未示出)的一端连接，该第二采样电阻的一端还与负极输出端口LD2‐连接，且该第二处理模块的第五引脚ISEN2可以通过电容C917与第二采样电阻的另一端连接，该第二采样电阻的另一端接地。其中，第二采样电阻可以包括一个或多个电阻，当其包括多个电阻时，该多个电阻并联，通过将多个电阻并联可以实现所需的电阻值，从而达到光源驱动电路的电流调节需求，保证光源驱动电路的电流的准确调节，例如第二采样电阻可以包括并联的电阻R925、电阻R976、电阻R975和电阻R920。该第二处理模块可以通过第二采样电阻实现对对应激光器的驱动电流的检测。
第一处理模块的第三引脚DRV1可以与开关晶体管V827连接。示例地，第一处理模块的第三引脚DRV1可以与开关晶体管V827的栅极连接。开关晶体管V827的源极分别与第一采样电阻的一端和变压器L810的一端连接，该变压器L810的另一端与负极输出端口LD1‐连接。开关晶体管V827的漏极与电源端VDD1连接。第一处理模块的第三引脚DRV1输出的信号可以控制开关晶体管V827的开关状态，从而使得该开关晶体管V827在导通状态下，连通电源端VDD1与变压器L810的一端，从而通过变压器L810改变负极输出端口LD1‐的输出电压，变压器L810的另一端不与其他端口连接。其中，开关晶体管可以是金属‐氧化物半导体(MOS，Metal Oxide Semiconductor)场效应晶体管。
示例的，第一处理模块的第三引脚DRV1可以分别与二极管VD901的一端和电阻R922的一端连接，二极管VD901的另一端和电阻R923的一端连接，电阻R922的另一端和电阻R923的另一端均与开关晶体管V827的栅极连接，且电阻R922的另一端和电阻R923的另一端还均通过电阻R932与第一采样电阻的一端连接。开关晶体管V827的漏极可以通过两个并联的二极管VD908与电源端 VDD1连接。开关晶体管V827的源极可以通过电容C923与变压器L810连接。第一处理模块对应的正极输出端口LD1+和负极输出端口LD1‐之间还串联有电容C16。该电容C16为降压电容，在电源端VDD1开启时，电容C16持续充电，在电源端VDD1关闭时，电容C16持续放电。该电容C16可以为一个或多个电容，当其包括多个电容时，该多个电容并联，通过将多个电容并联可以实现所需的电容值，从而达到光源驱动电路的电流调节需求，保证光源驱动电路的电流的准确调节。示例的，电容C16可以为4个并联的电容。
第二处理模块的第三引脚DRV2可以与开关晶体管V937连接。示例地，第二处理模块的第二输出引脚DRV2可以与开关晶体管V937的栅极连接。开关晶体管V937的源极分别与第二采样电阻的一端和变压器L812的一端连接，该变压器L812的另一端与负极输出端口LD2‐连接。开关晶体管V937的漏极与电源端VDD2连接。第二处理模块的第三引脚DRV1输出的信号可以控制开关晶体管V937的开关状态，从而使得该开关晶体管V937在导通状态下，连通电源端VDD2与变压器L812的一端，从而通过变压器L812改变负极输出端口LD2‐的输出电压。其中，开关晶体管可以是MOS场效应晶体管。
示例的，第二处理模块的第三引脚DRV2可以分别与二极管VD902的一端和电阻R921的一端连接，二极管VD902的另一端和电阻R924的一端连接，电阻R924的另一端和电阻R921的另一端均与开关晶体管V937的栅极连接，且电阻R921的另一端和电阻R924的另一端还均通过电阻R931与第二采样电阻的一端连接。开关晶体管V937的漏极可以通过两个并联的二极管VD909与电源端VDD2连接。开关晶体管V937的源极可以通过电容C924与变压器L812连接。第二处理模块对应的正极输出端口LD2+和负极输出端口LD2‐之间还串联有电阻 C17。该电容C17为降压电容，在电源端VDD2开启时，电容C17持续充电，在电源端VDD2关闭时，电容C17持续放电。该电阻C17可以为一个或多个电阻，当其包括多个电容时，该多个电容并联，通过将多个电容并联可以实现所需的电容值，从而达到光源驱动电路的电流调节需求，保证光源驱动电路的电流的准确调节。示例的，电容C17可以为4个并联的电阻。
第一处理模块的第四引脚PWM1分别与电阻R908的一端和电阻R959的一端连接，电阻R908的另一端分别与电阻R980的一端和开关晶体管V936的源极连接；第二处理模块的第四引脚PWM2分别与电阻R937的一端和电阻R959的另一端连接，电容C920与电阻R907并联，并联的电容C920与电阻R907一端与电阻R908的一端连接，另一端与电阻R937的另一端连接，电阻R980的另一端与第七引脚VREF连接，用于接收基准电压；开关晶体管V936的栅极通过电阻R981与第一引脚ADIM连接，电阻R982一端与开关晶体管V936的栅极连接，另一端接地。该第七引脚VREF与电容C915的一端连接，该电容C915的另一端接地。其中，电阻R907和电阻R937为下拉电阻，用于在第一引脚ADIM无信号时，拉低第四引脚PWM1和PWM2的电平，保证在第一引脚ADIM无信号时，第四引脚PWM1和PWM2的第二电流控制信号T_PWM均为低电平；电阻R959为0欧电阻，其为可以选择设置的电阻，当电路中有测试需求时，可以将该电阻串接在图14中的位置，以方便调试，该电阻R959可以把第四引脚PWM1和PWM2连接到一起，被第一引脚ADIM所控制；电阻R982是下拉电阻，用于在第一引脚ADIM无信号时，拉低第一引脚ADIM的电平，保证在第一引脚ADIM无信号时，第二电流控制信号T_PWM为低电平；当第一引脚ADIM为高电平时，开关晶体管V936导通并接地，此时进入到第四引脚PWM1和PWM2的信号为 低电平；当第一引脚ADIM为低电平时，开关晶体管V936截止，第七引脚VREF通过电阻R980连接到第四引脚PWM1和PWM2，第七引脚VREF的信号为高电平。这样，通过控制开关晶体管V936的导通与关断，实现了输入到第四引脚PWM1和PWM2的信号，与第一引脚ADIM信号提供的第二电流控制信号T_PWM反相。
驱动芯片222的第二引脚RT可以与电阻R904的一端连接，该电阻R904的另一端接地。
电阻R903一端与电源端VCC3连接，另一端与驱动芯片222的电源引脚VCC连接，电容C914的一端与电源引脚VCC连接，另一端接地。其中，电阻R903与电容C914组成低通滤波器，用于进行低频滤波，阻隔电路中的高频杂波。
进一步的，驱动芯片222还可以包括第八引脚ST，驱动芯片222的第八引脚ST可以与电阻R902的一端连接，该电阻R902的另一端分别与电阻R901的一端和三极管V901的基极连接，电阻R901的另一端与三极管V901的发射极连接，三极管V901的集电极接地。第八引脚ST连接的电路为保护电路，在光源驱动电路工作异常时，该第八引脚ST可以输出报错信号，触发光源驱动电路的保护机制。示例的，可以关闭激光光源或者整体电源，以实现该保护机制。
第六引脚BLON分别与电阻R905的一端和电阻R905的一端连接，电阻R905的另一端接地，电阻R905的另一端分别与电阻R962的一端，以及开关晶体管V938的源极连接，开关晶体管V938的栅极分别与电阻R963的一端以及电阻R964的一端连接，电阻R963的另一端用于接收点灯使能信号ENA连接，电阻R964的另一端与开关晶体管V938的漏极接地。当第六引脚BLON为高电平时，使能该驱动芯片222工作，当第六引脚BLON为低电平时，驱动芯片222停止工 作。该第六引脚BLON连接的包括开关晶体管V938的外围子电路，用于实现了ENA的反相。点灯使能信号ENA为用于控制驱动芯片222是否工作的信号。该点灯使能信号ENA由驱动芯片222之外的其他芯片生成，例如，图8所示的控制芯片2111还具有点灯引脚LEDEN(图中未标示)，该点灯使能信号ENA可以由图8所示的控制芯片2111生成，通过控制芯片2111的点灯引脚LEDEN输出。
值得说明的是，前述用于信号反向的开关晶体管(开关晶体管V936和开关晶体管V938)是根据实际设计逻辑可选的元件，其根据所在的电路中的前端设计逻辑与后端设计匹配而选择设置。例如显示控制模块21输出的信号经过反相后输入到后端，在进入驱动芯片222前需要进行反相调整成显示控制模块21实际输出的信号。
如图15所示，图15为本申请实施例提供的一种示意性的降压电路的结构示意性。图15以第一处理模块与其连接的降压电路为例进行说明，图15中的各个引脚和元器件的功能可以参考前述图14中的具体说明，本申请实施例对此不再赘述了。
请参考图14和图15中，两个bank激光器串联，工作电流为3A，每个bank激光器消耗的电压为34V，因此两个bank激光器串联需要68V的额定电压才能正常工作。则，在图14中，VDD1提供的电压可以为76V，VDD2提供的电压可以为38V。电阻R905的阻值均为1kΩ(千欧)。电源端VCC3和VCC4的电压可以为12V。
请参考图13和图14，前述电阻R987、电阻R986和电阻R974为分压电阻，能够对数据选择器213提供的第二电流控制信号T_PWM进行分压，使得分压后的模拟信号的电压输入驱动芯片222的第一引脚ADIM，驱动芯片222根据第一 引脚ADIM的输入电压U ADIM调整激光光源的驱动电流，以激光光源中的任一激光器为例，该激光器的驱动电流L Laser的大小计算公式如下：
Figure PCTCN2020089089-appb-000007
Figure PCTCN2020089089-appb-000008
其中，T_PWM表示T_PWM信号的平均电压幅值，U ADIM为第一引脚ADIM的输入电压，R ISEN为该任一激光器的采样电阻的阻值。例如，当该激光器为第一激光器时，R ISEN为第一采样电阻的阻值，其阻值为并联的电阻R977、电阻R978、电阻R927和电阻R979的等效阻值，即R ISEN＝R977//R978//R979//R927。当该激光器为第二激光器时，R ISEN为第二采样电阻的阻值，其阻值为并联的电阻R925、电阻R976、电阻R975和电阻R920的等效阻值，即R ISEN＝R925//R976//R975//R920。
以第一处理模块为例，第一处理模块通过第一采样电阻可以检测对应的第一激光器的实际驱动电流，通过第五引脚ISEN1反馈到比较器lm1的负极输入端，利用比较结果，通过第三引脚DRV1调整DRV方波的占空比来控制开关晶体管V827的开关动作，以调整负极输出端口LD1‐的电压进而调整第一激光器正负极两端的电压，使第一激光器实际驱动电流达到所需要的设定电流值，即前述驱动电流L Laser的电流值。示例的，通过驱动芯片222的内部调整，当检测电流比设定电流值小时，增大DRV方波的占空比，当检测电流大于设定电流值大时，减小DRV方波的占空比。
同理，第二处理模块通过第二采样电阻可以检测对应的第二激光器的实际驱动电流，通过第五引脚ISEN2反馈到比较器lm1的负极输入端，利用比较结果，通过第三引脚DRV2调整DRV方波的占空比来控制开关晶体管V937的开关 动作，以调整负极输出端口LD1‐的电压进而调整第二激光器正负极两端的电压，使第二激光器实际驱动电流达到所需要的设定电流值，即前述驱动电流L Laser的电流值。其调整原理参考前述第一处理模块的调整原理，在此不再赘述。
开关晶体管V827和V927的开关频率可以由第三引脚DRV输出的DRV方波决定，如前所述，该DRV方波的开关频率是开关频率方波发生器H基于电阻R904的阻值计算得到，因此，开关晶体管V827和V927的开关频率由该电阻R904的阻值决定。其中，该开关晶体管V827和V927的开关频率
Figure PCTCN2020089089-appb-000009
驱动芯片的第四引脚PWM1和PWM2输出的信号可以理解为驱动芯片工作的使能信号，在该信号为高电平时，驱动芯片正常工作，在该信号为低电平时，驱动芯片停止工作，通常情况下第四引脚PWM1和PWM2输出的信号为持续高电平，以保证驱动芯片持续工作。
在另一种可选实现方式中，激光光源23为多片状激光器(MCL，Multichiped Laser)，电压输出电路为升压电路。由于升压电路的初始输入电压Vi相对于降压电路较低，若该升压电路出现短路等故障，该较低的初始输入电压Vi没有超出激光器的额定电压Vo，不会引起激光器的损伤，也不会引起人体的触电风险。因此，升压电路相对于降压电路对设备损伤的可能性较低，安全性较高。
如图16所示，图16是本申请实施例提供的一种MCL的结构示意图。MCL通常包括4路激光单元232，每路激光单元232包括多个串联的TO。例如，可以通过有线串联和板串联两种方式串联该多路激光单元。线串联指的是通过线材将多路激光单元首尾依次相接。板串联指的是在光源驱动电路的绘制版图过程中，通过版图布线将多路激光单元首尾依次相接。串联的TO的个数可以根据激光电源的亮度设置。
示例的，每路激光单元232可以包括5个串联的TO。即该MCL可以采用4×5的布局，则该MCL一共包括20个TO。或者每路激光单元232可以包括6个串联的TO。即该MCL可以采用4×6的布局，则该MCL一共包括24个TO。或者每路激光单元232可以包括7个串联的TO。即该MCL可以采用4×7的布局，则该MCL一共包括28个TO。
需要说明的是，本申请实施例中，MCL还可以包括3路激光单元，每路激光单元包括5个串联的TO，即该MCL可以采用3×5的布局，则该MCL一共包括15个TO。或者，MCL还可以包括2路激光单元，每路激光单元包括7个串联的TO，即该MCL可以采用2×7的布局，则该MCL一共包括14个TO。图16中以MCL包括4路激光单元，每路激光单元包括6个串联的TO为例进行说明，并不对MCL的布局进行限定。
值得说明的是，当激光器为MCL时，其需要连接激光器串接电路，以对该MCL进行有效驱动。可选的，图17是本申请实施例提供的一种激光器串接电路的结构示意图，如图17所示，该激光器串接电路可以为XP插座。光源驱动电路的输出信号通过该XP插座到达激光器串接板，从而点亮激光器。该XP插座可以包括引脚1至引脚8共8个引脚。其中，引脚1可以与光源驱动电路22的负极输出端口连接，引脚7可以与光源驱动电路22的正极输出端口连接。引脚2用于与激光器的负极连接，引脚8用于与激光器的正极连接。
示例地，图18是本申请实施例提供的一种MCL的等效电路图。如图16和图18所示，假设图示MCL为蓝色MCL，该蓝色MCL包括4路激光单元101，每路激光单元101包括2个端口，则4路激光单元包括端口0至端口7共8个端口。端口0、端口2、端口4和端口6为正极，端口1、端口3、端口5和端 口7为负极。其中，端口5可以与端口6连接，端口7可以与端口2连接，端口3可以与端口0连接，则端口4可以与蓝色MCL的激光器串接电路的引脚8连接，端口1可以依次与蓝色MCL的激光器串接电路的引脚2连接。电源驱动电路02传输的140V的电压，可以通过的激光器串接电路传输至第3路激光单元，并在该第3路激光单元降压至108.5V，然后传输至第4路激光单元，并在该第4路激光单元降压至77V，之后传输至第2路激光单元，并在该第2路激光单元降压至45.5V，最后传输至第1路激光单元，并在该第1路激光单元降压至14V，从而使得MCL发光。
相应的，在该种可选的实现方式中，光源驱动电路可以如图19所示。该驱动芯片具有用于接收第二电流控制信号T_PWM的控制引脚CTRL，用于接收占空比控制信号LD_duty的占空比调节引脚PWM。该处理模块还具有PWM输出引脚PWMOUT，设置引脚RT、开关引脚GATE，第一电流控制引脚ISP和第二电流控制引脚ISN，调节引脚FB。
其中，控制引脚CTRL分别与电阻R812的一端和电阻R813的一端连接，电阻R812另一端通过R811与提供第二电流控制信号T_PWM的节点ADIM连接，例如与前述图10中的电阻R1427的另一端连接。电阻R813的另一端接地。其中，节点ADIM用于接收第二电流控制信号T_PWM，经过电阻R811、R812和R813所组成的分压电路，输入到控制引脚CTRL。设置引脚RT通过电阻R818接地。第一电流控制引脚ISP和第二电流控制引脚ISN之间串联有电流检测电阻，该电流检测电阻可以包括并联的电阻R825和电阻R855。调节引脚FB分别与电阻R823的一端和电阻R880的一端连接，电阻R823的另一端通过串联的电阻R822与正极输出端口LD+(即激光器正极)，电阻R880的另一端接地。PWM输 出引脚PWMOUT与负极输出端口LD‐(即激光器负极)，开关引脚GATE与开关晶体管连接，该开关晶体管可以为NMOS。正极输出端口的LD+和负极输出端口的LD‐可以分别连接前述激光器串接电路。
进一步的，如图20所示，图20是前述光源驱动电路的具体结构示意图。该驱动芯片还包括电源引脚VC，功能引脚SENSE，接地引脚GND，引脚VIN，引脚INTVCC，引脚OPENLED、引脚VERF和引脚SS。
控制引脚CTRL与节点k连接，电阻R813和电容C803并联，并联的电阻R813和电容C803的一端与节点k连接，另一端接地，节点k还与串联的电阻R811和R822的一端连接，串联的电阻R811和电阻R822的另一端分别与ADIM端口以及电阻R802的一端连接，电阻R802的另一端接地。ADIM端口用于接收占空比控制信号LD_duty。电容C803为可选电阻，设置电容C803可以抑制激光器的电流过充，实现滤波电路的功能。
电源引脚VC与地之间串联电阻R821和电容C808。电源引脚VC也称为跨导误差放大器输出引脚，其与外接的电阻R821和电容C808组成稳定电压环路，用于进行电路的稳压。
第一电流控制引脚ISP与节点f连接，第二电流控制引脚ISN与激光器正极LD+连接，电阻R825与电阻R855并联，并联的电阻R825与电阻R855串联在激光器正极LD+和节点f之间。
功能引脚SENSE用于检测外围电路中的驱动电流的大小，该功能引脚SENSE与电阻R826的一端连接，电阻R826的另一端通过电容C818接地。电阻R826的一端还与电阻R828的一端和电阻R856的一端连接，电阻R856的另一端接地。电阻R828的另一端分别连接电阻R827的一端、二极管VD805的正极以及 开关晶体管V928的栅极连接，二极管VD805的负极与电阻R984的一端连接，电阻R984的另一端和电阻R827的另一端分别与开关引脚GATE连接。开关晶体管V928的漏极与电阻R856的一端连接。电容C821和电容C822并联，电阻R832和电阻R830并联，并联的电容C821和电容C822，与并联的电阻R832和电阻R830串联在开关晶体管V928的源极与地之间。开关晶体管V928的源极还分别与电容C1003的一端、并联的两个二极管VD802的正极，以及电感L903的一端连接，电感L903的另一端分别与电源端VCC5，以及并联的电容C809和C810的一端连接，并联的电容C809和C810的另一端接地。电容C1003的另一端与电阻R986的一端连接，电阻R986的另一端分别与并联的两个二极管VD802的负极以及节点f连接，节点f与地之间还连接有并联的电阻C812、C813、C814、C815和C816。
调节引脚FB分别与电阻R822的一端和电阻R880的一端连接，电阻R880的另一端接地，电阻R822的另一端通过电阻R823与节点f连接。
PWM输出引脚PWMOUT与电阻R835的一端连接，电阻R835的另一端分别与开关晶体管V803的栅极以及电阻R836的一端连接，电阻R836的另一端与开关晶体管V803的漏极均接地，开关晶体管V803的源极与激光器负极LD‐连接。
接地引脚GND接地。
引脚VIN为驱动芯片的电源引脚，引脚VIN分别与电容C806的一端、C807的一端、电阻R819的一端、电阻R820的一端连接，电容C806的另一端、C807的另一端均接地，电阻R819的另一端和电阻R820的另一端与电源端VDD3连接。
引脚INTVCC用于提供稳压电源，引脚INTVCC分别与电容C805的一端以及电阻R816的一端连接，电容C805的另一端接地。电阻R816的另一端分别与引脚OPENLED和二极管VD801的负极连接，二极管VD801的正极与引脚SS连接。该引脚INTVCC，为内部负载，例如引脚GATE的驱动器(driver)和引脚PWMOUT的驱动器供电。引脚INTVCC的电压通常为7.15V。引脚OPENLED用于检测外围电路的负载是否开路，在外围电路的负载开路时输出用于指示开路的低电平信号。引脚SS是软启动引脚，用于控制软件启动的时间，该软启动时间由引脚SS外接的电容C804来设定。
引脚UVLO与C825的一端、电阻R842的一端、电阻R987的一端、电阻R841的一端和开关晶体管V805的源极连接，C825和电阻R842的另一端接地，电阻R987的另一端与电源端VDD4连接，电阻R841的另一端与电源端VDD5连接。开关晶体管V805的栅极分别与电阻R838的一端和电阻R849的一端连接，电阻R838的另一端与ENA连接，电阻R840的另一端与开关晶体管V805的漏极均接地。
设置引脚RT通过电阻R818接地。
占空比调节引脚PWM分别与电阻R809的一端、电阻R808的一端和开关晶体管V801的源极连接，电阻R808的另一端与电源端VDD6连接，开关晶体管V805的栅极分别与电阻R801的一端和电阻R807的一端连接，电阻R805的一端与PDIM连接，电阻R807的另一端与开关晶体管V801的漏极均接地。
引脚VREF是参考电压输出脚，其输出的参考电压可以为2V。该引脚VERF可以与用于测试参考电压的测试点TP3连接，也可以为空闲引脚。
图20所示的MCL的电流为3A，该MCL两端消耗电压为82V。可以选择从 60V开始升压。电阻R811、电阻R812和电阻R813为分压电阻，能够对数据选择器213提供的第二电流控制信号T_PWM进行分压。分压后的第二电流控制信号T_PWM的电压经过电阻R811、电阻R812和电阻R813分压后输入到驱动芯片222的控制引脚CTRL，驱动芯片222根据控制引脚CTRL输入电压调整MCL的驱动电流I LD，驱动电流I LD大小的计算公式如下：
Figure PCTCN2020089089-appb-000010
其中，
Figure PCTCN2020089089-appb-000011
ADIM表示T_PWM信号的平均电压幅值，V CTRL为引脚CTRL的输入电压，R LD为采样电阻的阻值，在图20中，其为并联的电阻R825、电阻R855的阻值，即R LD＝R825//R855。
引脚PWM连接LD_Duty(对应PDIM端口)，当引脚PWM的信号为高电平，引脚PWMOUT输出为高，使开关晶体管V803的导通，MCL负端接地，形成回路点亮激光器。
引脚RT用于设定开关晶体管V928的开关频率(引脚RT通过在芯片内部与引脚GATE直接或间接的连接来设定开关晶体管V928的开关频率)，其通过电阻R818接地，引脚FB用于设置升压电路的最大输出电压，使MCL两端的电压不会超过此限值，起到保护MCL的作用。
需要说明的是，前述电源端VCC5的电压可以为48V，电源端VDD5的电压可以为48V，电源端VDD6的电压可以为5V。
如图21所示，图21为本申请实施例提供的一种示意性的升压电路的结构示意性。图21中的各个引脚和元器件的功能可以参考前述图14中的具体说明， 本申请实施例对此不再赘述了。
如图22所示，显示控制模块21，还包括：位于处理模块与数据选择器213之间的数模转换器214。该数模转换器214可以为数字模拟转换器(Digital to analog converter，DAC)芯片。当电流控制信号为PWM信号时，由于处理模块211输出的是高频的PWM信号，而后端驱动电路(如光源驱动电路22)需要稳定的直流电压信号，因此通过该数模转换器214实现后端驱动电路的信号需求。
数模转换器214，用于接收数字信号形式的N个第一电流控制信号，分别将接收到的N个第一电流控制信号转换为模拟信号形式的N个第一电流控制信号，并将转换后的N个第一电流控制信号传输至数据选择器213。转换后的N个第一电流控制信号为直流电压信号。图22假设数字信号形式的N个第一电流控制信号包括R_PWM1、G_PWM1、B_PWM1和Y_PWM1共4个数字信号。对应转换得到的N个第一电流控制信号包括R_PWM2、G_PWM2、B_PWM2和Y_PWM2共4个模拟信号。
值得说明的是，本申请实施例提供的光源驱动电路中，各个开关晶体管均可以为MOS管，例如NMOS管或PMOS管时，外围电路的通断时间达到ns(纳秒)级，光源驱动电路的通断时间达到μs(微秒)级，从而使激光光源的电流响应速度快，精度高，大电流和低纹波，能够实现快速调整激光光源的亮度。并且，前述光源驱动电路通过采用快速响应器件(如MOS管)及驱动芯片，从而保证电流开启和关闭响应延迟时间在1us以内，电流上升和下降时间在20us以内，电流纹波频率在400kHz，幅度在±5％以内。从而实现了电流开启响应延迟较小、电流上升时间快、电流关闭响应延迟较小、电流下降时间快、纹波频率大及幅度小。以上对激光光源的电流的快速控制保证了超高对比度功能下激光光 源的电流可以快速的跟随图像显示对激光源控制的要求，保证电流的实时调制和图像显示的严格同步，从而实现后续的高对比度的图像显示算法。
随着社会的发展，人们对激光投影设备的显示效果要求越来越高，因此也对影响显示效果的一系列参数(例如，对比度)有了更高的要求。其中，激光投影设备的对比度通常分为静态对比度和动态对比度。静态对比度通常指的是采用美国国家标准学会(American national standards institute，ANSI)制定的对比度算法计算得到对比度，其指的是一张图片(即同一帧图像)中白色区域的亮度与黑色区域的亮度比。
动态对比度指的是同一帧图像在显示过程中的明暗比，其与显示过程中激光光源的亮度相关，也即是该一帧图像在显示过程中最亮的白色区域与最暗的黑色区域的亮度比。例如下述公式所示，动态对比度C满足：
Figure PCTCN2020089089-appb-000012
L w为该一帧图像在显示过程中最亮的白色区域的亮度，L B为该一帧图像在显示过程中最暗的黑色区域的亮度。
通过上述动态对比度的公式可知，当L w达到最大值时，可以通过降低L B的值，提高动态对比度。其中，激光投影设备的图像的实际显示亮度通常由两个因素决定，一个因素是激光光源的亮度，另一个因素是图像的灰阶值(也即是图像自身的亮度)，该两个因素的叠加最终可以确定一帧图像的实际显示亮度，因此，可以通过调节该两个因素的比例来优化显示效果。
通常情况下，激光投影设备所显示的视频中图像自身的亮度是基于其内容不断变化的，对于每一帧图像，均可以根据图像自身的亮度调整激光光源，从而调整图像的实际显示亮度。例如，当一帧图像为黑色画面时，可以通过降低 激光光源的亮度，使得该一帧图像的实际显示亮度相较于其自身亮度更低。这样，可以通过降低激光光源的亮度，降低激光投影设备在显示图像时的实际显示亮度的下限值，即最低实际显示亮度(L B)，提高该激光投影设备在显示图像时的动态对比度。同时由于降低了激光光源的亮度，因此，也降低了该激光投影设备的功耗。
本申请实施例提供的激光投影设备，可以在不改变图像的实际显示亮度，从而提高该激光投影设备的动态对比度。其图像显示算法为：对激光光源的亮度和每一帧图像的灰阶值分别进行处理，以增强图像的细节表达，进而在保证显示图像的亮度不变的前提下，降低光源亮度，提高激光投影设备的动态对比度。为了便于读者理解，本申请实施例以图23至图25为例对本申请实施例所涉及的图像显示原理进行说明：
如图23至图25，图23至图25示出了输入信号灰阶值(也称显示灰阶值或图像自身亮度)、屏幕亮度(也即是实际显示亮度)的关系。图23至图25中，横坐标为输入信号灰阶值，纵坐标为屏幕亮度。假设激光投影设备所能处理的图像的最大灰阶值为256，激光光源的功率(由于激光光源的功率与激光光源的亮度成正比，本申请实施例中，假设激光光源的功率等价于激光光源的亮度)为一个标准量(也即是参考量)，例如为单位以一，则，如图23所示，该激光投影设备的输入信号灰阶值与屏幕亮度的曲线(也即是伽马曲线)为图23中的实线。假设，当前显示的一帧图像A的输入信号灰阶值为160，则对应的屏幕亮度为96，如图24所示，将该帧图像A的输入的信号灰阶值增益D倍，该帧图像A转化为图像A’，该图像A’对应的屏幕亮度为192。如图25所示，可以通过降低激 光光源的功率使屏幕亮度降为96，从而将图像A’转化为图像A。这样，由于图像的显示灰阶值范围越大，图像的细节表达越丰富，而本申请实施例提供的激光投影设备可以将图像的显示灰阶值的范围扩大，也即是提高了显示灰阶值的上限值，因此，增强了图像的细节表达，同时，在保证图像A的实际显示亮度不变的前提下，激光光源的亮度降低，对比度提高，功耗降低。
可选的，如图26所示，激光投影设备还包括光调制器件24，该光调制器件24可以为数字微镜器件(Digital Micro mirror Device，DMD)或者液晶覆硅(Liquid Crystal on Silicon，LCOS)。
进一步的，处理模块211包括：算法处理器211a和控制处理模块211b，算法处理器211a与控制处理模块211b连接，控制处理模块211b还分别与数据选择器213以及光调制器件24连接。
算法处理器211a，用于根据每一帧图像的灰阶值，确定每一帧图像的的增益值α，α≥1。该算法处理器可以采用现场可编程门阵列(Field－Programmable Gate Array，FPGA)来实现。
其中，每一帧图像的图像显示数据可以反映出每一帧图像颜色的基本分布和基本色调，当图像显示数据为4K数据时，该4K数据可以以8路VBO(全称V‐by‐One，一种面向图像传输开发出的数字接口标准)信号的方式输入至算法处理器211a。
算法处理器211a，还用于向控制处理模块211b发送N个第一电流控制信号、M个使能信号和图像显示数据。
可选的，算法处理器211a可以通过多种方式生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号，在一种可选方式中，算法处理器211a确定 了每一帧图像的的增益值α后，计算得到每个基色的亮度，并通过第二预设算法基于该亮度生成相应基色的电流控制信号以及混色电流控制信号；在另一种可选方式中，算法处理器211a可以预存有电流控制信号与亮度的对应关系，在确定了每一帧图像的的增益值α后，算法处理器211a计算得到每个基色的亮度，然后根据计算得到的亮度查询该对应关系，得到与亮度相应的电流控制信号。例的，当电流控制信号为PWM信号时，该电流控制信号与电流的对应关系可以由PWM值与亮度的对应关系表征。
控制处理模块211b，用于将N个第一电流控制信号和M个使能信号传输至数据选择器213。还可以将M个使能信号传输至信号生成器212。
控制处理模块211b，还用于向光调制器件24发送图像显示数据，其中，前述每个电流控制信号用于指示对应的激光光源的调整后的亮度，调整后的亮度为调整前的亮度的1/α，图像显示数据用于指示调整后的每一帧图像的灰阶值，调整后的灰阶值为调整前的灰阶值的α倍。
光调制器件24，用于基于图像显示数据，对激光光源的光束进行调制，以生成影像光束，并将该影像光束投影至投影屏幕上，实现每一帧图像的显示。
需要说明的是，激光投影设备还可以包括多个光学透镜，该多个光学透镜位于光调制器件24与投影屏幕之间，该多个光学透镜用于对影像光束进行透射、反射和/或者折射后，投影至投影屏幕上。
在本申请实施例中，显示控制模块21可以基于每一帧图像的的增益值α，也即是每一帧图像的变化，实时地调节激光光源的亮度，从而实现动态对比度。并且由于激光器串接电路的光源开关电路中，当第一开关晶体管为MOS管，例如NMOS管时，光源开关电路的通断时间达到ns(纳秒)级，激光器串接电路 的通断时间达到μs(微秒)级，从而使激光光源的电流响应速度快，精度高，也即是该激光器串接电路可以快速，高精度地响应图像各个像素亮度的变化，且可以实现激光光源的亮度从0到额定电流值所对应亮度的之间任意调节，此驱动电路是实现高动态对比度的基础，即在硬件上支持了激光投影设备的动态亮度调节。
随着激光投影设备分辨率的提高，激光投影设备的图像显示数据越来越大，例如该图像显示数据为4K数据，即像素分辨率为4096×2160的数据，显示控制模块21只采用一个处理器容易引起处理器处理效率较低，因此，本申请实施例提出主从处理器协同处理图像显示数据的方式，以提高处理效率。如图27所示，控制处理模块211b包括主控处理器X1和从控处理器X2，算法处理器211a分别与主控处理器X1和从控处理器X2连接，主控处理器X1还分别与光源驱动电路22以及光调制器件24连接，从控处理器X2还与光调制器件24连接。需要说明是，在激光投影设备可以包括显示板、电源板和激光器板，算法处理器211a、主控处理器X1，从控处理器X2、数据选择器213、信号生成器212和前述数模转换器214均设置在显示板上，光源驱动电路22设置在电源板上，激光光源23设置在激光器板上。
算法处理器211a，用于根据每一帧图像的灰阶值，确定每一帧图像的的增益值α，α≥1。
算法处理器211a，还用于向主控处理器X1发送N个第一电流控制信号和第一子数据，并向从控处理器发送第二子数据，第一子数据和第二子数据组成图像显示数据。图27假设该N个第一电流控制信号包括：红色PWM信号R_PWM、 绿色PWM信号G_PWM、蓝色PWM信号B_PWM和混色PWM信号Y_PWM。
示例的，当图像显示数据为4K数据时，第一子数据和第二子数据均为60bit(比特)数据，且第一子数据和第二子数据均可以为低电压差分信号(Low‐Voltage Differential Signaling，LVDS)，其中，第一子数据为两路west(西)LVDS，第二子数据可以为两路east(东)LVDS。
每个电流控制信号用于指示调整后的亮度，调整后的亮度为调整前的亮度的1/α，图像显示数据用于指示调整后的每一帧图像的灰阶值，调整后的灰阶值为调整前的灰阶值的α倍。
主控处理器X1，用于接收所述N个第一电流控制信号，生成M个使能信号，并将接收的N个第一电流控制信号以及M个使能信号传输至数据选择器，还可以将M个使能信号传输至信号生成器，并向光调制器件发送第一子数据。图27假设M个使能信号分别为红色使能信号R_EN、绿色使能信号G_EN和蓝色使能信号B_EN。前述图5所示的处理模块211的信号输出电路可以集成在该主控处理器X1中。
从控处理器X2，用于向光调制器件24发送第二子数据。
光调制器件24，用于基于第一子数据和第二子数据，对激光光源的光束进行调制，以生成影像光束，并将该影像光束投影至投影屏幕上，实现每一帧图像的显示。
进一步可选的，如图28所示，该激光投影设备还包括：存储器26，振镜驱动电路27，振镜28和电源模块25，其中，存储器26与算法处理器211a连接，用于存储图像显示数据，请参考图24和25，即存储调整后的每一帧图像的灰阶值，例如，该存储器为双倍速率(Double Data Rate，DDR)存储器；振镜驱动电 路27分别与算法处理器211a以及振镜28连接，用于在算法处理器211a的控制下带动振镜28振动，示例的，该振镜28可以为4维振镜，也即是能够在4个方向上振动，通过设置该振镜驱动电路27以及振镜28，可以进行图像叠加显示，增加细节表现力，相当于分辨率提升；电源模块25用于为用电元件提供电能，其与激光投影设备中的各个用电元件分别连接，图12仅以其与算法处理器211a、主控处理器X1和从控处理器X2分别连接进行示意图说明。
值得说明的是，该激光投影设备中的激光光源23可以为图1中的蓝色激光光源130，进一步的，该激光投影设备还可以包括：光机20和投影镜头30，以及前述投影光源10中除蓝色激光光源130之外的其他元件等，各个元件的功能可以参考图1，本申请实施例对此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的申请后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (13)

  1. 一种激光投影设备，其特征在于，包括：
    依次连接的显示控制模块，光源驱动电路，以及激光光源；
    所述显示控制模块，用于生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号，并在所述N个第一电流控制信号中选择有效的第二电流控制信号，将所述第二电流控制信号传输至所述光源驱动电路，所述N个第一电流控制信号包括与所述每一帧图像的M个基色一一对应的单色电流控制信号以及混色电流控制信号，N为大于2的整数，M为正整数；
    所述光源驱动电路，用于基于接收到的所述第二电流控制信号，控制所述激光光源发光；
    其中，所述多帧显示图像中的至少两帧显示图像对应的第二电流控制信号的大小不同。
  2. 根据权利要求1所述的激光投影设备，其特征在于，所述显示控制模块，包括：处理模块、信号生成器和数据选择器，所述处理模块与所述数据选择器连接，所述处理模块，用于生成多帧显示图像中的每一帧图像对应的N个第一电流控制信号和M个使能信号，并将所述N个第一电流控制信号和所述M个使能信号传输至所述数据选择器；
    所述信号生成器，用于生成占空比控制信号，并输出至所述光源驱动电路；
    所述数据选择器，用于基于所述M个使能信号，在所述N个第一电流控制信号中选择所述第二电流控制信号，并将所述第二电流控制信号传输至所述光源驱动电路；
    所述光源驱动电路，用于基于接收到的所述第二电流控制信号，调节所述激光光 源的电流，并基于所述占空比控制信号控制所述激光光源的开启与关闭。
  3. 根据权利要求2所述的激光投影设备，其特征在于，N＝4，M＝3，所述数据选择器具有用于接收4个第一电流控制信号的数据输入端，用于接收3个使能信号的逻辑引脚，以及用于输出第二电流控制信号的输出引脚；
    所述数据选择器用于在对应某一基色的使能信号为有效电位，且对应其他基色的使能信号不为有效电位时，将对应所述某一基色的第一电流控制信号作为所述第二电流控制信号从所述输出引脚输出；在对应至少两个基色的使能信号为有效电位时，将所述混色电流控制信号作为所述第二电流控制信号从所述输出引脚输出。
  4. 根据权利要求2所述的激光投影设备，其特征在于，所述处理模块还与所述信号生成器连接，所述处理模块，还用于将所述M个使能信号传输至所述信号生成器；
    所述信号生成器，用于基于所述M个使能信号，生成所述占空比控制信号。
  5. 根据权利要求4所述的激光投影设备，其特征在于，M＝3，所述信号生成器包括：第一或门和第二或门；
    其中，所述第一或门的两个输入端用于分别接收3个使能信号中的两个使能信号，所述第二或门的一个输入端与所述第一或门的输出端连接，另一个输入端用于接收所述3个使能信号中除所述两个使能信号之外的其他使能信号，所述第二或门的输出端用于输出所述占空比控制信号。
  6. 根据权利要求2所述的激光投影设备，其特征在于，所述光源驱动电路包括：电压输出电路、驱动芯片和外围电路；
    所述电压输出电路，用于为所述外围电路提供所述激光光源的额定电压；
    所述驱动芯片，用于接收所述第二电流控制信号，并向所述外围电路提供所述第二电流控制信号对应的电流，以及，接收所述占空比控制信号，并基于所述占空比控制信号控制所述外围电路的导通和断开；
    所述外围电路分别与所述驱动芯片和所述激光光源连接，用于在所述外围电路导通时，在所述额定电压下向所述激光光源提供所述第二电流控制信号对应的电流。
  7. 根据权利要求6所述的显示装置，其特征在于，所述激光光源为MCL型激光器组件，所述电压输出电路为降压电路。
  8. 根据权利要求6所述的显示装置，其特征在于，所述激光光源为MCL型激光器，所述电压输出电路为升压电路。
  9. 根据权利要求2所述的激光投影设备，其特征在于，所述显示控制模块，还包括：位于所述处理模块与所述数据选择器之间的数模转换器，
    所述数模转换器，用于接收数字信号形式的N个第一电流控制信号，分别将接收到的N个第一电流控制信号转换为模拟信号形式的N个第一电流控制信号，并将转换后的N个第一电流控制信号传输至所述数据选择器。
  10. 根据权利要求2至9任一所述的激光投影设备，其特征在于，所述激光投影设备还包括光调制器件，所述处理模块包括：算法处理器和控制处理模块，所述算法处理器与所述控制处理模块连接，所述控制处理模块还分别与所述数据选择器以及所述光调制器件连接。
  11. 根据权利要求10所述的激光投影设备，其特征在于，所述控制处理模块包括：主控处理器和从控处理器，所述算法处理器分别与所述主控处理器和所述从控处理器连接，所述主控处理器还分别与所述数据选择器以及所述光调制器件 连接，所述从控处理器还与所述光调制器件连接，
    其中，所述算法处理器，用于根据所述每一帧图像的灰阶值，确定所述每一帧图像的增益值α，其中，α≥1；
    所述算法处理器，还用于向所述主控处理器发送所述N个第一电流控制信号和第一子数据，并向所述从控处理器发送第二子数据，所述第一子数据和所述第二子数据用于组成图像显示数据，每个所述电流控制信号用于指示调整后的亮度，所述图像显示数据用于指示调整后的每一帧图像的灰阶值；
    所述主控处理器，用于接收所述N个第一电流控制信号，生成M个使能信号，将接收的所述N个第一电流控制信号以及所述M个使能信号传输至所述数据选择器，并向所述光调制器件发送第一子数据；
    所述从控处理器，用于向所述光调制器件发送所述第二子数据；
    所述光调制器件，用于基于所述第一子数据和所述第二子数据，对激光光源的光束进行调制，以生成影像光束。
  12. 根据权利要求10所述的激光投影设备，其特征在于，每个所述电流控制信号所指示的调整后的亮度为调整前的亮度的1/α；以及，所述图像显示数据所指示的调整后的灰阶值为调整前的灰阶值的α倍。
  13. 根据权利要求12任一所述的激光投影设备，其特征在于，所述至少两帧显示图像为相邻的两帧显示图像；或者，所述至少两帧显示图像为间隔多帧的两帧图像。
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