WO2020247013A1 - Space efficient high-voltage termination and process for fabricating the same - Google Patents

Space efficient high-voltage termination and process for fabricating the same Download PDF

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Publication number
WO2020247013A1
WO2020247013A1 PCT/US2019/061857 US2019061857W WO2020247013A1 WO 2020247013 A1 WO2020247013 A1 WO 2020247013A1 US 2019061857 W US2019061857 W US 2019061857W WO 2020247013 A1 WO2020247013 A1 WO 2020247013A1
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Prior art keywords
extension region
termination
substrate
region
shallow trench
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PCT/US2019/061857
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French (fr)
Inventor
Amaury Gendron-Hansen
Dumitru Sdrulla
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Microchip Technology Inc
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Microchip Technology Inc
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Priority to DE112019007417.2T priority Critical patent/DE112019007417T5/en
Priority to CN201980096746.8A priority patent/CN113875021A/en
Publication of WO2020247013A1 publication Critical patent/WO2020247013A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/104—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H10P30/2042—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors into crystalline silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/30—Isolation regions comprising PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • the present invention relates to semiconductor device structures and
  • the present invention relates to a high- voltage termination structure for a semiconductor device and to a process for fabricating that structure.
  • the high-voltage termination structure accounts for a significant portion of the die total footprint, in some cases amounting to more than half of the footprint. Hence, reducing the length of the
  • termination structure would reduce the size and cost of the dies.
  • FFR floating field ring
  • JTE junction termination extension
  • deep trench designs Most of the prior-art high-voltage termination designs rely on floating field ring (FFR), junction termination extension (JTE), and/or deep trench designs.
  • FFR design provides a very robust termination however it has a large footprint (typically 10 times the thickness of the epitaxy).
  • the JTE design is more compact (about 3 times the thickness of the epitaxy) but has the drawback of being highly sensitive to normal process variations.
  • the deep trench design is very compact but expensive to fabricate in that it is difficult to control the dry etch process used.
  • the present invention relies on the combination of a shallow trench, a JTE region, and a field plate to provide a high breakdown voltage close to the full capability of the substrate, which may be a semiconductor substrate, a well formed in a semiconductor substrate or an epitaxial layer formed on a substrate.
  • the underlying principle is to suppress any high electric fields near convex junctions so that the avalanche breakdown of the termination is governed by the electric field of a planar junction.
  • the shallow trench allows the convex junction of the doped extension to be etched away.
  • the JTE and field plate are designed to relax the electric field at the interface between the extension and the trench.
  • a high-voltage termination for a semiconductor device includes a substrate of a first conductivity type, an implanted device region of a second conductivity type of the semiconductor device, a shallow trench disposed in the substrate adjacent to the implanted device region, a doped extension region of the second conductivity type extending between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region, a junction termination extension region of the second conductivity type formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer extending into at least a portion of the shallow trench and electrically connected to the extension region.
  • a length of the shallow trench and the doped extension region together form a termination length of the high-voltage
  • a second insulating layer is formed over the metal layer and the insulating layer.
  • sidewalls of the shallow trench are at angles between about 45° and about 60°.
  • the substrate of the first conductivity type is an epitaxial layer disposed over an underlying substrate.
  • the epitaxial layer is an epitaxial SiC layer
  • the underlying substrate is a SiC substrate.
  • the epitaxial SiC layer is doped with nitrogen, and the underlying SiC substrate is doped with nitrogen.
  • the epitaxial SiC layer is doped with nitrogen to a concentration of from about le 14/cm 3 to about 2e 16/cm 3
  • the underlying SiC substrate is doped with nitrogen to a resistivity of about 0.02 ohm-cm.
  • the extension region is implanted with one of aluminum and boron
  • the junction termination extension region is implanted with one of aluminum and boron
  • the extension region is implanted with one of aluminum and boron with a dose of between about le 13/cm 2 to about le 15/cm 2
  • the junction termination extension region is implanted with one of aluminum and boron with a dose of between about lei 1/cm 2 to about le 13/cm 2
  • the doping of the junction termination extension region is less than the doping of the extension region.
  • the shallow trench has a depth of between about 2 pm to about 5 pm, and a termination length defined by a width of the shallow trench and an extension of the junction termination extension region beyond the trench is selected to withstand a preselected blocking voltage.
  • the termination length is between about 21 pm to about 55 pm.
  • a method for forming a high voltage termination in a semiconductor device includes providing a substrate of a first
  • performing an ion implantation to form an extension region of a second conductivity type opposite the first conductivity type in the substrate comprises performing the ion implantation to form the extension region that extends from an edge of the shallow trench opposite the active area to define a
  • forming a shallow trench in the substrate comprises forming a shallow trench in the substrate having sidewalls disposed at angles between about 45° and about 60°.
  • providing a substrate of a first conductivity type comprises providing a SiC epitaxial layer over a SiC substrate.
  • providing a substrate of a first conductivity type comprises providing a SiC epitaxial layer doped with nitrogen over a SiC substrate doped with nitrogen.
  • forming an extension region of a second conductivity type comprises performing an implantation with one of aluminum and boron, and with a dose of between about le 13/cm 2 to about le 15/cm 2
  • forming the junction termination extension region of a second conductivity type comprises performing an implantation with one of aluminum and boron, and with a dose of between about lei 1/cm 2 to about le 13/cm 2 , and the doping of the junction termination extension region is less than the doping of the extension region.
  • a transistor with high-voltage termination includes a substrate of a first conductivity type, an active area in the substrate including source and drain regions of the transistor, a gate disposed over the source and drain regions, a shallow trench disposed in the substrate adjacent to the active area of the substrate, a doped extension region of a second conductivity type, opposite the first conductivity type, formed in the substrate and extending from a first edge of the shallow trench and contacting the source of the transistor, a junction termination extension region of the second conductivity type formed in the shallow trench and contacting the extension region, the junction termination region extending past a second edge of the shallow trench opposite the first edge, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer, the metal layer extending into at least a portion of the shallow trench, the metal layer electrically connected through a via in the insulating layer to the extension region.
  • the source region is disposed in a p-well formed in the substrate, and the doped extension region contacts the p-well.
  • a length of the shallow trench and the doped extension region together form a termination length of the high-voltage
  • FIG. 1 is a cross-sectional diagram of a portion of a semiconductor device including a high-voltage termination in accordance with an aspect of the present invention
  • FIGS. 2A through 2H are cross-sectional diagrams of the high-voltage termination of FIG. 1 showing progressive steps in an illustrative fabrication process in accordance with an aspect of the present invention.
  • FIG. 3A and 3B are cross-sectional diagrams of a portion of a semiconductor device including a high-voltage termination in accordance with an aspect of the present invention formed in different examples of substrates.
  • the present invention is particularly advantageous when employed with silicon carbide (SiC) Schottky diodes and SiC MOSFETS but persons of ordinary skill in the art will appreciate that the present invention can be used with other devices.
  • SiC silicon carbide
  • a substrate may be the layer in which the implanted regions are directly formed. In some instances it may be a substrate with no overlying layers. In other instances it may be in the form of an epitaxial layer formed over an underlying substrate. In other instances it may be in the form of a well structure formed in an underlying substrate. In any event persons of ordinary skill in the art will be readily able to determine the meaning of“substrate” by examining the context in which it is used.
  • FIG. 1 an illustrative embodiment of high-voltage termination 10 for a semiconductor device in accordance with an aspect of the present invention is shown in cross-sectional view along with a SiC MOSFET transistor 12 to be protected.
  • the particular embodiment shown in FIG. 1 is formed on an SiC epitaxial layer 14 grown on a SiC substrate 16 in a conventional manner.
  • the thickness of the SiC substrate 16 is about 350 pm +/- 25pm.
  • the substrate 16 is doped with an n-type dopant, such as nitrogen, to achieve a typical resistivity of 0.02 ohm-cm and the epitaxial layer 14 is doped with nitrogen to a typical concentration of about le 14/cm 3 to 2e 16/cm 3 .
  • an n-type dopant such as nitrogen
  • the thickness of the epitaxial layer 14 is chosen depending on the desired voltage rating, and the thickness of the epitaxial layer 14 varies approximately linearly with the desired voltage rating. In addition, a good approximation for a JTE termination is that it has a length equal to about 3 times the thickness of the epitaxial layer 14. For example, the thickness of the epitaxial layer 14 for a 1700 V rating should be about 13.5 pm-thick which results in a 40.5 pm-long JTE termination.
  • the epitaxial layer 14 thicknesses for 700 V, 1,200 V, 3,300 V, and 6,500 V ratings are 5 pm, 10 pm, 30 pm, and 60 pm respectively.
  • the MOSFET transistor 12 has a source region 18 formed in a p-well 20 disposed in the epitaxial layer 14.
  • aluminum or boron is used for doping of the p-well 20.
  • the p-well 20 is doped with aluminum or boron with a dose of between about 5el2cm 2 and about lel5cm 2 .
  • the transistor 12 has a drain 22 formed on the back side of the substrate 16 and a gate 24 insulated from the surface of the epitaxial layer 14 as is known in the art.
  • the transistor 12 may take the form of an annular transistor or have other geometries such as, for example, long stripes. The present invention is applicable to all such transistor geometries.
  • a p-type doped extension (PEXT) region 26 is formed on the surface of the SiC epitaxial layer 14 and extends to and is connected to the p-well 20.
  • the PEXT region 26 is doped with a species such as aluminum or boron.
  • the PEXT region 26 is doped with an implantation dose of about lel3cm 2 to lel5cm 2 , although the present invention is not limited to this doping range.
  • the PEXT region 26 is more heavily doped than the p-well 20. Junction depths of PEXT region 26 depend on the implantation energy which is usually between about 200 keV to 500 keV.
  • the shallow trench 28 is formed in the upper surface of the SiC epitaxial layer 14 and intersects the PEXT region 26.
  • the shallow trench 28 has a length L of about 20 pm to 50 pm.
  • the shallow trench 28 is formed to a depth D of about 2 pm to 5 pm.
  • a p-type doped junction termination extension (JTE) region 30 is formed in the shallow trench 28 and intersects the PEXT region 26.
  • the JTE region 30 additionally extends beyond the edge of the trench 28 in the direction opposite the transistor 12.
  • the p-type doped JTE region 30 is implanted with a species such as aluminum (or boron), and a dose of about lei 1/cm 2 to le 13 /cm 2 (typically about le 12/cm 2 ).
  • the doping of JTE region 30 is less than that of PEXT region 26, and further preferably 2 orders of magnitude less.
  • junction depth of JTE region 30 is about 1 pm. It is necessary that for any given design the JTE implantation dose be selected to assure that the JTE region is fully“depleted” under the reverse bias applied to the device.
  • a dielectric layer 32 formed from for example deposited silicon dioxide (oxide) to a thickness of between about 1 pm to 3 pm is disposed over a portion of the PEXT region 26 and over the JTE region 30.
  • a metal layer 34 is disposed over a portion of the dielectric layer 32 and extends into the trench 28.
  • the metal layer 34 extends beyond the edge of the trench 28 towards the transistor 12 and is in electrical contact with the source 18 of the transistor 12, with the p-well 20 and with PEXT region 26 through a via.
  • the metal layer 34 is formed from a metal such as but not limited to a stack of titanium and aluminum to a thickness of between about 1 pm to 5 pm, depending on the application. The targeted thickness is measured with respect to a flat surface, and then conforms to the topology. For high power devices the thickness of the metal layer 34 can be about 5 pm. If the present invention is incorporated into a low voltage integrated circuit, then a 1 pm thick layer of the metal used for that technology will be satisfactory.
  • a dielectric layer 36 formed from a material such as oxynitride to a thickness of between about 1 pm and about 4 pm is disposed over the portion of the dielectric layer 32 not covered by metal layer 34 and over the metal layer 34.
  • the length of the trench 28 plus the extension of the JTE region 30 beyond the edge of the trench 28 in the direction opposite the transistor 12 is referred to herein as the termination length.
  • the JTE region 30 extends beyond the edge of the trench 28 in the direction opposite the transistor 12 by at least 1 pm and typically extends beyond the edge of the trench 28 by between about 1 pm and about 5 pm.
  • the termination length is tailored to meet the blocking voltage requirement and is shown at arrows 38. In an embodiment where the blocking voltage is about 1,700V, the termination length 38 is about 40.5 pm.
  • the termination length 38 scales linearly with blocking voltage.
  • the high-voltage termination of the present invention presents a narrower design than other solutions such as floating field ring designs.
  • the metal layer 34 acts as a field plate to extend the applied voltage to a defined area and spreads the charge to reduce the electric field and avoid avalanche breakdown at relatively low voltages.
  • the high-voltage termination of the present invention presents a blocking voltage close to the full capability of the epitaxial layer 14 and exhibits a lower leakage current, hence improved reliability.
  • the breakdown voltage is significantly higher for the high voltage termination structure that spans the termination length 38 than for the active area of the transistor 12, resulting in a higher reliability under harsh electrical and environmental conditions.
  • FIGS. 2A through 2H a series of cross-sectional diagrams show the structure resulting after selected steps in an illustrative fabrication process have been performed.
  • the p-well 20 for the transistor 12 is shown as being formed prior to the PEXT region 26 and the JTE region 30.
  • the PEXT region 26 and the JTE region 30 are formed prior to forming the p-well 20.
  • FIG. 2A a cross-sectional view shows the structure resulting after an epitaxial SiC layer 14 doped with an n-type dopant such as, for example, nitrogen to a concentration from between le 14/cm 3 to 2e 16/cm 3 has been formed on a SiC substrate 16 having a resistivity typically close to 0.02 ohm-cm using an epitaxy growth process as is known in the art.
  • a p-well 20 has been formed in the epitaxial layer 14.
  • the p-well 20 is doped with aluminum or boron with a dose of between about 5el2cm 2 and about lel5cm 2 .
  • FIG. 2B a cross-sectional view shows the structure resulting after a p-type doped extension (PEXT) region 26 has been formed using a masked implant process as is known in the art and the mask has been removed.
  • the PEXT region 26 has been implanted using a dopant species such as aluminum (or boron) with a dose of between about le 13/cm 2 to le 15/cm 2 , with an implant energy of from about 200 keV to 500 keV although the invention is not limited to this range.
  • the PEXT region 26 partially overlaps the p-well 20 in an area opposite where the channel of the transistor 12 of FIG.
  • the PEXT region 26 is generally more heavily doped than the p-well 20.
  • FIG. 2C a cross-sectional view shows the structure resulting after a shallow trench 28 has been formed in the epitaxial SiC layer 12 using
  • the shallow trench 28 has a length of about 20 pm to 50 pm, depending on the blocking voltage requirement, and is formed to a depth of about 2 pm to 5 pm.
  • the shallow trench 28 consumes a portion of the PEXT implant 26 as shown in FIG. 2C.
  • FIG. 2D a cross-sectional view shows the structure resulting after a p-type doped junction termination extension (JTE) region 30 has been formed in the trench 28 using a masked implant process as is known in the art and the mask has been removed.
  • the p-type doped JTE region 30 intersects the p-type extension region 26 and further extends beyond the edge of the trench 28 in the direction opposite the transistor 12 by at least 1 pm and typically extends beyond the edge of the trench 28 by between about 1 pm and about 5 pm.
  • FIG. 2D shows the JTE region 30 separately from the PEXT implant 26 to illustrate the edges of the mask used to perform the masked implant process.
  • the p-type doped JTE region 30 is doped with a species such as aluminum or boron, using an implant dose of from about lei 1/cm 2 to le 13 /cm 2 (typically about le 12/cm 2 ).
  • the doping of JTE region 30 is less than that of PEXT region 26, and further preferably 2 orders of magnitude less.
  • the junction depth may be about 1 pm.
  • FIG. 2E a cross-sectional view shows the structure resulting after an activation step has been performed to activate the implanted dopant atoms in PEXT region 26 and p-type doped JTE region 30.
  • FIG. 2F a cross-sectional view shows the structure resulting after a dielectric layer 32 has been formed from, for example, deposited silicon dioxide to a thickness of between about 1 pm to 3 pm over the surface of the structure including the PEXT and p-type doped JTE regions 26 and 30.
  • the dielectric layer 32 extends past the edges of the p-type doped JTE region 30.
  • a via 40 has been formed in the dielectric layer 32 using conventional semiconductor processing techniques to expose the upper surface of the PEXT region 26 outside of the edge of the shallow trench 28 as well as the source 18 of the transistor 12 and the p-well 20 (as shown in FIG. 1).
  • FIG. 2G a cross-sectional view shows the structure resulting after a metal layer 34 has been deposited and patterned using a metal such as, but not limited to, a stack of titanium and aluminum employing conventional semiconductor processing techniques over the surface of the structure and into the via 40 to make an electrical connection to the PEXT region 26 and to the source 18 of the transistor 12 and p-well 20 (as shown in FIG. 1).
  • the thickness of the metal layer 34 is typically between about 1 pm to 5 pm, depending on the application. Power devices will employ thicker metal layers. If the present invention is practiced in an integrated circuit then a 1 pm thick layer of the metal used for that technology will be satisfactory.
  • FIG. 2H a cross-sectional view shows the structure resulting after a dielectric layer 36 formed from a material such as silicon oxynitride has been deposited over the exposed portion of the dielectric layer 32 and the metal layer 34.
  • FIGS. 3 A and 3B illustrate how the present invention may be practiced using two other exemplary technologies.
  • FIG. 3 A shows an embodiment of the high-voltage termination structure of the present invention formed on a substrate 50.
  • Substrate 50 may be an n-type substrate and the PEXT region 26 and JTE region 30 may be p-type implants.
  • Substrate 50 may also be a p-type substrate and the PEXT region 26 and p-type doped JTE region 30 may be replaced with n-type regions.
  • FIG. 3B shows an embodiment of the high-voltage termination structure of the present invention formed in a well 52 formed in a substrate 50.
  • the well 52 may be an n- well formed in a p-type substrate 50 and the PEXT region 26 and JTE region 30 may be p-type regions.
  • the well 52 may also be a p-well formed in an n-type substrate and the PEXT region 26 and p-type doped JTE region 30 may be replaced with n-type regions.
  • the present invention may be employed in high-voltage designs where the output voltage nodes can support voltages up to about 10,000 V.

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Abstract

A high-voltage termination for a semiconductor device includes a substrate, an implanted device region, a shallow trench adjacent to the implanted device region, and a doped extension region between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region. A junction termination extension region is formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region. An insulating layer is formed over at least a portion of the extension region and over the junction termination extension region. A metal layer is formed over the insulating layer.

Description

SPACE EFFICIENT HIGH-VOLTAGE TERMINATION AND
PROCESS FOR FABRICATING THE SAME
TECHNICAL FIELD
[0001] The present invention relates to semiconductor device structures and
manufacturing processes. More particularly, the present invention relates to a high- voltage termination structure for a semiconductor device and to a process for fabricating that structure.
BACKGROUND
[0002] For voltage nodes carrying 600 V and higher, the high-voltage termination structure accounts for a significant portion of the die total footprint, in some cases amounting to more than half of the footprint. Hence, reducing the length of the
termination structure would reduce the size and cost of the dies.
[0003] Most of the prior-art high-voltage termination designs rely on floating field ring (FFR), junction termination extension (JTE), and/or deep trench designs. The FFR design provides a very robust termination however it has a large footprint (typically 10 times the thickness of the epitaxy). The JTE design is more compact (about 3 times the thickness of the epitaxy) but has the drawback of being highly sensitive to normal process variations. The deep trench design is very compact but expensive to fabricate in that it is difficult to control the dry etch process used.
BRIEF DESCRIPTION
[0004] The present invention relies on the combination of a shallow trench, a JTE region, and a field plate to provide a high breakdown voltage close to the full capability of the substrate, which may be a semiconductor substrate, a well formed in a semiconductor substrate or an epitaxial layer formed on a substrate.
[0005] The underlying principle is to suppress any high electric fields near convex junctions so that the avalanche breakdown of the termination is governed by the electric field of a planar junction.
[0006] The shallow trench allows the convex junction of the doped extension to be etched away. The JTE and field plate are designed to relax the electric field at the interface between the extension and the trench.
[0007] According to an aspect of the invention, a high-voltage termination for a semiconductor device includes a substrate of a first conductivity type, an implanted device region of a second conductivity type of the semiconductor device, a shallow trench disposed in the substrate adjacent to the implanted device region, a doped extension region of the second conductivity type extending between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region, a junction termination extension region of the second conductivity type formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer extending into at least a portion of the shallow trench and electrically connected to the extension region.
[0008] According to an aspect of the invention, a length of the shallow trench and the doped extension region together form a termination length of the high-voltage
termin tion·
[0009] According to an aspect of the invention, a second insulating layer is formed over the metal layer and the insulating layer.
[0010] According to an aspect of the invention, sidewalls of the shallow trench are at angles between about 45° and about 60°.
[0011] According to an aspect of the invention, the substrate of the first conductivity type is an epitaxial layer disposed over an underlying substrate.
[0012] According to an aspect of the invention, the epitaxial layer is an epitaxial SiC layer, and the underlying substrate is a SiC substrate.
[0013] According to an aspect of the invention, the epitaxial SiC layer is doped with nitrogen, and the underlying SiC substrate is doped with nitrogen.
[0014] According to an aspect of the invention, the epitaxial SiC layer is doped with nitrogen to a concentration of from about le 14/cm3 to about 2e 16/cm3, and the underlying SiC substrate is doped with nitrogen to a resistivity of about 0.02 ohm-cm.
[0015] According to an aspect of the invention, the extension region is implanted with one of aluminum and boron, and the junction termination extension region is implanted with one of aluminum and boron.
[0016] According to an aspect of the invention, the extension region is implanted with one of aluminum and boron with a dose of between about le 13/cm2 to about le 15/cm2, and the junction termination extension region is implanted with one of aluminum and boron with a dose of between about lei 1/cm2 to about le 13/cm2,
[0017] According to an aspect of the invention, the doping of the junction termination extension region is less than the doping of the extension region.
[0018] According to an aspect of the invention, the shallow trench has a depth of between about 2 pm to about 5 pm, and a termination length defined by a width of the shallow trench and an extension of the junction termination extension region beyond the trench is selected to withstand a preselected blocking voltage.
[0019] According to an aspect of the invention, the termination length is between about 21 pm to about 55 pm.
[0020] According to an aspect of the invention, a method for forming a high voltage termination in a semiconductor device includes providing a substrate of a first
conductivity type, performing an ion implantation to form an extension region of a second conductivity type opposite the first conductivity type in the substrate, forming a shallow trench in the substrate adjacent to an active area of the substrate, the shallow trench extending past an edge of the extension region, performing an ion implantation to form a junction termination extension region of the second conductivity type in the shallow trench and intersects the extension region, forming an insulating layer over the extension region and the junction termination extension region, and forming a metal layer formed over the insulating layer, the metal layer extending into the shallow trench, the metal layer electrically connected through a via in the insulating layer to the extension region.
[0021] According to an aspect of the invention, performing an ion implantation to form an extension region of a second conductivity type opposite the first conductivity type in the substrate comprises performing the ion implantation to form the extension region that extends from an edge of the shallow trench opposite the active area to define a
termination length for the high-voltage termin tion·
[0022] According to an aspect of the invention, forming a shallow trench in the substrate comprises forming a shallow trench in the substrate having sidewalls disposed at angles between about 45° and about 60°.
[0023] According to an aspect of the invention, providing a substrate of a first conductivity type comprises providing a SiC epitaxial layer over a SiC substrate.
According to an aspect of the invention, providing a substrate of a first conductivity type comprises providing a SiC epitaxial layer doped with nitrogen over a SiC substrate doped with nitrogen. According to an aspect of the invention, forming an extension region of a second conductivity type comprises performing an implantation with one of aluminum and boron, and with a dose of between about le 13/cm2 to about le 15/cm2, and forming the junction termination extension region of a second conductivity type comprises performing an implantation with one of aluminum and boron, and with a dose of between about lei 1/cm2 to about le 13/cm2, and the doping of the junction termination extension region is less than the doping of the extension region.
According to an aspect of the invention, a transistor with high-voltage termination, includes a substrate of a first conductivity type, an active area in the substrate including source and drain regions of the transistor, a gate disposed over the source and drain regions, a shallow trench disposed in the substrate adjacent to the active area of the substrate, a doped extension region of a second conductivity type, opposite the first conductivity type, formed in the substrate and extending from a first edge of the shallow trench and contacting the source of the transistor, a junction termination extension region of the second conductivity type formed in the shallow trench and contacting the extension region, the junction termination region extending past a second edge of the shallow trench opposite the first edge, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer, the metal layer extending into at least a portion of the shallow trench, the metal layer electrically connected through a via in the insulating layer to the extension region.
[0024] According to an aspect of the invention, the source region is disposed in a p-well formed in the substrate, and the doped extension region contacts the p-well. [0025] According to an aspect of the invention, a length of the shallow trench and the doped extension region together form a termination length of the high-voltage
termination for the transistor.
BRIEF DESCRIPTION OF THE DRAWING FIGURES
[0026] The invention will be explained in more detail in the following with reference to embodiments and to the drawing in which are shown:
[0027] FIG. 1 is a cross-sectional diagram of a portion of a semiconductor device including a high-voltage termination in accordance with an aspect of the present invention;
[0028] FIGS. 2A through 2H are cross-sectional diagrams of the high-voltage termination of FIG. 1 showing progressive steps in an illustrative fabrication process in accordance with an aspect of the present invention; and
[0029] FIG. 3A and 3B are cross-sectional diagrams of a portion of a semiconductor device including a high-voltage termination in accordance with an aspect of the present invention formed in different examples of substrates.
DETAIFED DESCRIPTION
[0030] Persons of ordinary skill in the art will realize that the following description is illustrative only and not in any way limiting. Other embodiments will readily suggest themselves to such skilled persons.
[0031] The present invention is particularly advantageous when employed with silicon carbide (SiC) Schottky diodes and SiC MOSFETS but persons of ordinary skill in the art will appreciate that the present invention can be used with other devices.
[0032] The word“substrate” is used herein and may have several meanings that will be apparent from the context in which it is used. A substrate may be the layer in which the implanted regions are directly formed. In some instances it may be a substrate with no overlying layers. In other instances it may be in the form of an epitaxial layer formed over an underlying substrate. In other instances it may be in the form of a well structure formed in an underlying substrate. In any event persons of ordinary skill in the art will be readily able to determine the meaning of“substrate” by examining the context in which it is used.
[0033] Referring first of all to FIG. 1, an illustrative embodiment of high-voltage termination 10 for a semiconductor device in accordance with an aspect of the present invention is shown in cross-sectional view along with a SiC MOSFET transistor 12 to be protected. The particular embodiment shown in FIG. 1 is formed on an SiC epitaxial layer 14 grown on a SiC substrate 16 in a conventional manner. In one embodiment of the invention, the thickness of the SiC substrate 16 is about 350 pm +/- 25pm. The substrate 16 is doped with an n-type dopant, such as nitrogen, to achieve a typical resistivity of 0.02 ohm-cm and the epitaxial layer 14 is doped with nitrogen to a typical concentration of about le 14/cm3 to 2e 16/cm3.
[0034] The thickness of the epitaxial layer 14 is chosen depending on the desired voltage rating, and the thickness of the epitaxial layer 14 varies approximately linearly with the desired voltage rating. In addition, a good approximation for a JTE termination is that it has a length equal to about 3 times the thickness of the epitaxial layer 14. For example, the thickness of the epitaxial layer 14 for a 1700 V rating should be about 13.5 pm-thick which results in a 40.5 pm-long JTE termination. The epitaxial layer 14 thicknesses for 700 V, 1,200 V, 3,300 V, and 6,500 V ratings are 5 pm, 10 pm, 30 pm, and 60 pm respectively.
[0035] The MOSFET transistor 12 has a source region 18 formed in a p-well 20 disposed in the epitaxial layer 14. In exemplary embodiments of the invention aluminum or boron is used for doping of the p-well 20. In one illustrative embodiment of the invention, the p-well 20 is doped with aluminum or boron with a dose of between about 5el2cm 2 and about lel5cm 2.
[0036] In the particular embodiment depicted in FIG. 1, the transistor 12 has a drain 22 formed on the back side of the substrate 16 and a gate 24 insulated from the surface of the epitaxial layer 14 as is known in the art. As will be appreciated by persons of ordinary skill in the art, the transistor 12 may take the form of an annular transistor or have other geometries such as, for example, long stripes. The present invention is applicable to all such transistor geometries.
[0037] A p-type doped extension (PEXT) region 26 is formed on the surface of the SiC epitaxial layer 14 and extends to and is connected to the p-well 20. The PEXT region 26 is doped with a species such as aluminum or boron. In one illustrative embodiment of the invention, the PEXT region 26 is doped with an implantation dose of about lel3cm 2 to lel5cm 2, although the present invention is not limited to this doping range. The PEXT region 26 is more heavily doped than the p-well 20. Junction depths of PEXT region 26 depend on the implantation energy which is usually between about 200 keV to 500 keV.
[0038] A shallow trench 28 having a length L and a depth D as shown in FIG. 1. The shallow trench 28 is formed in the upper surface of the SiC epitaxial layer 14 and intersects the PEXT region 26. In one embodiment the shallow trench 28 has a length L of about 20 pm to 50 pm. The shallow trench 28 is formed to a depth D of about 2 pm to 5 pm.
[0039] It has been found that the slope of the wall of the shallow trench 28 should be preferably optimized for any particular design and should preferably be between about 45° and about 60°. [0040] A p-type doped junction termination extension (JTE) region 30 is formed in the shallow trench 28 and intersects the PEXT region 26. The JTE region 30 additionally extends beyond the edge of the trench 28 in the direction opposite the transistor 12. The p-type doped JTE region 30 is implanted with a species such as aluminum (or boron), and a dose of about lei 1/cm2 to le 13 /cm2 (typically about le 12/cm2). Preferably the doping of JTE region 30 is less than that of PEXT region 26, and further preferably 2 orders of magnitude less. The junction depth of JTE region 30 is about 1 pm. It is necessary that for any given design the JTE implantation dose be selected to assure that the JTE region is fully“depleted” under the reverse bias applied to the device. A dielectric layer 32 formed from for example deposited silicon dioxide (oxide) to a thickness of between about 1 pm to 3 pm is disposed over a portion of the PEXT region 26 and over the JTE region 30.
[0041] A metal layer 34 is disposed over a portion of the dielectric layer 32 and extends into the trench 28. The metal layer 34 extends beyond the edge of the trench 28 towards the transistor 12 and is in electrical contact with the source 18 of the transistor 12, with the p-well 20 and with PEXT region 26 through a via. The metal layer 34 is formed from a metal such as but not limited to a stack of titanium and aluminum to a thickness of between about 1 pm to 5 pm, depending on the application. The targeted thickness is measured with respect to a flat surface, and then conforms to the topology. For high power devices the thickness of the metal layer 34 can be about 5 pm. If the present invention is incorporated into a low voltage integrated circuit, then a 1 pm thick layer of the metal used for that technology will be satisfactory. A dielectric layer 36 formed from a material such as oxynitride to a thickness of between about 1 pm and about 4 pm is disposed over the portion of the dielectric layer 32 not covered by metal layer 34 and over the metal layer 34. [0042] The length of the trench 28 plus the extension of the JTE region 30 beyond the edge of the trench 28 in the direction opposite the transistor 12 is referred to herein as the termination length. The JTE region 30 extends beyond the edge of the trench 28 in the direction opposite the transistor 12 by at least 1 pm and typically extends beyond the edge of the trench 28 by between about 1 pm and about 5 pm. The termination length is tailored to meet the blocking voltage requirement and is shown at arrows 38. In an embodiment where the blocking voltage is about 1,700V, the termination length 38 is about 40.5 pm. The termination length 38 scales linearly with blocking voltage.
[0043] The high-voltage termination of the present invention presents a narrower design than other solutions such as floating field ring designs. The metal layer 34 acts as a field plate to extend the applied voltage to a defined area and spreads the charge to reduce the electric field and avoid avalanche breakdown at relatively low voltages. The high-voltage termination of the present invention presents a blocking voltage close to the full capability of the epitaxial layer 14 and exhibits a lower leakage current, hence improved reliability. The breakdown voltage is significantly higher for the high voltage termination structure that spans the termination length 38 than for the active area of the transistor 12, resulting in a higher reliability under harsh electrical and environmental conditions.
[0044] Referring now to FIGS. 2A through 2H, a series of cross-sectional diagrams show the structure resulting after selected steps in an illustrative fabrication process have been performed. In the illustrative embodiment depicted in FIGS. 2A through 2H, the p-well 20 for the transistor 12 is shown as being formed prior to the PEXT region 26 and the JTE region 30. Persons of ordinary skill in the art will appreciate that embodiments of the invention are contemplated where the PEXT region 26 and the JTE region 30 are formed prior to forming the p-well 20.
[0045] Referring first to FIG. 2A, a cross-sectional view shows the structure resulting after an epitaxial SiC layer 14 doped with an n-type dopant such as, for example, nitrogen to a concentration from between le 14/cm3 to 2e 16/cm3 has been formed on a SiC substrate 16 having a resistivity typically close to 0.02 ohm-cm using an epitaxy growth process as is known in the art. A p-well 20 has been formed in the epitaxial layer 14. In one illustrative embodiment of the invention, the p-well 20 is doped with aluminum or boron with a dose of between about 5el2cm 2 and about lel5cm 2.
[0046] Referring now to FIG. 2B, a cross-sectional view shows the structure resulting after a p-type doped extension (PEXT) region 26 has been formed using a masked implant process as is known in the art and the mask has been removed. The PEXT region 26 has been implanted using a dopant species such as aluminum (or boron) with a dose of between about le 13/cm2 to le 15/cm2, with an implant energy of from about 200 keV to 500 keV although the invention is not limited to this range. The PEXT region 26 partially overlaps the p-well 20 in an area opposite where the channel of the transistor 12 of FIG. 1 will be formed and will result in the dopant concentration of that portion of the p-well 20 being higher than the portion of the p-well 20 that is proximate to the channel of the transistor 12 of FIG. 1. This will not affect the performance of the transistor 12. The PEXT region 26 is generally more heavily doped than the p-well 20.
[0047] Referring now to FIG. 2C, a cross-sectional view shows the structure resulting after a shallow trench 28 has been formed in the epitaxial SiC layer 12 using
conventional semiconductor processing techniques. In one embodiment of the invention the shallow trench 28 has a length of about 20 pm to 50 pm, depending on the blocking voltage requirement, and is formed to a depth of about 2 pm to 5 pm. The shallow trench 28 consumes a portion of the PEXT implant 26 as shown in FIG. 2C.
[0048] Referring now to FIG. 2D, a cross-sectional view shows the structure resulting after a p-type doped junction termination extension (JTE) region 30 has been formed in the trench 28 using a masked implant process as is known in the art and the mask has been removed. The p-type doped JTE region 30 intersects the p-type extension region 26 and further extends beyond the edge of the trench 28 in the direction opposite the transistor 12 by at least 1 pm and typically extends beyond the edge of the trench 28 by between about 1 pm and about 5 pm. FIG. 2D shows the JTE region 30 separately from the PEXT implant 26 to illustrate the edges of the mask used to perform the masked implant process.
[0049] The p-type doped JTE region 30 is doped with a species such as aluminum or boron, using an implant dose of from about lei 1/cm2 to le 13 /cm2 (typically about le 12/cm2). Preferably the doping of JTE region 30 is less than that of PEXT region 26, and further preferably 2 orders of magnitude less. The junction depth may be about 1 pm.
[0050] Referring now to FIG. 2E, a cross-sectional view shows the structure resulting after an activation step has been performed to activate the implanted dopant atoms in PEXT region 26 and p-type doped JTE region 30.
[0051] Referring now to FIG. 2F, a cross-sectional view shows the structure resulting after a dielectric layer 32 has been formed from, for example, deposited silicon dioxide to a thickness of between about 1 pm to 3 pm over the surface of the structure including the PEXT and p-type doped JTE regions 26 and 30. The dielectric layer 32 extends past the edges of the p-type doped JTE region 30. A via 40 has been formed in the dielectric layer 32 using conventional semiconductor processing techniques to expose the upper surface of the PEXT region 26 outside of the edge of the shallow trench 28 as well as the source 18 of the transistor 12 and the p-well 20 (as shown in FIG. 1).
[0052] Referring now to FIG. 2G, a cross-sectional view shows the structure resulting after a metal layer 34 has been deposited and patterned using a metal such as, but not limited to, a stack of titanium and aluminum employing conventional semiconductor processing techniques over the surface of the structure and into the via 40 to make an electrical connection to the PEXT region 26 and to the source 18 of the transistor 12 and p-well 20 (as shown in FIG. 1). The thickness of the metal layer 34 is typically between about 1 pm to 5 pm, depending on the application. Power devices will employ thicker metal layers. If the present invention is practiced in an integrated circuit then a 1 pm thick layer of the metal used for that technology will be satisfactory.
[0053] Referring now to FIG. 2H, a cross-sectional view shows the structure resulting after a dielectric layer 36 formed from a material such as silicon oxynitride has been deposited over the exposed portion of the dielectric layer 32 and the metal layer 34.
[0054] Persons of ordinary skill in the art will appreciate that while the present invention has been disclosed using illustrative embodiments where p-type implants are used in n- type substrates and wells, it should be apparent that embodiments that employ n-type implants in p-type substrates and wells are contemplated to be within the scope of the present invention.
[0055] Persons of ordinary skill in the art will appreciate that the SiC epitaxial layer 14 over SiC substrate 16 embodiment described with reference to FIGS. 1 and 2A through 2H is illustrative only and is non-limiting. Such skilled persons will appreciate that the high-voltage termination structure of the present invention may be formed using other technologies. FIGS. 3 A and 3B illustrate how the present invention may be practiced using two other exemplary technologies.
[0056] FIG. 3 A shows an embodiment of the high-voltage termination structure of the present invention formed on a substrate 50. Substrate 50 may be an n-type substrate and the PEXT region 26 and JTE region 30 may be p-type implants. Substrate 50 may also be a p-type substrate and the PEXT region 26 and p-type doped JTE region 30 may be replaced with n-type regions.
[0057] FIG. 3B shows an embodiment of the high-voltage termination structure of the present invention formed in a well 52 formed in a substrate 50. The well 52 may be an n- well formed in a p-type substrate 50 and the PEXT region 26 and JTE region 30 may be p-type regions. The well 52 may also be a p-well formed in an n-type substrate and the PEXT region 26 and p-type doped JTE region 30 may be replaced with n-type regions.
[0058] The present invention may be employed in high-voltage designs where the output voltage nodes can support voltages up to about 10,000 V.
[0059] While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

What is claimed is:
1. A high-voltage termination for a semiconductor device comprising:
a substrate of a first conductivity type;
an implanted device region of a second conductivity type, opposite the first conductivity type, forming a part of the semiconductor device;
a shallow trench disposed in the substrate adjacent to the implanted device region;
a doped extension region of the second conductivity type formed in the substrate, the doped extension region extending between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region;
a junction termination extension region of the second conductivity type formed in the shallow trench and contacting the extension region, the junction
termination region extending past a second edge of the shallow trench opposite the implanted device region;
an insulating layer formed over at least a portion of the extension region and over the junction termination extension region; and
a metal layer formed over the insulating layer, the metal layer extending into at least a portion of the shallow trench, the metal layer electrically connected through a via in the insulating layer to the extension region.
2. The high-voltage termination of claim 1 wherein a length of the shallow trench and the doped extension region together form a termination length of the high- voltage termination.
3. The high-voltage termination of claim 1 further comprising a second insulating layer formed over the metal layer and the insulating layer.
4. The high-voltage termination of claim 1 wherein sidewalls of the shallow trench are at angles between about 45° and about 60°.
5. The high-voltage termination of claim 1 wherein the substrate of the first conductivity type is an epitaxial layer disposed over an underlying substrate.
6. The high-voltage termination of claim 5 wherein:
the epitaxial layer is an epitaxial SiC layer; and
the underlying substrate is a SiC substrate.
7. The high-voltage termination of claim 6 wherein:
the epitaxial SiC layer is doped with nitrogen; and
the underlying SiC substrate is doped with nitrogen.
8. The high-voltage termination of claim 7 wherein:
the epitaxial SiC layer is doped with nitrogen to a concentration of from about le 14/cm3 to about 2e 16/cm3; and
the underlying SiC substrate is doped with nitrogen to a resistivity of about
0.02 oh -cm.
9. The high-voltage termination of claim 1 wherein:
the extension region is implanted with one of aluminum and boron; and the junction termination extension region is implanted with one of aluminum and boron.
10. The high-voltage termination of claim 9 wherein:
the extension region is implanted with one of aluminum and boron with a dose of between about le 13/cm2 to about le 15/cm2; and
the junction termination extension region is implanted with one of aluminum and boron with a dose of between about lei 1/cm2 to about le 13/cm2,
wherein the doping of the junction termination extension region is less than the doping of the extension region.
11. The high-voltage termination of claim 1 wherein:
the shallow trench has a depth of between about 2 pm to about 5 pm; and a termination length defined by a width of the shallow trench and an extension of the junction termination extension region beyond the trench is selected to withstand a preselected blocking voltage.
12. The high-voltage termination of claim 1 wherein the termination length is between about 21 pm to about 55 pm.
13. A method for forming a high voltage termination for a semiconductor device comprising:
providing a substrate of a first conductivity type, the substrate having a semiconductor device including at least one implanted device region;
performing an ion implantation to form an extension region of a second conductivity type opposite the first conductivity type in the substrate, the extension region contacting the at least one implanted device region;
forming a shallow trench in the substrate, the shallow trench having a first edge defining an end of the extension region; performing an ion implantation to form a junction termination extension region of the second conductivity type in the shallow trench, the junction termination extension region connected to the extension region;
forming an insulating layer over the extension region and the junction termination extension region; and
forming a metal layer formed over the insulating layer, the metal layer extending into the shallow trench, the metal layer electrically connected through a via in the insulating layer to the extension region.
14. The method of claim 13 wherein performing the ion implantation to form the junction termination extension region of the second conductivity type opposite the first conductivity type in the substrate comprises performing the ion implantation to form the junction termination extension region that extends from a second edge of the shallow trench opposite the first edge to define a termination length for the high-voltage termin tion.
15. The method of claim 13 wherein:
forming the shallow trench in the substrate comprises forming the shallow trench in the substrate having sidewalls disposed at angles between about 45° and about 60°.
16. The method of claim 13 wherein:
providing a substrate of a first conductivity type comprises providing a SiC epitaxial layer over a SiC substrate.
17. The method of claim 16 wherein providing the substrate of the first conductivity type comprises providing a SiC epitaxial layer doped with nitrogen over a SiC substrate doped with nitrogen.
18. The method of claim 16 wherein:
forming the extension region of the second conductivity type comprises performing an implantation with one of aluminum and boron, and with a dose of between about le 13/cm2 to about le 15/cm2; and
forming the junction termination extension region of the second conductivity type comprises performing an implantation with one of aluminum and boron, and with a dose of between about lei 1/cm2 to about le 13/cm2:
wherein the doping of the junction termination extension region is less than the doping of the extension region
19. A transistor with high-voltage termination, comprising:
a substrate of a first conductivity type;
an active area in the substrate including source and drain regions of the transistor;
a gate disposed over the source and drain regions;
a shallow trench disposed in the substrate adjacent to the active area of the substrate;
a doped extension region of a second conductivity type, opposite the first conductivity type, formed in the substrate and extending from a first edge of the shallow trench and contacting the source of the transistor;
a junction termination extension region of the second conductivity type formed in the shallow trench and contacting the doped extension region, the junction termination region extending past a second edge of the shallow trench opposite the first edge in a direction away from the active area;
an insulating layer formed over at least a portion of the extension region and over the junction termination extension region; and
a metal layer formed over the insulating layer, the metal layer extending into at least a portion of the shallow trench, the metal layer electrically connected through a via in the insulating layer to the extension region.
20. The transistor of claim 19 wherein:
the source region is disposed in a p-well formed in the substrate; and the doped extension region contacts the p-well,
wherein the extension region is doped to a greater concentration than both the p-well and the junction termination extension region.
21. The high-voltage termination of claim 19 wherein a length of the shallow trench and the extension of the junction termination region past the second edge of the shallow trench together form a termination length of the high-voltage termination for the transistor.
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