GB2563110A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Silicon carbide semiconductor device and manufacturing method thereof Download PDF

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Publication number
GB2563110A
GB2563110A GB1801487.8A GB201801487A GB2563110A GB 2563110 A GB2563110 A GB 2563110A GB 201801487 A GB201801487 A GB 201801487A GB 2563110 A GB2563110 A GB 2563110A
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region
conductor portion
element isolation
semiconductor
silicon carbide
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GB2563110B (en
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Masunaga Masahiro
Shima Akio
Sato Shintaroh
Kuwana Ryo
Shinma Daisuke
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L28/20—Resistors

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device includes a semiconductor element 1 formed on a surface of a silicon carbide (SiC) semiconductor substrate 2, an element isolation layer 3 formed in the surface of the substrate 2 surrounding a periphery of the semiconductor element 1, and a conductor portion 5, which may be a field plate (Fig. 8: 29), formed just above the element isolation layer via an insulating layer 4, and electrically connected to the element isolation layer via a contact plug (Fig. 2: 7). Charge trapping due to ionising radiation in the insulator layer 4 disposed between the conductor portion 5 and element isolation region, is reduced. The conductor portion 5 may be just below a wiring layer (Fig. 4: 10). The semiconductor element may be a MOSFET, with n-type source and drain regions (Fig. 8: 12, 13) formed in a p-well (Fig. 8: 18) at the surface of an epitaxial SiC substrate (Fig. 8: 17), and the isolation layer 3 may be formed by p-type doping of the SiC substrate to a high doping concentration compared to that of the p-well region 18. In another embodiment, the semiconductor element comprises a diffusion resistor formed from a low doped region (Fig. 18: 19) in contact with a high doped region (Fig. 18: 20) with impurity concentration higher than 1 * 1018 cm-3 in the surface of the SiC substrate 2. The conductor portion 5 is formed above the high doped region (Fig. 18: 20) rather than an element isolation layer, and is electrically connected to the high doped region.

Description

SPECIFICATION
TITLE OF THE INVENTION
SILICON CARBIDE SEMICONDUCTOR DEVICE
AND
MANUFACTURING METHOD THEREOF
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, for example, a silicon carbide semiconductor device exposed to a high-radiation environment.
BACKGROUND OF THE INVENTION
Currently, many of manufactured industrial products have adopted semiconductor elements made of silicon (hereinafter, referred to as Si) , and the performance thereof has been greatly improved along with the progress of Si. Meanwhile, general-purpose Si devices cannot be applied to the products exposed to a severe environment such as a high-radiation field, and thus the development of semiconductor elements capable of operating under the severe environment is awaited.
Patent Document 1 (Japanese Patent Application Laid-Open Publication No. S62-133726) discloses a silicon carbide semiconductor device provided with an oxide film with radiation resistance .
SUMMARY OF THE INVENTION
There are two main influences exerted by radiation on semiconductor devices. One is the interface state formed at an interface between a semiconductor and an insulating film, and the other is the increase of trapped charges in an insulating film. 1
Silicon carbide (hereinafter, referred to as SiC) is a compound semiconductor made of Si and carbon, and a band gap thereof is three times as large as that of Si. Therefore, as for the interface state formed at the interface between the semiconductor and the insulating film, the increase of the leakage current flowing through the interface state on a semiconductor side can be suppressed. On the other hand, the same insulating material as that of the Si device is used for the insulating film in many cases, and the influence due to the trapped charges still exists as a problem.
Patent Document 1 describes that positive charges generated by ionizing radiation and trapped can be reduced by covering a field oxide film formed on a main surface of a semiconductor substrate with a silicon nitride film and a silicon oxide film. However, the device described in Patent Document 1 cannot suppress the invasion of γ ray, and thus has a problem of being incapable of reducing the generation of accumulated charges. An object of the present invention is to provide a silicon carbide semiconductor device capable of maintaining an isolation property of an element isolation for a long period in an SiC device exposed to a high-radiation environment.
The above and other objects and novel characteristics of the present invention will be apparent from the description of the present specification and the accompanying drawings.
The following is a brief description of an outline of the typical invention disclosed in the present application.
A silicon carbide semiconductor device according to a representative embodiment includes: a semiconductor substrate having a semiconductor element provided in the vicinity of a main surface thereof; an element isolation layer formed on the main surface of the semiconductor substrate and surrounding the periphery of the semiconductor element; an insulating layer formed on an upper surface of the element isolation layer; and a conductor portion 2 formed in the insulating layer, and the conductor portion and the element isolation layer are electrically connected to each other.
According to the representative embodiment, it is possible to improve the reliability of the silicon carbide semiconductor device. In particular, holes generated by γ ray are less likely to be trapped in an oxide film, and it is thus possible to maintain the element isolation for a long period.
BRIEF DESCRIPTIONS OF THE DRAWINGS
FIG. 1 is cross-sectional view showing a silicon carbide semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a planar layout of the silicon carbide semiconductor device according to the first embodiment of the present invention;
FIG. 3 is a graph showing a change in relationship between a gate voltage and a capacity ratio of a gate and an oxide film;
FIG. 4 is a cross-sectional view showing a silicon carbide semiconductor device according to a second embodiment of the present invention;
FIG. 5 is a planar layout of the silicon carbide semiconductor device according to the second embodiment of the present invention;
FIG. 6 is a graph showing a relationship between a maximum electric field at an interface between SiC and an insulating film and an overhang amount of a conductor portion;
FIG. 7 is a planar layout of a silicon carbide semiconductor device according to a third embodiment of the present invention;
FIG. 8 a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention;
FIG. 9 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention in a manufacturing process;
FIG. 10 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention in the manufacturing process continued from FIG. 9;
FIG. 11 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention in the manufacturing process continued from FIG. 10;
FIG. 12 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention in the manufacturing process continued from FIG. 11;
FIG. 13 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention in the manufacturing process continued from FIG. 12;
FIG. 14 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention in the manufacturing process continued from FIG. 13;
FIG. 15 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention in the manufacturing process continued from FIG. 14;
FIG. 16 is a cross-sectional view showing a silicon carbide semiconductor device according to a modification example of the third embodiment of the present invention;
FIG. 17 is a cross-sectional view showing a silicon carbide semiconductor device according to a fourth embodiment of the present invention;
FIG. 18 is a cross-sectional view showing the silicon carbide semiconductor device according to the fourth embodiment of the 4 present invention;
FIG. 19 is a cross-sectional view showing a silicon carbide semiconductor device according to a comparative example; and
FIG. 20 is a graph showing a change in relationship between a gate voltage and a capacity ratio of a gate and an oxide film.
DESCRIPTIONS OF THE PREFERRED EMBODIMENTS
Hereinafter, embodiments of the present invention will be described in detail based on drawings. Note that components having the same function are denoted by the same reference characters throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In addition, the description of the same or similar portions is not repeated in principle unless particularly required in the following embodiments
Also, reference symbols and + represent relative concentrations of an impurity of an n or p conductivity type, and for example, the impurity concentration becomes higher in an order of n_, n and n+ in the case of an n type impurity.
(First Embodiment) <Structure of Silicon Carbide Semiconductor Device>
FIG. 1 shows a cross-sectional view of a silicon carbide semiconductor device according to a first embodiment of the present invention.
As shown in FIG. 1, the silicon carbide semiconductor device according to the present embodiment includes a semiconductor substrate 2 made of SiC (silicon carbide). A semiconductor element 1 is integrated on a main surface of the semiconductor substrate 2. Namely, the semiconductor substrate 2 is an SiC substrate having the main surface and a back surface opposite to the main surface, and a plurality of the semiconductor elements 1 are arranged in the vicinity of the main surface. Note that FIG. 1 illustrates only one semiconductor element 1.
The semiconductor substrate 2 may be a laminated substrate made up of an SiC substrate and an epitaxial layer (semiconductor layer) formed on the SiC substrate. The laminated substrate including an epitaxial layer may be referred to as a semiconductor substrate. The semiconductor element 1 may be made up of only a semiconductor region formed on the main surface (upper surface) of the semiconductor substrate 2, and may include the semiconductor region formed on the main surface of the semiconductor substrate 2 and electrodes and others formed on the main surface. The electrodes may be buried in trenches formed in the main surface of the semiconductor substrate 2.
Examples of the semiconductor element 1 include elements such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: MOS field effect transistor), a diode, and a BJT (Bipolar Junction Transistor) . The semiconductor element 1 has a current path in the semiconductor substrate 2 and needs to be isolated from other regions or elements by an element isolation layer (element isolation region, element isolation portion) 3.
The element isolation layer 3 surrounding the periphery of the semiconductor element 1 is formed on the main surface of the semiconductor substrate 2, and an insulating layer 4 covering an upper surface of the element isolation layer 3 and a conductor portion (conductive film) 5 formed in the insulating layer 4 are formed on the semiconductor substrate 2. The conductor portion 5 and the element isolation layer 3 are electrically connected to each other. The element isolation layer 3 has an annular shape in a plan view. There may be one or more semiconductor elements 1 disposed inside the annular element isolation layer 3 in a plan view. In this case, the conductor portion 5 is formed just above the element isolation layer 3. The periphery of the conductor portion 5 is covered with the insulating layer 4. The insulating layer 4 serving as an interlayer insulating film is mainly made of, 6
The back surface of the for example, a silicon oxide film.
semiconductor substrate 2 is covered with a back surface electrode in contact with the back surface. The back surface electrode 6 is made of, for example, a metal film containing gold (Au).
FIG. 2 is a planar layout of the silicon carbide semiconductor device according to the present embodiment. The insulating layer on the semiconductor substrate is not illustrated in FIG. 2. As shown in FIG. 2, the element isolation layer 3 has an annular structure so as to surround the periphery of the semiconductor element 1 having a rectangular layout in a plan view. The conductor portion 5 on the element isolation layer 3 extends along three sides of the element isolation layer 3 having an annular structure with a rectangular shape, and the element isolation layer 3 and the conductor portion 5 are overlapped with each other in a plan view.
Namely, the element isolation layer 3 has a frame-like layout including two extension portions extending in an X direction which is a direction along the main surface of the semiconductor substrate (see FIG. 1) and two extension portions extending in a Y direction which is another direction along the main surface of the semiconductor substrate 2. The X direction and the Y direction are orthogonal to each other. The conductor portion 5 has a U-shaped layout including two extension portions extending in the X direction and one extension portion extending in the Y direction. End portions on one side of the two extension portions extending in the X direction are connected to end portions on both sides of the extension portion constituting the conductor portion 5 and extending in the Y direction, respectively.
From the viewpoint that an electric field applied to the insulating layer 4 (see FIG. 1) between the element isolation layer and the conductor portion 5 is brought close to 0, it is preferable that the conductor portion 5 is also formed into an annular shape along the shape of the element isolation layer 3; however, the 7 effect of the present embodiment to be described later can be achieved if the conductor portion 5 is formed in a region 9 in which a high electric field is applied to the insulating layer 4. In FIG. 2, an outline of the region 9 is indicated by a broken line.
A width in a short-side direction of the conductor portion 5 extending in a predetermined direction is larger than a width in a short-side direction of the element isolation layer 3 extending in the predetermined direction. Accordingly, in the short-side direction, the end portion of the conductor portion 5 overhangs outward from the end portion of the element isolation layer 3. In other words, in a direction along the main surface of the semiconductor substrate 2 (lateral direction, horizontal direction), the position where the conductor portion 5 terminates is closer to the semiconductor element 1 than the position where the element isolation layer 3 terminates is. This is because if the region in which the conductor portion 5 is not formed just above the element isolation layer 3 is present in the region 9 to which a high electric field is applied, the high electric field is applied to the insulating layer 4 in that region, so that positive charges are accumulated when irradiated with the γ ray.
Plugs (conductive connecting portion) 7 are formed just above the conductor portion 5 and just above the element isolation layer 3 exposed from the conductor portion 5, respectively, and the plugs 7 are formed to penetrate through the insulating layer 4. Upper surfaces of the plugs 7 are connected to a lower surface of one wiring 8. Therefore, the conductor portion 5 and the element isolation layer 3 are electrically connected through the two plugs 7 and the wiring 8. The plug 7 connected to the conductor portion 5 is formed just above the extension portion constituting the conductor portion 5 and extending in the Y direction.
<Effect of Present Embodiment>
Hereinafter, a comparative example will be described with 8 reference to FIGs. 19 and 20, and the effect of the present invention will be described. FIG. 19 is a cross-sectional view showing a silicon carbide semiconductor device according to a comparative example. FIG. 20 is a graph showing a change in relationship between a gate voltage and a capacity ratio of a gate and an oxide film when irradiating the silicon carbide semiconductor device according to the comparative example with the γ ray.
The silicon carbide semiconductor device shown in FIG. 19 includes the semiconductor substrate 2 which is an SiC substrate, the back surface electrode 6 which covers the back surface of the semiconductor substrate 2, and a MOSFET formed in the vicinity of the main surface of the semiconductor substrate 2. The MOSFET includes a source region 12 and a drain region 13 formed on the main surface of the semiconductor substrate 2, and a gate electrode 14 formed on the main surface via an insulating film 24 serving as a gate insulating film. The gate electrode 14 is formed just above the upper surface of the semiconductor substrate 2 between the source region 12 and the drain region 13. The gate electrode 14 is covered with a silicon nitride film 26 and an insulating layer 27 formed in order on the insulating film 24. The insulating layer 27 serving as an interlayer insulating film is made of, for example, a silicon oxide film.
The MOSFET is isolated from other elements by a field oxide film (element isolation portion) 25. The field oxide film 25 is an insulating layer made of a silicon oxide film formed by oxidizing the main surface of the semiconductor substrate 2 by, for example, the LOCOS (Local Oxidation of Silicon) method. The field oxide film 25 is formed to be thicker than the insulating film 24 and others, and the isolation between the elements is achieved by the field oxide film 25 formed by eroding a part of the main surface of the semiconductor substrate 2.
The field oxide film 25 is covered with the silicon nitride film 2 6 and the insulating layer 27 formed in order. The silicon nitride film 26 and the insulating layer 27 are opened just above each of the source region 12 and the drain region 13, and plugs connected to the source region 12 and the drain region 13 are formed in the openings. The plug connected to the source region 12 is connected to a source electrode (source wiring) 15 on the insulating layer 27. Also, the plug connected to the drain region 13 is connected to a drain electrode (drain wiring) 16 on the insulating layer 27.
Subsequently, generation of accumulated charges due to the γ ray will be described. The γ ray is a type of radiation and is an electromagnetic wave with a wavelength shorter than 10 pm. Since the γ ray has high permeability to substances, when irradiating the silicon carbide semiconductor device shown in FIG. 19 with the γ ray, the γ ray penetrates through the insulating layer 27 made of a silicon oxide film and the silicon nitride film 26 to reach the field oxide film 25, and electron-hole pairs are generated in the field oxide film 25. The electrons and holes thus generated are affected by the electric field in the field oxide film 25, and drift (move) to the side with lower potential energy. Holes are lower in mobility than electrons, and are thus more likely to be trapped at the hole-trapped center and are more likely to be accumulated as positive charges in the field oxide film 25.
Namely, although the element isolation is achieved by increasing the film thickness of the field oxide film 25 in the silicon carbide semiconductor device according to the comparative example, the γ ray generates positive charges in the silicon oxide film. Therefore, in order to obtain high reliability by maintaining the element isolation property of the element isolation portion for a long period under the γ ray irradiation environment, it is important to reduce the positive charges trapped in the insulating layer in contact with the upper surface of the semiconductor 10 substrate 2 in the element isolation portion. The insulating layer in contact with the upper surface of the semiconductor substrate 2 in the element isolation portion corresponds to the field oxide film 25 shown in FIG. 19 in this comparative example.
FIG. 2 0 is a graph showing the comparison of capacity characteristics when irradiating the MOSFET using SiC as a material with the γ ray. The horizontal axis of the graph represents the gate voltage of the MOSFET. The vertical axis of the graph represents the ratio of the capacity of the gate electrode and the capacity of the oxide film (insulating film). In this graph, the solid line indicates the flat band voltage in the state before the irradiation of the γ ray, that is, in the case where the amount of radiation of the γ ray is 0 kGy, and the broken line indicates the flat band voltage in the state where the γ ray has been irradiated, that is, in the case where the amount of radiation of the γ ray is 100 kGy. The insulating film mentioned here corresponds to, for example, the insulating layer 27 constituting the interlayer insulating film, the silicon nitride film 26, or the field oxide film 25 serving as the element isolation layer shown in FIG. 19.
In the case of irradiating the insulating film with the γ ray of 100 kGy under the condition that 3.0 MV/cm is applied from outside, the flat band voltage after the irradiation has shifted
6.5 V in parallel toward the negative side compared with that before the irradiation. This indicates that the surface potential of the insulating film is changed by trapping the positive charges in the insulating film. The reduction in the flat band voltage is equivalent to the reduction in the net impurity concentration of the surface of the SiC substrate, and this leads to the occurrence of the erroneous turn-on of the parasitic MOSFET and the decrease in reliability of the element isolation layer.
Namely, when the silicon carbide semiconductor device is irradiated with the γ ray, positive charges are accumulated in the 11 field oxide film 25 which is an insulating film made of a silicon oxide film shown in FIG. 19. As a result, electrons are induced on the main surface of the semiconductor substrate 2 in contact with the field oxide film 25, so that a current is likely to flow between the MOSFET and other elements and the element isolation property of the field oxide film 25 is deteriorated. In the parasitic MOSFET mentioned above, for example, the drain electrode 16 functions as a gate electrode, and the drain electrode 13 which is an n+ type semiconductor region and another n+ type semiconductor region formed on the main surface of the semiconductor substrate 2 in a different region (not shown) are provided as source/drain regions. When positive charges are accumulated in the field oxide film 25 between the source/drain regions, a channel is likely to be formed on the main surface of the semiconductor substrate 2 just below the field oxide film 25, and the parasitic MOSFET is brought into an ON state, with the result of the occurrence of the erroneous turn-on mentioned above.
The decrease in the reliability of the element isolation has a high possibility of causing not only the functional loss as the silicon carbide semiconductor device but also the serious damage on the system in which the silicon carbide semiconductor device is introduced. Therefore, in the silicon carbide semiconductor device exposed to a high-radiation environment in particular, it is important to prevent the decrease in reliability due to radiation exposure. The main reason why the above-described problem occurs in the comparative example is that the insulating film has a high electric field and is thus in a state of easily accumulating positive charges.
On the other hand, one of main characteristics of the present embodiment is that the conductor portion 5 is provided on the element isolation layer 3 via the insulating layer 4 and the conductor portion 5 and the element isolation layer 3 are 12 electrically connected to each other. With this configuration, the electric field of the insulating layer 4 sandwiched between the element isolation layer 3 and the conductor portion 5 can be brought much close to 0. Thus, it is possible to make it difficult to trap the holes generated when the silicon carbide semiconductor device is irradiated with the γ ray which is a type of radiation, as the positive charges. Further, holes are trapped in the insulating layer 4 on the side of the other main surface (upper surface) of the conductor portion 5 due to the influence of external electric field, but since positive charges to be trapped can be kept away from the main surface of the semiconductor substrate 2, the influence of the surface potential can be reduced.
Here, FIG. 3 is a graph showing a change in relationship between a gate voltage and a capacity ratio of a gate and an oxide film in the case where the silicon carbide semiconductor device of the present embodiment is irradiated with the γ ray. The graph of FIG. 3 shows the capacity characteristics when irradiating the MOSFET using SiC as a material with the γ ray of 100 kGy, and actual measurement is performed under the condition that no external voltage is applied to the insulating film unlike the measurement conditions described with reference to FIG. 20. Namely, the voltage applied to the insulating film is 0 V. The insulating film mentioned here corresponds to the insulating layer 4 between the element isolation layer 3 and the conductor portion 5.
In FIG. 3, the solid line indicates the flat band voltage before the irradiation of the γ ray and the broken line indicates the flat band voltage after the irradiation of the γ ray as in FIG.
20. In addition, the gate capacity of the vertical axis of FIG. 3 is the capacity in the case where the conductor portion 5 shown in FIG. 1 is taken as the gate electrode, and the capacity of the oxide film of the vertical axis corresponds to the capacity of the insulating layer 4 between the element isolation layer 3 and the 13 conductor portion 5 shown in FIG. 1.
In the graph shown in FIG. 3, since there is a difference between the work function of the gate electrode and the work function of SiC, a weak electric field in accordance with the work function difference is applied to the insulation film, but the capacity characteristics before the irradiation and after the irradiation almost coincide with each other irrespective of the integrated dose up to 100 kGy. This is probably because the electron-hole pairs generated by the γ ray are re-coupled without drifting in the insulating film and are not trapped as positive charges. Namely, by adopting the structure in which application of an electric field to the insulating film is prevented as much as possible, the influence due to the exposure to the γ ray can be suppressed. In other words, the tolerated dose against the γ ray of the silicon carbide semiconductor device can be improved, so that the reliability of the silicon carbide semiconductor device can be improved.
Also, in this case, instead of forming only the element isolation portion made of an insulating film as the element isolation region, the element isolation layer 3 is formed of the semiconductor region formed by introducing an n type or p type impurity into the main surface of the semiconductor substrate 2. An insulating layer such as a silicon oxide film is made of a material in which electron-hole pairs are more likely to be generated when irradiated with the γ ray and positive charges are more likely to be accumulated in comparison with the semiconductor region. Thus, in the present embodiment, from the viewpoint of preventing the accumulation of the positive charges, the element isolation layer 3 is formed of the semiconductor region, thereby suppressing the accumulation of the positive charges in the element isolation region.
(Second Embodiment)
FIG. 4 shows a cross-sectional view of a silicon carbide semiconductor device according to a second embodiment of the present invention. Also, FIG. 5 shows a planar layout of the silicon carbide semiconductor device according to the second embodiment of the present invention.
As shown in FIG. 4 and FIG. 5, the silicon carbide semiconductor device according to the present embodiment is different from that of the first embodiment described above in that an electrode wiring 10 is formed just above the conductor portion 5 via the insulating layer 4. The electrode wiring 10 is insulated from the conductor portion 5 and the element isolation layer 3. The electrode wiring 10 is formed just above the element isolation layer 3, and extends along the conductor portion 5 and is arranged to be overlapped with the conductor portion 5 in a plan view. In other words, the conductor portion 5 is arranged in a part or entire region sandwiched between the electrode wiring 10 and the element isolation layer 3.
The electrode wiring 10 has a U-shaped layout including two extension portions extending in the X direction and one extension portion extending in the Y direction. As shown in FIG. 5, the plugs 7 connected to the conductor portion 5 are arranged just above end portions on one side of the two extension portions constituting the conductor portion 5 and extending in the X direction, the end portions being on an opposite side of the extension portion constituting the conductor portion 5 and extending in the Y direction.
The electrode wiring 10 is connected to, for example, the semiconductor element 1, and an electric field of the insulating layer 4 around the electrode wiring 10 is likely to be increased due to the influence of a potential of the electrode wiring 10.
Accordingly, in the region in which the electrode wiring 10 is formed, in particular, the accumulation of positive charges due to 15 irradiation of the γ ray to the insulating layer 4 having high electric field needs to be prevented.
In this case, the electric field of the insulating layer 4 in the vicinity of the element isolation layer 3 can be brought close to 0 by forming the conductor portion 5 electrically connected to the element isolation layer 3 between the electrode wiring 10 and the element isolation layer 3 just below the electrode wiring
10. Accordingly, it is possible to prevent the accumulation of the positive charges in the insulating layer 4 due to the irradiation of the γ ray.
Also, in a short-side direction of the conductor portion 5 extending along the element isolation layer 3, an end portion of the conductor portion 5 overhangs outward from an end portion of the electrode wiring 10. In other words, in a lateral direction, a width of the conductor portion 5 in the short-side direction is larger than that of the electrode wiring 10, and a position where the conductor portion 5 terminates is closer to the semiconductor element 1 than a position where the electrode wiring 10 terminates is. A length (overhang amount) 11 between the end portion of the conductor portion 5 and the end portion of the electrode wiring 10 in that direction is 0.2 pm or larger. In the direction perpendicular to the main surface of the semiconductor substrate 2 (perpendicular direction, longitudinal direction, vertical direction), the conductor portion 5 is arranged without fail between the electrode wiring 10 and the element isolation layer 3.
FIG. 6 is a graph showing a relationship between a maximum electric field at an interface between SiC and an insulating film and the overhang amount 11 of the conductor portion 5 with respect to the electrode wiring 10. Namely, the horizontal axis of the graph shown in FIG. 6 represents the length (overhang amount) 11 shown in FIG. 5, and the vertical axis represents the maximum electric field at the interface between the SiC (semiconductor substrate 2) and the insulating film (insulating layer 4). FIG. 6 shows the results calculated by simulations. In FIG. 6, the graph of low voltage in the case where the power supply voltage is relatively low is indicated by plots of white triangles, the graph of intermediate voltage in the case where the power supply voltage is higher than the low voltage is indicated by plots of white squares, and the graph of high voltage in the case where the power supply voltage is higher than the intermediate voltage is indicated by plots of white circles.
From FIG. 6, the maximum electric field at the interface between the semiconductor substrate 2 and the insulating layer 4 is reduced as the overhang length 11 of the conductor portion 5 becomes larger, and when the length 11 exceeds 0.2 pm, the electric field reaches its lower limit value determined by the difference in work function irrespective of the magnitude of the power supply voltage. Namely, the influence of the electrode wiring 10 can be brought much close to 0 when the overhang length 11 of the conductor portion 5 is 0.2 pm or larger. Accordingly, it is possible to effectively reduce the influence of the electrode wiring 10 shown in FIG. 5 by setting the length 11 to 0.2 pm or larger.
(Third Embodiment)
FIG. 7 shows a planar layout of a silicon carbide semiconductor device according to a third embodiment of the present invention, and FIG. 8 is a cross-sectional view showing the silicon carbide semiconductor device according to the third embodiment of the present invention. FIG. 8 is a cross-sectional view taken along a line A-A of FIG. 7.
The descriptions of the specific structure of the semiconductor element are omitted in the first embodiment; however, the specific structure of the semiconductor element and the insulating layer in the case where the semiconductor element is a
MOSFET will be described in the present embodiment. Here, the 17 descriptions will be given with an n channel MOSFET in mind, but if the conductivity type of the semiconductor layer is changed from an n type to a p type or from a p type to an n type, for example, the present embodiment can be applied also to a p channel MOSFET. In addition, a field plate electrode 29 that corresponds to the conductor portion 5 described with reference to FIG. 1 and FIG. 2 in the first embodiment and is made of a conductive material is formed in the present embodiment. The field plate electrode 29 is formed for the purpose of improving the withstand voltage of the semiconductor element.
As shown in FIG. 8, the silicon carbide semiconductor device according to the third embodiment includes the semiconductor substrate 2 and an epitaxial layer (semiconductor layer) 17 on the semiconductor substrate 2. The semiconductor substrate 2 and the epitaxial layer 17 correspond to the semiconductor substrate 2 described with reference to FIG. 1 in the first embodiment. Namely, a MOSFET serving as a semiconductor element is formed in the vicinity of a main surface of the epitaxial layer 17.
The MOSFET includes the source region 12 and the drain region which are n+ type semiconductor regions formed on a main surface (upper surface) of the epitaxial layer 17, and the gate electrode formed on the main surface (upper surface) of the epitaxial layer via the insulating film 24 serving as a gate insulating film.
The gate electrode 14 is used to control a current flowing between the source region 12 and the drain region 13 which are separated from each other. Namely, the MOSFET is a semiconductor element having a current path between the source region 12 and the drain region 13. A well region 18 which is a p type semiconductor region deeper than the source region 12 and the drain region 13 is formed on the main surface of the epitaxial layer 17. The back surface electrode 6 in contact with a back surface of the semiconductor substrate 2 is formed so as to cover the back surface.
The semiconductor substrate 2, the epitaxial layer 17, the well region 18, the source region 12, and the drain region 13 are made of SiC (silicon carbide) . The well region 18 is a semiconductor region in which a p type impurity (for example, Al (aluminum)) has been introduced into the main surface of the epitaxial layer 17. The source region 12 and the drain region 13 are semiconductor regions in which an n type impurity (for example, N (nitrogen)) has been introduced into the main surface of the epitaxial layer 17. The semiconductor substrate 2 is an n_ type semiconductor layer, and the epitaxial layer 17 is an n type semiconductor layer. The insulating film 24 is made of, for example, a silicon oxide film. The back surface electrode 6 is formed of, for example, a laminated metal film containing Au (gold).
As shown in FIG. 7 and FIG. 8, the element isolation layer 3 which is a p+ type semiconductor region is formed on the upper surface of the epitaxial layer 17 so as to surround the periphery of the MOSFET in a plan view. Namely, the element isolation layer surrounds the periphery of the source region 12 and the drain region 13. The element isolation layer 3 is a semiconductor region in which a p type impurity (for example, Al (aluminum)) has been introduced into the main surface of the epitaxial layer 17. An impurity concentration of the element isolation layer 3 is higher than an impurity concentration of the well region 18, and the element isolation layer 3 is shallower than the well region 18.
An interlayer insulating film including the insulating film 24 and the insulating layer 4 is formed on the main surface of the epitaxial layer 17. The insulating film 24 and the insulating layer correspond to the insulating layer 4 described with reference to
FIG. 1 in the first embodiment. The insulating layer 4 has a plurality of openings, the opening (contact hole, connection hole) penetrating through the insulating layer 4 from an upper surface to a back surface of the insulating layer 4 is formed just above each 19 of the source region 12 and the drain region 13, and the plug 7 is buried in the openings. The plug 7 is connected to each upper surface of the source region 12 and the drain region 13. In addition, the opening is formed just above the element isolation layer 3, and the plug 7 electrically connected to the element isolation layer 3 is buried in that opening.
The field plate electrode 29 is formed just above the element isolation layer 3 via the insulating film 24. Side surfaces and upper surfaces of the gate electrode 14 and the field plate electrode 29 are covered with the insulating layer 4. In the regions adjacent to the side surfaces of the gate electrode 14 and the field plate electrode 29, the insulating film 24 and the insulating layer 4 are formed on the epitaxial layer 17, and the plurality of openings are separated from the gate electrode 14 and the field plate electrode 29 with the insulating layer 4 interposed therebetween. The gate electrode 14 and the field plate electrode 29 are made of, for example, polysilicon, Al (aluminum) , or W (tungsten).
Also, an opening penetrating through the insulating layer 4 is provided just above a part of the upper surface of the field plate electrode 29, and the plug 7 electrically connected to the field plate electrode 29 is buried in that opening. Similarly, an opening penetrating through the insulating layer 4 is provided just above a part of the upper surface of the gate electrode 14, and the plug 7 electrically connected to the gate electrode 14 is buried in that opening.
Electrodes and wirings are formed on the plurality of plugs and the insulating layer 4. Namely, the drain electrode 16 integrated with the plug 7 connected to the drain region 13 is formed on the insulating layer 4. In addition, a gate wiring 28 integrated with the plug 7 connected to the gate electrode 14 is formed on the insulating layer 4. Further, the source electrode 15 20 integrated with each of the plugs connected to the source region 12, the element isolation layer 3, and the field plate electrode 29 is formed on the insulating layer 4. Namely, the source region 12, the element isolation layer 3, and the field plate electrode 29 are electrically connected to each other through the plurality of plugs 7 and the source electrode 15 on the insulating layer 4.
The source electrode 15 and the drain electrode 16 are wirings which supply a potential to each of the source region 12 and the drain region 13, and the source electrode 15 has also a function of electrically connecting the element isolation layer 3 and the field plate electrode 29. Namely, the source electrode 15 corresponds to the wiring 8 described with reference to FIG. 2 in the first embodiment. The gate wiring 28, the source region 12, and the drain region 13 are isolated from each other and are insulated from each other. The insulating film 24 and the insulating layer 4 are made of, for example, a silicon oxide film. The plug 7, the gate wiring 28, the source region 12, and the drain region 13 are mainly made of, for example, Al (aluminum).
As shown in FIG. 7, the source electrode 15, the drain electrode 16, and the gate wiring 28 are overlapped with the element isolation layer 3 in a plan view. However, at the position where the source electrode 15, the drain electrode 16, and the gate wiring are overlapped with the element isolation layer 3 in a perpendicular direction, the field plate electrode 29 which is a conductor portion is formed without fail between the source electrode 15, the drain electrode 16, and the gate wiring 28 and the element isolation layer 3. In other words, the field plate electrode 29 is formed at the position where the wiring (electrode) and the element isolation layer 3 are overlapped with each other.
Accordingly, even in the insulating layer whose electric field is likely to be increased due to being positioned just below the wiring, the electrode or the like, the increase of the electric field in 21 the insulating layer can be prevented as in the second embodiment described above by positioning the insulating layer between the element isolation layer 3 and the field plate electrode 29 electrically connected to the element isolation layer 3.
However, in the case where the extension portion of the wiring (electrode) and the extension portion of the element isolation layer 3 are orthogonal to each other, it is difficult to form the end portion of the field plate electrode 29 which is a conductor portion so as to overhang outward from the end portion of the wiring (electrode) in the short-side direction of the element isolation layer 3 as in the second embodiment described above. Even in such a case, in order to prevent the increase of the electric field of the insulating film 24 between the element isolation layer 3 and the field plate electrode 29 due to the influence of the wiring (electrode), the field plate electrode 29 is formed just above the element isolation layer 3 having a first width in the short-side direction of the element isolation layer 3, the field plate electrode 29 having a second width larger than the first width in the short-side direction. In this manner, the upper surface of the element isolation layer 3 and the insulating film 24 in contact with the upper surface are all covered with the field plate electrode 29 in the short-side direction. As a result, since the increase of the electric field in the insulating film 24 can be prevented, the tolerated dose against the γ ray can be improved.
Hereinafter, a manufacturing method of a silicon carbide semiconductor device according to the present embodiment will be described with reference to FIGs. 9 to 15. FIGs. 9 to 15 are crosssectional views showing the silicon carbide semiconductor device according to the present embodiment in a manufacturing process.
First, as shown in FIG. 9, the n_ type semiconductor substrate having a main surface and a back surface opposite to the main surface is prepared. The semiconductor substrate 2 is a 22 substrate made of SiC (silicon carbide), that is, an SiC substrate. An active region 1A and an element isolation region IB surrounding the active region 1A in a plan view are present on the main surface of the semiconductor substrate 2. The active region 1A is a region in which a semiconductor element is to be formed in a following process, and the element isolation region IB is a region in which an element isolation layer is to be formed in a following process.
Subsequently, the n type epitaxial layer 17 is formed on the main surface of the semiconductor substrate 2 by the epitaxial growth method. In this case, an impurity concentration of the epitaxial layer 17 can be designed to a desired value by growing the epitaxial layer 17 while introducing an n type impurity (for example, N (nitrogen)) into the epitaxial layer 17.
Next, as shown in FIG. 10, a p type impurity (for example, Al (aluminum)) is implanted into the upper surface of the epitaxial layer 17 by the photolithography technique and the ion implantation method. In this manner, the element isolation layer 3 which is a P+ type semiconductor region is formed on the upper surface of the epitaxial layer 17. The element isolation layer 3 which reaches an intermediate depth of the epitaxial layer 17 from the upper surface of the epitaxial layer 17 is formed in the element isolation region
IB.
Next, as shown in FIG. 11, a p type impurity (for example,
Al (aluminum)) is implanted into the upper surface of the epitaxial layer 17 by the photolithography technique and the ion implantation method. In this manner, the well region 18 which is a p type semiconductor region is formed on the upper surface of the epitaxial layer 17. The well region 18 has a p type impurity concentration lower than that of the element isolation layer 3 and has a deeper formation depth than that of the element isolation layer 3. However, a lower surface of the well region 18 does not reach the interface between the epitaxial layer 17 and the semiconductor substrate 2. 23
The element isolation layer 3 is positioned on the upper surface of the well region 18 and has an annular shape in a plan view.
Next, as shown in FIG. 12, an n type impurity (for example, N (nitrogen)) is implanted into the upper surface of the epitaxial layer 17 by the photolithography technique and the ion implantation method. In this manner, the source region 12 and the drain region 13 which are n+ type semiconductor regions are formed on the upper surface of the epitaxial layer 17. A formation depth of each of the source region 12 and the drain region 13 is shallower than that of the well region 18. An impurity concentration of each of the source region 12 and the drain region 13 is higher than that of the well region 18. The source region 12 and the drain region 13 are formed in the active region 1A, which is a region surrounded by the element isolation layer 3 in a plan view, on the upper surface of the well region 18.
Next, as shown in FIG. 13, the thin insulating film 24 and a conductive film are formed in order over the epitaxial layer 17 by, for example, the CVD (Chemical Vapor Deposition) method. The insulating film 24 is made of, for example, a silicon oxide film, and the conductive film is made of, for example, polysilicon, Al (aluminum) , or W (tungsten) . Subsequently, the conductive film is processed by the photolithography technique and the etching method, thereby exposing a part of the upper surface of the insulating film
24.
By processing the conductive film as described above, the gate electrode 14 and the field plate electrode 29 made of the conductive film are formed. The gate electrode 14 is formed just above the upper surface of the epitaxial layer 17 (well region 18) between the source region 12 and the drain region 13 via the insulating film 24 serving as the gate insulating film in the active region 1A. The field plate electrode 29 is formed just above the element isolation layer 3 via the insulating film 24.
Next, as shown in FIG. 14, the insulating layer 4 serving as the interlayer insulating film is formed over the epitaxial layer 17 by, for example, the CVD method. The insulating layer 4 is made of, for example, a silicon oxide film. In this case, side surfaces and upper surfaces of the gate electrode 14 and the field plate electrode 29 and the upper surface of the insulating film 24 are covered with the insulating layer 4. Subsequently, the insulating layer 4 and the insulating film 24 are processed by the photolithography technique and the etching method. In this manner, the plurality of connection holes (openings) that penetrate through the insulating layer 4 and the insulating film 24 and expose the upper surface of the epitaxial layer 17 are formed. At this time, the connection hole that penetrates through the insulating layer 4 just above the field plate electrode 29 and exposes the upper surface of the field plate electrode 29 is also formed. Further, the connection hole that penetrates through the insulating layer 4 just above the gate electrode 14 and exposes the upper surface of the gate electrode 14 is also formed. At a bottom portion of each connection hole, a part of each upper surface of the source region 12, the drain electrode 13, the element isolation layer 3, and the field plate electrode 29 is exposed from the laminated film made up of the insulating layer 4 and the insulating film 24.
Next, as shown in FIG. 15, a metal film is formed over the epitaxial layer 17 and the insulating layer 4 by, for example, the sputtering method. The metal film is made of, for example, Al (aluminum) , and fills the inside of each of the plurality of openings described above. Subsequently, the metal film on the insulating layer 4 is processed by the photolithography technique and the etching method, thereby exposing a part of the upper surface of the insulating layer 4. By processing the metal film as described above, the metal film is separated to form the gate wiring 28, the source electrode 15, and the drain electrode 16 made of the metal film. The gate wiring 28 is formed just above the gate electrode via the plug 7 made of the metal film buried in the connection hole. The source electrode 15 is formed just above the source region 12 via the plug 7 made of the metal film buried in the connection hole. The drain electrode 16 is formed just above the drain region 13 via the plug 7 made of the metal film buried in the connection hole.
In addition, the source electrode 15 is formed just above the element isolation layer 3 and the field plate electrode 29 via the plugs 7 made of the metal film buried in the connection holes. Namely, the element isolation layer 3 and the field plate electrode 29 are electrically connected to each other through the plugs 7 and the source electrode 15.
The source electrode 15 is electrically connected to the source region 12, the element isolation layer 3, and the field plate electrode 29, the drain electrode 16 is electrically connected to the drain region 13, and the gate wiring 28 is electrically connected to the gate electrode 14. Subsequently, the back surface electrode 6 which covers the back surface of the semiconductor substrate 2 is formed by, for example, the sputtering method. The back surface electrode 6 is made of, for example, a conductive film containing Au (gold) , and is connected to, for example, a power supply voltage (not shown).
Through the process described above, the n channel MOSFET including the gate electrode 14, the source region 12, and the drain region 13 can be formed as the silicon carbide semiconductor device according to the present embodiment.
The main characteristic of the silicon carbide semiconductor device according to the present embodiment is that the element isolation layer 3 and the field plate electrode 29 just above the element isolation layer 3 are electrically connected to each other.
With the configuration described above, when a MOSFET is formed as 26 a semiconductor element, the tolerated dose against the γ ray can be improved as in the first embodiment described above.
<Modification Example>
Hereinafter, a silicon carbide semiconductor device according to a modification example of the present embodiment will be described with reference to FIG. 16. FIG. 16 is a cross-sectional view showing the silicon carbide semiconductor device according to the modification example of the present embodiment.
As shown in FIG. 16, the silicon carbide semiconductor device according to the modification example is similar to the semiconductor device shown in FIG. 8 in that it has a MOSFET as a semiconductor element. However, unlike the semiconductor device shown in FIG. 8, a p+ type contact layer 103 which is a p+ type semiconductor region is formed on the upper surface of the epitaxial layer 17 in addition to the element isolation layer 3. The p+ type contact layer 103 is a connection portion for fixing the potential of the substrate in the vicinity of the MOSFET, that is, the well region 18, the epitaxial layer 17, and others.
An impurity concentration and a depth of the p+ type contact layer 103 are the same as those of the element isolation layer 3. Also, the p+ type contact layer 103 is electrically connected to the source electrode 15 through the plug 7 like the element isolation layer 3. Note that the source electrode 15 electrically connected to the p+ type contact layer 103 may be regarded as a substrate electrode for fixing the potential of the substrate. The P+ type contact layer 103 may be separated from or integrated with the element isolation layer 3.
In the manufacturing process of the silicon carbide semiconductor device according to the modification example, first, the laminated substrate made up of the semiconductor substrate 2 and the epitaxial layer 17 is prepared as described with reference to FIG. 9.
Subsequently, by performing the ion implantation in the same manner as the process described with reference to FIG. 10, the element isolation layer 3 and the p+ type contact layer 103 are formed on the upper surface of the epitaxial layer 17.
Then, the same processes as those described with reference to FIGs. 11 to 13 are performed. Here, the field plate electrode 29 which is a conductor portion is formed just above each of the element isolation layer 3 and the p+ type contact layer 103 via the insulating film 24.
Thereafter, by performing the same processes as those described with reference to FIGs. 14 and 15, the silicon carbide semiconductor device according to the modification example shown in FIG. 16 is formed. Here, the source electrode 15 connected to each of the source region 12, the element isolation layer 3, the p+ type contact layer 103, and the field plate electrode 29 through the plugs 7 is formed.
When the p+ type contact layer 103 and the element isolation layer 3 are integrated and the p+ type contact layer 103 is used as the element isolation layer, the tolerated dose against the γ ray can be improved by electrically connecting the element isolation layer 3 and the p+ type contact layer 103 to the field plate electrode 29 which is a conductor portion in the manner described in the modification example.
(Fourth Embodiment)
FIG. 17 is a cross-sectional view showing a silicon carbide semiconductor device according to a fourth embodiment of the present invention. In the silicon carbide semiconductor device according to the present embodiment, a conductor portion is not formed on the element isolation layer, but a conductor portion electrically connected to a low-resistance portion constituting a diffusion resistor formed on the main surface of the semiconductor substrate is formed just above the low-resistance portion.
The silicon carbide semiconductor device according to the present embodiment includes a diffusion resistor (resistor element) whose resistance value is controlled by an impurity concentration and a length in a lateral direction of a low-concentration layer 19 formed on the main surface of the semiconductor substrate 2. The diffusion resistor is made up of the low-concentration layer 19 and a high-concentration layer 20 which are formed on the main surface of the semiconductor substrate 2 and are in contact with each other in the lateral direction. The low-concentration layer 19 and the high-concentration layer 20 are semiconductor regions in which an n type or p type impurity has been introduced into the main surface of the semiconductor substrate 2, and an impurity concentration of the low-concentration layer 19 is lower than an impurity concentration of the high-concentration layer 20. The impurity concentration of the high-concentration layer 20 is higher than 1 x 28 err3, and the impurity concentration of the low-concentration layer 19 is 1 x 28 enr3 or lower. The high-concentration layer 20 has the impurity concentration higher than 1 x 28 err3, and is thus regarded as substantially a conductor.
The back surface of the semiconductor substrate 2 is covered with the back surface electrode 6, and the main surface of the semiconductor substrate 2 is covered with the insulating layer 4.
The plug 7 is buried in each of the plurality of connection holes (openings) penetrating through the insulating layer 4. The plug 7 is connected to the upper surface of the low-concentration layer
19, and the plug 7 is further connected to an electrode 21 on the insulating layer 4. In addition, the plug 7 is connected to the upper surface of the high-concentration layer 20, and the plug 7 is further connected to an electrode 22 on the insulating layer 4.
Namely, the electrode 21 and the electrode 22 are electrically connected to each other through the plugs 7, the low-concentration layer 19, and the high-concentration layer 20, and the diffusion resistor described above constitutes a current path between the electrode 21 and the electrode 22. Note that the conductor portion 5 is not formed just above the low-concentration layer 19, and the low-concentration layer 19 is not covered with the conductor portion
5. In other words, the low-concentration layer 19 is exposed from the conductor portion 5.
As a silicon carbide semiconductor device according to a comparative example, a device having a structure in which a diffusion resistor made up of only a low-concentration layer instead of both a low-concentration layer and a high-concentration layer is formed on a main surface of a semiconductor substrate and the conductor portion 5 described above is not formed is conceivable. In this case, as described based on the comparative example of FIG. 19, when the insulating layer having a high electric field is irradiated with the γ ray, positive charges are accumulated in the insulating layer in the vicinity of the main surface of the semiconductor substrate on which the diffusion resistor is formed. Consequently, a channel is likely to be formed on the upper surface of the diffusion resistor, resulting in the occurrence of the problem that the diffusion resistor does not function as a resistor element. In this diffusion resistor, the equipotential lines pass in a direction perpendicular to the entire diffusion resistor.
Then, if a conductor portion electrically connected to the diffusion resistor made of only the low-concentration layer is formed in the insulating layer, the accumulation of positive charges can be prevented in the region where the potential difference between the diffusion resistor and the conductor portion is brought close to 0. However, the diffusion resistor is an element whose potential gradually changes between one end portion and the other end portion. Namely, since potential drop occurs in the diffusion resistor, the potential is not uniform depending on the position in the diffusion resistor. Accordingly, the potential difference 30 occurs in some cases between the diffusion resistor and the conductor portion even in the region just below the conductor portion. In this case, since the electric field becomes high even in the region between the conductor portion and the diffusion resistor, the accumulation of positive charges in the insulating layer due to the exposure to the γ ray cannot be prevented.
Also, when the conductor portion electrically connected to the diffusion resistor made up of only a low-concentration layer is formed so as to be overlapped with a part of the diffusion resistor in a plan view, the equipotential lines do not pass in the conductor portion, and thus avoid the conductor portion. As a result, the equipotential lines which have passed the diffusion resistor just below the conductor portion collectively pass in the vicinity of the end portion of the insulating layer 4 just below the conductor portion. This means that the electric field concentrates in the vicinity of the end portion of the insulating layer 4 just below the conductor portion. Therefore, when the silicon carbide semiconductor device according to the comparative example is irradiated with the γ ray, positive charges are locally accumulated in a part of the insulating layer on the diffusion resistor, and thus the reliability of the diffusion resistor is decreased.
Thus, in the present embodiment, the conductor portion 5 is provided in the insulating layer 4 just above the diffusion resistor, and the diffusion resistor just below the conductor portion 5 is made up of the high-concentration layer 20 with an impurity concentration higher than 1 x 2s cut3 . Since the high-concentration layer 20 can be regarded as substantially a conductor, the potential of the high-concentration layer 20 is uniform throughout the highconcentration layer 20 even when different potentials are applied between the electrode 21 and the electrode 22. Therefore, since the conductor portion 5 electrically connected to the highconcentration layer 2 0 and the whole of the high-concentration layer 31 have equal potential, the electric field is brought close to 0 in any region between the high-concentration layer 20 and the conductor portion 5. Accordingly, compared with the case where the whole of the diffusion resistor is made up of the low-concentration layer, the effect to suppress positive charges from being trapped in the insulating layer 4 just below the region in which the conductor portion 5 is formed can be obtained in a wider range in the present embodiment. Namely, since the diffusion resistor is made up of the low-concentration layer 19 and the high-concentration layer 20, the influence due to the potential drop in the diffusion resistor when the conductor portion 5 is formed can be reduced.
In addition, the equipotential lines do not pass in the highconcentration layer 20 which can be regarded as substantially a conductor, but pass through the low-concentration layer 19 along the perpendicular direction. Therefore, it is possible to prevent the equipotential lines from concentrating in the region in the vicinity of the end portion of the insulating layer 4 just below the conductor portion, and is thus possible to prevent the electric field in that region from being locally increased. Accordingly, since it is possible to prevent positive charges from being locally accumulated in the insulating layer 4, the reliability of the silicon carbide semiconductor device can be improved.
Also, when the electrode wiring is formed on the insulating layer 4 just above the diffusion resistor, the electric field in the insulating layer 4 below the electrode wiring is increased due to the potential applied to the electrode wiring, with the result that positive charges are likely to be accumulated in the insulating layer 4 due to the irradiation of the γ ray. Thus, when the electrode wiring 10 is formed on the insulating layer 4 as shown in FIG. 18, the increase of the electric field in the insulating film 4 due to the electrode wiring 10 can be prevented by forming the electrode wiring 10 just above each of the high-concentration layer 32 and the conductor portion 5.
Further, as described in the second embodiment, it is desirable that the end portion of the conductor portion 5 overhangs outward from the end portion of the electrode wiring 10 in the lateral direction. In this manner, the influence of the electrode wiring 10 arranged on the diffusion resistor can be reduced as much as possible.
In the foregoing, the invention made by the inventors of the present invention has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be made within the scope of the present invention.
For example, the insulating layer 4 interposed between the conductor portion 5 and the element isolation layer 3 in FIG. 1 may have the LOCOS structure.

Claims (14)

What is claimed is:
1. A silicon carbide semiconductor device comprising:
a semiconductor substrate having a first region and a second region and containing silicon carbide;
a semiconductor element having a current path on a main surface of the first region of the semiconductor substrate;
an element isolation layer made of a semiconductor region formed in the second region surrounding the first region in a plan view; and a conductor portion formed just above the element isolation layer via an insulating layer and electrically connected to the element isolation layer.
2. The silicon carbide semiconductor device according to claim
1, wherein a first wiring insulated from the conductor portion is formed just above the conductor portion.
3. The silicon carbide semiconductor device according to claim
2, wherein the conductor portion is arranged between the first wiring and the element isolation layer in a direction perpendicular to the main surface of the semiconductor substrate.
4. The silicon carbide semiconductor device according to claim
2, wherein an end portion of the conductor portion overhangs outward from an end portion of the first wiring in a direction along the main surface of the semiconductor substrate.
5. The silicon carbide semiconductor device according to claim
4, wherein the end portion of the conductor portion overhangs outward from the end portion of the first wiring in the direction along the main surface of the semiconductor substrate by 0.2 pm or more .
6. The silicon carbide semiconductor device according to claim
1, wherein the semiconductor element is a field effect transistor including a source region and a drain region formed on the main surface of the first region of the semiconductor substrate and a gate electrode formed via an insulating film on the main surface of the semiconductor substrate between the source region and the drain region.
7. The silicon carbide semiconductor device according to claim 1, further comprising:
a second wiring formed on the conductor portion; a first conductive connection portion electrically connecting the second wiring and the element isolation layer; and a second conductive connection portion electrically connecting the second wiring and the conductor portion, wherein the element isolation layer and the conductor portion are electrically connected to each other through the first conductive connection portion, the second wiring, and the second conductive connection portion.
8. A silicon carbide semiconductor device comprising:
a semiconductor substrate containing silicon carbide; a first semiconductor region of a first conductivity type which is formed on a main surface of the semiconductor substrate;
a second semiconductor region of the first conductivity type which is formed on the main surface of the semiconductor substrate and is in contact with the first semiconductor region; and a conductor portion which is formed just above the second semiconductor region via an insulating layer and is electrically connected to the second semiconductor region, wherein an impurity concentration of the second semiconductor region is higher than 1 x 1018 cim3, and the first semiconductor region and the second semiconductor region constitute a resistor element.
9. A manufacturing method of a silicon carbide semiconductor device comprising the steps of:
(a) preparing a semiconductor substrate containing silicon carbide;
(b) forming a first semiconductor region on a main surface of a first region of the semiconductor substrate;
(c) forming an element isolation layer made of a second semiconductor region on the main surface of the semiconductor substrate in a second region surrounding the first region of the semiconductor substrate in a plan view; and (d) after the step (b) and the step (c), forming a conductor portion, which is electrically connected to the element isolation layer, just above the element isolation layer via a first insulating layer, wherein the first semiconductor region constitutes a semiconductor element having a current path on the main surface of the first region of the semiconductor substrate.
10. The manufacturing method of a silicon carbide semiconductor device according to claim 9, wherein the step (d) includes the steps of:
(dl) forming the conductor portion just above the element isolation layer via the first insulating layer;
(d2) forming a second insulating layer, which covers the conductor portion, on the semiconductor substrate and the first insulating layer; and (d3) forming a first conductive connection portion penetrating through the second insulating layer and connected to an upper surface of the element isolation layer, a second conductive connection portion penetrating through the second insulating layer and connected to an upper surface of the conductor portion, and a second wiring connected to the first conductive connection portion and the second conductive connection portion and located on the second insulating layer, and the element isolation layer and the conductor portion are electrically connected to each other through the first conductive connection portion, the second wiring, and the second conductive connection portion.
11. The manufacturing method of a silicon carbide semiconductor device according to claim 9, wherein, in the step (d) , in addition to the conductor portion, a first wiring is formed just above the conductor portion via a second insulating layer, and the conductor portion is arranged between the first wiring and the element isolation layer in a direction perpendicular to the main surface of the semiconductor substrate.
12. The manufacturing method of a silicon carbide semiconductor device according to claim 9, wherein, in the step (d) , in addition to the conductor portion, a first wiring is formed just above the conductor portion via a second insulating layer, and an end portion of the conductor portion overhangs outward from an end portion of the first wiring in a direction along the 37 main surface of the semiconductor substrate.
13. The manufacturing method of a silicon carbide semiconductor device according to claim 12, wherein the end portion of the conductor portion overhangs outward from the end portion of the first wiring in the direction along the main surface of the semiconductor substrate by 0.2 pm or more .
14. The manufacturing method of a silicon carbide semiconductor device according to claim 9, wherein, in the step (b) , the first semiconductor region of a first conductivity type and a third semiconductor region of the first conductivity type separated from the first semiconductor region on the main surface of the first region of the semiconductor substrate are formed, the step (d) includes the steps of:
(dl) forming the conductor portion just above the element isolation layer via the first insulating layer and forming a gate electrode via a gate insulating film on the semiconductor substrate in the first region;
(d2) forming a second insulating layer, which covers the conductor portion, on the semiconductor substrate and the first insulating layer; and (d3) forming a first conductive connection portion penetrating through the second insulating layer and connected to an upper surface of the element isolation layer, a second conductive connection portion penetrating through the second insulating layer and connected to an upper surface of the conductor portion, and a second wiring connected to the first conductive connection portion and the second conductive connection portion and located on the second insulating layer, and a source region made up of the first semiconductor region, a drain region made up of the second semiconductor region, and the gate electrode constitute a field effect transistor corresponding to the semiconductor element.
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