JP2019192664A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2019192664A
JP2019192664A JP2018079593A JP2018079593A JP2019192664A JP 2019192664 A JP2019192664 A JP 2019192664A JP 2018079593 A JP2018079593 A JP 2018079593A JP 2018079593 A JP2018079593 A JP 2018079593A JP 2019192664 A JP2019192664 A JP 2019192664A
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insulating film
semiconductor device
element isolation
semiconductor
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昌弘 増永
Masahiro Masunaga
昌弘 増永
島　明生
Akio Shima
明生 島
慎太郎 佐藤
Shintaro Sato
慎太郎 佐藤
諒 桑名
Ryo Kuwana
諒 桑名
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Hitachi Ltd
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Hitachi Ltd
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Priority to US16/265,455 priority patent/US11239314B2/en
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Abstract

To prevent leakage current from occurring by accumulation of charges in an insulating film due to exposure to γ rays, thereby improving the reliability of a semiconductor device exposed to a high radiation environment.SOLUTION: A MOSFET having a drain region 2 and a source region 3 on the upper surface of a semiconductor substrate and a gate electrode 4 formed on the semiconductor substrate, and an element isolation insulating film 9 having an opening exposing an active region are formed on the semiconductor substrate. Here, a gate lead-out wiring 16 that overlaps an element isolation insulating film 9 in plan view and is integrated with the gate electrode 4 is formed at a position that does not straddle between the drain region 2 and the source region 3 in plan view in the region exposed from the gate electrode 4.SELECTED DRAWING: Figure 1

Description

本発明は半導体装置およびその製造方法に係り、特に、放射線量の高い環境に曝される半導体装置に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device exposed to an environment with a high radiation dose.

現在、製造されている工業品の多くはケイ素（以下、Ｓｉとする）を材料とした半導体素子を採用し、Ｓｉの発展と共に大きく性能を向上させてきた。一方で、高放射線場などの過酷環境に曝される製品では汎用Ｓｉデバイスが適用できないため、過酷環境で動作する半導体素子の開発が待たれている。   Currently, many of the manufactured industrial products employ semiconductor elements made of silicon (hereinafter referred to as Si), and have greatly improved performance with the development of Si. On the other hand, since general-purpose Si devices cannot be applied to products exposed to harsh environments such as high radiation fields, development of semiconductor elements that operate in harsh environments is awaited.

特許文献１（特開平５−５５４７５号公報）には、半導体基板の上面に形成された溝内に埋め込まれた素子分離絶縁膜と、当該素子分離絶縁膜により分離されたＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）が記載されている。   Patent Document 1 (Japanese Patent Laid-Open No. 5-55475) discloses an element isolation insulating film embedded in a groove formed on the upper surface of a semiconductor substrate, and a MOSFET (Metal Oxide Semiconductor Field) isolated by the element isolation insulating film. Effect Transistor).

特開平５−５５４７５号公報JP-A-5-55475

放射線が半導体デバイスに照射された場合、絶縁膜中に捕獲電荷が溜まる問題がある。この電荷により、半導体基板と絶縁膜との界面には欠陥が生じ、当該欠陥に起因してリーク電流が増大する。捕獲電荷は、当該絶縁膜が厚い箇所、および、ゲート電極と半導体基板との間において特に溜まり易い。したがって、ソース領域とドレイン領域との間に亘って、素子分離絶縁膜上にゲート電極が形成されている場合、当該ゲート電極の下のソース領域とドレイン領域との間では界面欠陥が生じ易くなり、リーク電流が流れる問題が生じる。   When the semiconductor device is irradiated with radiation, there is a problem that trapped charges accumulate in the insulating film. Due to this charge, a defect is generated at the interface between the semiconductor substrate and the insulating film, and a leakage current increases due to the defect. The trapped charges are particularly liable to be accumulated particularly in a portion where the insulating film is thick and between the gate electrode and the semiconductor substrate. Therefore, when a gate electrode is formed on the element isolation insulating film between the source region and the drain region, an interface defect is likely to occur between the source region and the drain region under the gate electrode. This causes a problem of leakage current.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される実施の形態のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

代表的な実施の形態による半導体装置は、半導体基板の上面に形成されたソース領域およびドレイン領域と、半導体基板上のゲート電極とを有するトランジスタにおいて、半導体基板上の素子分離絶縁膜と重なり、ゲート電極と一体となったゲート引き出し配線を、ソース領域またはドレイン領域に対し平面視で離間した位置に配置するものである。   A semiconductor device according to a typical embodiment is a transistor having a source region and a drain region formed on an upper surface of a semiconductor substrate and a gate electrode on the semiconductor substrate, and overlaps with an element isolation insulating film on the semiconductor substrate. The gate lead wiring integrated with the electrode is disposed at a position separated from the source region or the drain region in plan view.

代表的な実施の形態によれば、半導体装置の信頼性を向上させることができる。特に、γ線の被曝により絶縁膜中に蓄積された捕獲電荷に起因してリーク電流が生じることを防ぐことができる。   According to the representative embodiment, the reliability of the semiconductor device can be improved. In particular, leakage current due to trapped charges accumulated in the insulating film due to exposure to γ rays can be prevented.

本発明の実施の形態１である半導体装置を示す平面図である。1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. 図１のＡ−Ａ線における断面図である。It is sectional drawing in the AA of FIG. 図１のＢ−Ｂ線における断面図である。It is sectional drawing in the BB line of FIG. 本発明の実施の形態１の変形例である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is a modification of Embodiment 1 of this invention. 本発明の実施の形態２である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is Embodiment 2 of this invention. 図５のＣ−Ｃ線における断面図である。It is sectional drawing in the CC line of FIG. 図５のＤ−Ｄ線における断面図である。It is sectional drawing in the DD line | wire of FIG. 本発明の実施の形態２である半導体装置の製造工程中の断面図である。It is sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 2 of this invention. 図８に続く半導体装置の製造工程中の断面図である。FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; 図９に続く半導体装置の製造工程中の断面図である。FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; 図１０に続く半導体装置の製造工程中の断面図である。FIG. 11 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10; 図１１に続く半導体装置の製造工程中の断面図である。FIG. 12 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11; 図１２に続く半導体装置の製造工程中の断面図である。FIG. 13 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12; 図１３に続く半導体装置の製造工程中の断面図である。FIG. 14 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13; 本発明の実施の形態３である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is Embodiment 3 of this invention. 本発明の実施の形態４である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is Embodiment 4 of this invention. 本発明の実施の形態４の変形例１である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is the modification 1 of Embodiment 4 of this invention. 本発明の実施の形態４の変形例２である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is the modification 2 of Embodiment 4 of this invention. 本発明の実施の形態５である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is Embodiment 5 of this invention. 比較例である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is a comparative example. 図２０のＥ−Ｅ線における断面図である。It is sectional drawing in the EE line | wire of FIG. ゲート電圧とゲートおよび酸化膜の容量比との関係の変化を示すグラフである。It is a graph which shows the change of the relationship between a gate voltage and the capacitance ratio of a gate and an oxide film. ゲート電圧とゲートおよび酸化膜の容量比との関係の変化を示すグラフである。It is a graph which shows the change of the relationship between a gate voltage and the capacitance ratio of a gate and an oxide film.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。また、実施の形態では、特に必要なときを除き、同一または同様な部分の説明を原則として繰り返さない。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

また、符号「−」および「＋」は、導電型がｎ型またはｐ型の不純物の相対的な濃度を表しており、例えばｎ型不純物の場合は、「ｎ−」、「ｎ」、「ｎ＋」の順に不純物濃度が高くなる。 The symbols “ − ” and “ + ” represent the relative concentrations of impurities of n-type or p-type conductivity. For example, in the case of n-type impurities, “n − ”, “n”, “ The impurity concentration increases in the order of “n + ”.

（実施の形態１）
＜半導体装置の構造＞
以下では、放射線に曝される環境で使用される半導体装置において、放射線被曝に起因するリーク電流の発生を防ぎ、半導体装置の信頼性を向上させることについて説明する。 (Embodiment 1)
<Structure of semiconductor device>
Hereinafter, in a semiconductor device used in an environment exposed to radiation, description will be given of preventing the occurrence of leakage current due to radiation exposure and improving the reliability of the semiconductor device.

図１に、本発明の実施の形態１である半導体装置の平面図を示し、図２および図３に、本実施の形態の半導体装置の断面図を示す。図２は、図１のＡ−Ａ線における断面図であり、図３は、図１のＢ−Ｂ線における断面図である。図３は、ソース・ドレイン領域上のプラグと、ゲート引き出し配線とを含む断面図である。図１を含む本願の平面図では、ゲート電極を輪郭だけ示してゲート電極の下の構造を透過して示している。また、図１では、素子分離絶縁膜の輪郭だけを示し、素子分離絶縁膜を透過して素子分離絶縁膜の下の構造を示している。図１では素子分離絶縁膜を貫通する開口部の輪郭を破線で示している。これは、他の平面図でも同様である。すなわち、図で示す破線で囲まれた領域の内側はアクティブ領域であり、当該破線で囲まれた領域の外側には素子分離絶縁膜が形成されている。また、図１ではゲート絶縁膜および層間絶縁膜を示していない。   FIG. 1 is a plan view of a semiconductor device according to the first embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of the semiconductor device according to the present embodiment. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG. FIG. 3 is a cross-sectional view including plugs on the source / drain regions and gate lead-out wiring. In the plan view of the present application including FIG. 1, only the outline of the gate electrode is shown, and the structure under the gate electrode is shown transparently. In FIG. 1, only the outline of the element isolation insulating film is shown, and the structure below the element isolation insulating film is shown through the element isolation insulating film. In FIG. 1, the outline of the opening that penetrates the element isolation insulating film is indicated by a broken line. The same applies to other plan views. That is, the inside of the region surrounded by the broken line shown in the figure is the active region, and the element isolation insulating film is formed outside the region surrounded by the broken line. Further, FIG. 1 does not show the gate insulating film and the interlayer insulating film.

ここでは、ｎチャネル型のＭＯＳＦＥＴについて記載するが、本願発明は、ｐチャネル型ＭＯＳＦＥＴにも適用することができる。ｐチャネル型ＭＯＳＦＥＴは、以下に説明するｎチャネル型ＭＯＳＦＥＴの各半導体層の導電型を反転させることで形成することができる。これは、本実施の形態に限らず、後述する他の実施の形態でも同様である。   Although an n-channel MOSFET is described here, the present invention can also be applied to a p-channel MOSFET. A p-channel MOSFET can be formed by inverting the conductivity type of each semiconductor layer of an n-channel MOSFET described below. This is not limited to this embodiment, and the same applies to other embodiments described later.

図１および図２に示すように、本実施の形態の半導体装置は、ワイドバンドギャップ材料であるＳｉＣ（炭化ケイ素）から成る半導体基板を有している。つまり、半導体基板は、Ｓｉ（シリコン）よりもバンドギャップが大きい材料から成る。半導体基板の上面には、半導体素子であるＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor：ＭＯＳ型電界効果トランジスタ）が形成されている。すなわち、本実施の形態の半導体装置は、炭化ケイ素半導体装置である。このように、半導体基板は、主面（上面）と、主面の反対側の裏面（下面）とを有しており、当該主面近傍には、複数のＭＯＳＦＥＴが並べて形成されている。なお、図１〜図３では、ＭＯＳＦＥＴを１つのみ示している。以下では、半導体基板の主面を、半導体基板の上面と呼ぶ。   As shown in FIGS. 1 and 2, the semiconductor device of the present embodiment has a semiconductor substrate made of SiC (silicon carbide), which is a wide band gap material. That is, the semiconductor substrate is made of a material having a larger band gap than Si (silicon). On the upper surface of the semiconductor substrate, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is a semiconductor element is formed. That is, the semiconductor device of the present embodiment is a silicon carbide semiconductor device. Thus, the semiconductor substrate has a main surface (upper surface) and a back surface (lower surface) opposite to the main surface, and a plurality of MOSFETs are formed side by side in the vicinity of the main surface. 1 to 3 show only one MOSFET. Hereinafter, the main surface of the semiconductor substrate is referred to as the upper surface of the semiconductor substrate.

半導体基板は、ｎ型のＳｉＣ基板１０と、ＳｉＣ基板１０上に形成されたｎ型のエピタキシャル層（半導体層）１１との積層基板により構成されている。ここでは、ＳｉＣ基板１０とエピタキシャル層１１とを含む当該積層基板を半導体基板と呼ぶ。エピタキシャル層１１の上面には、ｐ型の半導体領域であるウェル１が形成されている。ウェル１は、エピタキシャル層１１の上面から、エピタキシャル層１１の途中深さに亘って、エピタキシャル層１１内に形成されている。ウェル１は、エピタキシャル層１１の上面にｐ型の不純物（例えばＡｌ（アルミニウム））が導入された半導体領域である。また、ＳｉＣ基板１０の裏面に接して、例えば金属膜から成る裏面電極１４が形成されている。裏面電極１４は、例えばＡｕ（金）を含む導電膜であり、半導体チップが単体デバイスであるなら、例えばドレイン電極５に電気的に接続されている。   The semiconductor substrate is configured by a laminated substrate of an n-type SiC substrate 10 and an n-type epitaxial layer (semiconductor layer) 11 formed on the SiC substrate 10. Here, the multilayer substrate including the SiC substrate 10 and the epitaxial layer 11 is referred to as a semiconductor substrate. On the upper surface of the epitaxial layer 11, a well 1 which is a p-type semiconductor region is formed. The well 1 is formed in the epitaxial layer 11 from the upper surface of the epitaxial layer 11 to an intermediate depth of the epitaxial layer 11. The well 1 is a semiconductor region in which a p-type impurity (for example, Al (aluminum)) is introduced into the upper surface of the epitaxial layer 11. Further, a back electrode 14 made of, for example, a metal film is formed in contact with the back surface of the SiC substrate 10. The back electrode 14 is a conductive film containing, for example, Au (gold), and is electrically connected to, for example, the drain electrode 5 if the semiconductor chip is a single device.

半導体基板の上面上には、ＭＯＳＦＥＴの周囲を囲む素子分離絶縁膜９が形成されている。素子分離絶縁膜９は、例えば酸化シリコン膜から成る。図１に破線で示すように、半導体基板の上面に沿って広がる素子分離絶縁膜９は、平面視で矩形の開口部を有している。つまり、図１において符号９は、破線で囲まれた矩形領域の内側ではなく破線で囲まれた矩形領域の外側に形成された膜を指している。素子分離絶縁膜９の当該開口部の内側の領域、つまりアクティブ領域において、半導体基板の上面には、互いに離間するソース領域３およびドレイン領域２が形成されている。ソース領域３およびドレイン領域２のそれぞれは、ウェル１の上面からウェル１の途中深さまで形成されたｎ＋型半導体領域である。ソース領域３およびドレイン領域２は、半導体基板の上面に沿う方向であるＸ方向に並んで配置されている。ソース領域３およびドレイン領域２のそれぞれは、半導体基板の上面にｎ型の不純物（例えばＮ（窒素））を導入することで形成されている。 An element isolation insulating film 9 surrounding the periphery of the MOSFET is formed on the upper surface of the semiconductor substrate. The element isolation insulating film 9 is made of, for example, a silicon oxide film. As indicated by broken lines in FIG. 1, the element isolation insulating film 9 extending along the upper surface of the semiconductor substrate has a rectangular opening in plan view. That is, reference numeral 9 in FIG. 1 indicates a film formed outside the rectangular area surrounded by the broken line, not inside the rectangular area surrounded by the broken line. In the region inside the opening of the element isolation insulating film 9, that is, in the active region, a source region 3 and a drain region 2 that are separated from each other are formed on the upper surface of the semiconductor substrate. Each of the source region 3 and the drain region 2 is an n + type semiconductor region formed from the upper surface of the well 1 to an intermediate depth of the well 1. The source region 3 and the drain region 2 are arranged side by side in the X direction, which is a direction along the upper surface of the semiconductor substrate. Each of the source region 3 and the drain region 2 is formed by introducing an n-type impurity (for example, N (nitrogen)) into the upper surface of the semiconductor substrate.

なお、プラグ７は素子分離絶縁膜９を除去した箇所において半導体基板に達して形成されるため、実際には、プラグ７の直下に素子分離絶縁膜９は形成されていない。すなわち、素子分離絶縁膜９の開口部の一部とプラグ７の一部とが平面視で重なる場合、当該開口部の輪郭の一部は、プラグ７の輪郭に沿った形状となる。   Note that since the plug 7 is formed to reach the semiconductor substrate at a position where the element isolation insulating film 9 is removed, the element isolation insulating film 9 is not actually formed immediately below the plug 7. That is, when a part of the opening of the element isolation insulating film 9 and a part of the plug 7 overlap in plan view, a part of the outline of the opening has a shape along the outline of the plug 7.

ここで、素子分離絶縁膜９の開口部は、ソース領域３およびドレイン領域２のそれぞれの一部のみと重なっており、ソース領域３およびドレイン領域２のそれぞれの他の一部は、素子分離絶縁膜９に覆われている。また、ソース領域３およびドレイン領域２のそれぞれは、当該開口部よりもＹ方向における長さが長く、Ｙ方向の当該開口部の両端よりも外側に、ソース領域３およびドレイン領域２のそれぞれの一部が延在している。このため、アクティブ領域内のみならず、アクティブ領域の外の領域、つまり、素子分離絶縁膜９と平面視で重なる領域においても、ソース領域３およびドレイン領域２はウェル１を挟んで対向している。つまり、素子分離絶縁膜９は、ソース領域３およびドレイン領域２の相互間の半導体基板の上面の一部を、開口部において露出している。Ｙ方向は、半導体基板の上面に沿う方向であって、平面視でＸ方向に対し直交する方向である。   Here, the opening of the element isolation insulating film 9 overlaps only a part of each of the source region 3 and the drain region 2, and the other part of each of the source region 3 and the drain region 2 is element isolation insulating. It is covered with a film 9. In addition, each of the source region 3 and the drain region 2 is longer in the Y direction than the opening, and one of the source region 3 and the drain region 2 is located outside both ends of the opening in the Y direction. The department is extended. For this reason, the source region 3 and the drain region 2 are opposed to each other with the well 1 interposed therebetween not only in the active region but also in a region outside the active region, that is, a region overlapping the element isolation insulating film 9 in plan view. . That is, the element isolation insulating film 9 exposes a part of the upper surface of the semiconductor substrate between the source region 3 and the drain region 2 in the opening. The Y direction is a direction along the upper surface of the semiconductor substrate and is orthogonal to the X direction in plan view.

半導体基板の上面、つまり、ウェル１の上面では、アクティブ領域、ソース領域３およびドレイン領域２のそれぞれを囲むように、ｐ型半導体領域から成る素子分離領域（素子分離層）８が形成されている。素子分離領域８は、エピタキシャル層１１の上面にｐ型の不純物（例えばＡｌ（アルミニウム））が導入された半導体領域である。素子分離領域８は、ウェル１の上面からウェル１の途中深さに亘ってウェル１内に形成されている。アクティブ領域、ソース領域３およびドレイン領域２のそれぞれと素子分離領域８とは、ウェル１を介して離間している。   On the upper surface of the semiconductor substrate, that is, the upper surface of the well 1, an element isolation region (element isolation layer) 8 made of a p-type semiconductor region is formed so as to surround each of the active region, the source region 3 and the drain region 2. . The element isolation region 8 is a semiconductor region in which a p-type impurity (for example, Al (aluminum)) is introduced into the upper surface of the epitaxial layer 11. The element isolation region 8 is formed in the well 1 from the upper surface of the well 1 to an intermediate depth of the well 1. Each of the active region, the source region 3 and the drain region 2 is separated from the element isolation region 8 via the well 1.

アクティブ領域の半導体基板上には、素子分離絶縁膜９よりも厚さが薄いゲート絶縁膜１２と、ゲート絶縁膜１２上のゲート電極４とが形成されている。ゲート絶縁膜１２は、上記開口部の端部である素子分離絶縁膜９と、アクティブ領域の半導体基板の上面とを覆っている。アクティブ領域内において、ソース領域３の直上の領域から、ドレイン領域２の直上の領域に亘って、ゲート電極４が形成されている。ゲート電極４はＹ方向に延在している。アクティブ領域の外、つまり素子分離絶縁膜９の上では、ゲート電極４のＹ方向の一方の端部と一体となって接続されているゲート引き出し配線（ゲート配線）１６が、Ｙ方向に延在している。ゲート引き出し配線１６は、アクティブ領域側から、ウェル１および素子分離領域８のそれぞれの上を通るように延在している。   On the semiconductor substrate in the active region, a gate insulating film 12 thinner than the element isolation insulating film 9 and a gate electrode 4 on the gate insulating film 12 are formed. The gate insulating film 12 covers the element isolation insulating film 9 which is the end of the opening and the upper surface of the semiconductor substrate in the active region. In the active region, the gate electrode 4 is formed from a region immediately above the source region 3 to a region immediately above the drain region 2. The gate electrode 4 extends in the Y direction. Outside the active region, that is, on the element isolation insulating film 9, a gate lead-out wiring (gate wiring) 16 connected integrally with one end in the Y direction of the gate electrode 4 extends in the Y direction. is doing. The gate lead-out wiring 16 extends from the active region side so as to pass over each of the well 1 and the element isolation region 8.

ゲート電極４は、Ｙ方向において、アクティブ領域内ではなく素子分離絶縁膜９の直上で終端している。つまり、ゲート電極４のＹ方向（ゲート幅方向）の両端部は素子分離絶縁膜９上に乗り上げている。これは、ゲート電極４の端部近傍は電界が集中しやすい領域であり、アクティブ領域内でゲート電極４および比較的薄い酸化シリコン膜などから成るゲート絶縁膜が終端していると、ゲート電極４の端部近傍で絶縁破壊が起き易いためである。つまり、ゲート電極４の端部は厚い素子分離絶縁膜９上で終端させることが望ましい。このように、ゲート電極４は素子分離絶縁膜９の開口部をＹ方向に跨がるように延在しており、当該開口部の外側では、ゲート電極４に電位を供給するために素子分離絶縁膜９上で延在するゲート引き出し配線１６に接続されている。   The gate electrode 4 terminates not directly in the active region but directly above the element isolation insulating film 9 in the Y direction. That is, both end portions of the gate electrode 4 in the Y direction (gate width direction) run on the element isolation insulating film 9. This is because the electric field tends to concentrate near the end of the gate electrode 4, and when the gate electrode 4 and a gate insulating film made of a relatively thin silicon oxide film terminate in the active region, the gate electrode 4 This is because dielectric breakdown is likely to occur in the vicinity of the end portion. That is, it is desirable that the end portion of the gate electrode 4 is terminated on the thick element isolation insulating film 9. As described above, the gate electrode 4 extends across the opening of the element isolation insulating film 9 in the Y direction, and the element isolation is performed outside the opening to supply a potential to the gate electrode 4. The gate lead wiring 16 extending on the insulating film 9 is connected.

また、ゲート電極４の幅は、Ｙ方向（ゲート幅方向）において、ドレイン領域２およびソース領域３のそれぞれよりの幅よりも小さい。したがって、Ｙ方向におけるゲート電極４の端部よりも外側において、ドレイン領域２およびソース領域３は互いに対向している。   The width of the gate electrode 4 is smaller than the width of each of the drain region 2 and the source region 3 in the Y direction (gate width direction). Therefore, the drain region 2 and the source region 3 face each other outside the end of the gate electrode 4 in the Y direction.

半導体基板上には、素子分離絶縁膜９、ゲート絶縁膜１２およびゲート電極４を覆う層間絶縁膜１３が形成されている。層間絶縁膜１３は、例えば酸化シリコン膜から成り、その上面は平坦化されている。層間絶縁膜１３には、層間絶縁膜１３を貫通する複数の貫通孔（接続孔）が形成されている。接続孔は、ソース領域３、ドレイン領域２および素子分離領域８のそれぞれの直上に形成されている。また、図示していない領域では、延在するゲート引き出し配線１６の先でゲート引き出し配線１６の直上にも接続孔が形成されている。半導体基板の上面に達している接続孔は、層間絶縁膜１３に加え、ゲート絶縁膜１２および素子分離絶縁膜９も貫通している。   On the semiconductor substrate, an interlayer insulating film 13 covering the element isolation insulating film 9, the gate insulating film 12, and the gate electrode 4 is formed. The interlayer insulating film 13 is made of, for example, a silicon oxide film, and its upper surface is flattened. In the interlayer insulating film 13, a plurality of through holes (connection holes) penetrating the interlayer insulating film 13 are formed. The connection hole is formed immediately above each of the source region 3, the drain region 2, and the element isolation region 8. Further, in a region not shown, a connection hole is also formed immediately above the gate lead-out wiring 16 beyond the gate lead-out wiring 16 that extends. In addition to the interlayer insulating film 13, the connection hole reaching the upper surface of the semiconductor substrate also penetrates the gate insulating film 12 and the element isolation insulating film 9.

各接続孔の内側には、プラグ７が埋め込まれている。また、層間絶縁膜１３上には、プラグ７を介してドレイン領域２に電気的に接続されたドレイン電極５と、他のプラグ７を介してソース領域３に電気的に接続されたソース電極６とが形成されている。ソース電極６は、他のプラグ７を介して、素子分離領域８にも電気的に接続されている。つまり、ソース領域３と素子分離領域８とは同電位（ソース電位）となる。また、ソース領域３と素子分離領域８とに接続されたウェル１も、ソース電位となる。プラグ７、ドレイン電極５およびソース電極６のそれぞれは、例えばＡｌ（アルミニウム）膜から成る。   A plug 7 is embedded inside each connection hole. Further, on the interlayer insulating film 13, the drain electrode 5 electrically connected to the drain region 2 through the plug 7 and the source electrode 6 electrically connected to the source region 3 through the other plug 7. And are formed. The source electrode 6 is also electrically connected to the element isolation region 8 through another plug 7. That is, the source region 3 and the element isolation region 8 have the same potential (source potential). The well 1 connected to the source region 3 and the element isolation region 8 also has a source potential. Each of the plug 7, the drain electrode 5, and the source electrode 6 is made of, for example, an Al (aluminum) film.

本実施の形態の主な特徴は、Ｘ方向においてソース領域３上とドレイン領域２上に亘って形成されているゲート電極４のゲート長方向の長さ（幅）ａ１に比べて、Ｘ方向におけるゲート引き出し配線１６の長さ（幅）ｂ１の方が小さいことにより、ゲート引き出し配線１６がソース領域３およびドレイン領域２の相互間に亘って形成されていないことにある。つまり、ここでは、素子分離絶縁膜９と重なる領域（フィールド領域）では、ソース領域３の直上から、ドレイン領域２の直上に亘って、ゲート電極４（ゲート引き出し配線１６）が形成されていない。言い換えれば、ゲート電極４はソース領域３およびドレイン領域２のそれぞれと平面視で重なっているが、ゲート引き出し配線１６は、ソース領域３に対し平面視で離間している。   The main feature of the present embodiment is that the length (width) a1 in the gate length direction of the gate electrode 4 formed over the source region 3 and the drain region 2 in the X direction is larger in the X direction. Since the length (width) b1 of the gate lead-out wiring 16 is smaller, the gate lead-out wiring 16 is not formed between the source region 3 and the drain region 2. That is, here, in the region (field region) overlapping with the element isolation insulating film 9, the gate electrode 4 (gate lead-out wiring 16) is not formed from just above the source region 3 to just above the drain region 2. In other words, the gate electrode 4 overlaps each of the source region 3 and the drain region 2 in plan view, but the gate lead-out wiring 16 is separated from the source region 3 in plan view.

＜本実施の形態の効果＞
図２０および図２１を用いて、本実施の形態の効果について説明する。図２０は、比較例の半導体装置を示す平面図であり、図２１は、比較例の半導体装置を示す断面図である。図２１は、図２０のＥ−Ｅ線における断面図である。 <Effects of the present embodiment>
The effect of the present embodiment will be described with reference to FIGS. FIG. 20 is a plan view showing a semiconductor device of a comparative example, and FIG. 21 is a cross-sectional view showing the semiconductor device of a comparative example. 21 is a cross-sectional view taken along line EE in FIG.

図２０および図２１に示す比較例のＭＯＳＦＥＴの構造は、Ｙ方向に延在するゲート引き出し配線２０（ゲート電極４）が、平面視で素子分離絶縁膜９と重なる領域において、ソース領域３およびドレイン領域２の間に亘って形成されている点で、本実施の形態の半導体装置と異なる。   20 and FIG. 21, the structure of the MOSFET of the comparative example is such that the source region 3 and the drain in the region where the gate lead-out wiring 20 (gate electrode 4) extending in the Y direction overlaps the element isolation insulating film 9 in plan view. The semiconductor device of the present embodiment is different in that it is formed between the regions 2.

半導体装置の多くでは、Ｓｉ（シリコン）を材料とした半導体素子を採用することが考えられる。一方で、高放射線場などの過酷環境に曝される産業製品では汎用Ｓｉデバイスが適用できないため、バンドギャップが大きい材料である炭化ケイ素を用いることがある。   In many semiconductor devices, it is conceivable to employ a semiconductor element made of Si (silicon). On the other hand, since general-purpose Si devices cannot be applied to industrial products exposed to harsh environments such as high radiation fields, silicon carbide, which is a material with a large band gap, may be used.

放射線が与える影響には、主に、トータルドーズ効果、はじき出し損傷効果およびシングルイベント効果の３つがあり、エネルギーレベルの高いγ線は特にトータルドーズ効果による影響が問題となる。トータルドーズ効果とは、バンドギャップよりも大きなエネルギーを吸収材（例えば半導体および絶縁膜）へ照射した際に、吸収材内で電子−正孔対が発生し、そのようにして生じたキャリアが吸収材内に蓄積されることを指す。半導体内で発生した電子−正孔対は、無電界下であれば再結合し、電界効果が働いているのであれば、拡散またはドリフトし、電流としてデバイス外へ取り出される。このため、誘起されたキャリア（電子および正孔）は半導体内で残留することなく、その影響は殆ど無視できる。   There are three main effects of radiation: a total dose effect, a sprout damage effect, and a single event effect, and γ rays with high energy levels are particularly affected by the total dose effect. The total dose effect means that when an absorber (such as a semiconductor and an insulating film) is irradiated with energy larger than the band gap, an electron-hole pair is generated in the absorber and the carriers thus generated are absorbed. Refers to accumulation in the material. The electron-hole pairs generated in the semiconductor are recombined when there is no electric field, and if the field effect is working, they are diffused or drifted and taken out of the device as current. For this reason, the induced carriers (electrons and holes) do not remain in the semiconductor, and their influence can be almost ignored.

一方、酸化膜などの絶縁材内で生成された電子と正孔は膜中の電界の影響を受け、それぞれポテンシャルエネルギーが低い方へドリフトする。正孔は電子と比較して移動度が低く、正孔捕獲中心に捕獲される確率が高いため、絶縁膜中に蓄積され易い。捕獲された正孔（捕獲電荷）は絶縁膜内で正電荷を形成するため、この結果生成される空間電場は、トランジスタのしきい値電圧を負へ変化させる。十分な量の正電荷が蓄積された場合、ｎチャネル型トランジスタは、ゲートに０Ｖが入力されても電流を流し続けるデプレッション型デバイスとなり、リーク電流が増大する。   On the other hand, electrons and holes generated in an insulating material such as an oxide film are affected by the electric field in the film and drift to lower potential energies. Holes have a lower mobility than electrons and have a high probability of being trapped in the hole trapping centers, so that they are easily accumulated in the insulating film. Since the trapped holes (capture charges) form a positive charge in the insulating film, the resultant spatial electric field changes the threshold voltage of the transistor to negative. When a sufficient amount of positive charges is accumulated, the n-channel transistor becomes a depletion type device that continues to flow current even when 0 V is input to the gate, and leakage current increases.

また、捕獲電荷の影響としては、次のようなものもある。絶縁膜内に捕獲電荷が蓄積されると、絶縁膜と半導体層との界面に欠陥が誘起され、しきい値電圧の変動、および、キャリアの移動度低下などの問題が起きる。欠陥密度が増大すると、欠陥を介して流れるオフリーク電流も増大するため、しきい値電圧の変動などのパラメータ不良の問題、および、ＳＮ（シグナル−ノイズ）比を確保できない問題などの機能的な不良を発生させる。   Further, the influence of trapped charges includes the following. When trapped charges are accumulated in the insulating film, defects are induced at the interface between the insulating film and the semiconductor layer, causing problems such as fluctuations in threshold voltage and lower carrier mobility. As the defect density increases, the off-leakage current that flows through the defect also increases, so that functional defects such as parameter failure problems such as threshold voltage fluctuations and a problem that the SN (signal-noise) ratio cannot be secured. Is generated.

ＳｉＣ（炭化ケイ素）はＳｉ（シリコン）とＣ（炭素）で構成される化合物半導体であり、バンドギャップがＳｉと比較し３倍程度大きい。このため、半導体と絶縁膜との界面に形成される界面準位で、半導体側に形成されるものについては、その準位を介して流れるリーク電流の増大を抑制することができる。しかし、絶縁膜についてはＳｉデバイスと同じ材料を用いることが多く、積算線量の増大に伴う捕獲電荷の増加がリーク電流に悪影響を及ぼすことが懸念される。   SiC (silicon carbide) is a compound semiconductor composed of Si (silicon) and C (carbon), and its band gap is about three times larger than Si. For this reason, an interface level formed at the interface between the semiconductor and the insulating film and formed on the semiconductor side can suppress an increase in leakage current flowing through the level. However, the same material as the Si device is often used for the insulating film, and there is a concern that an increase in trapped charge accompanying an increase in accumulated dose may adversely affect the leakage current.

図２０および図２１に示す比較例の半導体装置では、ゲート電極４は素子を区画する素子分離絶縁膜９に乗り上げる構造となっている。比較例の半導体装置にγ線を照射した場合、素子分離絶縁膜９を含む絶縁膜中には正孔−電子対が生成される。生成されるキャリア数は絶縁膜の厚さに依存して増加するため、素子分離絶縁膜９と半導体基板との界面では、アクティブ領域のゲート絶縁膜１２内よりも多くの捕獲電荷が蓄積される。これは、素子周辺（フィールド領域）、つまり素子分離絶縁膜９が形成された領域において界面欠陥がより誘起され易く、リーク電流がより発生し易いことを意味している。図２１には、正孔を黒丸で示し、界面欠陥を×で示している。   In the semiconductor device of the comparative example shown in FIGS. 20 and 21, the gate electrode 4 has a structure that rides on the element isolation insulating film 9 that partitions the elements. When the semiconductor device of the comparative example is irradiated with γ rays, hole-electron pairs are generated in the insulating film including the element isolation insulating film 9. Since the number of carriers generated increases depending on the thickness of the insulating film, more trapped charges are accumulated at the interface between the element isolation insulating film 9 and the semiconductor substrate than in the gate insulating film 12 in the active region. . This means that interface defects are more likely to be induced in the element periphery (field region), that is, the region where the element isolation insulating film 9 is formed, and a leak current is more likely to occur. In FIG. 21, holes are indicated by black circles, and interface defects are indicated by x.

本発明者らは、比較例のＭＯＳＦＥＴを構成する各絶縁膜に外部より３ＭＶ／ｃｍを印加した条件で５０ｋＧｙのγ線を照射する実験を行った。その結果、１ＭＶ／ｃｍにおける相互コンダクタンスが、界面欠陥に起因して３桁以上増加することを見出した。相互コンダクタンスは抵抗の逆数を示しているため、同じ電界強度であるなら、相互コンダクタンスが大きいほど電流が大きいことを示している。つまり、積算線量が十分に高ければ、ＳｉＣでもオフリーク電流が増大することが分かる。   The present inventors conducted an experiment of irradiating 50 kGy of γ rays under the condition that 3 MV / cm was applied from the outside to each insulating film constituting the MOSFET of the comparative example. As a result, it was found that the mutual conductance at 1 MV / cm increased by 3 orders of magnitude or more due to interface defects. Since the mutual conductance indicates the reciprocal of the resistance, if the mutual electric field strength is the same, the larger the mutual conductance is, the larger the current is. That is, it can be seen that if the integrated dose is sufficiently high, the off-leakage current increases even with SiC.

上記のように放射線被曝により特性変動したデバイスを３００℃でアニール処理すると、相互コンダクタンス特性はγ線を照射する前の波形と重なる。これは、欠陥を誘起していた絶縁膜中の捕獲電荷が取り除かれた影響によりオフリークが低減されたことを意味している。すなわち、γ線照射環境下において長期にわたる高い信頼性を得るためには、絶縁膜中に捕獲される正電荷を減少させることも重要である。しかし、特性変動したデバイスを３００℃でアニール処理することが困難である場合もある。   As described above, when a device whose characteristics are changed by radiation exposure is annealed at 300 ° C., the mutual conductance characteristics overlap with the waveform before irradiating γ rays. This means that off-leakage has been reduced due to the removal of trapped charges in the insulating film that has induced defects. That is, in order to obtain long-term high reliability under the γ-ray irradiation environment, it is also important to reduce the positive charges trapped in the insulating film. However, it may be difficult to anneal the device whose characteristics have changed at 300 ° C.

そこで、本実施の形態では、リーク電流の原因となる界面欠陥が生じた場合に、界面欠陥がドレイン−ソース間を跨がないようにすることで、リーク電流の発生を防ぐことを可能としている。すなわち、本実施の形態では、図１〜図３に示すように、放射線の被曝に起因してゲート電極４と半導体基板との間の素子分離絶縁膜９に電荷が蓄積された際、電荷の蓄積に起因してフィールド領域のソース領域３およびドレイン領域２間でリーク電流が流れることを防ぐことができる。   Therefore, in the present embodiment, when an interface defect that causes a leakage current occurs, the generation of the leakage current can be prevented by preventing the interface defect from straddling between the drain and the source. . That is, in this embodiment, as shown in FIGS. 1 to 3, when charge is accumulated in the element isolation insulating film 9 between the gate electrode 4 and the semiconductor substrate due to radiation exposure, Leakage current can be prevented from flowing between the source region 3 and the drain region 2 in the field region due to the accumulation.

つまり、放射線（γ線）が照射された半導体装置では、ゲート電極と半導体基板（ウェル）との間の厚い素子分離絶縁膜内に正電荷が溜まり易い。このため、図２０に示す比較例のように、素子分離絶縁膜９が形成された領域（フィールド領域）において、ソース領域３およびドレイン領域２の間に亘ってゲート電極４（ゲート引き出し配線２０）が形成されている場合、ゲート電極４（ゲート引き出し配線２０）の直下の素子分離絶縁膜９内に正孔が蓄積され、ゲート電極４の直下の素子分離絶縁膜９と半導体基板との間に界面欠陥が生じる。フィールド領域においてソース領域３およびドレイン領域２の間に亘ってゲート電極４が形成されている比較例では、ソース領域３およびドレイン領域２の間に亘って界面欠陥が形成されるため、ソース領域３およびドレイン領域２間にリーク電流の流れる経路であるチャネル層が形成される。   That is, in a semiconductor device irradiated with radiation (γ rays), positive charges are likely to accumulate in a thick element isolation insulating film between the gate electrode and the semiconductor substrate (well). Therefore, as in the comparative example shown in FIG. 20, in the region (field region) where the element isolation insulating film 9 is formed, the gate electrode 4 (gate lead-out wiring 20) extends between the source region 3 and the drain region 2. When holes are formed, holes are accumulated in the element isolation insulating film 9 immediately below the gate electrode 4 (gate lead-out wiring 20), and between the element isolation insulating film 9 immediately below the gate electrode 4 and the semiconductor substrate. Interface defects occur. In the comparative example in which the gate electrode 4 is formed between the source region 3 and the drain region 2 in the field region, an interface defect is formed between the source region 3 and the drain region 2. A channel layer, which is a path through which a leakage current flows, is formed between the drain region 2 and the drain region 2.

これに対し、本実施の形態では、フィールド領域のゲート電極４、つまり、素子分離絶縁膜９の直上のゲート引き出し配線１６のＸ方向の長さｂ１を、アクティブ領域内のゲート電極４のＸ方向（ゲート長方向）の長さａ１より小さくしている。言い換えれば、素子分離絶縁膜９と平面視で重なる領域（フィールド領域）において、ゲート電極４（ゲート引き出し配線１６）は、ソース領域３およびドレイン領域２間に亘って形成されていない。つまり、ゲート引き出し配線１６は、ソース領域３またはドレイン領域２のいずれか一方と平面視で接しているとしても、他方とは平面視で離間している。言い換えれば、ゲート引き出し配線１６は、平面視でソース領域３またはドレイン領域２のいずれか一方と離間している。すなわち、素子分離絶縁膜９と平面視で重なり、ゲート電極４と一体となっているゲート引き出し配線１６を、ゲート電極４から露出する領域において、平面視でドレイン領域２およびソース領域３の相互間に跨がらないように形成している。   In contrast, in the present embodiment, the length b1 in the X direction of the gate electrode 4 in the field region, that is, the gate lead-out wiring 16 immediately above the element isolation insulating film 9 is set to the X direction of the gate electrode 4 in the active region. It is smaller than the length a1 (in the gate length direction). In other words, the gate electrode 4 (gate lead-out wiring 16) is not formed between the source region 3 and the drain region 2 in a region (field region) overlapping the element isolation insulating film 9 in plan view. That is, the gate lead-out wiring 16 is in contact with either the source region 3 or the drain region 2 in plan view, but is separated from the other in plan view. In other words, the gate lead-out wiring 16 is separated from either the source region 3 or the drain region 2 in plan view. That is, the gate lead-out wiring 16 that overlaps the element isolation insulating film 9 in plan view and is integrated with the gate electrode 4 is exposed between the drain region 2 and the source region 3 in plan view in the region exposed from the gate electrode 4. It is formed so as not to straddle.

このため、放射線被曝によりゲート電極４（ゲート引き出し配線１６）の直下の素子分離絶縁膜９内に正孔が蓄積され、素子分離絶縁膜９と半導体基板との界面に欠陥が生じたとしても、ソース領域３およびドレイン領域２間に亘る界面欠陥は形成されない。よって、ソース領域３およびドレイン領域２間にリークパスが形成されないため、リーク電流（オフリーク電流）の発生を防ぐことができる。また、界面欠陥の発生に起因するしきい値電圧の変動およびキャリアの移動度低下などの問題が起きることを防ぐことができ、ＳＮ（シグナル−ノイズ）比の確保も容易となる。以上より、半導体装置の信頼性を向上させることができる。   For this reason, even if holes are accumulated in the element isolation insulating film 9 immediately below the gate electrode 4 (gate lead wiring 16) due to radiation exposure, and a defect occurs at the interface between the element isolation insulating film 9 and the semiconductor substrate, An interface defect extending between the source region 3 and the drain region 2 is not formed. Therefore, since no leak path is formed between the source region 3 and the drain region 2, it is possible to prevent the occurrence of a leak current (off leak current). In addition, it is possible to prevent problems such as fluctuations in threshold voltage due to occurrence of interface defects and a decrease in carrier mobility, and it is easy to ensure an SN (signal-noise) ratio. As described above, the reliability of the semiconductor device can be improved.

本実施の形態では、図１に示すゲート電極４のゲート幅がドレイン領域２およびソース領域３のそれぞれの幅よりも小さく、Ｙ方向におけるゲート電極４の端部よりも外側において、ドレイン領域２およびソース領域３は互いに対向している場合について説明した。これに対し、ゲート電極４のＹ方向のゲート幅が、ドレイン領域２およびソース領域３のそれぞれのＹ方向の幅よりも長くてもよい。つまり、平面視において、ドレイン領域２およびソース領域３のそれぞれのＹ方向の端部よりも外側に、ゲート電極４のＹ方向の端部が突出していてもよい。この場合、本実施の形態の半導体装置では、平面視でゲート電極４のＹ方向の端部の外側を回り込むようにドレイン領域２およびソース領域３の相互間のリークパスが形成されることを防ぐことができる。つまり、リーク電流の発生を防ぐことができる。ただし、このような構成よりも、図１に示すようにゲート電極４のゲート幅が、Ｙ方向のソース領域３およびドレイン領域２のそれぞれの幅より小さい場合の方が、リーク電流の抑制効果は高い。   In the present embodiment, the gate width of the gate electrode 4 shown in FIG. 1 is smaller than the width of each of the drain region 2 and the source region 3, and outside the end portion of the gate electrode 4 in the Y direction, The case where the source regions 3 face each other has been described. On the other hand, the gate width in the Y direction of the gate electrode 4 may be longer than the width in the Y direction of each of the drain region 2 and the source region 3. That is, in the plan view, the end of the gate electrode 4 in the Y direction may protrude outside the end of the drain region 2 and the source region 3 in the Y direction. In this case, in the semiconductor device of the present embodiment, it is possible to prevent a leak path between the drain region 2 and the source region 3 from being formed so as to wrap around outside the end portion in the Y direction of the gate electrode 4 in plan view. Can do. That is, the occurrence of leakage current can be prevented. However, rather than such a configuration, when the gate width of the gate electrode 4 is smaller than the width of each of the source region 3 and the drain region 2 in the Y direction as shown in FIG. high.

なお、本実施の形態１の半導体装置は、後述する実施の形態２の半導体装置と平面レイアウトが異なるが、実施の形態２の半導体装置と同様の製造方法により形成することができる。よって、ここでは本実施の形態１の半導体装置の製造方法の説明は省略する。   The semiconductor device of the first embodiment can be formed by the same manufacturing method as the semiconductor device of the second embodiment, although the planar layout is different from that of the semiconductor device of the second embodiment to be described later. Therefore, the description of the manufacturing method of the semiconductor device of the first embodiment is omitted here.

＜変形例＞
図４に、本実施の形態１の半導体装置の変形例の平面図を示す。図４に示す構造は、図１に示す構造に比べて、ゲート引き出し配線１６のレイアウトのみが異なる。 <Modification>
FIG. 4 shows a plan view of a modification of the semiconductor device according to the first embodiment. The structure shown in FIG. 4 differs from the structure shown in FIG. 1 only in the layout of the gate lead-out wiring 16.

すなわち、ゲート引き出し配線１６の数は複数本であってもよい。ここでは、複数のゲート引き出し配線１６のうちの１つはソース領域３と重なり、複数のゲート引き出し配線１６のうちの他の１つはドレイン領域２と重なっているが、それらの２つのゲート引き出し配線１６同士の間は離間している。ここでも、２つのゲート引き出し配線１６のそれぞれは、平面視でソース領域３またはドレイン領域２のいずれか一方と離間している。よって、２つのゲート引き出し配線１６同士の間の領域の直下の素子分離絶縁膜９近傍には正孔が蓄積され難く、界面欠陥が生じ難い。このため、図１〜図３を用いて説明した構造と同様の効果を得ることができる。   That is, the number of gate lead-out wirings 16 may be plural. Here, one of the plurality of gate lead-out wirings 16 overlaps with the source region 3 and the other one of the plurality of gate lead-out wirings 16 overlaps with the drain region 2. The wirings 16 are separated from each other. Again, each of the two gate lead-out wirings 16 is separated from either the source region 3 or the drain region 2 in plan view. Therefore, holes are unlikely to be accumulated in the vicinity of the element isolation insulating film 9 immediately below the region between the two gate lead-out wirings 16, and interface defects are unlikely to occur. For this reason, the effect similar to the structure demonstrated using FIGS. 1-3 can be acquired.

（実施の形態２）
次に、図５〜図７を用いて、本実施の形態２の半導体装置について説明する。図５に、本発明の実施の形態２である半導体装置の平面図を示し、図６および図７に、本実施の形態の半導体装置の断面図を示す。図６は、図５のＣ−Ｃ線における断面図であり、図７は、図５のＤ−Ｄ線における断面図である。 (Embodiment 2)
Next, the semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 5 shows a plan view of the semiconductor device according to the second embodiment of the present invention, and FIGS. 6 and 7 show sectional views of the semiconductor device according to the present embodiment. 6 is a cross-sectional view taken along line CC in FIG. 5, and FIG. 7 is a cross-sectional view taken along line DD in FIG.

図５〜図７に示すように、本実施の形態の半導体装置は、ドレイン領域２、ゲート電極４、ゲート引き出し配線１６のそれぞれのＸ方向の幅が大きい点で、前記実施の形態１と異なる。また、ここでは、平面視において、ドレイン領域２とゲート電極４とが重なる部分のＸ方向の幅が、ソース領域３とゲート電極４とが重なる部分のＸ方向の幅よりも大きい点、および、ゲート引き出し配線１６が、互いに対向するドレイン領域２とソース領域３との間の領域と平面視で重なっていない点で、前記実施の形態１と異なる。また、素子分離絶縁膜９の開口部のＸ方向の幅が小さく、Ｘ方向においてもゲート電極４の両端が素子分離絶縁膜９上に乗り上げている点で、前記実施の形態１と異なる。   As shown in FIGS. 5 to 7, the semiconductor device of the present embodiment is different from that of the first embodiment in that the width of each of the drain region 2, the gate electrode 4, and the gate lead-out wiring 16 in the X direction is large. . Here, in plan view, the width in the X direction of the portion where the drain region 2 and the gate electrode 4 overlap is larger than the width in the X direction of the portion where the source region 3 and the gate electrode 4 overlap, and This is different from the first embodiment in that the gate lead-out wiring 16 does not overlap with the region between the drain region 2 and the source region 3 facing each other in plan view. Moreover, the width in the X direction of the opening of the element isolation insulating film 9 is small, and both ends of the gate electrode 4 run on the element isolation insulating film 9 also in the X direction, which is different from the first embodiment.

本実施の形態では、ゲート引き出し配線１６を、ソース領域３およびドレイン領域２同士の間の領域と重ねず、当該領域の横に配置することができるため、ソース領域３およびドレイン領域２同士の間が狭い場合でも、無理なくゲート引き出し配線１６を最小加工寸法以上の幅で形成することができる。つまり、ゲート電極４の長さａ１が仮に最小加工寸法である場合、前記実施の形態１のように、ゲート電極４のＹ方向の端部から、ゲート電極４よりも細いゲート引き出し配線１６を延ばそうとすると、最小加工寸法よりも長さｂ１が小さいゲート引き出し配線１６を形成することになるため、半導体装置の製造が困難となる。   In the present embodiment, the gate lead-out wiring 16 can be arranged beside the region between the source region 3 and the drain region 2 without overlapping with the region between the source region 3 and the drain region 2. Even when the width is narrow, the gate lead-out wiring 16 can be formed with a width equal to or larger than the minimum processing dimension without difficulty. That is, if the length a1 of the gate electrode 4 is the minimum processing dimension, the gate lead-out wiring 16 narrower than the gate electrode 4 is extended from the end of the gate electrode 4 in the Y direction as in the first embodiment. In this case, the gate lead-out wiring 16 having a length b1 smaller than the minimum processing dimension is formed, so that it becomes difficult to manufacture the semiconductor device.

これに対し、ここではゲート電極４の長さａ１を広げている。このため、素子分離絶縁膜９の開口部のＸ方向の幅が最小加工寸法である場合でも、ゲート引き出し配線１６を最小加工寸法より小さい幅で形成する必要はない。よって、ゲート引き出し配線１６の長さｂ１を大きくすることができるため、加工条件の緩和に伴う歩留り向上が可能となる。また、ゲート引き出し配線１６を比較的太く形成することができるため、ゲート引き出し配線１６の抵抗を低減することができる。   In contrast, the length a1 of the gate electrode 4 is increased here. For this reason, even when the width in the X direction of the opening of the element isolation insulating film 9 is the minimum processing dimension, it is not necessary to form the gate lead-out wiring 16 with a width smaller than the minimum processing dimension. Therefore, since the length b1 of the gate lead-out wiring 16 can be increased, it is possible to improve the yield accompanying the relaxation of the processing conditions. Further, since the gate lead-out wiring 16 can be formed relatively thick, the resistance of the gate lead-out wiring 16 can be reduced.

また、図６に示すように、ゲート電極４はドレイン領域２上において素子分離絶縁膜９上に広く乗り上げた構成となっている。このようにゲート電極４が乗り上げた長さの分、ドレイン領域２上の接続孔とソース領域３上の接続孔との間の間隔が広くなる。よって、図７に示すように、ゲート電極４から引き出したゲート引き出し配線１６をドレイン領域２上から引き出すことができる。したがって、ドレイン領域２とソース領域３との間の領域の直上にはゲート電極４（ゲート引き出し配線１６）が設けられていない。言い換えれば、ゲート引き出し配線１６は、ドレイン領域２とソース領域３との間の領域に対し、平面視で離間している。このため、素子分離絶縁膜９の下部においてドレイン−ソース間に界面欠陥が生成されることを防ぐことができ、前記実施の形態１に比べて、オフリーク電流をより低減することができる。   In addition, as shown in FIG. 6, the gate electrode 4 is configured to run over the element isolation insulating film 9 over the drain region 2. Thus, the distance between the connection hole on the drain region 2 and the connection hole on the source region 3 is increased by the length over which the gate electrode 4 rides. Therefore, as shown in FIG. 7, the gate lead wiring 16 drawn from the gate electrode 4 can be drawn from the drain region 2. Therefore, the gate electrode 4 (gate lead-out wiring 16) is not provided immediately above the region between the drain region 2 and the source region 3. In other words, the gate lead-out wiring 16 is separated from the region between the drain region 2 and the source region 3 in plan view. For this reason, it is possible to prevent generation of an interface defect between the drain and the source in the lower part of the element isolation insulating film 9, and the off-leakage current can be further reduced as compared with the first embodiment.

次に、図８〜図１４を用いて、本実施の形態の半導体装置の製造方法について説明する。図８〜図１４は、本実施の形態の半導体装置の製造工程中の断面図である。図８〜図１４は、図６と同じ位置を示す断面である。   Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 8 to 14 are sectional views of the semiconductor device according to the present embodiment during the manufacturing process. 8 to 14 are cross sections showing the same positions as those in FIG.

まず、図８に示すように、上面と、上面の反対側の裏面とを有するｎ型のＳｉＣ基板（半導体基板）１０を準備する。ＳｉＣ基板１０は、ＳｉＣ（炭化ケイ素）から成る基板である。続いて、ＳｉＣ基板１０の上面上に、エピタキシャル成長法を用いて、ＳｉＣから成るｎ型のエピタキシャル層１１を形成する。ここでは、エピタキシャル層１１にｎ型の不純物（例えばＮ（窒素））を導入しながらエピタキシャル層１１を成長させることにより、エピタキシャル層１１を所望の不純物濃度で形成することが可能となる。   First, as shown in FIG. 8, an n-type SiC substrate (semiconductor substrate) 10 having an upper surface and a rear surface opposite to the upper surface is prepared. SiC substrate 10 is a substrate made of SiC (silicon carbide). Subsequently, an n-type epitaxial layer 11 made of SiC is formed on the upper surface of the SiC substrate 10 using an epitaxial growth method. Here, the epitaxial layer 11 can be formed at a desired impurity concentration by growing the epitaxial layer 11 while introducing an n-type impurity (for example, N (nitrogen)) into the epitaxial layer 11.

次に、図９に示すように、フォトリソグラフィ技術およびイオン注入法を用いて、エピタキシャル層１１の上面にｐ型の不純物（例えばＡｌ（アルミニウム））を打ち込む。これにより、エピタキシャル層１１の上面に、ｐ型半導体領域である素子分離領域８を形成する。素子分離領域８は、エピタキシャル層１１の上面から、エピタキシャル層１１の途中深さまで達してアイソレーション領域に形成される。つまり、素子分離領域８は、後にＭＯＳＦＥＴが形成される領域を平面視で囲むように形成される。   Next, as shown in FIG. 9, a p-type impurity (for example, Al (aluminum)) is implanted into the upper surface of the epitaxial layer 11 by using a photolithography technique and an ion implantation method. Thereby, the element isolation region 8 which is a p-type semiconductor region is formed on the upper surface of the epitaxial layer 11. The element isolation region 8 is formed in the isolation region from the upper surface of the epitaxial layer 11 to the midway depth of the epitaxial layer 11. That is, the element isolation region 8 is formed so as to surround a region where a MOSFET is formed later in a plan view.

次に、図１０に示すように、フォトリソグラフィ技術およびイオン注入法を用いて、エピタキシャル層１１の上面にｐ型の不純物（例えばＡｌ（アルミニウム））を打ち込む。これにより、エピタキシャル層１１の上面に、ｐ型半導体領域（ｐ型拡散層）であるウェル１を形成する。ウェル１は、素子分離領域８よりもｐ型不純物濃度が低く、形成深さが深い。ただし、ウェル１の下面は、エピタキシャル層１１とＳｉＣ基板１０との界面に達していない。素子分離領域８は、ウェル１の上面に位置し、平面視で環状の形状を有している。   Next, as shown in FIG. 10, a p-type impurity (for example, Al (aluminum)) is implanted into the upper surface of the epitaxial layer 11 by using a photolithography technique and an ion implantation method. Thereby, the well 1 which is a p-type semiconductor region (p-type diffusion layer) is formed on the upper surface of the epitaxial layer 11. The well 1 has a lower p-type impurity concentration and a deeper formation depth than the element isolation region 8. However, the lower surface of the well 1 does not reach the interface between the epitaxial layer 11 and the SiC substrate 10. The element isolation region 8 is located on the upper surface of the well 1 and has an annular shape in plan view.

次に、図１１に示すように、フォトリソグラフィ技術およびイオン注入法を用いて、エピタキシャル層１１の上面にｎ型の不純物（例えばＮ（窒素））を高濃度で打ち込む。これにより、エピタキシャル層１１の上面に、ｎ＋型半導体領域であるソース領域３およびｎ＋型半導体領域であるドレイン領域２を形成する。ソース領域３およびドレイン領域２のそれぞれの形成深さは、ウェル１の深さよりも浅い。ソース領域３およびドレイン領域２は、ウェル１の上面において、平面視で素子分離領域８に囲まれる位置に形成する。 Next, as shown in FIG. 11, an n-type impurity (for example, N (nitrogen)) is implanted at a high concentration into the upper surface of the epitaxial layer 11 by using a photolithography technique and an ion implantation method. Thus, the upper surface of the epitaxial layer 11 to form the drain region 2 for the source region 3 and the n + -type semiconductor region and n + -type semiconductor region. The formation depth of each of the source region 3 and the drain region 2 is shallower than the depth of the well 1. The source region 3 and the drain region 2 are formed on the upper surface of the well 1 at a position surrounded by the element isolation region 8 in plan view.

次に、図１２に示すように、エピタキシャル層１１上に、例えばＣＶＤ（Chemical Vapor Deposition）法を用いて、比較的厚い絶縁膜を形成する。この絶縁膜は例えば酸化シリコンから成る。その後、当該絶縁膜をフォトリソグラフィ技術およびエッチング法を用いて加工（パターニング）し、これによりエピタキシャル層１１の上面を露出させ、当該絶縁膜から成る素子分離絶縁膜９を形成する。ここでは、互いに対向するソース領域３およびドレイン領域２同士の間の領域を露出する開口部を素子分離絶縁膜９に形成する。   Next, as shown in FIG. 12, a relatively thick insulating film is formed on the epitaxial layer 11 by using, for example, a CVD (Chemical Vapor Deposition) method. This insulating film is made of, for example, silicon oxide. Thereafter, the insulating film is processed (patterned) using a photolithography technique and an etching method, whereby the upper surface of the epitaxial layer 11 is exposed, and an element isolation insulating film 9 made of the insulating film is formed. Here, an opening for exposing a region between the source region 3 and the drain region 2 facing each other is formed in the element isolation insulating film 9.

続いて、エピタキシャル層１１上に、素子分離絶縁膜９よりも膜厚が薄いゲート絶縁膜１２と、導電膜とを例えばＣＶＤ法を用いて順に形成する。ゲート絶縁膜１２は例えば酸化シリコン膜から成り、導電膜は、例えばポリシリコン、Ａｌ（アルミニウム）またはＷ（タングステン）などから成る。続いて、フォトリソグラフィ技術およびエッチング法を用いて、上記導電膜を加工（パターニング）し、これにより、ゲート絶縁膜１２の一部の上面を露出させ、当該導電膜から成るゲート電極４およびゲート引き出し配線１６（図５参照）を形成する。すなわち、ゲート電極４は、ソース領域３およびドレイン領域２の相互間のエピタキシャル層１１（ウェル１）の上面の直上に、ゲート絶縁膜１２を介して形成される。   Subsequently, a gate insulating film 12 having a thickness smaller than that of the element isolation insulating film 9 and a conductive film are sequentially formed on the epitaxial layer 11 by using, for example, a CVD method. The gate insulating film 12 is made of, for example, a silicon oxide film, and the conductive film is made of, for example, polysilicon, Al (aluminum), W (tungsten), or the like. Subsequently, the conductive film is processed (patterned) by using a photolithography technique and an etching method, thereby exposing a part of the upper surface of the gate insulating film 12, and the gate electrode 4 and the gate lead made of the conductive film. A wiring 16 (see FIG. 5) is formed. That is, the gate electrode 4 is formed via the gate insulating film 12 immediately above the upper surface of the epitaxial layer 11 (well 1) between the source region 3 and the drain region 2.

次に、図１３に示すように、例えばＣＶＤ法を用いて、エピタキシャル層１１上に層間絶縁膜１３を形成する。層間絶縁膜１３は、例えば酸化シリコン膜から成る。ここでは、層間絶縁膜１３によりゲート電極４の側面および上面を覆い、ゲート絶縁膜１２および素子分離絶縁膜９のそれぞれの上面を覆う。続いて、層間絶縁膜１３をフォトリソグラフィ技術およびエッチング法を用いて加工することで、層間絶縁膜１３、ゲート絶縁膜１２および素子分離絶縁膜９を貫通し、エピタキシャル層１１の上面を露出する複数の接続孔を形成する。各接続孔の底部では、ソース領域３、ドレイン領域２または素子分離領域８が、層間絶縁膜１３、ゲート絶縁膜１２および素子分離絶縁膜９から成る積層膜から露出する。   Next, as shown in FIG. 13, an interlayer insulating film 13 is formed on the epitaxial layer 11 by using, for example, a CVD method. The interlayer insulating film 13 is made of, for example, a silicon oxide film. Here, the side surface and the upper surface of the gate electrode 4 are covered with the interlayer insulating film 13, and the upper surfaces of the gate insulating film 12 and the element isolation insulating film 9 are covered. Subsequently, the interlayer insulating film 13 is processed by using a photolithography technique and an etching method, thereby penetrating the interlayer insulating film 13, the gate insulating film 12, and the element isolation insulating film 9 and exposing the upper surface of the epitaxial layer 11. The connection hole is formed. At the bottom of each connection hole, the source region 3, the drain region 2, or the element isolation region 8 is exposed from the laminated film including the interlayer insulating film 13, the gate insulating film 12, and the element isolation insulating film 9.

次に、図１４に示すように、例えばスパッタリング法を用いて、上記接続孔内を含むエピタキシャル層１１上および層間絶縁膜１３上に金属膜を形成する。金属膜は、例えばＡｌ（アルミニウム）から成り、上記複数の接続孔のそれぞれの内部を埋め込んでいる。続いて、層間絶縁膜１３上の当該金属膜を、フォトリソグラフィ技術およびエッチング法を用いて加工し、これにより、層間絶縁膜１３の上面の一部を露出させる。この加工工程により、当該金属膜を分離し、当該金属膜から成るソース電極６およびドレイン電極５を形成する。ソース電極６はソース領域３に電気的に接続され、ドレイン電極５はドレイン領域２に電気的に接続されている。   Next, as shown in FIG. 14, a metal film is formed on the epitaxial layer 11 and the interlayer insulating film 13 including the inside of the connection hole by using, for example, a sputtering method. The metal film is made of, for example, Al (aluminum) and embeds each of the plurality of connection holes. Subsequently, the metal film on the interlayer insulating film 13 is processed using a photolithography technique and an etching method, thereby exposing a part of the upper surface of the interlayer insulating film 13. By this processing step, the metal film is separated, and the source electrode 6 and the drain electrode 5 made of the metal film are formed. The source electrode 6 is electrically connected to the source region 3, and the drain electrode 5 is electrically connected to the drain region 2.

続いて、例えばスパッタリング法を用いて、ＳｉＣ基板１０の裏面を覆う裏面電極１４を形成する。裏面電極１４は、例えばＡｕ（金）を含む導電膜であり、例えば単体デバイスであるならドレイン電極５に電気的に接続される。   Subsequently, the back electrode 14 covering the back surface of the SiC substrate 10 is formed by using, for example, a sputtering method. The back electrode 14 is a conductive film containing, for example, Au (gold), and is electrically connected to the drain electrode 5 if it is a single device, for example.

以上の工程により、本実施の形態の半導体装置として、ゲート電極４、ソース領域３およびドレイン領域２を備えたｎチャネル型ＭＯＳＦＥＴを形成することができる。これにより形成したＭＯＳＦＥＴでは、図５〜図７を用いて説明した半導体装置と同様の効果を得ることができる。また、本実施の形態の半導体装置を形成する工程では、図２０および図２１に示す比較例の半導体装置の製造工程に比べ、新たな工程を加える必要はなく、素子のレイアウトを変更するだけで、上記効果を得ることができる。つまり、半導体装置の製造工程が煩雑になること、および、半導体装置の製造コストが増大することを避けることができる。   Through the above steps, an n-channel MOSFET including the gate electrode 4, the source region 3, and the drain region 2 can be formed as the semiconductor device of the present embodiment. With the MOSFET thus formed, the same effects as those of the semiconductor device described with reference to FIGS. Further, in the process of forming the semiconductor device of this embodiment, it is not necessary to add a new process as compared with the manufacturing process of the semiconductor device of the comparative example shown in FIGS. 20 and 21, and only the element layout is changed. The above effects can be obtained. That is, it is possible to avoid a complicated manufacturing process of the semiconductor device and an increase in manufacturing cost of the semiconductor device.

ここでは、ゲート電極４からの引き出し配線１６をドレイン領域２の上を通るように配置することについて説明したが、引き出し配線１６は、ソース領域３の上を通るように配置されていてもよい。   Here, it has been described that the lead-out wiring 16 from the gate electrode 4 is disposed so as to pass over the drain region 2, but the lead-out wiring 16 may be disposed so as to pass over the source region 3.

（実施の形態３）
図１５に、本実施の形態３である半導体装置の平面図を示す。 (Embodiment 3)
FIG. 15 is a plan view of the semiconductor device according to the third embodiment.

本実施の形態の半導体装置は、ゲート幅方向におけるゲート電極４の両端のそれぞれの近傍において、素子分離絶縁膜９の下のドレイン領域２とソース領域３との間に、ウェル１より不純物濃度が高いｐ型の半導体領域である高濃度層１５が形成されている点で、前記実施の形態２と異なる。すなわち、ドレイン領域２とソース領域３との間のウェル１の上面であって、素子分離絶縁膜９に覆われた領域に、ｐ型の不純物（例えばＡｌ（アルミニウム））が導入された領域である高濃度層１５が形成されている。   In the semiconductor device of the present embodiment, the impurity concentration is higher than that of the well 1 between the drain region 2 and the source region 3 under the element isolation insulating film 9 in the vicinity of both ends of the gate electrode 4 in the gate width direction. The second embodiment is different from the second embodiment in that a high concentration layer 15 which is a high p-type semiconductor region is formed. That is, in a region where a p-type impurity (for example, Al (aluminum)) is introduced into a region covered with the element isolation insulating film 9 on the upper surface of the well 1 between the drain region 2 and the source region 3. A certain high concentration layer 15 is formed.

２つの高濃度層１５のそれぞれは、ゲート幅方向（Ｙ方向）におけるゲート電極４の端部と平面視で重なっている。また、高濃度層１５のＹ方向の端部であって、ゲート電極４側の端部は、素子分離絶縁膜９の開口部内のアクティブ領域と平面視で重なっている。高濃度層１５は、ウェル１を介して素子分離領域８と電気的に接続されているため、ソース領域３および素子分離領域８と同電位となる。つまり、高濃度層１５はソース領域３と電気的に接続されている。   Each of the two high concentration layers 15 overlaps the end portion of the gate electrode 4 in the gate width direction (Y direction) in plan view. Further, the end of the high concentration layer 15 in the Y direction, which is on the side of the gate electrode 4, overlaps with the active region in the opening of the element isolation insulating film 9 in plan view. Since the high concentration layer 15 is electrically connected to the element isolation region 8 through the well 1, it has the same potential as the source region 3 and the element isolation region 8. That is, the high concentration layer 15 is electrically connected to the source region 3.

上述した構成により、電界が集中し易いゲート電極４のゲート幅方向の端部において捕獲電荷の蓄積が促進されても、ウェル１の主表面においてチャネル層が形成されることを抑制できる。このため、前記実施の形態２に比べて、リーク電流の発生をさらに抑制できる。   With the configuration described above, it is possible to suppress the formation of a channel layer on the main surface of the well 1 even if the accumulation of trapped charges is promoted at the end in the gate width direction of the gate electrode 4 where the electric field tends to concentrate. For this reason, it is possible to further suppress the occurrence of leakage current as compared with the second embodiment.

（実施の形態４）
図１６に、本実施の形態４である半導体装置の平面図を示す。 (Embodiment 4)
FIG. 16 is a plan view of the semiconductor device according to the fourth embodiment.

本実施の形態の半導体装置は、ソース領域３と電気的に接続されたソース電極６の一部が、高濃度層１５と平面視で重なっている点で前記実施の形態３と異なる。このような構成により、電界が集中するゲート電極４の端部から漏れる電界に起因して素子分離絶縁膜９に蓄積される捕獲電荷を低減することができる。このため、前記実施の形態３に比べ、さらにリーク電流を低減できる。   The semiconductor device of this embodiment is different from that of Embodiment 3 in that a part of the source electrode 6 electrically connected to the source region 3 overlaps the high concentration layer 15 in plan view. With such a configuration, trapped charges accumulated in the element isolation insulating film 9 due to the electric field leaking from the end portion of the gate electrode 4 where the electric field concentrates can be reduced. For this reason, the leakage current can be further reduced as compared with the third embodiment.

ここで、図２２に、ゲート電圧とゲートおよび酸化膜の容量比との関係の変化をグラフで示す。図２２に示すグラフは、本発明者らが行った実験の結果であって、半導体装置を構成する絶縁膜に３ＭＶ／ｃｍを印加した条件でγ線を照射したＳｉＣデバイスのＣＶｇ特性（フラットバンド電圧特性）を示すものである。図２２に実線で示すグラフは、γ線照射前のフラットバンド電圧特性を示すものであり、破線で示すグラフは、γ線照射後のフラットバンド電圧特性を示すものである。図２２の縦軸のゲート容量Ｃｇは、ゲート電極の容量であり、当該縦軸の酸化膜容量Ｃｏｘは、絶縁膜の容量である。   Here, FIG. 22 is a graph showing a change in the relationship between the gate voltage and the capacitance ratio of the gate and the oxide film. The graph shown in FIG. 22 is a result of an experiment conducted by the present inventors, and shows a CVg characteristic (flat band) of an SiC device irradiated with γ rays under the condition that 3 MV / cm is applied to an insulating film constituting a semiconductor device. Voltage characteristics). The graph shown by the solid line in FIG. 22 shows the flat band voltage characteristic before γ-ray irradiation, and the graph shown by the broken line shows the flat band voltage characteristic after γ-ray irradiation. The gate capacitance Cg on the vertical axis in FIG. 22 is the capacitance of the gate electrode, and the oxide film capacitance Cox on the vertical axis is the capacitance of the insulating film.

図２２に示すように、１００ｋＧｙのγ線を照射した後のフラットバンド電圧は、照射前と比較して６．５Ｖ負側へシフトしている。これは、放射線により絶縁膜中で励起した電子−正孔対が、絶縁膜中の電界により分離され、絶縁膜と半導体層との界面で正孔がトラップされたことを示している。   As shown in FIG. 22, the flat band voltage after irradiating 100 kGy of γ-rays is shifted to the 6.5 V negative side compared to before irradiation. This indicates that electron-hole pairs excited in the insulating film by radiation are separated by an electric field in the insulating film, and holes are trapped at the interface between the insulating film and the semiconductor layer.

また、図２３に、ゲート電圧とゲートおよび酸化膜の容量比との関係の変化をグラフで示す。図２３は、本発明者らが行った実験の結果であって、半導体装置を構成する絶縁膜に電界を印加せずにγ線を照射したＳｉＣデバイスのＣＶｇ特性を示すものである。図２３に実線で示すグラフは、γ線照射前のフラットバンド電圧特性を示すものであり、破線で示すグラフは、γ線照射後のフラットバンド電圧特性を示すものである。図２３の縦軸のゲート容量Ｃｇは、ゲート電極の容量であり、当該縦軸の酸化膜容量Ｃｏｘは、絶縁膜の容量である。   FIG. 23 is a graph showing a change in the relationship between the gate voltage and the capacitance ratio of the gate and the oxide film. FIG. 23 shows the result of an experiment conducted by the present inventors and shows the CVg characteristics of an SiC device irradiated with γ rays without applying an electric field to an insulating film constituting a semiconductor device. A graph indicated by a solid line in FIG. 23 indicates a flat band voltage characteristic before γ-ray irradiation, and a graph indicated by a broken line indicates a flat band voltage characteristic after γ-ray irradiation. The gate capacitance Cg on the vertical axis in FIG. 23 is the capacitance of the gate electrode, and the oxide film capacitance Cox on the vertical axis is the capacitance of the insulating film.

図２３に示すように、γ線を１００ｋＧｙ照射した素子のＣＶ波形は照射前と殆ど一致しており、絶縁膜中の捕獲電荷の蓄積が確認されなかった。これは、絶縁膜に電界を印加していない場合、放射線により励起されたキャリアはドリフトできず、再結合確率が高くなるためである。このため、絶縁膜中の正孔は絶縁膜と半導体層との界面でトラップされ難くなっており、フラットバンド電圧は殆ど変化しなかった。   As shown in FIG. 23, the CV waveform of the element irradiated with 100 kGy of γ rays almost coincided with that before irradiation, and accumulation of trapped charges in the insulating film was not confirmed. This is because when an electric field is not applied to the insulating film, carriers excited by radiation cannot drift and the recombination probability increases. For this reason, holes in the insulating film are hardly trapped at the interface between the insulating film and the semiconductor layer, and the flat band voltage hardly changes.

以上に示した２つのグラフより、電界が印加されていない絶縁膜であれば、放射線が照射されたとしても、正電荷が蓄積され難いことが分かる。   From the two graphs shown above, it can be seen that, if an insulating film is not applied with an electric field, it is difficult to accumulate positive charges even when irradiated with radiation.

図１６に示すように、本実施の形態の高濃度層１５は、ウェル１および素子分離領域８を介してソース電極６と電気的に接続されており、高濃度層１５とソース電極６との間に挟まれた絶縁膜には殆ど電界が掛からない。このため、ゲート電極４から素子分離絶縁膜９および層間絶縁膜１３（図６参照）などに電界が漏れたとしても、平面視で互いに重なる高濃度層１５とソース電極６とに挟まれた領域においては界面欠陥が発生し難いため、リーク電流を抑制することができる。つまり、ソース領域３およびドレイン領域２の間の高濃度層１５上の絶縁膜（例えば素子分離絶縁膜９）を、互いに同電位の高濃度層１５とソース電極６とにより挟むことで、ソース領域３およびドレイン領域２の間でリークパスとなる界面欠陥が生じることを防ぐことができる。よって、前記実施の形態３に比べ、リーク電流の発生を防ぐことができる。   As shown in FIG. 16, the high concentration layer 15 of the present embodiment is electrically connected to the source electrode 6 through the well 1 and the element isolation region 8, and the high concentration layer 15 and the source electrode 6 are connected to each other. Almost no electric field is applied to the insulating film sandwiched therebetween. Therefore, even if an electric field leaks from the gate electrode 4 to the element isolation insulating film 9 and the interlayer insulating film 13 (see FIG. 6), the region sandwiched between the high concentration layer 15 and the source electrode 6 that overlap each other in plan view. In this case, since the interface defect hardly occurs, the leakage current can be suppressed. In other words, an insulating film (for example, the element isolation insulating film 9) on the high concentration layer 15 between the source region 3 and the drain region 2 is sandwiched between the high concentration layer 15 and the source electrode 6 having the same potential, whereby the source region It is possible to prevent an interface defect serving as a leak path between 3 and the drain region 2. Therefore, compared with the third embodiment, the occurrence of leakage current can be prevented.

＜変形例１＞
図１７に、本実施の形態４の変形例１である半導体装置の平面図を示す。図１７に示すように、高濃度層１５は、素子分離領域８と接していてもよい。これにより、高濃度層１５は素子分離領域８と電気的により低抵抗で接続される。このような構成とすることで、高濃度層１５とソース電極６との間に設けられた絶縁膜（例えば素子分離絶縁膜９）の電界がより緩和されるため、捕獲電荷の蓄積を、図１６に示した構造に比べて低減できる。 <Modification 1>
FIG. 17 is a plan view of a semiconductor device that is a first modification of the fourth embodiment. As shown in FIG. 17, the high concentration layer 15 may be in contact with the element isolation region 8. Thereby, the high concentration layer 15 is electrically connected to the element isolation region 8 with a lower resistance. With such a configuration, the electric field of the insulating film (for example, the element isolation insulating film 9) provided between the high concentration layer 15 and the source electrode 6 is further relaxed. Compared to the structure shown in FIG.

＜変形例２＞
図１８に、本実施の形態４の変形例２である半導体装置の平面図を示す。図１８に示すように、高濃度層１５と平面視で重なり、高濃度層１５と同電位となる電極は、ソース電極６でなくてもよい。ソース電極６およびドレイン電極５とは絶縁され、ソース電極６およびドレイン電極５とは離間している電極１７が、高濃度層１５と平面視で重なって形成されている。電極１７は、ソース電極６およびドレイン電極５と同じ工程で形成することができる金属パターンから成り、ソース電極６およびドレイン電極５と同じ高さに形成されている。 <Modification 2>
FIG. 18 is a plan view of a semiconductor device that is a second modification of the fourth embodiment. As shown in FIG. 18, the electrode overlapping the high concentration layer 15 in plan view and having the same potential as the high concentration layer 15 may not be the source electrode 6. An electrode 17 that is insulated from the source electrode 6 and the drain electrode 5 and separated from the source electrode 6 and the drain electrode 5 is formed so as to overlap the high concentration layer 15 in plan view. The electrode 17 is made of a metal pattern that can be formed in the same process as the source electrode 6 and the drain electrode 5, and is formed at the same height as the source electrode 6 and the drain electrode 5.

電極１７には、高濃度層１５と同じ電位が印加される。例えば、高濃度層１５にソース電位、つまり０Ｖが印加される場合には、電極１７にも０Ｖが印加される。このように、高濃度層１５上の絶縁膜の電界を緩和するために、高濃度層１５と平面視で重ねて配置される電極１７は、ソース電極６と異なる電極であってもよい。これにより、図１６を用いて説明した半導体装置と同様の効果を得ることができる。   The same potential as that of the high concentration layer 15 is applied to the electrode 17. For example, when a source potential, that is, 0 V is applied to the high concentration layer 15, 0 V is also applied to the electrode 17. As described above, in order to relax the electric field of the insulating film on the high concentration layer 15, the electrode 17 disposed so as to overlap the high concentration layer 15 in plan view may be an electrode different from the source electrode 6. Thereby, the same effect as that of the semiconductor device described with reference to FIG. 16 can be obtained.

（実施の形態５）
図１９に、本実施の形態５である半導体装置の平面図を示す。図１９に示すように、本願発明は、半導体基板の主表面において互いに近接して設けられた複数のトランジスタのそれぞれに適用してもよい。当該複数のトランジスタは、ｎチャネル型トランジスタ５０とｐチャネル型トランジスタ５１であり、共に１つの集積回路を構成している。 (Embodiment 5)
FIG. 19 is a plan view of the semiconductor device according to the fifth embodiment. As shown in FIG. 19, the present invention may be applied to each of a plurality of transistors provided close to each other on the main surface of a semiconductor substrate. The plurality of transistors are an n-channel transistor 50 and a p-channel transistor 51, which together constitute one integrated circuit.

ｎチャネル型トランジスタ５０は、前記実施の形態２のＭＯＳＦＥＴと同じ構造を有している。ただし、ドレイン電極５は、ｐチャネル型トランジスタ５１側に延在している。ｐチャネル型トランジスタ５１は、ドレイン電極５と重なる線を軸としてｎチャネル型トランジスタ５０と線対称なレイアウトを有している。すなわち、ｐチャネル型トランジスタ５１は、半導体基板の上面に形成されたｎ型のウェル４１をチャネル層として有し、ウェル４１の上面には、ｐ型の半導体領域であるソース領域４３とドレイン領域４２とが形成されている。ウェル４１、ソース領域４３およびドレイン領域４２を囲むように、ｎ型の半導体領域である素子分離領域４８がウェル４１の上面に形成されており、ウェル４１上には、開口部を有する素子分離絶縁膜９が形成されている。当該開口部を覆うように、ウェル４１上にはゲート絶縁膜（図示しない）を介してゲート電極４４が形成されている。ドレイン領域４２はプラグ７を介してドレイン電極５に接続されており、ソース領域４３はプラグ７を介してソース電極４６に接続されている。ｐチャネル型トランジスタ５１は、ゲート電極４４、ソース領域４３およびドレイン領域４２により構成されている。   The n-channel transistor 50 has the same structure as the MOSFET of the second embodiment. However, the drain electrode 5 extends to the p-channel transistor 51 side. The p-channel transistor 51 has a layout that is symmetrical with the n-channel transistor 50 about the line overlapping the drain electrode 5 as an axis. That is, the p-channel transistor 51 has an n-type well 41 formed on the upper surface of the semiconductor substrate as a channel layer. And are formed. An element isolation region 48, which is an n-type semiconductor region, is formed on the upper surface of the well 41 so as to surround the well 41, the source region 43, and the drain region 42. A film 9 is formed. A gate electrode 44 is formed on the well 41 via a gate insulating film (not shown) so as to cover the opening. The drain region 42 is connected to the drain electrode 5 through the plug 7, and the source region 43 is connected to the source electrode 46 through the plug 7. The p-channel transistor 51 includes a gate electrode 44, a source region 43, and a drain region 42.

ゲート電極４４から引き出されたゲート引き出し配線５６は、ドレイン領域４２上を通ってＹ方向に延在しており、ドレイン領域４２とソース領域４３との間の領域の直上には形成されていない。このため、ｎチャネル型トランジスタ５０およびｐチャネル型トランジスタ５１のそれぞれにおいて、前記実施の形態２と同様の効果を得ることができる。すなわち、耐放射線性の優れた集積回路を形成することが可能となる。   The gate lead wiring 56 led out from the gate electrode 44 extends in the Y direction through the drain region 42 and is not formed immediately above the region between the drain region 42 and the source region 43. Therefore, in each of the n-channel transistor 50 and the p-channel transistor 51, the same effect as in the second embodiment can be obtained. That is, an integrated circuit having excellent radiation resistance can be formed.

以上、本発明者らによってなされた発明をその実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能である。   As mentioned above, the invention made by the present inventors has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. is there.

例えば、上述した各実施の形態およびそれらの変形例は、互いに組み合わせてもよい。   For example, the above-described embodiments and modifications thereof may be combined with each other.

１、４１ ウェル
２、４２ ドレイン領域
３、４３ ソース領域
４、４４ ゲート電極
５ ドレイン電極
６、４６ ソース電極
８、４８ 素子分離領域
９ 素子分離絶縁膜
１６、２０、５６ ゲート引き出し配線 1, 41 Well 2, 42 Drain region 3, 43 Source region 4, 44 Gate electrode 5 Drain electrode 6, 46 Source electrode 8, 48 Element isolation region 9 Element isolation insulating film 16, 20, 56 Gate lead wiring

Claims (10)

半導体基板と、
前記半導体基板の上面に形成され、互いに第１方向に隣り合うソース領域およびドレイン領域と、
前記半導体基板上に形成され、前記ソース領域および前記ドレイン領域の相互間の前記半導体基板の前記上面である第１領域の一部を露出する素子分離絶縁膜と、
前記素子分離絶縁膜から露出する前記第１領域の一部の上に、前記素子分離絶縁膜より薄いゲート絶縁膜を介して形成されたゲート電極と、
前記ゲート電極と一体となって接続されており、前記素子分離絶縁膜上に形成されたゲート引き出し配線と、
を有し、
前記ゲート電極、前記ソース領域および前記ドレイン領域は、電界効果トランジスタを構成しており、
前記ゲート引き出し配線は、平面視において、前記ソース領域または前記ドレイン領域の一方と離間している、半導体装置。 A semiconductor substrate;
A source region and a drain region formed on the upper surface of the semiconductor substrate and adjacent to each other in the first direction;
An element isolation insulating film formed on the semiconductor substrate and exposing a portion of the first region which is the upper surface of the semiconductor substrate between the source region and the drain region;
A gate electrode formed on a part of the first region exposed from the element isolation insulating film via a gate insulating film thinner than the element isolation insulating film;
A gate lead wiring formed integrally on the gate electrode and formed on the element isolation insulating film;
Have
The gate electrode, the source region and the drain region constitute a field effect transistor,
The semiconductor device, wherein the gate lead wiring is separated from one of the source region and the drain region in plan view. 請求項１記載の半導体装置において、
前記ゲート引き出し配線は、前記第１領域に対し平面視で離間している、半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the gate lead wiring is separated from the first region in plan view. 請求項１記載の半導体装置において、
前記半導体基板の前記上面に形成され、上面に前記ソース領域および前記ドレイン領域が形成されたウェルと、
平面視で前記ゲート電極のゲート幅方向の端部と重なる前記第１領域に形成され、前記ウェルよりも不純物濃度が高い第１半導体領域と、
をさらに有し、
前記ウェルおよび前記第１半導体領域は、前記ソース領域および前記ドレイン領域とは異なる導電型を有している、半導体装置。 The semiconductor device according to claim 1,
A well formed on the upper surface of the semiconductor substrate and having the source region and the drain region formed on the upper surface;
A first semiconductor region formed in the first region overlapping with an end of the gate electrode in the gate width direction in plan view and having a higher impurity concentration than the well;
Further comprising
The semiconductor device, wherein the well and the first semiconductor region have a different conductivity type from the source region and the drain region. 請求項３記載の半導体装置において、
前記第１半導体領域は、前記ソース領域と電気的に接続されている、半導体装置。 The semiconductor device according to claim 3.
The semiconductor device, wherein the first semiconductor region is electrically connected to the source region. 請求項３記載の半導体装置において、
前記第１半導体領域の直上に前記素子分離絶縁膜を介して形成された第１電極をさらに有し、
前記第１電極には、前記第１半導体領域と同じ電位が印加される、半導体装置。 The semiconductor device according to claim 3.
A first electrode formed directly on the first semiconductor region via the element isolation insulating film;
The semiconductor device, wherein the same potential as that of the first semiconductor region is applied to the first electrode. 請求項４記載の半導体装置において、
前記第１半導体領域の直上に前記素子分離絶縁膜を介して形成され、前記ソース領域と電気的に接続されたソース電極をさらに有する、半導体装置。 The semiconductor device according to claim 4.
A semiconductor device further comprising a source electrode formed directly above the first semiconductor region via the element isolation insulating film and electrically connected to the source region. 請求項３記載の半導体装置において、
前記半導体基板の前記上面に形成され、前記ウェル、前記ソース領域および前記ドレイン領域を平面視で囲む第２半導体領域である素子分離領域をさらに有し、
前記素子分離領域は、前記ウェルと同じ導電型を有しており、
前記素子分離領域と前記第１半導体領域とは、互いに接している、半導体装置。 The semiconductor device according to claim 3.
An element isolation region which is a second semiconductor region formed on the upper surface of the semiconductor substrate and surrounds the well, the source region, and the drain region in plan view;
The element isolation region has the same conductivity type as the well,
The element isolation region and the first semiconductor region are in contact with each other. 請求項１記載の半導体装置において、
前記ゲート電極のゲート長方向において、前記ゲート引き出し配線の長さは、前記ゲート電極の長さよりも小さい、半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein a length of the gate lead-out wiring is smaller than a length of the gate electrode in a gate length direction of the gate electrode. 請求項１記載の半導体装置において、
前記半導体基板は、シリコンよりもバンドギャップが大きい材料から成る、半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the semiconductor substrate is made of a material having a larger band gap than silicon. （ａ）半導体基板を準備する工程、
（ｂ）前記半導体基板の上面にソース領域およびドレイン領域を形成する工程、
（ｃ）前記（ｂ）工程の後、前記半導体基板上に第１絶縁膜を形成する工程、
（ｄ）前記第１絶縁膜をパターニングすることで、前記ソース領域および前記ドレイン領域の相互間の前記半導体基板の前記上面である第１領域の一部を露出する開口部を備えた、前記第１絶縁膜から成る素子分離絶縁膜を形成する工程、
（ｅ）前記第１領域および前記素子分離絶縁膜を覆うように、前記半導体基板上に、前記素子分離絶縁膜より膜厚が小さいゲート絶縁膜と、導電膜とを順に形成する工程、
（ｆ）前記導電膜をパターニングすることで、前記導電膜から成り、前記開口部内で前記第１領域上に位置するゲート電極と、前記導電膜から成り、前記ゲート電極と一体となって接続されているゲート引き出し配線とを形成する工程と、
を有し、
前記ゲート電極、前記ソース領域および前記ドレイン領域は、電界効果トランジスタを構成しており、
前記ゲート引き出し配線は、平面視において、前記ソース領域または前記ドレイン領域の一方と離間している、半導体装置の製造方法。 (A) a step of preparing a semiconductor substrate;
(B) forming a source region and a drain region on the upper surface of the semiconductor substrate;
(C) after the step (b), forming a first insulating film on the semiconductor substrate;
(D) The first insulating film is patterned to include an opening that exposes a part of the first region that is the upper surface of the semiconductor substrate between the source region and the drain region. Forming an element isolation insulating film comprising one insulating film;
(E) a step of sequentially forming a gate insulating film having a thickness smaller than the element isolation insulating film and a conductive film on the semiconductor substrate so as to cover the first region and the element isolation insulating film;
(F) The conductive film is patterned to form the conductive film, the gate electrode located on the first region in the opening, and the conductive film, which are integrally connected to the gate electrode. Forming a gate lead-out wiring,
Have
The gate electrode, the source region and the drain region constitute a field effect transistor,
The method of manufacturing a semiconductor device, wherein the gate lead-out wiring is separated from one of the source region and the drain region in plan view.
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