WO2020239028A1 - 栅极驱动电路、显示装置及显示控制方法 - Google Patents

栅极驱动电路、显示装置及显示控制方法 Download PDF

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Publication number
WO2020239028A1
WO2020239028A1 PCT/CN2020/092932 CN2020092932W WO2020239028A1 WO 2020239028 A1 WO2020239028 A1 WO 2020239028A1 CN 2020092932 W CN2020092932 W CN 2020092932W WO 2020239028 A1 WO2020239028 A1 WO 2020239028A1
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Prior art keywords
circuit
display area
signal
sub
gate driving
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PCT/CN2020/092932
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English (en)
French (fr)
Inventor
黄耀
黄炜赟
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/264,695 priority Critical patent/US11482156B2/en
Publication of WO2020239028A1 publication Critical patent/WO2020239028A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology. Specifically, the present application relates to a gate driving circuit, a display device, and a display control method.
  • a conventional display device in different display areas of the display device, such as the first display area and the second display area, when simultaneous display is required, two separate gate activation signal terminals STV1 and STV2 are directed to the corresponding The display area outputs a gate start signal.
  • the first display area and the second display area are displayed under the control of the gate start signals output by the corresponding gate start signal terminals STV1 and STV2.
  • an embodiment of the present application provides a gate driving circuit, including: a first gate driving sub-circuit, an input terminal of the first gate driving sub-circuit is electrically connected to a gate start signal terminal, the The multiple output terminals of the first gate driving sub-circuit are electrically connected to the multiple sub-pixel rows in the first display area of the display device, and are used to output scan signals and control the first display area to display according to the scan signals;
  • An area control unit the input end of the display area control unit is connected to one of the output ends of the first gate drive sub-circuit, and is used to receive the scan signal output by the first gate drive sub-circuit
  • the control terminal of the display area control unit is connected to the split-screen control signal terminal, and is used to receive the split-screen control signal output by the split-screen control signal terminal, and the output terminal of the display area control unit is used to Screen control signal and output or not output the scanning signal; and a second gate driving sub-circuit, the input terminal of the second gate driving sub-circuit is electrically connected
  • the display area control unit includes: a first transistor; a first pole of the first transistor is used as an input terminal of the display area control unit, and an output terminal of the first gate driving sub-circuit Electrically connected, the control electrode of the first transistor is electrically connected to the split-screen control signal end, the second electrode of the first transistor is used as the output end of the display area control unit, and the display area control unit is configured In order to receive the first control signal output by the split-screen control signal terminal in the full-screen display stage, output the scanning signal output from one output terminal of the first gate driving sub-circuit at the output terminal, and receive the The second control signal output by the split-screen control signal terminal does not output the scanning signal at the output terminal.
  • the display area control unit further includes a capacitor; two ends of the capacitor are electrically connected to the input end and the output end of the display area control unit, respectively.
  • the first gate driving sub-circuit includes M cascaded first shift registers
  • the second gate driving sub-circuit includes N cascaded second shift registers.
  • the M, N is a positive integer greater than or equal to 2
  • the signal input terminal of the first shift register of the first stage is connected to the gate start signal terminal
  • the output terminal of the first shift register of the Mth stage is connected to the display area control unit
  • the signal input terminal of the first second shift register is connected to the output terminal of the display area control unit.
  • an embodiment of the present application provides a display device, including a first display area, a second display area, and the gate driving circuit described above; the first gate driver in the gate driving circuit The circuit is electrically connected to each sub-pixel row in the first display area; the display area control unit in the gate drive circuit is electrically connected to the first gate drive sub-circuit and the second gate drive sub-circuit Between circuits; the second gate driving sub-circuit in the gate driving circuit is electrically connected to each sub-pixel row in the second display area.
  • the display device further includes: a drive control circuit for providing the gate start signal and the split screen control signal.
  • an embodiment of the present application provides a display control method, which is applied to the aforementioned gate drive circuit, and includes: in a full-screen display stage, providing a first control signal to the split-screen control signal terminal so that the The display area control unit transmits the scan signal output from one output terminal of the first gate driving sub-circuit to the input terminal of the second gate driving sub-circuit; and in the split-screen display stage, to the split-screen control The signal terminal provides a second control signal, so that the display area control unit does not transmit a scan signal output from an output terminal of the first gate driving sub-circuit to the input terminal of the second gate driving sub-circuit.
  • FIG. 1A is a schematic diagram of the overall circuit structure of the display panel
  • FIG. 1B shows a schematic typical structure of EMGOA
  • FIG. 1C shows the working sequence diagram of EMGOA
  • FIG. 2 is a schematic diagram of the difference in display conditions between two adjacent display areas in a conventional display device
  • FIG. 3 is a schematic diagram of the waveform of the EOUT' signal output by the shift register EM-(n) in a conventional display device;
  • FIG. 4 is a schematic diagram of the waveform of the ESTV2' signal output by the shift register EM-(n+1) in a conventional display device;
  • FIG. 5 is a schematic diagram of a part of the structure of the gate driving circuit in an embodiment of the application, and the corresponding relationship between the gate driving circuit and the display area, and the corresponding relationship with the sub-pixel row;
  • FIG. 6 is a schematic diagram of a part of the structure of the gate driving circuit in an embodiment of the application, and the corresponding relationship between the gate driving circuit and the display area, and the corresponding relationship with the sub-pixel row;
  • FIG. 7 is a schematic diagram of a part of the structure of the gate driving circuit in an embodiment of the application, and the corresponding relationship between the gate driving circuit and the display area, and the corresponding relationship with the sub-pixel row;
  • Fig. 8 is the gate drive circuit in the embodiment of the application.
  • the EOUT' signal output by the shift register EM-(n) and the ESTV2' signal output by the shift register EM-(n+1) Schematic diagram of the waveform;
  • Figure 9 is a gate drive circuit in an embodiment of the application.
  • the EOUT' signal output by the shift register EM-(n) and the ESTV2' signal output by the shift register EM-(n+1) Schematic diagram of waveform
  • FIG. 10 is a schematic diagram of the signal output status of the gate driving circuit in the embodiment of the application in the multi-area display stage and the partial display stage, the split-screen display control signal terminal V1, the half-screen control signal terminal V2, and the display area adjustment signal terminal V3 ;
  • FIG. 11 is a schematic diagram of a part of the structure of the gate driving circuit in an embodiment of the application, and the corresponding relationship between the gate driving circuit and the display area, and the corresponding relationship with the sub-pixel row;
  • FIG. 12 is a schematic diagram of the signal output status of the split-screen display control signal terminal V1 during the multi-area display stage and the partial display stage of the gate driving circuit in the embodiment of the application.
  • Fig. 13 shows a flowchart of a display control method according to an embodiment of the present application.
  • FIG. 1A is a schematic diagram of the overall circuit structure of a display panel.
  • the display panel includes a base substrate 101, and the base substrate 101 includes a display area (ie, a pixel array area) 102 and a peripheral area 106 located around the display area 102.
  • the peripheral area 106 surrounds the display area 102.
  • the display area 102 includes pixel units 103 arranged in an array, and the peripheral area 106 includes a shift register unit 104.
  • a plurality of cascaded shift register units 104 form a gate drive circuit, which is used to transfer the array in the display area 102 of the display panel.
  • the arranged pixel units 103 provide, for example, gate scan signals shifted row by row.
  • the peripheral area 106 also includes a light-emitting control unit 105.
  • a plurality of cascaded light-emitting control units 105 form a light-emitting control array for providing, for example, row-by-row shifted light emission to the pixel units 103 arranged in the array in the display area 102 of the display panel. control signal.
  • the display panel further includes a data driving chip IC located in the peripheral area 106, and the data driving chip IC is configured to provide data signals to the pixel units 103 arranged in an array.
  • the data lines D1-DN (N is an integer greater than 1) connected to the data driving chip IC pass through the display area 102 longitudinally (for example, the vertical direction in the figure) to provide data signals for the pixel units 103 of each column.
  • the gate line G1-GM (M is an integer greater than 1) connected to the shift register unit 104 crosses the display area 102 laterally (for example, the horizontal direction in the figure), and the light-emitting control line E1-EM(M) connected to the light-emitting control unit 105 Is an integer greater than 1) transversely penetrates the display area 102 to provide gate scanning signals and light emission control signals for the pixel units 103 arranged in an array.
  • each pixel unit 103 may include pixel circuits and light-emitting elements with circuit structures such as 7T1C, 8T2C, or 4T1C in the art.
  • the pixel circuits transmit data signals through data lines and gate scan signals through gate lines and emit light It works under the control of the light-emitting control signal transmitted by the control line E1-EM to drive the light-emitting element to emit light to realize operations such as display.
  • the light emitting element may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).
  • Fig. 1B shows a schematic typical structure of EMGOA
  • Fig. 1C shows a working sequence diagram of EMGOA.
  • the first clock signal CK is low, so the first transistor M1 and the third transistor M3 are turned on, and the turned-on first transistor M1 transmits the high-level start signal ESTV to the first Node N1, so that the level of the first node N1 becomes a high level, so the second transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned off.
  • the turned-on third transistor M3 transmits the low-level fourth voltage VGL to the second node N2, so that the level of the second node N2 becomes low, so the fifth transistor M5 and the sixth transistor M6 Is turned on.
  • the seventh transistor M7 Since the second clock signal CB is at a high level, the seventh transistor M7 is turned off. In addition, due to the storage effect of the third capacitor C3, the level of the fourth node N4 can be maintained at a high level, so that the ninth transistor M9 is turned off. In the first stage P1, since the ninth transistor M9 and the tenth transistor M10 are both turned off, the emission control pulse signal EM output by the emission control shift register unit EGOA maintains the previous low level.
  • the second clock signal CB is low, so the fourth transistor M4 and the seventh transistor M7 are turned on. Since the first clock signal CK is at a high level, the first transistor M1 and the third transistor M3 are turned off. Due to the storage function of the first capacitor C1, the second node N2 can continue to maintain the low level of the previous stage, so the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the high-level third voltage VGH is transmitted to the first node N1 through the turned-on fifth transistor M5 and the fourth transistor M4, so that the level of the first node N1 continues to maintain the high level of the previous stage, so the second The transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned off.
  • the low-level second clock signal CB is transmitted to the fourth node N4 through the turned-on sixth transistor M6 and the seventh transistor M7, so that the level of the fourth node N4 becomes low, so the ninth The transistor M9 is turned on, and the turned-on ninth transistor M9 outputs a high-level third voltage VGH, so the light-emission control pulse signal EM output by the light-emission control shift register unit EGOA in the second phase P2 is high.
  • the first clock signal CK is low, so the first transistor M1 and the third transistor M3 are turned on.
  • the second clock signal CB is at a high level, so the fourth transistor M4 and the seventh transistor M7 are turned off. Due to the storage function of the third capacitor C3, the level of the fourth node N4 can maintain the low level of the previous stage, so that the ninth transistor M9 remains in the on state, and the turned-on ninth transistor M9 will be high.
  • the third voltage VGH is output, so the emission control pulse signal EM output by the emission control shift register unit EGOA in the third stage P3 is still at a high level.
  • the first clock signal CK is at a high level, so the first transistor M1 and the third transistor M3 are turned off.
  • the second clock signal CB is low, so the fourth transistor M4 and the seventh transistor M7 are turned on. Due to the storage effect of the second capacitor C2, the level of the first node N1 maintains the high level of the previous stage, so that the second transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned off. Due to the storage effect of the first capacitor C1, the second node N2 continues to maintain the low level of the previous stage, so that the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the low-level second clock signal CB is transmitted to the fourth node N4 through the turned-on sixth transistor M6 and the seventh transistor M7, so that the level of the fourth node N4 becomes low, so the ninth The transistor M9 is turned on, and the turned-on ninth transistor M9 outputs a high-level third voltage VGH, so the light-emission control pulse signal EM output by the light-emission control shift register unit EGOA in the second stage P2 is still at a high level .
  • the first clock signal CK is low, so the first transistor M1 and the third transistor M3 are turned on.
  • the second clock signal CB is at a high level, so the fourth transistor M4 and the seventh transistor M7 are turned off.
  • the turned-on first transistor M1 transmits the low-level start signal ESTV to the first node N1, so that the level of the first node N1 becomes low, so the second transistor M2, the eighth transistor M8, and the first node N1 Ten transistor M10 is turned on.
  • the turned-on second transistor M2 transmits the low-level first clock signal CK to the second node N2, thereby further lowering the level of the second node N2, so the second node N2 continues to maintain the low power level of the previous stage Level, so that the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the turned-on eighth transistor M8 transmits the high-level third voltage VGH to the fourth node N4, so that the level of the fourth node N4 becomes high, so the ninth transistor M9 is turned off.
  • the turned-on tenth transistor M10 outputs a low-level fourth voltage VGL, so the light-emission control pulse signal EM output by the light-emission control shift register unit EGOA in the fifth stage P5 becomes a low level.
  • the inventor of the present application found that there are differences in display conditions between two adjacent display areas in a conventional display device.
  • two adjacent display areas that are bounded by the folding position of the display device are prone to display differences when both display areas are displayed.
  • the first There is a difference in display conditions between the display area 1'and the second display area 2', which obviously affects the screen display effect of the display device.
  • the inventor of the present application has discovered through research that, in a conventional display device, it is required that the two gate activation signal terminals STV1 and STV2 can be connected to their respective display areas (for example, the first display area 1'and the second display area 2 in FIG. ') Only by outputting the same gate start signal can the two display areas show coordinated pictures at the same time.
  • the control system of the display device needs to be provided with a control module that adjusts the frame synchronization of the two gate start signal terminals. To a certain extent, frame control for the two gate signal terminals increases the control burden of the display device.
  • the inventor of the present application also found that even if the gate activation signal terminals STV1 and STV2 corresponding to the two display areas can output the same gate activation signal, at the boundary position of the two adjacent display areas, the first The waveform of the signal EOUT' received by the last row of sub-pixels Pixel(n) in one display area and output by the shift register EM-(n) is the same as the first row of sub-pixels Pixel(n+1) in the second display area. ) The waveforms of the signal ESTV2' received and output by the shift register EM-(n+1) are different. The waveforms of EOUT' and ESTV2' are shown in Figure 3 and Figure 4, respectively. This also causes a difference in display conditions between the first display area and the second display area, which affects the screen display effect of the display device.
  • the gate driving circuit, the display device, and the display control method provided in the present application aim to at least partially solve the technical problem of display differences that occur when adjacent display areas output images at the same time in the prior art.
  • the embodiment of the application provides a gate driving circuit, as shown in FIG. 5 to FIG. 7, comprising: a first gate driving sub-circuit 4, a second gate driving sub-circuit 5, a display area control unit 3, and a gate Start the signal terminal STV.
  • the first gate driving sub-circuit is electrically connected to the gate activation signal terminal STV, and is electrically connected to the sub-pixel row corresponding to the first display area 1 of the display device, for receiving the gate activation signal through the gate activation signal terminal STV and
  • the gate start signal is output to the display area control unit, and the first display area 1 is controlled to display according to the gate start signal.
  • the display area control unit 3 is electrically connected between the first gate drive sub-circuit and the second gate drive sub-circuit, and is used at least to control the electrical connection between the first gate drive sub-circuit and the second gate drive sub-circuit.
  • the connection is on or off to control whether to transmit the gate start signal.
  • the gate start signal is a gate start signal output from the gate start signal terminal STV.
  • the second gate driving sub-circuit is electrically connected to the display area control unit 3, and is electrically connected to the sub-pixel row corresponding to the second display area 2 of the display device, for controlling the second display area according to whether the gate activation signal is received 2 display status.
  • the gate driving circuit provided by the embodiment of the present invention includes two gate driving sub-circuits for controlling the display conditions of different display areas.
  • the two gate driving sub-circuits are the first gate driving sub-circuit and the second gate driving sub-circuit.
  • Gate drive sub-circuit The display area control unit controls the display state of the second display area 2 according to whether the gate activation signal is transmitted.
  • the first gate driving sub-circuit is used to control the display status of the first display area 1 at least
  • the second gate driving sub-circuit is used to control the display status of the second display area 2 at least.
  • the first gate driving sub-circuit and the second gate driving sub-circuit of the gate driving circuit in the embodiments of the present application share a gate enable signal terminal STV, so that the first display area 1 and the second display area of the display device 2
  • the source of the gate start signal received by the two gate drive sub-circuits respectively used to control the first display area 1 and the second display area 2 is the same; the two gate drive sub-circuits
  • the timing of the gate activation signal received by each circuit is also the same.
  • the display device does not need to implement special control operations to coordinate the timing relationship between the two display areas, or add corresponding timing adjustment modules, which reduces the control burden of the system and ensures the display Good coordination between the first display area 1 and the second display area of the device.
  • the technical means of configuring a gate start signal terminal STV for each display area is adopted, so that during the manufacturing process of the display device, it is necessary to target each gate Start the signal terminal STV for separate detection, which increases the complexity of the production process.
  • the technical solutions in the embodiments of the present application can avoid increasing the amount of inspection work for the gate start signal terminal STV to a greater extent.
  • the gate start signal terminal STV in the embodiment of the present application may only be a circuit for transmitting the gate start signal, and does not include a signal source for generating the gate start signal. It may also include a circuit for transmitting the gate start signal and a signal source for generating the gate start signal.
  • the specific design scheme of the gate start signal terminal STV can be a conventional gate start signal terminal STV, which will not be repeated here.
  • the gate start signal terminal STV when the first display area 1 and the second display area 2 both perform display functions, the gate start signal terminal STV outputs the gate start signal to the first gate driving sub-circuit, The first gate driving sub-circuit outputs the received gate start signal to each sub-pixel row corresponding to the first gate driving sub-circuit, and each sub-pixel row corresponding to the first gate driving sub-circuit is based on the gate The gate start signal output by the start signal terminal STV performs image display.
  • the first The gate drive sub-circuit outputs the gate start signal to the display area control unit 3, and the display area control unit 3 outputs the gate start signal to the second gate drive sub-circuit.
  • the second gate driving sub-circuit outputs the received gate activation signal to each sub-pixel row corresponding to the second gate driving sub-circuit, so that each sub-pixel row corresponding to the second gate driving sub-circuit is based on the gate
  • the gate start signal output by the start signal terminal STV performs image display.
  • the first display area 1 and the second display area 2 in the embodiment of the present application are both displayed according to the gate start signal output by the same gate start signal terminal STV, which greatly reduces the source of the gate start signal.
  • the difference in the display conditions between the two display areas caused by the difference and the waveform difference ensures the image output effect of the display device in the multi-area display stage.
  • the shift register EM-(n) of the first gate driving sub-circuit outputs the signal EOUT1 to the corresponding sub-pixel row Pixel(n).
  • the waveform of the signal EOUT2 output by the corresponding sub-pixel row Pixel(n+1) is shown in FIG. 8. It can be seen that the waveforms of the signal EOUT1, the signal EOUT1-1, and the signal EOUT2 are basically the same, and the timing of the three signals is also basically the same.
  • the gate driving circuit of the embodiment of the present application can eliminate the difference in the waveform of the signal received by each sub-pixel row of the first display area 1 and the second display area 2 and the signal timing The way to reduce the display difference between the first display area 1 and the second display area 2, where n is a positive integer.
  • the display area control unit 3 is used to control the signal communication between the first gate driving sub-circuit and the second gate driving sub-circuit.
  • the off part is disconnected, the gate start signal terminal STV outputs the gate start signal to the first gate driver sub-circuit, and the first gate driver sub-circuit outputs the received gate start signal to the first gate driver
  • Each sub-pixel row corresponding to the sub-circuit makes each sub-pixel row corresponding to the first gate driving sub-circuit perform image display according to the gate start signal output by the gate start signal terminal STV.
  • the display area control unit 3 turns off the second gate driving sub-circuit to receive the gate start signal from the first gate driving sub-circuit, and the second gate driving sub-circuit stops receiving the gate start from the first gate driving sub-circuit The gate start signal output by the signal terminal STV. Then, the second gate driving sub-circuit no longer controls the display state of each sub-pixel row corresponding to the second gate driving sub-circuit according to the gate start signal generated at the gate start signal terminal STV.
  • the first display area 1 and the second display area 2 are adjacent display areas in the display device.
  • the attribution of the sub-pixel row can be divided according to the light-emitting condition of the sub-pixel row and the display condition of the display area. When a certain display area is displayed and a certain sub-pixel stops receiving the gate start signal, the sub-pixel Pixels do not belong to the display area.
  • the boundary between the first display area 1 and the second display area 2 is the folding position of the display device.
  • the folding and flattening operations of the display device are used to trigger the display area control unit 3 to control the gate activation signal output path between the first gate driving sub-circuit and the second gate driving sub-circuit to close and conduct Operation.
  • the display area control unit 3 controls the gate activation signal between the first gate driving sub-circuit and the second gate driving sub-circuit The output path is closed, and the second gate drive sub-circuit no longer controls the display status of the second display area 2 according to the gate start signal output by the gate start signal terminal STV; when the first display area 1 and the second display area 2 are When the relative position of the flattening changes, the display area control unit 3 controls the gate start signal output path between the first gate driving sub-circuit and the second gate driving sub-circuit to conduct, and the second gate driving sub-circuit is based on The gate start signal output by the gate start signal terminal STV controls the display status of the second display area 2.
  • the gate driving circuit includes: a first gate driving sub-circuit, a second gate driving sub-circuit, a third gate driving sub-circuit, a first display area control unit, a second The display area control unit and the gate start signal terminal STV.
  • the gate start signal terminal STV is electrically connected with the first gate driving sub-circuit.
  • the first display area control unit is electrically connected to the first gate driving sub-circuit and the second gate driving sub-circuit, and is used to control the electrical connection between the first gate driving sub-circuit and the second gate driving sub-circuit. On and off, to control whether to transmit the gate start signal.
  • the second gate driving sub-circuit is electrically connected to the first display area control unit, and is electrically connected to the sub-pixel row corresponding to the second display area of the display device, for controlling the second display according to whether the gate activation signal is received The display status of the area.
  • the second display area control unit is electrically connected to the second gate driving sub-circuit and the third gate driving sub-circuit, respectively, for controlling the electrical connection between the second gate driving sub-circuit and the third gate driving sub-circuit On and off, to control whether to transmit the gate start signal.
  • the third gate driving sub-circuit is electrically connected to the second display area control unit, and is electrically connected to the sub-pixel row corresponding to the third display area of the display device, for controlling the third display area according to whether the gate activation signal is received
  • the second display area control unit is electrically connected to the first gate driving sub-circuit and the third gate driving sub-circuit, for controlling the first gate driving sub-circuit and the third gate driving sub-circuit
  • the electrical connection between the circuits is turned on and off to control whether to transmit the gate start signal.
  • the gate driving circuit may further include more gate driving sub-circuits and more display area control units.
  • the gate driving sub-circuit electrically connected to the gate start signal terminal STV is the first gate driving sub-circuit.
  • the second gate driving sub-circuit and the third gate driving sub-circuit can be determined according to the transmission sequence of the gate start signal, or according to the relative positional relationship with the first gate driving sub-circuit on the display device.
  • the first gate driving sub-circuit and the second gate driving sub-circuit each include a plurality of In the shift register, the first gate driving sub-circuit or the second gate driving sub-circuit of the two adjacent shift registers in the starting sequence, the signal output terminal of the previous shift register is electrically connected to the next shift register Signal input terminal.
  • the signal input end of the display area control unit 3 is electrically connected to the signal output end of the shift register EM-(n) in the first gate driving sub-circuit, and the signal output end of the display area control unit 3 is electrically connected to the second gate driver
  • the signal input end of the first shift register EM-(n+1) of the circuit is electrically connected.
  • the gate start signal is from the first gate
  • the shift register EM-(n) in the driving sub-circuit is transferred to the first shift register EM-(n+1) of the second gate driving sub-circuit.
  • the shift registers in the first gate driving sub-circuit and the second gate driving sub-circuit may be conventional shift registers. Each shift register is used at least to output a gate activation signal to at least one sub-pixel row, and then control the display status of the sub-pixel row according to the gate activation signal.
  • the first shift register EM-(1) in the first gate driving sub-circuit is electrically connected to the gate start signal terminal STV.
  • the gate start signal output by the gate start signal terminal STV is output to the first shift register EM-(1) in the first gate drive sub-circuit, and the first shift register in the first gate drive sub-circuit
  • the register EM-(1) outputs the gate activation signal to the corresponding sub-pixel row Pixel(1), and outputs the gate activation signal to the second shift register EM in the first gate driving sub-circuit -(2).
  • the order of the shift registers and the gate start signal are among the shift registers in the gate driving sub-circuit.
  • the transmission sequence is the same between.
  • the shift register directly electrically connected to the gate start signal terminal STV is the first shift register EM-(1) of the first gate driving sub-circuit.
  • the signal input terminal of each shift register in the embodiment of the application is a signal input terminal with a signal input function.
  • the signal input terminal of the first shift register EM-(1) in the first gate driving sub-circuit is electrically connected to the gate start signal terminal STV, and is at least used to receive the gate start signal from the gate start signal terminal STV .
  • the signal input terminals of the remaining shift registers are at least electrically connected to the signal output terminal of the previous shift register in the output sequence of the gate start signal, and are at least used to receive the gate start signal output by the previous shift register .
  • the signal output terminal of each shift register is a signal output terminal with signal output function.
  • the signal output end of each shift register is at least electrically connected with the signal input end of the next shift register in the output sequence of the gate start signal, and is at least used for outputting the gate start signal to the next shift register.
  • the signal input terminal of the display area control unit 3 is a signal input terminal with a signal input function.
  • the signal output terminal of the display area control unit 3 is a signal output terminal with a signal output function.
  • the signal input terminal of the display area control unit 3 is at least used to receive a gate start signal from the signal output terminal electrically connected to the shift register,
  • the gate start signal is output to the signal output end of the display area control unit 3, and the signal output end of the display area control unit 3 outputs the gate start signal to the signal input end of the shift register electrically connected to it.
  • the circuit transmitting the gate start signal from the first gate driving sub-circuit to the second gate driving sub-circuit is disconnected, and the first The second display area 2 stops displaying according to the gate start signal.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is electrically connected to the signal output terminal of the display area control unit 3.
  • the “shift register EM-(n)” is a shift register that is electrically connected to the display area control unit 3 in the first gate driving sub-circuit and outputs a gate activation signal to the display area control unit 3.
  • the display area control unit 3 is used to control the on/off of the gate start signal between the first gate drive sub-circuit and the second gate drive sub-circuit, and the display area control unit 3 is also used to control the shift register EM -(n) and the corresponding sub-pixel row Pixel (n) between the gate start signal on and off.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is under the control of the display area control unit 3
  • the gate start signal output by the shift register EM-(n) is received, and the corresponding display is performed.
  • the sub-pixel row Pixel(n) and the second display area 2 corresponding to the shift register EM-(n) are displayed in the display area control unit Under the control of 3, stop receiving the gate start signal output by the shift register EM-(n), and stop performing the corresponding display.
  • the display area control unit 3 includes: a first transistor TFT1, a second transistor TFT2, a split-screen display control signal terminal V1, a half-screen control signal terminal V2, and a display area adjustment signal terminal V3.
  • the first electrode of the first transistor TFT1 is used as the signal input terminal of the display area control unit 3.
  • the control electrode of the first transistor TFT1 is electrically connected to the split-screen display control signal terminal V1; the first electrode of the second transistor TFT2 is connected to the display area adjustment signal
  • the terminal V3 is electrically connected, the control electrode of the second transistor TFT2 is electrically connected to the half-screen control signal terminal V2, and the respective second electrodes of the first transistor TFT1 and the second transistor TFT2 are used together as the signal output terminal of the display area control unit 3.
  • the signal output end of the shift register EM-(n) is electrically connected to the first electrode of the first transistor TFT1, and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) It is electrically connected to the second electrode of the first transistor TFT1, and the signal input terminal of the first shift register EM-(n+1) of the second gate driving sub-circuit is electrically connected to the second electrode of the first transistor TFT1.
  • the gate enable signal output from the signal output terminal of the shift register EM-(n) is directed to the second gate drive sub-circuit and to the shift register EM-(n)
  • the output path of the sub-pixel row Pixel(n) is turned on.
  • the second gate driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) display according to the gate start signal output from the signal output terminal of the shift register EM-(n) .
  • the gate enable signal output from the signal output terminal of the shift register EM-(n) is directed to the second gate driving sub-circuit and to the corresponding shift register EM-(n)
  • the output path of the sub-pixel row Pixel(n) is broken. Then the second gate driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) no longer display according to the gate start signal output by the shift register EM-(n).
  • the on and off states of the first transistor TFT1 are controlled by the split screen display control signal terminal V1 electrically connected to the control electrode of the first transistor TFT1.
  • the split-screen display control signal terminal V1 outputs a high-level second signal to the control electrode of the first transistor TFT1
  • the split-screen display control signal terminal V1 controls the first transistor TFT1
  • the first control signal at the low level is output, the first transistor TFT1 is turned on.
  • the high or low level of the signal for controlling the on or off of the first transistor TFT1 depends on the type of the first transistor.
  • the first electrode of the second transistor TFT2 is electrically connected to the display area adjustment signal terminal V3.
  • the second pole of the second transistor TFT2 and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n), the first shift register EM-(n+1) of the second gate driving sub-circuit The signal input terminal and the second electrode of the first transistor TFT1 are electrically connected.
  • the second display area 2 When the second display area 2 is no longer displaying, or when the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the high-level off display signal output by the display area adjustment signal terminal V3 is output to the second gate
  • the driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) the second display area 2 corresponding to the second gate driving sub-circuit and the shift register EM-(n)
  • the corresponding sub-pixel row Pixel(n) stops displaying.
  • the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the gate start signal output by the display area adjustment signal terminal V3 is output to The second gate driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n), the second display area 2 corresponding to the second gate driving sub-circuit and the shift register EM -(n)
  • the corresponding sub-pixel row Pixel (n) is displayed according to the gate start signal output from the display area adjustment signal terminal V3.
  • the on and off states of the second transistor TFT2 are controlled by the half-screen control signal terminal V2 electrically connected to the control electrode of the second transistor TFT2.
  • the half-screen control signal terminal V2 when the half-screen control signal terminal V2 outputs the second signal at a high level to the control electrode of the second transistor TFT2, the second transistor TFT2 is turned off; when the half-screen control signal terminal V2 controls the second transistor TFT2 When the first control signal at the low level is output, the second transistor TFT2 is turned on.
  • the high or low level of the signal for controlling the turning on or off of the second transistor TFT2 depends on the type of the second transistor.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is electrically connected to the signal output terminal of the shift register EM-(n) .
  • the “shift register EM-(n)” is a shift register in the first gate driving sub-circuit that is electrically connected to the display area control unit 3 and outputs a gate start signal to the display area control unit 3.
  • the shift register EM-(n) is the shift register in the first gate driving sub-circuit corresponding to the first display area 1.
  • the shift register EM-(n) is electrically connected to the display area control unit 3 through its signal output terminal, and the shift register EM-(n) is connected to the shift register EM-(n) through its signal output terminal.
  • the corresponding sub-pixel row Pixel(n) is electrically connected.
  • the signal output terminal of the shift register EM-(n) is used to output a signal to the signal input terminal of the display area control unit 3 and also to output a signal to the corresponding sub-pixel row Pixel(n).
  • each shift register has the same structure as the shift register EM-(n), the arrangement of the signal terminals, and the The connection relationship of the corresponding sub-pixel rows.
  • the gate activation signal output by the signal output terminal of the shift register EM-(n) is output to the corresponding sub-pixel row Pixel(n) and the signal input terminal of the display area control unit 3.
  • the display area control unit 3 outputs the gate start signal to the second gate drive sub-circuit, then the first display area 1 and the second display area 2 are based on The gate start signal of the gate start signal terminal STV performs a display function.
  • each sub-pixel row in the first display area (including the sub-pixel row Pixel(n) corresponding to the shift register EM-(n))
  • the display function is performed according to the gate start signal of the gate start signal terminal STV, and the second display area 2 does not perform the display function according to the gate start signal of the gate start signal terminal STV.
  • the display area control unit 3 includes: a first transistor TFT1, a second transistor TFT2, a split-screen display control signal terminal V1, a half-screen control signal terminal V2, and a display area adjustment signal terminal V3.
  • the first electrode of the first transistor TFT1 is used as the signal input terminal of the display area control unit 3.
  • the control electrode of the first transistor TFT1 is electrically connected to the split-screen display control signal terminal V1; the first electrode of the second transistor TFT2 is connected to the display area adjustment signal
  • the terminal V3 is electrically connected, the control electrode of the second transistor TFT2 is electrically connected to the half-screen control signal terminal V2, and the respective second electrodes of the first transistor TFT1 and the second transistor TFT2 are used together as the signal output terminal of the display area control unit 3.
  • the signal output terminal of the shift register EM-(n) is respectively connected to the first pole of the first transistor TFT1, and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) Electric connection.
  • the second electrode of the first transistor TFT1 is electrically connected to the signal input terminal of the first shift register EM-(n+1) in the second gate driving sub-circuit.
  • the gate start signal output from the signal output terminal of the shift register EM-(n) is turned on to the second gate driving sub-circuit. Then, each sub-pixel row corresponding to each of the second gate driving sub-circuit and the first gate driving sub-circuit is displayed according to the gate activation signal.
  • the path of the gate start signal output from the signal output terminal of the shift register EM-(n) to the second gate driving sub-circuit is disconnected. Then the second gate driving sub-circuit no longer displays according to the gate start signal.
  • the electrical connection relationship between the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) and the shift register EM-(n) is no longer affected by the display area control unit 3 control.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is also displayed.
  • the on and off states of the first transistor TFT1 are controlled by the split-screen display control signal terminal V1 electrically connected to the control electrode of the first transistor TFT1.
  • the split-screen display control signal terminal V1 when the split-screen display control signal terminal V1 outputs a high-level second signal to the control electrode of the first transistor TFT1, the first transistor TFT1 is turned off; when the split-screen display control signal terminal V1 controls the first transistor TFT1 When the second signal at the low level is output, the first transistor TFT1 is turned on.
  • the high or low level of the signal controlling the on or off of the first transistor TFT1 depends on the type of the first transistor.
  • the first transistor TFT1 may be a P-type transistor or an N-type transistor.
  • the first electrode of the second transistor TFT2 is electrically connected to the display area adjustment signal terminal V3, the second electrode of the second transistor TFT2 is electrically connected to the second electrode of the first transistor TFT1, and the first shift register of the second gate driving sub-circuit
  • the first pole of Pixel(n+1) is electrically connected.
  • the shift register EM-(n) of the first gate driving sub-circuit outputs the signal EOUT1 to the corresponding sub-pixel row Pixel(n), and the first gate driving sub-circuit
  • the signal EOUT1-1 output by two shift registers EM-(n), and the first shift register EM-(n+1) of the second gate drive sub-circuit to the corresponding sub-pixel row Pixel(n+ 1)
  • the waveform of the output signal EOUT2 is shown in Figure 8. It can be seen that the waveforms of the signal EOUT1, the signal EOUT1-1, and the signal EOUT2 are basically the same, and the timing of the three signals is also basically the same.
  • the gate driving circuit introduced in the embodiments of the present application can eliminate the difference in the waveforms and signal waveforms of the signals received by each sub-pixel row in the first display area 1 and the second display area 2.
  • the difference in timing reduces the display difference between the first display area 1 and the second display area 2.
  • the shift register EM-(n) outputs the signal EOUT1 to the corresponding sub-pixel row Pixel(n), to the first shift register of the second gate drive sub-circuit
  • the signal EOUT1-1 output by EM-(n+1) and the first shift register EM-(n+1) of the second gate drive sub-circuit to the corresponding sub-pixel row Pixel(n+1)
  • the waveform of the output signal EOUT2 is shown in Figure 9. It can be seen that in the partial display stage, the second display area 2 does not display, the second display area 2 does not receive the gate start signal, and the corresponding EOUT1-1 has no effective waveform display. At this time, the signal EOUT2 output by the first shift register EM-(n+1) of the second gate driving sub-circuit to the corresponding sub-pixel row is the high-level signal output from the display area adjustment signal terminal V3 Turn off the display signal.
  • the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the gate start signal output by the display area adjustment signal terminal V3 is output to The second gate driving sub-circuit, then the second display area 2 performs display.
  • the on and off states of the second transistor TFT2 are controlled by the half-screen control signal terminal V2 electrically connected to the control electrode of the second transistor TFT2.
  • the half-screen control signal terminal V2 when the half-screen control signal terminal V2 outputs the second signal at a high level to the control electrode of the second transistor TFT2, the second transistor TFT2 is turned off; when the half-screen control signal terminal V2 controls the first transistor TFT1 When the first control signal at the low level is output, the second transistor TFT2 is turned on.
  • the high or low level of the signal for controlling the turning on or off of the second transistor TFT2 depends on the type of the second transistor.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is electrically connected to the second signal of the shift register EM-(n) The output terminal.
  • the “shift register EM-(n)” is a shift register that is electrically connected to the display area control unit 3 in the first gate driving sub-circuit and outputs a gate activation signal to the display area control unit 3.
  • the shift register EM-(n) is the shift register in the first gate driving sub-circuit corresponding to the first display area 1.
  • the shift register EM-(n) is electrically connected to the display area control unit 3 through its signal output terminal, and the shift register EM-(n) is connected to the shift register EM-( n) The corresponding sub-pixel row Pixel(n) is electrically connected.
  • the signal output terminal of the shift register EM-(n) is used to output a gate start signal to the display area control unit 3, and the second signal output terminal of the shift register EM-(n) is used to output a corresponding signal
  • the sub-pixel row Pixel(n) outputs a gate start signal.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) receives the shift register EM-(n)
  • the second signal output terminal outputs the gate start signal and performs corresponding display.
  • the second gate driving sub-circuit receives the gate start signal output from the signal output terminal of the shift register EM-(n), and performs corresponding display.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) receives the output of the shift register EM-(n)
  • the second gate drive sub-circuit under the control of the display area control unit 3, stops receiving the gate output from the signal output terminal of the shift register EM-(n) and performs corresponding display; Start signal, stop corresponding display according to grid start signal.
  • the display area control unit 3 includes: a first transistor TFT1, a second transistor TFT2, a split-screen display control signal terminal V1, a half-screen control signal terminal V2, and a display area adjustment signal terminal V3.
  • the first electrode of the first transistor TFT1 is used as the signal input terminal of the display area control unit 3.
  • the control electrode of the first transistor TFT1 is electrically connected to the split-screen display control signal terminal V1; the first electrode of the second transistor TFT2 is connected to the display area adjustment signal
  • the terminal V3 is electrically connected, the control electrode of the second transistor TFT2 is electrically connected to the half-screen control signal terminal V2, and the respective second electrodes of the first transistor TFT1 and the second transistor TFT2 are used together as the signal output terminal of the display area control unit 3.
  • the signal output terminal of the shift register EM-(n) is electrically connected to the first electrode of the first transistor TFT1.
  • the second signal output terminal of the shift register EM-(n) is electrically connected to the sub-pixel row Pixel(n) corresponding to the shift register EM-(n).
  • the signal output terminal and the second signal output terminal of the shift register EM-(n) are both signal output terminals with signal output function.
  • the gate start signal output from the signal output terminal of the shift register EM-(n) is turned on to the second gate driving sub-circuit. Then, each sub-pixel row corresponding to each of the second gate driving sub-circuit and the first gate driving sub-circuit is displayed according to the gate activation signal.
  • the path of the gate start signal output from the signal output terminal of the shift register EM-(n) to the second gate driving sub-circuit is disconnected. Then the second gate driving sub-circuit does not display according to the gate start signal output by the shift register EM-(n).
  • the electrical connection between the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) and the shift register EM-(n) is provided by the shift register EM-(n)
  • the second signal output terminal controls that the display status of the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) will no longer be affected by the display area control unit 3.
  • the on and off states of the first transistor TFT1 are controlled by the split-screen display control signal terminal V1 electrically connected to the control electrode of the first transistor TFT1.
  • the split-screen display control signal terminal V1 outputs a high-level second signal to the control electrode of the first transistor TFT1
  • the split-screen display control signal terminal V1 controls the first transistor TFT1
  • the first control signal at the low level is output, the first transistor TFT1 is turned on.
  • the high or low level of the signal for controlling the on or off of the first transistor TFT1 depends on the type of the first transistor.
  • the first electrode of the second transistor TFT2 is electrically connected to the display area adjustment signal terminal V3, the second electrode of the second transistor TFT2 is electrically connected to the second electrode of the first transistor TFT1, and the first shift register of the second gate driving sub-circuit
  • the signal input terminal of EM-(n+1) is electrically connected.
  • the shift register EM-(n) of the first gate driving sub-circuit outputs the signal EOUT1 to the corresponding sub-pixel row Pixel(n), and the first gate driving sub-circuit
  • the signal EOUT1-1 output by two shift registers EM-(n+1) and the first shift register EM-(n+1) of the second gate drive sub-circuit to the corresponding sub-pixel row Pixel( n+1)
  • the waveform of the output signal EOUT2 is shown in Figure 8. It can be seen that the waveforms of the signal EOUT1, the signal EOUT1-1, and the signal EOUT2 are basically the same, and the timing of the three signals is also basically the same.
  • the gate driving circuit introduced in the embodiments of the present application can eliminate the difference in the waveforms and signal waveforms of the signals received by each sub-pixel row in the first display area 1 and the second display area 2.
  • the difference in timing reduces the display difference between the first display area 1 and the second display area 2.
  • the shift register EM-(n) outputs the signal EOUT1 to the corresponding sub-pixel row, and outputs the signal to the first shift register EM-(n+1) of the second gate drive sub-circuit
  • the signal EOUT1-1 and the waveform of the signal EOUT2 output by the first shift register EM-(n+1) of the second gate driving sub-circuit to the corresponding sub-pixel row are shown in FIG. 9. It can be seen that in the partial display stage, the second display area 2 does not display, the second display area 2 does not receive the gate start signal, and the corresponding EOUT1-1 has no effective waveform display.
  • the signal EOUT2 output by the first shift register EM-(n+1) of the second gate driving sub-circuit to the corresponding sub-pixel row Pixel(n+1) is the display area adjustment signal terminal V3 output
  • the off display signal is a high level signal in this embodiment.
  • the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the gate start signal output by the display area adjustment signal terminal V3 is output to The second gate driving sub-circuit, and the second display area 2 corresponding to the second gate driving sub-circuit performs display.
  • the on and off states of the second transistor TFT2 are controlled by the half-screen control signal terminal V2 electrically connected to the control electrode of the second transistor TFT2.
  • the half-screen control signal terminal V2 when the half-screen control signal terminal V2 outputs the second signal at a high level to the control electrode of the second transistor TFT2, the second transistor TFT2 is turned off; when the half-screen control signal terminal V2 controls the first transistor TFT1 When the first control signal at the low level is output, the second transistor TFT2 is turned on.
  • the high or low level of the signal for controlling the turning on or off of the second transistor TFT2 depends on the type of the second transistor.
  • both the first gate driving sub-circuit and the second gate driving sub-circuit include a plurality of shift registers electrically connected in sequence.
  • the signal input end of the display area control unit 3 is electrically connected to the signal output end of the shift register EM-(n) in the first gate driving sub-circuit, and the signal output end of the display area control unit 3 is electrically connected to the second gate driver
  • the signal input end of the first shift register EM-(n+1) of the circuit is electrically connected.
  • the gate start signal is from the first gate
  • the shift register EM-(n) in the driving sub-circuit is transferred to the first shift register EM-(n+1) of the second gate driving sub-circuit.
  • the signal output terminal of the previous shift register is electrically connected to the signal input terminal of the next shift register.
  • the shift registers in the first gate driving sub-circuit and the second gate driving sub-circuit may be conventional shift registers. Each shift register is used at least to output a gate activation signal to at least one sub-pixel row, and then control the display status of the sub-pixel row according to the gate activation signal.
  • the first shift register EM-(1) in the first gate driving sub-circuit is electrically connected to the gate start signal terminal STV.
  • the gate start signal output by the gate start signal terminal STV is output to the first shift register EM-(1) in the first gate drive sub-circuit, and the first shift register in the first gate drive sub-circuit
  • the register EM-(1) outputs the gate activation signal to the corresponding sub-pixel row Pixel(1), and outputs the gate activation signal to the second shift register EM in the first gate driving sub-circuit -(2).
  • the order of the shift registers and the gate start signal are among the shift registers in the gate driving sub-circuit.
  • the transmission sequence is the same between.
  • the shift register directly electrically connected to the gate start signal terminal STV is the first shift register of the first gate driving sub-circuit.
  • the signal input terminal of each shift register in the embodiment of the application is a signal input terminal with a signal input function.
  • the signal input terminal of the first shift register EM-(1) in the first gate driving sub-circuit is electrically connected to the gate start signal terminal STV, and is at least used to receive the gate start signal from the gate start signal terminal STV .
  • the signal input terminals of the remaining shift registers are at least electrically connected to the signal output terminal of the previous shift register in the output sequence of the gate start signal, and are at least used to receive the gate start signal output by the previous shift register.
  • the signal output terminal of each shift register is a signal output terminal with signal output function.
  • each shift register is at least electrically connected with the signal input end of the next shift register in the output sequence of the gate start signal, and is at least used for outputting the gate start signal to the next shift register.
  • the second signal output terminal of each shift register is a signal output terminal with a signal output function.
  • the second signal output terminal of each shift register is electrically connected to at least the sub-pixel row corresponding to the shift register, and is used to output a gate activation signal to the sub-pixel row.
  • the signal input terminal of the display area control unit 3 is a signal input terminal with a signal input function.
  • the signal output terminal of the display area control unit 3 is a signal output terminal with a signal output function.
  • the signal input terminal of the display area control unit 3 is at least used to receive the gate start signal from the signal output terminal of the shift register electrically connected to it , And output the gate start signal to the signal output end of the display area control unit 3, and the signal output end of the display area control unit 3 outputs the gate start signal to the signal input end of the shift register electrically connected to it.
  • the circuit transmitting the gate start signal from the first gate driving sub-circuit to the second gate driving sub-circuit is disconnected, and the first The second display area 2 stops displaying according to the gate start signal.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is electrically connected to the signal output terminal of the display area control unit 3.
  • the “shift register EM-(n)” is a shift register that is electrically connected to the display area control unit 3 in the first gate driving sub-circuit and outputs a gate activation signal to the display area control unit 3.
  • the display area control unit 3 is used to control the on/off of the gate start signal between the first gate drive sub-circuit and the second gate drive sub-circuit, and the display area control unit 3 is also used to control the shift register EM -(n) and the corresponding sub-pixel row Pixel (n) between the gate start signal on and off.
  • the sub-pixel row Pixel(n) and the second display area 2 corresponding to the shift register EM-(n) are in the display area Under the control of the control unit 3, the gate start signal output by the shift register EM-(n) is received, and the corresponding display is performed.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) stops receiving under the control of the display area control unit 3.
  • the gate start signal output by the shift register EM-(n) stops the corresponding display.
  • the display area control unit 3 includes: a first transistor TFT1, a second transistor TFT2, a split-screen display control signal terminal V1, a half-screen control signal terminal V2, and a display area adjustment signal terminal V3.
  • the first electrode of the first transistor TFT1 is used as the signal input terminal of the display area control unit 3.
  • the control electrode of the first transistor TFT1 is electrically connected to the split-screen display control signal terminal V1; the first electrode of the second transistor TFT2 is connected to the display area adjustment signal
  • the terminal V3 is electrically connected, the control electrode of the second transistor TFT2 is electrically connected to the half-screen control signal terminal V2, and the respective second electrodes of the first transistor TFT1 and the second transistor TFT2 are used together as the signal output terminal of the display area control unit 3.
  • the signal output terminal of the shift register EM-(n) is electrically connected to the first electrode of the first transistor TFT1.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is electrically connected to the second electrode of the first transistor TFT1, and the first shift register EM-(n+1 of the second gate driving sub-circuit
  • the signal input terminal of) is electrically connected to the second electrode of the first transistor TFT1.
  • the gate start signal output from the signal output terminal of the shift register EM-(n) is directed to the second gate driving sub-circuit and to the corresponding shift register EM-(n)
  • the output path of the sub-pixel row Pixel(n) is turned on.
  • the second gate driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) perform display according to the gate start signal output by the shift register EM-(n).
  • the gate enable signal output from the signal output terminal of the shift register EM-(n) is directed to the second gate driving sub-circuit and to the sub-circuit corresponding to the shift register EM-(n).
  • the output path of the pixel row Pixel(n) is broken.
  • the second gate driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) no longer display according to the gate activation signal.
  • the electrical connection relationship between the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) and the shift register EM-(n) is controlled by the display area control unit 3.
  • the on and off states of the first transistor TFT1 are controlled by the split-screen display control signal terminal V1 electrically connected to the control electrode of the first transistor TFT1.
  • the split-screen display control signal terminal V1 outputs a high-level second signal to the control electrode of the first transistor TFT1
  • the first transistor TFT1 is turned off; when the split-screen display control signal terminal V1 controls the first transistor TFT1
  • the first control signal at the low level is output, the first transistor TFT1 is turned on.
  • the high or low level of the signal for controlling the on or off of the first transistor TFT1 depends on the type of the first transistor.
  • the first transistor TFT1 may be a P-type transistor or an N-type transistor.
  • the first electrode of the second transistor TFT2 is electrically connected to the display area adjustment signal terminal V3.
  • the second electrode of the second transistor TFT2 is electrically connected to the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) and the second electrode of the first transistor TFT1.
  • the second display area 2 is no longer displaying, or when the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the high-level off display signal output by the display area adjustment signal terminal V3 is output to the second gate
  • the driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) then the second gate driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) n) Stop displaying.
  • the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the gate start signal output by the display area adjustment signal terminal V3 is output to
  • the second gate driving sub-circuit and the sub-pixel corresponding to the shift register EM-(n) Line Pixel(n) for display.
  • the on and off states of the second transistor TFT2 are controlled by the half-screen control signal terminal V2 electrically connected to the control electrode of the second transistor TFT2.
  • the half-screen control signal terminal V2 when the half-screen control signal terminal V2 outputs the second signal at a high level to the control electrode of the second transistor TFT2, the second transistor TFT2 is turned off; when the half-screen control signal terminal V2 controls the first transistor TFT1 When the first control signal at the low level is output, the second transistor TFT2 is turned on.
  • the high or low level of the signal for controlling the turning on or off of the second transistor TFT2 depends on the type of the second transistor.
  • the second transistor TFT2 may be a P-type transistor or an N-type transistor.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is electrically connected to the second signal output terminal of the shift register EM-(n).
  • the “shift register EM-(n)” is a shift register that is electrically connected to the display area control unit 3 in the first gate driving sub-circuit and outputs a gate activation signal to the display area control unit 3.
  • the display area control unit 3 is used to control the on and off of the gate start signal between the first gate driving sub-circuit and the second gate driving sub-circuit.
  • the second gate driving sub-circuit and the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) receive The gate start signal output by the second signal output terminal of the shift register EM-(n) is displayed accordingly.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is received by the shift register EM-(n)
  • the gate start signal output by the second signal output terminal of the performs corresponding display.
  • the second display area 2 stops receiving the gate start signal output from the second signal output terminal of the shift register EM-(n), and stops performing corresponding display.
  • the display area control unit 3 includes: a first transistor TFT1, a second transistor TFT2, a split-screen display control signal terminal V1, a half-screen control signal terminal V2, and a display area adjustment signal terminal V3.
  • the first electrode of the first transistor TFT1 is used as the signal input terminal of the display area control unit 3.
  • the control electrode of the first transistor TFT1 is electrically connected to the split-screen display control signal terminal V1; the first electrode of the second transistor TFT2 is connected to the display area adjustment signal
  • the terminal V3 is electrically connected, the control electrode of the second transistor TFT2 is electrically connected to the half-screen control signal terminal V2, and the respective second electrodes of the first transistor TFT1 and the second transistor TFT2 are used together as the signal output terminal of the display area control unit 3.
  • the second signal output terminal of the shift register EM-(n) is electrically connected to the first electrode of the first transistor TFT1, and the sub-pixel row corresponding to the shift register EM-(n) Pixel(n) is electrically connected.
  • the second pole of the first transistor TFT1 is electrically connected to the signal input terminal of the first shift register EM-(n+1) and the second pole of the second transistor TFT2 in the second gate driving sub-circuit.
  • the gate start signal output from the second signal output terminal of the shift register EM-(n) is turned on to the second gate driving sub-circuit. Then, each sub-pixel row corresponding to each of the second gate driving sub-circuit and the first gate driving sub-circuit is displayed according to the gate activation signal.
  • the path of the gate start signal output from the second signal output terminal of the shift register EM-(n) to the second gate driving sub-circuit is disconnected. Then the second gate driving sub-circuit does not display according to the gate start signal output by the second signal output terminal of the shift register EM-(n), but the second signal output of the shift register EM-(n) The electrical connection state between the terminal and the corresponding sub-pixel row Pixel(n) remains unchanged, and the corresponding sub-pixel row Pixel(n) continues to output according to the second signal of the shift register EM-(n) The output gate start signal is displayed.
  • the electrical connection relationship between the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) and the shift register EM-(n) is no longer affected by the display area control unit 3 control.
  • the sub-pixel row Pixel(n) corresponding to the shift register EM-(n) is also displayed.
  • the on and off states of the first transistor TFT1 are controlled by the split-screen display control signal terminal V1 electrically connected to the control electrode of the first transistor TFT1.
  • the split-screen display control signal terminal V1 outputs a high-level second signal to the control electrode of the first transistor TFT1
  • the first transistor TFT1 is turned off; when the split-screen display control signal terminal V1 controls the first transistor TFT1
  • the first control signal at the low level is output, the first transistor TFT1 is turned on.
  • the high or low level of the signal for controlling the on or off of the first transistor TFT1 depends on the type of the first transistor.
  • the first transistor TFT1 may be a P-type transistor or an N-type transistor.
  • the first electrode of the second transistor TFT2 is electrically connected to the display area adjustment signal terminal V3, the second electrode of the second transistor TFT2 is electrically connected to the second electrode of the first transistor TFT1, and the first shift register of the second gate driving sub-circuit
  • the first pole of EM-(n+1) is electrically connected.
  • the second signal output terminal of the shift register EM-(n) outputs the signal EOUT1 to the corresponding sub-pixel row, through the display area control unit 3 to the first gate drive sub-circuit
  • the signal EOUT1-1 output by two shift registers EM-(n+1) and the first shift register EM-(n+1) of the second gate drive sub-circuit to the corresponding sub-pixel row Pixel( n+1)
  • the waveform of the output signal EOUT2 is shown in Figure 8.
  • the first display area 1 and the second display area 2 are both displayed, and the waveforms of the signal EOUT1, the signal EOUT1-1, and the signal EOUT2 are basically the same, so the sub-pixel rows in the first display area and The difference in signal waveform received between the sub-pixel rows in the second display area is greatly reduced.
  • the second signal output terminal of the shift register EM-(n) outputs the signal EOUT1 to the corresponding sub-pixel row, and the first gate drive sub-circuit through the display area control unit 3
  • the signal EOUT1-1 output by the shift register EM-(n+1) and the first shift register EM-(n+1) of the second gate drive sub-circuit to the corresponding sub-pixel row Pixel(n +1)
  • the waveform of the output signal EOUT2 is shown in Figure 9. It can be seen that in the partial display stage, the second display area 2 does not display, and the second display area 2 does not receive the signal output by the shift register EM-(n), then the corresponding EOUT1-1 has no effective waveform display.
  • the signal EOUT2 output from the first shift register EM-(n+1) of the second gate driving sub-circuit to the corresponding sub-pixel row Pixel(n+1) is the off display output from the display area adjustment signal terminal V3 Signal.
  • the off display signal is a high level signal.
  • the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the gate start signal output by the display area adjustment signal terminal V3 is output to
  • the second gate driving sub-circuit displays the sub-pixel row corresponding to the second gate driving sub-circuit.
  • the on and off states of the second transistor TFT2 are controlled by the half-screen control signal terminal V2 electrically connected to the control electrode of the second transistor TFT2.
  • the half-screen control signal terminal V2 when the half-screen control signal terminal V2 outputs the second signal at a high level to the control electrode of the second transistor TFT2, the second transistor TFT2 is turned off; when the half-screen control signal terminal V2 controls the first transistor TFT1 When the second signal at the low level is output, the second transistor TFT2 is turned on.
  • the high or low level of the signal for controlling the turning on or off of the second transistor TFT2 depends on the type of the second transistor.
  • the second transistor TFT2 may be a P-type transistor or an N-type transistor.
  • any one or several of the split-screen display control signal terminal V1, the half-screen control signal terminal V2, and the display area adjustment signal terminal V3 in the embodiment of the present application may be only one line for transmitting the corresponding signal.
  • the signal output state of the split-screen display control signal terminal V1 is triggered by the folding and flattening operations of the display device. Specifically, when the relative positional relationship between the first display area 1 and the second display area 2 is such that the display device is folded, the split-screen display control signal terminal V1 outputs a second signal to the control electrode of the first transistor TFT1 to turn off TFT1 ; When the relative positional relationship between the first display area 1 and the second display area 2 is such that the display device is flattened, the split-screen display control signal terminal V1 outputs the first control signal to the control electrode of the first transistor TFT1 to turn on TFT1 .
  • the signal output state of the half-screen control signal terminal V2 is triggered by the folding and flattening operations of the display device. Specifically, when the relative positional relationship between the first display area 1 and the second display area 2 is such that the display device is flattened, the half-screen control signal terminal V2 outputs the second signal to the control electrode of the second transistor TFT2 to turn off the TFT2; When the relative positional relationship between the first display area 1 and the second display area 2 is such that the display device is folded, the half-screen control signal terminal V2 outputs the first control signal for turning on the TFT2 to the control electrode of the second transistor TFT2.
  • the signal output state of the display area adjustment signal terminal V3 can also be performed by folding and flattening the display device. trigger.
  • the second signal output terminal of each shift register is used to electrically connect to the corresponding sub-pixel row;
  • the second signal output terminals of the shift registers other than one shift register EM-(n) are used to electrically connect to the corresponding sub-pixel row.
  • each shift register in the second gate driving sub-circuit corresponding to the second display area 2 has the same structure and connection relationship.
  • all shift registers except for the shift register EM-(n) have the same structure and connection relationship; and except for the shift register
  • the shift registers other than EM-(n) have the same structure and connection relationship as the shift registers in the second gate driving sub-circuit corresponding to the second display area 2.
  • the shift registers in the first gate driving sub-circuit and the second gate driving sub-circuit corresponding to the first display area 1 and the second display area 2 respectively have the same structure and connection relationship.
  • the first gate driving sub-circuit includes M cascaded first shift registers EM(1) electrically connected in sequence.
  • the second gate driving sub-circuit includes N cascaded second shift registers EM(n+1)-EM(n+N) electrically connected in sequence, where M and N are respectively greater than Or a positive integer equal to 2.
  • the input terminal of the first gate driving sub-circuit is electrically connected to the gate start signal terminal STV, and the multiple output terminals of the first gate driving sub-circuit are electrically connected to the multiple sub-pixel rows in the first display area of the display device , For outputting a scan signal and controlling the first display area to display according to the scan signal.
  • the input terminal of the display area control unit is connected to one of the output terminals of the first gate drive sub-circuit, and is used to receive the scanning signal output by the first gate drive sub-circuit.
  • the display area controls The control terminal of the unit is connected to the split-screen control signal terminal, and is used to receive the split-screen control signal output by the split-screen control signal terminal.
  • the output terminal of the display area control unit is used to output or The scan signal is not output.
  • the input terminal of the second gate driving sub-circuit is electrically connected to the output terminal of the display area control unit, and the multiple output terminals of the second gate driving sub-circuit are connected to the multiple sub-pixel rows in the second display area of the display device. The electrical connection is used to control the display state of the second display area according to whether the scan signal is received.
  • the sub-pixel row of the first display area corresponding to the first gate driving sub-circuit receives the first gate driving The scan signal output by the sub-circuit, and display the corresponding display.
  • the screen split control signal terminal receives the first control signal, so that the output terminal of the display area control unit outputs a scanning signal according to the screen split control signal.
  • the sub-pixel rows of the second display area corresponding to the second gate driving sub-circuit perform corresponding display according to the received scan signal.
  • the sub-pixel rows of the first display area corresponding to the first gate driving sub-circuit receive the first The scanning signal outputted by the gate drive sub-circuit and corresponding display.
  • the screen split control signal terminal receives the second control signal, so that the output terminal of the display area control unit does not output a scan signal according to the screen split control signal. Since the sub-pixel row of the second display area corresponding to the second gate driving sub-circuit does not receive the scan signal, the display is not performed.
  • the display area control unit includes: a first transistor TFT1.
  • the first electrode of the first transistor TFT1 is used as the input terminal of the display area control unit 3 and is electrically connected to an output terminal of the first gate driving sub-circuit, and the control electrode of the first transistor TFT1 is electrically connected to the split-screen control signal terminal
  • the second pole of the first transistor TFT1 is used as the output terminal of the display area control unit.
  • the display area control unit is configured to receive the first control signal output from the split-screen control signal terminal at the full-screen display stage, and to output the scan signal output from an output terminal of the first gate driving sub-circuit at the output terminal.
  • the screen display stage receives the second control signal output from the split-screen control signal terminal without outputting the scan signal at the output terminal.
  • the signal output terminal of the shift register EM-(n) is electrically connected to the first electrode of the first transistor TFT1
  • the signal input terminal of the shift register EM-(n+1) is electrically connected to the first transistor TFT1.
  • the second pole is electrically connected.
  • the scanning signal output from the signal output terminal of the shift register EM-(n) is turned on to the output path of the second gate driving sub-circuit. Then, the second gate driving sub-circuit drives the sub-pixel rows of the second display area corresponding to the second gate driving sub-circuit to perform corresponding display according to the received scanning signal.
  • the path of the scan signal output from the signal output terminal of the shift register EM-(n) to the second gate driving sub-circuit is disconnected. Therefore, the second gate driving sub-circuit does not receive the scan signal, and the sub-pixel row of the second display area corresponding to the second gate driving sub-circuit is no longer driven according to the scan signal to perform corresponding display.
  • the on and off states of the first transistor TFT1 are controlled by the split-screen control signal terminal V1 electrically connected to the control electrode of the first transistor TFT1.
  • the screen split control signal terminal V1 outputs the second signal at a high level to the control electrode of the first transistor TFT1
  • the first transistor TFT1 is turned off; when the screen split control signal terminal V1 outputs to the control electrode of the first transistor TFT1
  • the first control signal is at a low level, the first transistor TFT1 is turned on.
  • the high or low level of the signal for controlling the on or off of the first transistor TFT1 depends on the type of the first transistor.
  • the split-screen control signal terminal V1 in the embodiment of the present application may only be a line for transmitting the corresponding signal, and does not include the signal source that generates the corresponding signal. It may also include a line for transmitting the corresponding signal and a signal source for generating the corresponding signal.
  • the display area control unit 3 further includes a capacitor C, and both ends of the capacitor C are electrically connected to the input end and the output end of the display area control unit 3, respectively.
  • the capacitor C is used to adjust the continuity of the signal passing through the first transistor TFT1.
  • the number, arrangement, and connection relationship of the first shift register, the second shift register, and the display area control unit 3 for output signals and input signals can be designed according to actual requirements.
  • the number, arrangement, and connection relationship of the terminals for outputting and inputting signals in the foregoing embodiments are merely examples of the gate driving circuit provided in the embodiments of the present application.
  • the number, arrangement, and connection relationship of the shift registers in the gate drive circuit and the terminals of the display area control unit 3 provided in the embodiment of the application can be adjusted adaptively, and the technical solution obtained after the adaptive adjustment still belongs to the embodiment of the application The scope of protection.
  • the embodiment of the present application also provides a display device. As shown in FIGS. 5-7 and 11, the display device includes a first display area 1, a second display area 2, and the gate driving circuit in the foregoing embodiments.
  • the first gate driving sub-circuit in the gate driving circuit is electrically connected to each sub-pixel row in the first display area 1.
  • the display area control unit 3 in the gate driving circuit is electrically connected between the first gate driving sub-circuit and the second gate driving sub-circuit.
  • the second gate driving sub-circuit in the gate driving circuit is electrically connected to each sub-pixel row in the second display area 2.
  • the display device provided by the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments.
  • the content not shown in the display device in detail please refer to the previous embodiments, which will not be repeated here.
  • the display device may further include a drive control circuit for providing a gate start signal and a split screen control signal.
  • the embodiment of the present application also provides a display control method. As shown in FIG. 13, the display control method 1300 can be applied to the gate driving circuit in the foregoing embodiments.
  • the method includes first determining the display state of the display device, that is, whether it is in the full-screen display stage or in the split-screen display stage.
  • the drive control circuit provides a gate start signal to the gate start signal terminal, so that the first gate driving sub-circuit controls the first display area 1 according to the gate start signal.
  • the first gate driving sub-circuit controls the first display area 1 according to the gate start signal.
  • Display and provide the first control signal to the split-screen control signal terminal, so that the display area control unit 3 transmits the scan signal output from one output terminal of the first gate driving sub-circuit to the input terminal of the second gate driving sub-circuit ,
  • the second gate driving sub-circuit controls the second display area 2 to display according to the scan signal.
  • the drive control circuit provides a gate start signal to the gate start signal terminal, so that the first gate driving sub-circuit controls the first display area 1 to perform according to the gate start signal.
  • the display area control unit 3 disconnects the first gate drive sub-circuit and the second gate drive sub-circuit The electrical connection therebetween does not transmit the scan signal output from one output terminal of the first gate driving sub-circuit to the input terminal of the second gate driving sub-circuit, so that the second display area 2 stops displaying.
  • the gate start signal terminal STV outputs the gate start signal to the first gate drive sub-circuit, and the first gate drive sub-circuit communicates with the first gate drive sub-circuit according to the received gate start signal.
  • Each corresponding sub-pixel row outputs a scan signal, and each sub-pixel row corresponding to the first gate driving sub-circuit performs image display according to the scan signal.
  • the first gate driving sub-circuit will scan The signal is output to the display area control unit 3, and the display area control unit 3 outputs the scan signal to the second gate driving sub-circuit.
  • the second gate driving sub-circuit outputs a scan signal to each sub-pixel row corresponding to the second gate driving sub-circuit according to the received scan signal, and each sub-pixel row corresponding to the second gate driving sub-circuit is based on the scan signal Perform image display.
  • the first display area 1 and the second display area 2 in the embodiment of the present application are both displayed according to the gate start signal output by the same gate start signal terminal STV, which greatly reduces the two signal differences caused by the difference.
  • the display status difference between the display areas are both displayed according to the gate start signal output by the same gate start signal terminal STV, which greatly reduces the two signal differences caused by the difference.
  • the display area control unit 3 in the gate drive circuit outputs the gate start signal of the first gate drive sub-circuit to the second gate drive sub-circuit in the gate drive circuit ,include:
  • the first transistor TFT1 in the display area control unit 3 is turned on according to the first control signal from the split-screen display control signal terminal V1 received by the control electrode.
  • the second transistor TFT2 in the display area control unit 3 is turned off according to the second signal from the half-screen control signal terminal V2 received by the control electrode.
  • the gate start signal is sequentially output to the signal input terminal of the second gate driving sub-circuit through the first gate driving sub-circuit and the first transistor TFT1.
  • the gate start signal output by the gate signal module EM-(n) is directed to the second gate driving sub-circuit and to the gate signal module EM-( n)
  • the output path of the corresponding sub-pixel row is turned on.
  • the second gate driving sub-circuit and the sub-pixel row corresponding to the gate signal module EM-(n) display according to the gate start signal output by the gate signal module EM-(n).
  • the off state of the second transistor TFT2 disconnects the electrical connection between the display area adjustment signal terminal V3 and the second gate drive sub-circuit, and the signal of the display area adjustment signal terminal V3 will not be output to the second gate drive Sub-circuit.
  • the respective signal output conditions of the split-screen control signal terminal V1, the half-screen control signal terminal V2, and the display area adjustment signal terminal V3 are shown in FIG. 10.
  • the split-screen display control signal terminal V1 outputs a first control signal at a low level
  • the half-screen control signal terminal V2 outputs a second signal at a high level.
  • the signal output by the display area adjustment signal terminal V3 is not limited, and can be a low-level signal or a high-level signal, as shown in the dotted line in FIG. 10; or no signal is output.
  • the first display area 1 is displayed, and the second display area 2 is not displayed.
  • the part for controlling the signal on and off between the first gate driving sub-circuit and the second gate driving sub-circuit is turned off, and the gate start signal terminal STV outputs the gate start signal to the second gate driving sub-circuit.
  • the first gate driving sub-circuit outputs the received gate start signal to each sub-pixel row corresponding to the first gate driving sub-circuit, and each corresponding to the first gate driving sub-circuit
  • the sub-pixel rows perform image display according to the gate start signal output from the gate start signal terminal STV.
  • the display area control unit 3 turns off the second gate driving sub-circuit to receive the gate start signal from the first gate driving sub-circuit, and the second gate driving sub-circuit stops receiving the gate start from the first gate driving sub-circuit signal. Then, the second gate driving sub-circuit no longer controls the display state of each sub-pixel row corresponding to the second gate driving sub-circuit according to the gate start signal.
  • the display area control unit disconnecting the electrical connection between the first gate driving sub-circuit and the second gate driving sub-circuit includes:
  • the first transistor TFT1 in the display area control unit is turned off according to the second signal from the split-screen display control signal terminal V1 received by the control electrode.
  • the first transistor TFT1 is turned on or off under the control of the split-screen display control signal terminal V1.
  • the on and off operations of the first transistor TFT1 are at least used to control the on and off of the gate start signal between the first gate driving sub-circuit and the second gate driving sub-circuit.
  • the second signal is a high-level signal.
  • the display area control unit 3 disconnects the electrical connection between the first gate driving sub-circuit and the second gate driving sub-circuit, so that after the second display area 2 stops displaying, include:
  • the display area control unit 3 outputs an off display signal to the second gate drive sub-circuit, and the second gate drive sub-circuit controls the second display area 2 to stop displaying according to the off display signal.
  • the shift register EM-(n) outputs the signal EOUT1 to the corresponding sub-pixel row, and outputs the signal to the first shift register EM-(n+1) of the second gate drive sub-circuit
  • the signal EOUT1-1 and the waveform of the signal EOUT2 output by the first shift register EM-(n+1) of the second gate driving sub-circuit to the corresponding sub-pixel row are shown in FIG. 9. It can be seen that in the partial display stage, the second display area 2 does not display, the second display area 2 does not receive the gate start signal output by the shift register EM-(n), and the corresponding EOUT1-1 has no effective waveform display.
  • the signal EOUT2 output by the first shift register EM-(n+1) of the second gate driving sub-circuit to the corresponding sub-pixel row is the display-off signal output from the display area adjustment signal terminal V3, and the display is turned off at this time
  • the signal is a high level signal.
  • the display control method further includes, in the partial display phase, the display area control unit 3 disconnects the electrical connection between the first gate driving sub-circuit and the second gate driving sub-circuit, And output the gate start signal from the display area adjustment signal terminal V3, while the first gate drive sub-circuit receives the turn-off display signal through the gate start signal terminal STV, so that the second gate drive sub-circuit adjusts according to the display area
  • the gate start signal of the signal terminal V3 controls the second display area 2 to display
  • the first gate driving sub-circuit controls the first display area 1 to stop displaying according to the display turn-off signal.
  • the first transistor TFT1 when the first display area 1 is no longer displaying and the second display area 2 is displaying, the first transistor TFT1 is turned off, the second transistor TFT2 is turned on, and the display area adjusts the gate output of the signal terminal V3
  • the start signal is output to the second gate driving sub-circuit, and the second gate driving sub-circuit performs display.
  • the gate activation signal output by the display area adjustment signal terminal V3 is output to the second gate driving sub-circuit and the sub-pixel row corresponding to the shift register EM-(n), then the second gate driving sub-circuit and the The sub-pixel row corresponding to the shift register EM-(n) is displayed.
  • the first display area 1 stops displaying.
  • the display area control unit 3 outputting a gate start signal to the second gate driving sub-circuit includes:
  • the second transistor TFT2 in the display area control unit 3 is turned on according to the first control signal from the half-screen control signal terminal V2 received by the control electrode.
  • the gate start signal of the display area adjustment signal terminal V3 sequentially passes through the first pole and the second pole of the second transistor TFT2, and is output to the signal input terminal of the second gate driving sub-circuit.
  • the display area control unit 3 in the gate driving circuit outputs the scan signal of the first gate driving sub-circuit to the second gate driving sub-circuit in the gate driving circuit, including :
  • the first transistor TFT1 in the display area control unit 3 is turned on according to the first control signal from the split-screen control signal terminal V1 received by the control electrode.
  • the scan signal is sequentially output to the input terminal of the second gate driving sub-circuit through the first gate driving sub-circuit and the first transistor TFT1.
  • the scan signal output by the shift register EM-(n) is turned on to the output path of the second gate driving sub-circuit.
  • the second gate driving sub-circuit controls the sub-pixel row corresponding to the second gate driving sub-circuit to display according to the scanning signal output by the shift register EM-(n).
  • the split-screen display of the signal output status of the control signal terminal V1 is as shown in FIG. 12.
  • the split-screen display control signal terminal V1 outputs the first control signal at a low level.
  • the first display area 1 is displayed, and the second display area 2 is not displayed.
  • the part for controlling the signal on and off between the first gate driving sub-circuit and the second gate driving sub-circuit is turned off, and the gate start signal terminal STV outputs the gate start signal to the second gate driving sub-circuit.
  • the first gate driving sub-circuit outputs the received gate start signal to each sub-pixel row corresponding to the first gate driving sub-circuit, and each corresponding to the first gate driving sub-circuit
  • the sub-pixel rows perform image display according to the gate start signal output from the gate start signal terminal STV.
  • the display area control unit 3 turns off the second gate driving sub-circuit to receive the gate start signal from the first gate driving sub-circuit, and the second gate driving sub-circuit stops receiving the gate start from the first gate driving sub-circuit signal. Then, the second gate driving sub-circuit no longer controls the display state of each sub-pixel row corresponding to the second gate driving sub-circuit according to the gate start signal.
  • the display area control unit disconnecting the electrical connection between the first gate driving sub-circuit and the second gate driving sub-circuit includes:
  • the first transistor TFT1 in the display area control unit is turned off according to the second control signal from the split-screen display control signal terminal V1 received by the control electrode.
  • the first transistor TFT1 is turned on or off under the control of the split-screen display control signal terminal V1.
  • the on and off operations of the first transistor TFT1 are at least used to control the on and off of the gate start signal between the first gate driving sub-circuit and the second gate driving sub-circuit.
  • the second control signal is a high-level signal.
  • the display device further includes a third display area. Therefore, the display control method of each embodiment of the present application can also be applied between the third display area and other display areas that have a display cooperation relationship with the third display area. Therefore, the related technical solutions in the multi-area display stage in the display control method of each embodiment of the present application are not limited to the case where the display device has the first display area 1 and the second display area 2, but can also be applied to the display device The situation with more display areas.
  • the gate activation signal is established between at least two adjacent display areas, and at least between adjacent display areas
  • the gate start signal in the first display area can be output to the second display area under certain conditions, so that the first display area and the second display area can be displayed under the control of the same gate start signal, at least It is possible to reduce the display difference between adjacent display areas due to the difference in the received gate activation signal.
  • the gate driving circuit, the display device, and the display control method provided in the embodiments of the present application can make any two adjacent rows of sub-pixels of the display device be controlled by the gate activation signal from the same source.
  • the gate activation signal from the same source.
  • the gate activation signal terminal or the display area control unit is used to provide The area output turns off the display signal, so that the display area that does not need to be displayed stops displaying. Avoid affecting the display effect of other display areas that need to be displayed.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the present invention, unless otherwise specified, “plurality” means two or more.

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Abstract

本申请实施例提供了一种栅极驱动电路、显示装置及显示控制方法。该栅极驱动电路包括：第一栅极驱动子电路，输入端与栅极启动信号端电连接，多个输出端与显示装置的第一显示区域的多个子像素行电连接，用于输出扫描信号并根据所述扫描信号控制所述第一显示区域进行显示；显示区域控制单元，输入端连接所述第一栅极驱动子电路的多个输出端中的一个输出端，用于接收所述第一栅极驱动子电路输出的扫描信号，控制端与分屏控制信号端连接，用于接收所述分屏控制信号端输出的分屏控制信号，输出端用于根据所述分屏控制信号而输出或不输出所述扫描信号；以及第二栅极驱动子电路，输入端与所述显示区域控制单元的输出端电连接，多个输出端与显示装置的第二显示区域的多个子像素行电连接，用于根据接收是否接收到扫描信号，控制所述第二显示区域的显示状态。

Description

栅极驱动电路、显示装置及显示控制方法
交叉引用
本公开要求于2019年5月31日提交的发明名称为“栅极驱动电路、显示装置及显示控制方法”的中国专利申请201910471610.2的优先权益，在此引出以将其一并并入本文。
技术领域
本申请涉及显示技术领域，具体而言，本申请涉及一种栅极驱动电路、显示装置及显示控制方法。
背景技术
现有的显示装置，在具有可分别显示的、相邻的两个显示区域的情况下，通常针对每个显示区域设置单独的栅极启动信号端。
在常规的显示装置中，在显示装置的不同显示区域，例如第一显示区域和第二显示区域，在需要同时显示时，两个单独的栅极启动信号端STV1和STV2分别向与之对应的显示区域输出栅极启动信号。第一显示区域和第二显示区域在各自对应的栅极启动信号端STV1和STV2输出的栅极启动信号的控制下进行显示。
发明内容
第一方面，本申请实施例提供了一种栅极驱动电路，包括：第一栅极驱动子电路，所述第一栅极驱动子电路的输入端与栅极启动信号端电连接，所述第一栅极驱动子电路的多个输出端与显示装置的第一显示区域的多个子像素行电连接，用于输出扫描信号并根据所述扫描信号控制所述第一显示区域进行显示；显示区域控制单元，所述显示区域控制单元的输入端连接所述第一栅极驱动子电路的多个输出端中的一个输出端，用于接收所述第一栅极驱动子电路输出的扫描信号，所述显示区域控制单元的控制端与分屏控制信号端连接，用于接收所述分屏控制信号端输出的分屏控制信号，所述显示区域控制单元的输 出端用于根据所述分屏控制信号而输出或不输出所述扫描信号；以及第二栅极驱动子电路，所述第二栅极驱动子电路的输入端与所述显示区域控制单元的输出端电连接，所述第二栅极驱动子电路的多个输出端与显示装置的第二显示区域的多个子像素行电连接，用于根据接收是否接收到扫描信号，控制所述第二显示区域的显示状态。
可选地，所述显示区域控制单元包括：第一晶体管；所述第一晶体管的第一极作为所述显示区域控制单元的输入端，与所述第一栅极驱动子电路的一个输出端电连接，所述第一晶体管的控制极与所述分屏控制信号端电连接，所述第一晶体管的第二极作为所述显示区域控制单元的输出端，所述显示区域控制单元被配置为在全屏显示阶段接收所述分屏控制信号端输出的第一控制信号而在输出端输出所述第一栅极驱动子电路的一个输出端输出的扫描信号，在分屏显示阶段接收所述分屏控制信号端输出的第二控制信号而不在输出端输出所述扫描信号。
可选地，所述显示区域控制单元还包括电容；所述电容的两端分别与所述显示区域控制单元的输入端和输出端电连接。
可选地，所述第一栅极驱动子电路包括M个级联的第一移位寄存器，所述第二栅极驱动子电路包括N个级联的第二移位寄存器，所述M、N分别为大于或等于2的正整数，第1级第一移位寄存器的信号输入端连接所述栅极启动信号端，第M级第一移位寄存器的输出端连接所述显示区域控制单元的输入端，第一个第二移位寄存器的信号输入端连接所述显示区域控制单元的输出端。
第二方面，本申请实施例提供了一种显示装置，包括第一显示区域、第二显示区域、以及如上所述的栅极驱动电路；所述栅极驱动电路中的第一栅极驱动子电路与所述第一显示区域中的各子像素行电连接；所述栅极驱动电路中的显示区域控制单元电连接在所述第一栅极驱动子电路和所述第二栅极驱动子电路之间；所述栅极驱动电路中的第二栅极驱动子电路与所述第二显示区域中的各子像素行电连接。
可选地，显示装置还包括：驱动控制电路，用于提供所述栅极启动信号和所述分屏控制信号。
第三方面，本申请实施例提供了一种显示控制方法，应用于前述的栅极驱动电路，包括：在全屏显示阶段，向所述分屏控制信号端提供第一控制信号，以使得所述显示区域控制单元将所述第一栅极驱动子电路的一个输出端输出的扫描信号传输到所述第二栅极驱动子电路的输入端；以及在分屏显示阶段，向所述分屏控制信号端提供第二控制信号，以使得所述显示区域控制单元不将所述第一栅极驱动子电路的一个输出端输出的扫描信号传输到所述第二栅极驱动子电路的输入端。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1A为显示面吧的整体电路架构的示意图；
图1B示出了EMGOA的示意性典型结构；
图1C示出了EMGOA的工作时序图；
图2为常规的显示装置中，相邻的两个显示区域之间的显示状况差异示意图；
图3为常规的显示装置中，移位寄存器EM-(n)输出的EOUT’信号的波形示意图；
图4为常规的显示装置中，移位寄存器EM-(n+1)输出的ESTV2’信号的波形示意图；
图5为本申请实施例中的栅极驱动电路的部分结构，以及栅极驱动电路与显示区域的对应关系、与子像素行的对应关系示意图；
图6为本申请实施例中的栅极驱动电路的部分结构，以及栅极驱动电路与显示区域的对应关系、与子像素行的对应关系示意图；
图7为本申请实施例中的栅极驱动电路的部分结构，以及栅极驱动电路与显示区域的对应关系、与子像素行的对应关系示意图；
图8为本申请实施例中的栅极驱动电路，在多区域显示阶段，移位寄存器EM-(n)输出的EOUT’信号，与移位寄存器EM-(n+1)输出的ESTV2’信号的波形示意图；
图9为本申请实施例中的栅极驱动电路，在局部显示阶段，移位寄 存器EM-(n)输出的EOUT’信号，与移位寄存器EM-(n+1)输出的ESTV2’信号的波形示意图；
图10为本申请实施例中的栅极驱动电路，在多区域显示阶段和局部显示阶段，分屏显示控制信号端V1、半屏控制信号端V2和显示区域调整信号端V3的信号输出状况示意图；
图11为本申请实施例中的栅极驱动电路的部分结构，以及栅极驱动电路与显示区域的对应关系、与子像素行的对应关系示意图；
图12为本申请实施例中的栅极驱动电路，在多区域显示阶段和局部显示阶段，分屏显示控制信号端V1的信号输出状况示意图；以及
图13示出了根据本申请实施例的显示控制方法的流程图。
具体实施方式
下面详细描述本申请，本申请实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外，如果已知技术的详细描述对于示出的本申请的特征是不必要的，则将其省略。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但是并不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或它们的组。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。下面这几个具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例中不再赘述。下面将结合附图，对本申请的实施例进行描述。
图1A为一种显示面板的整体电路架构的示意图。例如，如图1A所示，显示面板包括衬底基板101，衬底基板101包括显示区(即像素阵列区)102以及位于显示区102周边的周边区106。例如周边区106围绕显示区102。显示区102包括阵列排布的像素单元103，周边区106包括移位寄存器单元104，多个级联的移位寄存器单元104组成栅极驱动电路，用于向显示面板的显示区102中的阵列排布的像素单元103提供例如逐行移位的栅极扫描信号。周边区106还包括发光控制单元105，多个级联的发光控制单元105组成发光控制阵列，用于向显示面板的显示区102中的阵列排布的像素单元103提供例如逐行移位的发光控制信号。
如图1A所示，显示面板还包括位于周边区106的数据驱动芯片IC，数据驱动芯片IC配置为向阵列排布的像素单元103提供数据信号。与数据驱动芯片IC连接的数据线D1-DN(N为大于1的整数)纵向(例如图中的竖直方向)穿过显示区102，以分别为每一列的像素单元103提供数据信号。与移位寄存器单元104连接的栅线G1-GM(M为大于1的整数)横向(例如图中的水平方向)穿显示区102，与发光控制单元105连接的发光控制线E1-EM(M为大于1的整数)横向穿显示区102，以为阵列排布的像素单元103提供栅极扫描信号和发光控制信号。
例如，各个像素单元103可以包括本领域内的具有7T1C、8T2C或4T1C等电路结构的像素电路和发光元件，像素电路在通过数据线传输的数据信号和通过栅线传输的栅极扫描信号和发光控制线E1-EM传输的发光控制信号的控制下工作，以驱动发光元件发光从而实现显示等操作。该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)。
图1B示出了EMGOA的示意性典型结构，图1C示出了EMGOA的工作时序图。在第一阶段P1，第一时钟信号CK为低电平，所以第一 晶体管M1和第三晶体管M3被导通，导通的第一晶体管M1将高电平的起始信号ESTV传输至第一节点N1，从而使得第一节点N1的电平变为高电平，所以第二晶体管M2、第八晶体管M8以及第十晶体管M10被截止。另外，导通的第三晶体管M3将低电平的第四电压VGL传输至第二节点N2，从而使得第二节点N2的电平变为低电平，所以第五晶体管M5和第六晶体管M6被导通。由于第二时钟信号CB为高电平，所以第七晶体管M7被截止。另外，由于第三电容C3的存储作用，第四节点N4的电平可以保持高电平，从而使得第九晶体管M9被截止。在第一阶段P1中，由于第九晶体管M9以及第十晶体管M10均被截止，该发光控制移位寄存器单元EGOA输出的发光控制脉冲信号EM保持之前的低电平。
在第二阶段P2，第二时钟信号CB为低电平，所以第四晶体管M4、第七晶体管M7被导通。由于第一时钟信号CK为高电平，所以第一晶体管M1和第三晶体管M3被截止。由于第一电容C1的存储作用，所以第二节点N2可以继续保持上一阶段的低电平，所以第五晶体管M5以及第六晶体管M6被导通。高电平的第三电压VGH通过导通的第五晶体管M5以及第四晶体管M4传输至第一节点N1，从而使得第一节点N1的电平继续保持上一阶段的高电平，所以第二晶体管M2、第八晶体管M8以及第十晶体管M10被截止。另外，低电平的第二时钟信号CB通过导通的第六晶体管M6以及第七晶体管M7被传输至第四节点N4，从而使得第四节点N4的电平变为低电平，所以第九晶体管M9被导通，导通的第九晶体管M9将高电平的第三电压VGH输出，所以该发光控制移位寄存器单元EGOA在第二阶段P2输出的发光控制脉冲信号EM为高电平。
在第三阶段P3，第一时钟信号CK为低电平，所以第一晶体管M1以及第三晶体管M3被导通。第二时钟信号CB为高电平，所以第四晶体管M4以及第七晶体管M7被截止。由于第三电容C3的存储作用，所以第四节点N4的电平可以保持上一阶段的低电平，从而使得第九晶体管M9保持导通状态，导通的第九晶体管M9将高电平的第三电压VGH输出，所以该发光控制移位寄存器单元EGOA在第三阶段P3输出的发 光控制脉冲信号EM仍然为高电平。
在第四阶段P4，第一时钟信号CK为高电平，所以第一晶体管M1以及第三晶体管M3被截止。第二时钟信号CB为低电平，所以第四晶体管M4以及第七晶体管M7被导通。由于第二电容C2的存储作用，所以第一节点N1的电平保持上一阶段的高电平，从而使得第二晶体管M2、第八晶体管M8以及第十晶体管M10被截止。由于第一电容C1的存储作用，第二节点N2继续保持上一阶段的低电平，从而使得第五晶体管M5以及第六晶体管M6被导通。另外，低电平的第二时钟信号CB通过导通的第六晶体管M6以及第七晶体管M7被传输至第四节点N4，从而使得第四节点N4的电平变为低电平，所以第九晶体管M9被导通，导通的第九晶体管M9将高电平的第三电压VGH输出，所以该发光控制移位寄存器单元EGOA在第二阶段P2输出的发光控制脉冲信号EM仍然为高电平。
在第五阶段P5，第一时钟信号CK为低电平，所以第一晶体管M1以及第三晶体管M3被导通。第二时钟信号CB为高电平，所以第四晶体管M4以及第七晶体管M7被截止。导通的第一晶体管M1将低电平的起始信号ESTV传输至第一节点N1，从而使得第一节点N1的电平变为低电平，所以第二晶体管M2、第八晶体管M8以及第十晶体管M10被导通。导通的第二晶体管M2将低电平的第一时钟信号CK传输至第二节点N2，从而可以进一步拉低第二节点N2的电平，所以第二节点N2继续保持上一阶段的低电平，从而使得第五晶体管M5以及第六晶体管M6被导通。另外，导通的第八晶体管M8将高电平的第三电压VGH传输至第四节点N4，从而使得第四节点N4的电平变为高电平，所以第九晶体管M9被截止。导通的第十晶体管M10将低电平的第四电压VGL输出，所以该发光控制移位寄存器单元EGOA在第五阶段P5输出的发光控制脉冲信号EM变为低电平。
本申请的发明人发现，常规的显示装置中相邻两个显示区域之间存在显示状况的差异。在可折叠的显示装置中，以显示装置的折叠位置为界限的相邻两个显示区域，在该两个显示区域都进行显示时很容易产生显示状况的差异，如图2所示，第一显示区域1’和第二显示区域2’之 间产生了显示状况的差异，明显影响了显示装置的画面显示效果。
本申请的发明人经过研究发现，常规的显示装置中，要求两个栅极启动信号端STV1和STV2能够向各自对应的显示区域(例如图2的第一显示区域1’和第二显示区域2’)输出相同的栅极启动信号，才能够使得两个显示区域同时展示出协调的画面。为使得两个栅极启动信号端STV1和STV2的信号输出状态相同，需要显示装置的控制系统设有调整两个栅极启动信号端的帧同步的控制模块。一定程度上，针对两个栅极信号端的帧控制增加了显示装置的控制负担。
并且，本申请的发明人还发现，即使两个显示区域各自对应的栅极启动信号端STV1和STV2能够输出相同的栅极启动信号，但是，在相邻的两个显示区域的交界位置，第一显示区域的最末行子像素Pixel(n)接收到的且由移位寄存器EM-(n)输出的信号EOUT’的波形，与第二显示区域的第一行子像素Pixel(n+1)接收到的且由移位寄存器EM-(n+1)输出的信号ESTV2’的波形相异，EOUT’的波形和ESTV2’的波形分别如图3和图4所示。这也造成在第一显示区域和第二显示区域之间产生显示状况的差异，影响了显示装置的画面显示效果。
本申请提供的栅极驱动电路、显示装置及显示控制方法，旨在至少部分地解决现有技术中的相邻显示区域同时输出画面时出现的显示差异的技术问题。
本申请实施例提供了一种栅极驱动电路，如图5至图7所示，包括：第一栅极驱动子电路4、第二栅极驱动子电路5、显示区域控制单元3和栅极启动信号端STV。
第一栅极驱动子电路与栅极启动信号端STV电连接，并与显示装置的第一显示区域1对应的子像素行电连接，用于通过栅极启动信号端STV接收栅极启动信号并向显示区域控制单元输出栅极启动信号，且根据栅极启动信号控制第一显示区域1进行显示。
显示区域控制单元3，电连接在第一栅极驱动子电路和第二栅极驱动子电路之间，至少用于通过控制第一栅极驱动子电路与第二栅极驱动子电路之间电连接的通断，来控制是否传输栅极启动信号。该栅极启动信号为栅极启动信号端STV输出的栅极启动信号。
第二栅极驱动子电路与显示区域控制单元3电连接，并与显示装置的第二显示区域2对应的子像素行电连接，用于根据是否接收到栅极启动信号，控制第二显示区域2的显示状态。
本发明实施例提供的栅极驱动电路，包括两个分别用于控制不同显示区域的显示状况的栅极驱动子电路，两个栅极驱动子电路分别为第一栅极驱动子电路和第二栅极驱动子电路。显示区域控制单元根据是否传输栅极启动信号，控制第二显示区域2的显示状态。第一栅极驱动子电路至少用于控制第一显示区域1的显示状况，第二栅极驱动子电路至少用于控制第二显示区域2的显示状况。
本申请实施例中的栅极驱动电路的第一栅极驱动子电路和第二栅极驱动子电路共用一个栅极启动信号端STV，使得在显示装置的第一显示区域1和第二显示区域2均发挥显示功能时，分别用于控制第一显示区域1和第二显示区域2的两个栅极驱动子电路各自接收到的栅极启动信号的来源是相同的；两个栅极驱动子电路各自接收到的栅极启动信号的时序也是相同的，显示装置无需为协调两个显示区域的时序关系实施专门的控制操作，或者增加相应的时序调整模块，减轻了系统的控制负担，保证显示装置的第一显示区域1和第二显示区域之间良好的协调性。
并且，常规的显示装置中设置有两个可用于局部显示的显示区域时，采用每个显示区域配置一个栅极启动信号端STV的技术手段，使得显示设备制造过程中，需要针对每个栅极启动信号端STV进行分别的检测，增加了生产工艺的复杂性。本申请实施例中的技术方案则可较大程度的避免增加针对栅极启动信号端STV的检测作业量。
本申请实施例中的栅极启动信号端STV，可仅为一个用于传输栅极启动信号的线路，不包含产生栅极启动信号的信号源。也可包括用于传输栅极启动信号的线路和产生栅极启动信号的信号源。栅极启动信号端STV的具体设计方案，可采用常规的栅极启动信号端STV，在此不做赘述。
在本申请一个可选地实施例中，在第一显示区域1和第二显示区域2均发挥显示功能时，栅极启动信号端STV将栅极启动信号输出至第一栅极驱动子电路，第一栅极驱动子电路将接收到的栅极启动信号输出至 与第一栅极驱动子电路对应的各子像素行，该与第一栅极驱动子电路对应的各子像素行根据栅极启动信号端STV输出的栅极启动信号进行图像显示。并且，在显示区域控制单元3中用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的栅极启动信号传输的通断的部分处于导通状态的情况下，第一栅极驱动子电路将栅极启动信号输出至显示区域控制单元3，显示区域控制单元3再将该栅极启动信号输出至第二栅极驱动子电路。第二栅极驱动子电路将接收的栅极启动信号输出至与第二栅极驱动子电路对应的各子像素行，使得该与第二栅极驱动子电路对应的各子像素行根据栅极启动信号端STV输出的栅极启动信号进行图像显示。则，本申请实施例中的第一显示区域1和第二显示区域2均根据同一栅极启动信号端STV输出的栅极启动信号进行显示，较大程度地降低了由于栅极启动信号的来源差异和波形差异引起的两个显示区域之间的显示状况差异，保证多区域显示阶段的显示装置的图像输出效果。
本申请一个可选的实施例中，在多区域显示阶段，第一栅极驱动子电路的移位寄存器EM-(n)向与之对应的子像素行Pixel(n)输出的信号EOUT1、向第二栅极驱动子电路的第一个移位寄存器EM-(n)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2的波形如图8所示。可知，信号EOUT1、信号EOUT1-1和信号EOUT2的波形基本相同，并且该三个信号的时序也基本相同。在多区域显示阶段或者全屏显示阶段，本申请实施例的栅极驱动电路可通过消除第一显示区域1和第二显示区域2的各子像素行接收到的信号的波形的差异和信号的时序的差异的方式，减小第一显示区域1和第二显示区域2的显示差异，其中n为正整数。
当第一显示区域1进行显示，而第二显示区域2不进行显示时，在显示区域控制单元3中用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的信号通断的部分断开，栅极启动信号端STV将栅极启动信号输出至第一栅极驱动子电路，第一栅极驱动子电路将接收到的栅极启动信号输出至与第一栅极驱动子电路对应的各子像素行，使得与第一栅极驱动子电路对应的各子像素行根据栅极启动信号端STV输出的栅极启 动信号进行图像显示。显示区域控制单元3断开第二栅极驱动子电路从第一栅极驱动子电路接收栅极启动信号的电路，第二栅极驱动子电路停止从第一栅极驱动子电路接收栅极启动信号端STV输出的栅极启动信号。则，第二栅极驱动子电路不再根据栅极启动信号端STV端产生的栅极启动信号控制与第二栅极驱动子电路对应的各子像素行的显示状态。
在本申请一个可选地实施例中，第一显示区域1和第二显示区域2为在显示装置中位置相邻的显示区域。可选地，子像素行的归属划分，可根据子像素行的发光情况与显示区域的显示状况划分，当某一显示区域进行显示，而某一子像素停止接收栅极启动信号，则该子像素不归属于该显示区域。
可选地，当本申请实施例介绍的栅极驱动电路对应的显示装置为可折叠的显示装置时，第一显示区域1和第二显示区域2之间的界线为显示装置的折叠位置。可选地，对显示装置的折叠、展平操作，为触发显示区域控制单元3控制第一栅极驱动子电路与第二栅极驱动子电路之间的栅极启动信号输出路径关闭、导通的操作。当第一显示区域1和第二显示区域2之间发生折叠的相对位置变化时，显示区域控制单元3控制第一栅极驱动子电路与第二栅极驱动子电路之间的栅极启动信号输出路径关闭，第二栅极驱动子电路不再根据栅极启动信号端STV输出的栅极启动信号控制第二显示区域2的显示状况；当第一显示区域1和第二显示区域2之间发生展平的相对位置变化时，显示区域控制单元3控制第一栅极驱动子电路与第二栅极驱动子电路之间的栅极启动信号输出路径导通，第二栅极驱动子电路根据栅极启动信号端STV输出的栅极启动信号控制第二显示区域2的显示状况。
在本申请一个可选地实施例中，栅极驱动电路包括：第一栅极驱动子电路、第二栅极驱动子电路、第三栅极驱动子电路、第一显示区域控制单元、第二显示区域控制单元和栅极启动信号端STV。栅极启动信号端STV与第一栅极驱动子电路电连接。第一显示区域控制单元分别与第一栅极驱动子电路和第二栅极驱动子电路电连接，用于通过控制第一栅极驱动子电路与第二栅极驱动子电路之间电连接的通断，来控制是否传输栅极启动信号。第二栅极驱动子电路与第一显示区域控制单元电连接， 并与显示装置的第二显示区域对应的子像素行电连接，用于根据是否接收到的栅极启动信号，控制第二显示区域的显示状态。第二显示区域控制单元分别与第二栅极驱动子电路和第三栅极驱动子电路电连接，用于通过控制第二栅极驱动子电路与第三栅极驱动子电路之间电连接的通断，来控制是否传输栅极启动信号。第三栅极驱动子电路与第二显示区域控制单元电连接，并与显示装置的第三显示区域对应的子像素行电连接，用于根据是否接收到栅极启动信号，控制第三显示区域的显示状态；或者，第二显示区域控制单元分别与第一栅极驱动子电路和第三栅极驱动子电路电连接，用于通过控制第一栅极驱动子电路与第三栅极驱动子电路之间电连接的通断，来控制是否传输栅极启动信号。
在本申请一个可选地实施例中，栅极驱动电路中还可包括更多个栅极驱动子电路和更多个显示区域控制单元。可选地，在确定各栅极驱动子电路的次序关系时，与栅极启动信号端STV电连接的栅极驱动子电路为第一栅极驱动子电路。第二栅极驱动子电路以及第三栅极驱动子电路可根据栅极启动信号的传递次序而定，或者根据与第一栅极驱动子电路在显示装置上的相对位置关系而定。
在本申请一个可选地实施例中，如图5至图7所示，在栅极驱动电路中，第一栅极驱动子电路和第二栅极驱动子电路均包括依次电连接的多个移位寄存器，第一栅极驱动子电路或第二栅极驱动子电路中两个启动顺序相邻的移位寄存器中，前一个移位寄存器的信号输出端电连接至下一个移位寄存器的信号输入端。
显示区域控制单元3的信号输入端与第一栅极驱动子电路中的移位寄存器EM-(n)的信号输出端电连接，显示区域控制单元3的信号输出端与第二栅极驱动子电路的第一个移位寄存器EM-(n+1)的信号输入端电连接，显示区域控制单元3的信号输入端与信号输出端之间导通时，栅极启动信号从第一栅极驱动子电路中的移位寄存器EM-(n)传输至第二栅极驱动子电路的第一个移位寄存器EM-(n+1)。
第一栅极驱动子电路和第二栅极驱动子电路中移位寄存器可为常规的移位寄存器。各移位寄存器至少用于将栅极启动信号输出至至少一个子像素行，进而控制该子像素行根据栅极启动信号的显示状况。可选 地，第一栅极驱动子电路中的第一个移位寄存器EM-(1)与栅极启动信号端STV电连接。栅极启动信号端STV输出的栅极启动信号输出至第一栅极驱动子电路中的第一个移位寄存器EM-(1)，该第一栅极驱动子电路中的第一个移位寄存器EM-(1)将栅极启动信号输出至与之对应的子像素行Pixel(1)，并将该栅极启动信号输出至第一栅极驱动子电路中的第二个移位寄存器EM-(2)。
可选地，在第一栅极驱动子电路中和/或第二栅极驱动子电路中，各移位寄存器的次序与栅极启动信号在该栅极驱动子电路中的各移位寄存器之间的传输次序相同。与栅极启动信号端STV直接电连接的移位寄存器即为第一栅极驱动子电路的第一移位寄存器EM-(1)。
本申请实施例的各移位寄存器的信号输入端为具备信号输入功能的信号输入端。第一栅极驱动子电路中的第一个移位寄存器EM-(1)的信号输入端与栅极启动信号端STV电连接，至少用于从栅极启动信号端STV中接收栅极启动信号。其余各移位寄存器的信号输入端，至少与在栅极启动信号的输出次序上的前一个移位寄存器的信号输出端电连接，至少用于接收该前一个移位寄存器输出的栅极启动信号。
各移位寄存器的信号输出端为具备信号输出功能的信号输出端。各移位寄存器的信号输出端至少与在栅极启动信号的输出次序上的下一个移位寄存器的信号输入端电连接，至少用于向该下一个移位寄存器输出栅极启动信号。
显示区域控制单元3的信号输入端为具备信号输入功能的信号输入端。显示区域控制单元3的信号输出端为具备信号输出功能的信号输出端。在显示区域控制单元3的信号输入端和信号输出端之间导通时，显示区域控制单元3的信号输入端至少用于从与之电连接移位寄存器的信号输出端接收栅极启动信号，并将该栅极启动信号输出至显示区域控制单元3的信号输出端，显示区域控制单元3的信号输出端将该栅极启动信号输出至与之电连接的移位寄存器的信号输入端。当显示区域控制单元3的信号输入端和信号输出端之间电连接断开时，栅极启动信号从第一栅极驱动子电路向第二栅极驱动子电路传输的电路被断开，第二显示区域2停止根据栅极启动信号进行显示。
在本申请一个可选地实施例中，如图5所示，与移位寄存器EM-(n)对应的子像素行Pixel(n)电连接至显示区域控制单元3的信号输出端。
本申请实施中，“移位寄存器EM-(n)”为第一栅极驱动子电路中与显示区域控制单元3电连接，并向显示区域控制单元3输出栅极启动信号的移位寄存器。显示区域控制单元3用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的栅极启动信号的通断，并且，显示区域控制单元3还用于控制该移位寄存器EM-(n)和与之对应的子像素行Pixel(n)之间的栅极启动信号的通断。
可选地，当第一显示区域1和第二显示区域2共同发挥显示功能时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)在显示区域控制单元3的控制下接收由该移位寄存器EM-(n)输出的栅极启动信号，并进行相应的显示。当第一显示区域1进行显示，而第二显示区域2不进行显示时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)和第二显示区域2在显示区域控制单元3的控制下停止接收由该移位寄存器EM-(n)输出的栅极启动信号，并停止进行相应的显示。
在本申请一个可选的实施例中，显示区域控制单元3包括：第一晶体管TFT1、第二晶体管TFT2、分屏显示控制信号端V1、半屏控制信号端V2和显示区域调整信号端V3。
第一晶体管TFT1的第一极作为显示区域控制单元3的信号输入端，第一晶体管TFT1的控制极与分屏显示控制信号端V1电连接；第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的控制极与半屏控制信号端V2电连接，第一晶体管TFT1和第二晶体管TFT2各自的第二极共同作为显示区域控制单元3的信号输出端。
在本申请实施例中，移位寄存器EM-(n)的信号输出端与第一晶体管TFT1的第一极电连接，与该移位寄存器EM-(n)对应的子像素行Pixel(n)和第一晶体管TFT1的第二极电连接，第二栅极驱动子电路的第一个移位寄存器EM-(n+1)的信号输入端与第一晶体管TFT1的第二极电连接。
当第一晶体管TFT1导通时，由移位寄存器EM-(n)的信号输出端 输出的栅极启动信号向第二栅极驱动子电路、以及向与该移位寄存器EM-(n)对应的子像素行Pixel(n)输出的路径导通。则第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)根据该移位寄存器EM-(n)的信号输出端输出的栅极启动信号进行显示。
当第一晶体管TFT1关闭时，由移位寄存器EM-(n)的信号输出端输出的栅极启动信号向第二栅极驱动子电路、以及向与该移位寄存器EM-(n)对应的子像素行Pixel(n)输出的路径断开。则第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)不再根据该移位寄存器EM-(n)输出的栅极启动信号进行显示。
第一晶体管TFT1的导通和关闭状态，由与第一晶体管TFT1的控制极电连接的分屏显示控制信号端V1控制。可选地，当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于高电平的第二信号时，第一晶体管TFT1关闭；当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第一晶体管TFT1导通。控制第一晶体管TFT1导通或关闭的信号的高低电平取决于第一晶体管的类型。
第二晶体管TFT2的第一极与显示区域调整信号端V3电连接。第二晶体管TFT2的第二极和与该移位寄存器EM-(n)对应的子像素行Pixel(n)、第二栅极驱动子电路的第一个移位寄存器EM-(n+1)的信号输入端、以及第一晶体管TFT1的第二极电连接。当第二显示区域2不再进行显示时、或者第一晶体管TFT1关闭时，第二晶体管TFT2导通，将显示区域调整信号端V3输出的处于高电平的关闭显示信号输出至第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)，则第二栅极驱动子电路对应的第二显示区域2和与该移位寄存器EM-(n)对应的子像素行Pixel(n)停止显示。
或者，当第一显示区域1不再进行显示，而第二显示区域2进行显示时，第一晶体管TFT1关闭，第二晶体管TFT2导通，显示区域调整信号端V3输出的栅极启动信号输出至第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)，则第二栅极驱动子电路对应的第二显示区域2和与该移位寄存器EM-(n)对应的子像素行Pixel (n)根据显示区域调整信号端V3输出的栅极启动信号进行显示。
第二晶体管TFT2的导通和关闭状态，由与第二晶体管TFT2的控制极电连接的半屏控制信号端V2控制。可选地，当半屏控制信号端V2向第二晶体管TFT2的控制极输出处于高电平的第二信号时，第二晶体管TFT2关闭；当半屏控制信号端V2向第二晶体管TFT2的控制极输出处于低电平的第一控制信号时，第二晶体管TFT2导通。控制第二晶体管TFT2导通或关闭的信号的高低电平取决于第二晶体管的类型。
在本申请一个可选地实施例中，如图6所示，与移位寄存器EM-(n)对应的子像素行Pixel(n)电连接至移位寄存器EM-(n)的信号输出端。
本申请实施中，“移位寄存器EM-(n)”为第一栅极驱动子电路中与显示区域控制单元3电连接、并向显示区域控制单元3输出栅极启动信号的移位寄存器。该移位寄存器EM-(n)为第一显示区域1对应的第一栅极驱动子电路中的移位寄存器。该移位寄存器EM-(n)通过其信号输出端与显示区域控制单元3电连接，并且，该移位寄存器EM-(n)通过其信号输出端和与该移位寄存器EM-(n)对应的子像素行Pixel(n)电连接。则，该移位寄存器EM-(n)的信号输出端既用于向显示区域控制单元3的信号输入端输出信号，又用于向与之对应的子像素行Pixel(n)输出信号。
可选地，在第一栅极驱动子电路和/或第二栅极驱动子电路中，各移位寄存器均具有和该移位寄存器EM-(n)相同的结构、信号端的布置以及与之对应的子像素行的连接关系。
可选地，当第一显示区域1和第二显示区域2共同发挥显示功能时，该移位寄存器EM-(n)的信号输出端输出的栅极启动信号输出至与之对应的子像素行Pixel(n)和显示区域控制单元3的信号输入端，显示区域控制单元3将该栅极启动信号输出至第二栅极驱动子电路，则第一显示区域1和第二显示区域2均根据栅极启动信号端STV的栅极启动信号发挥显示功能。当第一显示区域1进行显示，第二显示区域2不进行显示时，第一显示区域中的各子像素行(包括与移位寄存器EM-(n)对应的子像素行Pixel(n))根据栅极启动信号端STV的栅极启动信号 发挥显示功能，而第二显示区域2不会根据栅极启动信号端STV的栅极启动信号发挥显示功能。
在本申请一个可选的实施例中，显示区域控制单元3包括：第一晶体管TFT1、第二晶体管TFT2、分屏显示控制信号端V1、半屏控制信号端V2和显示区域调整信号端V3。
第一晶体管TFT1的第一极作为显示区域控制单元3的信号输入端，第一晶体管TFT1的控制极与分屏显示控制信号端V1电连接；第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的控制极与半屏控制信号端V2电连接，第一晶体管TFT1和第二晶体管TFT2各自的第二极共同作为显示区域控制单元3的信号输出端。
在本申请实施例中，移位寄存器EM-(n)的信号输出端分别与第一晶体管TFT1的第一极，以及与该移位寄存器EM-(n)对应的子像素行Pixel(n)电连接。第一晶体管TFT1的第二极与第二栅极驱动子电路中的第一个移位寄存器EM-(n+1)的信号输入端电连接。
当第一晶体管TFT1导通时，由移位寄存器EM-(n)的信号输出端输出的栅极启动信号向第二栅极驱动子电路输出的路径导通。则第二栅极驱动子电路与第一栅极驱动子电路各自对应的各子像素行均根据栅极启动信号进行显示。
当第一晶体管TFT1关闭时，由移位寄存器EM-(n)的信号输出端输出的栅极启动信号向第二栅极驱动子电路输出的路径断开。则第二栅极驱动子电路不再根据栅极启动信号进行显示。本申请实施例中，与该移位寄存器EM-(n)对应的子像素行Pixel(n)和该移位寄存器EM-(n)之间的电连接关系不再受显示区域控制单元3的控制。第一显示区域1进行显示时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)也进行显示。
第一晶体管TFT1的导通和关闭状态由与第一晶体管TFT1的控制极电连接的分屏显示控制信号端V1控制。可选地，当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于高电平的第二信号时，第一晶体管TFT1关闭；当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于低电平的第二信号时，第一晶体管TFT1导通。控制第 一晶体管TFT1导通或关闭的信号的高低电平取决于第一晶体管的类型。可选地，第一晶体管TFT1可为P型晶体管或者N型晶体管。
第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的第二极与第一晶体管TFT1的第二极以及第二栅极驱动子电路的第一个移位寄存器Pixel(n+1)的第一极电连接。当第二显示区域2不再进行显示时、或者第一晶体管TFT1关闭时，第二晶体管TFT2导通，将显示区域调整信号端V3输出的处于高电平的关闭显示信号输出至第二栅极驱动子电路，则第二显示区域2停止显示。
在多区域显示阶段，第一栅极驱动子电路的移位寄存器EM-(n)向与之对应的子像素行Pixel(n)输出的信号EOUT1、向第二栅极驱动子电路的第一个移位寄存器EM-(n)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2的波形如图8所示。可知，信号EOUT1、信号EOUT1-1和信号EOUT2的波形基本相同，并且该三个信号的时序也基本相同。在多区域显示阶段或者全屏显示阶段，本申请实施例介绍的栅极驱动电路可通过消除第一显示区域1和第二显示区域2的各子像素行接收到的信号的波形的差异和信号的时序的差异的方式，减小第一显示区域1和第二显示区域2的显示差异。
在局部显示阶段或者分屏显示阶段，移位寄存器EM-(n)向与之对应的子像素行Pixel(n)输出的信号EOUT1、向第二栅极驱动子电路的第一个移位寄存器EM-(n+1)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2的波形如图9所示。可知，在局部显示阶段中，第二显示区域2不进行显示，第二显示区域2未接收到栅极启动信号，对应的EOUT1-1无有效波形显示。此时，第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行输出的信号EOUT2为显示区域调整信号端V3输出的处于高电平的关闭显示信号。
或者，当第一显示区域1不再进行显示，而第二显示区域2进行显示时，第一晶体管TFT1关闭，第二晶体管TFT2导通，显示区域调整信号端V3输出的栅极启动信号输出至第二栅极驱动子电路，则第二显 示区域2进行显示。
第二晶体管TFT2的导通和关闭状态由与第二晶体管TFT2的控制极电连接的半屏控制信号端V2控制。可选地，当半屏控制信号端V2向第二晶体管TFT2的控制极输出处于高电平的第二信号时，第二晶体管TFT2关闭；当半屏控制信号端V2向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第二晶体管TFT2导通。控制第二晶体管TFT2导通或关闭的信号的高低电平取决于第二晶体管的类型。
在本申请一个可选地实施例中，如图7所示，与移位寄存器EM-(n)对应的子像素行Pixel(n)电连接至移位寄存器EM-(n)的第二信号输出端。
本申请实施中，“移位寄存器EM-(n)”为第一栅极驱动子电路中与显示区域控制单元3电连接，并向显示区域控制单元3输出栅极启动信号的移位寄存器。该移位寄存器EM-(n)为第一显示区域1对应的第一栅极驱动子电路中的移位寄存器。该移位寄存器EM-(n)通过其信号输出端与显示区域控制单元3电连接，并且，该移位寄存器EM-(n)通过其第二信号输出端和与该移位寄存器EM-(n)对应的子像素行Pixel(n)电连接。则，该移位寄存器EM-(n)的信号输出端用于向显示区域控制单元3输出栅极启动信号，该移位寄存器EM-(n)的第二信号输出端用于向与之对应的子像素行Pixel(n)输出栅极启动信号。
可选地，当第一显示区域1和第二显示区域2共同发挥显示功能时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)接收移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号，并进行相应的显示。第二栅极驱动子电路在显示区域控制单元3的控制下，接收该移位寄存器EM-(n)的信号输出端输出的栅极启动信号，并进行相应的显示。当第一显示区域1进行显示，而第二显示区域2不进行显示时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)接收该移位寄存器EM-(n)输出的栅极启动信号，并进行相应的显示；并且，第二栅极驱动子电路在显示区域控制单元3的控制下，停止接收该移位寄存器EM-(n)的信号输出端输出的栅极启动信号，停止根据栅极启动信号进行相应的显示。
在本申请一个可选的实施例中，显示区域控制单元3包括：第一晶体管TFT1、第二晶体管TFT2、分屏显示控制信号端V1、半屏控制信号端V2和显示区域调整信号端V3。
第一晶体管TFT1的第一极作为显示区域控制单元3的信号输入端，第一晶体管TFT1的控制极与分屏显示控制信号端V1电连接；第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的控制极与半屏控制信号端V2电连接，第一晶体管TFT1和第二晶体管TFT2各自的第二极共同作为显示区域控制单元3的信号输出端。
在本申请实施例中，移位寄存器EM-(n)的信号输出端和第一晶体管TFT1的第一极电连接。移位寄存器EM-(n)的第二信号输出端和与该移位寄存器EM-(n)对应的子像素行Pixel(n)电连接。移位寄存器EM-(n)的信号输出端和第二信号输出端均为具有信号输出功能的信号输出端。
当第一晶体管TFT1导通时，由移位寄存器EM-(n)的信号输出端输出的栅极启动信号向第二栅极驱动子电路输出的路径导通。则第二栅极驱动子电路与第一栅极驱动子电路各自对应的各子像素行均根据栅极启动信号进行显示。
当第一晶体管TFT1关闭时，由移位寄存器EM-(n)的信号输出端输出的栅极启动信号向第二栅极驱动子电路输出的路径断开。则第二栅极驱动子电路不再根据该移位寄存器EM-(n)输出的栅极启动信号进行显示。本申请实施例中，与该移位寄存器EM-(n)对应的子像素行Pixel(n)和该移位寄存器EM-(n)之间的电连接由移位寄存器EM-(n)的第二信号输出端控制，与该移位寄存器EM-(n)对应的子像素行Pixel(n)的显示状况将不再受到显示区域控制单元3的影响。
第一晶体管TFT1的导通和关闭状态由与第一晶体管TFT1的控制极电连接的分屏显示控制信号端V1控制。可选地，当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于高电平的第二信号时，第一晶体管TFT1关闭；当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第一晶体管TFT1导通。控制第一晶体管TFT1导通或关闭的信号的高低电平取决于第一晶体管的 类型。
第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的第二极与第一晶体管TFT1的第二极以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)的信号输入端电连接。当第二显示区域2不再进行显示时、或者第一晶体管TFT1关闭时，第二晶体管TFT2导通，将显示区域调整信号端V3输出的处于高电平的关闭显示信号输出至第二栅极驱动子电路，则第二显示区域2停止显示。
在多区域显示阶段，第一栅极驱动子电路的移位寄存器EM-(n)向与之对应的子像素行Pixel(n)输出的信号EOUT1、向第二栅极驱动子电路的第一个移位寄存器EM-(n+1)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2的波形如图8所示。可知，信号EOUT1、信号EOUT1-1和信号EOUT2的波形基本相同，并且该三个信号的时序也基本相同。在多区域显示阶段或者全屏显示阶段，本申请实施例介绍的栅极驱动电路可通过消除第一显示区域1和第二显示区域2的各子像素行接收到的信号的波形的差异和信号的时序的差异的方式，减小第一显示区域1和第二显示区域2的显示差异。
在局部显示阶段，移位寄存器EM-(n)向与之对应的子像素行输出的信号EOUT1、向第二栅极驱动子电路的第一个移位寄存器EM-(n+1)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行输出的信号EOUT2的波形如图9所示。可知，在局部显示阶段中，第二显示区域2不进行显示，第二显示区域2未接收到栅极启动信号，对应的EOUT1-1无有效波形显示。此时，第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2为显示区域调整信号端V3输出的关闭显示信号，在该实施例中关闭显示信号为高电平信号。
或者，当第一显示区域1不再进行显示，而第二显示区域2进行显示时，第一晶体管TFT1关闭，第二晶体管TFT2导通，显示区域调整信号端V3输出的栅极启动信号输出至第二栅极驱动子电路，第二栅极驱动子电路对应的第二显示区域2进行显示。
第二晶体管TFT2的导通和关闭状态由与第二晶体管TFT2的控制极电连接的半屏控制信号端V2控制。可选地，当半屏控制信号端V2向第二晶体管TFT2的控制极输出处于高电平的第二信号时，第二晶体管TFT2关闭；当半屏控制信号端V2向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第二晶体管TFT2导通。控制第二晶体管TFT2导通或关闭的信号的高低电平取决于第二晶体管的类型。
在本申请可选的实施例中，第一栅极驱动子电路和第二栅极驱动子电路均包括依次电连接的多个移位寄存器。
显示区域控制单元3的信号输入端与第一栅极驱动子电路中的移位寄存器EM-(n)的信号输出端电连接，显示区域控制单元3的信号输出端与第二栅极驱动子电路的第一个移位寄存器EM-(n+1)的信号输入端电连接，显示区域控制单元3的信号输入端与信号输出端之间导通时，栅极启动信号从第一栅极驱动子电路中的移位寄存器EM-(n)传输至第二栅极驱动子电路的第一个移位寄存器EM-(n+1)。
第一栅极驱动子电路的除该移位寄存器EM-(n)之外的其它各移位寄存器中或第二栅极驱动子电路中的移位寄存器中，针对两个启动顺序相邻的移位寄存器，前一个移位寄存器的信号输出端电连接至下一个移位寄存器的信号输入端。
第一栅极驱动子电路和第二栅极驱动子电路中移位寄存器可为常规的移位寄存器。各移位寄存器至少用于将栅极启动信号输出至至少一个子像素行，进而控制该子像素行根据栅极启动信号的显示状况。可选地，第一栅极驱动子电路中的第一个移位寄存器EM-(1)与栅极启动信号端STV电连接。栅极启动信号端STV输出的栅极启动信号输出至第一栅极驱动子电路中的第一个移位寄存器EM-(1)，该第一栅极驱动子电路中的第一个移位寄存器EM-(1)将栅极启动信号输出至与之对应的子像素行Pixel(1)，并将该栅极启动信号输出至第一栅极驱动子电路中的第二个移位寄存器EM-(2)。
可选地，在第一栅极驱动子电路中和/或第二栅极驱动子电路中，各移位寄存器的次序与栅极启动信号在该栅极驱动子电路中的各移位寄存器之间的传输次序相同。与栅极启动信号端STV直接电连接的移位寄存 器即为第一栅极驱动子电路的第一移位寄存器。
本申请实施例的各移位寄存器的信号输入端为具备信号输入功能的信号输入端。第一栅极驱动子电路中的第一个移位寄存器EM-(1)的信号输入端与栅极启动信号端STV电连接，至少用于从栅极启动信号端STV中接收栅极启动信号。其余各移位寄存器的信号输入端至少与在栅极启动信号的输出次序上的前一个移位寄存器的信号输出端电连接，至少用于接收该前一个移位寄存器输出的栅极启动信号。各移位寄存器的信号输出端为具备信号输出功能的信号输出端。各移位寄存器的信号输出端至少与在栅极启动信号的输出次序上的下一个移位寄存器的信号输入端电连接，至少用于向该下一个移位寄存器输出栅极启动信号。各移位寄存器的第二信号输出端为具备信号输出功能的信号输出端。各移位寄存器的第二信号输出端至少与该移位寄存器对应的子像素行电连接，用于向该子像素行输出栅极启动信号。
显示区域控制单元3的信号输入端为具备信号输入功能的信号输入端。显示区域控制单元3的信号输出端为具备信号输出功能的信号输出端。在显示区域控制单元3的信号输入端和信号输出端之间导通时，显示区域控制单元3的信号输入端至少用于从与之电连接的移位寄存器的信号输出端接收栅极启动信号，并将该栅极启动信号输出至显示区域控制单元3的信号输出端，显示区域控制单元3的信号输出端将该栅极启动信号输出至与之电连接的移位寄存器的信号输入端。当显示区域控制单元3的信号输入端和信号输出端之间电连接断开时，栅极启动信号从第一栅极驱动子电路向第二栅极驱动子电路传输的电路被断开，第二显示区域2停止根据栅极启动信号进行显示。
在本申请一个可选地实施例中，与移位寄存器EM-(n)对应的子像素行Pixel(n)电连接至显示区域控制单元3的信号输出端。
本申请实施中，“移位寄存器EM-(n)”为第一栅极驱动子电路中与显示区域控制单元3电连接，并向显示区域控制单元3输出栅极启动信号的移位寄存器。显示区域控制单元3用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的栅极启动信号的通断，并且，显示区域控制单元3还用于控制该移位寄存器EM-(n)和与之对应的子像素行 Pixel(n)之间的栅极启动信号的通断。
可选地，当第一显示区域1和第二显示区域2共同发挥显示功能时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)和第二显示区域2在显示区域控制单元3的控制下接收由该移位寄存器EM-(n)输出的栅极启动信号，并进行相应的显示。当第一显示区域1进行显示，而第二显示区域2不进行显示时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)在显示区域控制单元3的控制下停止接收由该移位寄存器EM-(n)输出的栅极启动信号，并停止进行相应的显示。
在本申请一个可选的实施例中，显示区域控制单元3包括：第一晶体管TFT1、第二晶体管TFT2、分屏显示控制信号端V1、半屏控制信号端V2和显示区域调整信号端V3。
第一晶体管TFT1的第一极作为显示区域控制单元3的信号输入端，第一晶体管TFT1的控制极与分屏显示控制信号端V1电连接；第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的控制极与半屏控制信号端V2电连接，第一晶体管TFT1和第二晶体管TFT2各自的第二极共同作为显示区域控制单元3的信号输出端。
在本申请实施例中，移位寄存器EM-(n)的信号输出端与第一晶体管TFT1的第一极电连接。该移位寄存器EM-(n)对应的子像素行Pixel(n)和第一晶体管TFT1的第二极电连接，第二栅极驱动子电路的第一个移位寄存器EM-(n+1)的信号输入端与第一晶体管TFT1的第二极电连接。
当第一晶体管TFT1导通时，由移位寄存器EM-(n)的信号输出端输出的栅极启动信号向第二栅极驱动子电路以及向与该移位寄存器EM-(n)对应的子像素行Pixel(n)输出的路径导通。第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)根据该移位寄存器EM-(n)输出的栅极启动信号进行显示。
当第一晶体管TFT1关闭时，由移位寄存器EM-(n)的信号输出端输出的栅极启动信号向第二栅极驱动子电路以及向与该移位寄存器EM-(n)对应的子像素行Pixel(n)输出的路径断开。第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)不再根据栅极启 动信号进行显示。本申请实施例中，与该移位寄存器EM-(n)对应的子像素行Pixel(n)和该移位寄存器EM-(n)之间的电连接关系受到显示区域控制单元3的控制。
第一晶体管TFT1的导通和关闭状态由与第一晶体管TFT1的控制极电连接的分屏显示控制信号端V1控制。可选地，当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于高电平的第二信号时，第一晶体管TFT1关闭；当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第一晶体管TFT1导通。控制第一晶体管TFT1导通或关闭的信号的高低电平取决于第一晶体管的类型。可选地，第一晶体管TFT1可为P型晶体管或者N型晶体管。
第二晶体管TFT2的第一极与显示区域调整信号端V3电连接。第二晶体管TFT2的第二极和与该移位寄存器EM-(n)对应的子像素行Pixel(n)以及第一晶体管TFT1的第二极电连接。当第二显示区域2不再进行显示时、或者第一晶体管TFT1关闭时，第二晶体管TFT2导通，将显示区域调整信号端V3输出的处于高电平的关闭显示信号输出至第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)，则第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)停止显示。
或者，当第一显示区域1不再进行显示，而第二显示区域2进行显示时，第一晶体管TFT1关闭，第二晶体管TFT2导通，显示区域调整信号端V3输出的栅极启动信号输出至第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)，第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)进行显示。
第二晶体管TFT2的导通和关闭状态由与第二晶体管TFT2的控制极电连接的半屏控制信号端V2控制。可选地，当半屏控制信号端V2向第二晶体管TFT2的控制极输出处于高电平的第二信号时，第二晶体管TFT2关闭；当半屏控制信号端V2向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第二晶体管TFT2导通。控制第二晶体管TFT2导通或关闭的信号的高低电平取决于第二晶体管的类型。可选地，第二晶体管TFT2可为P型晶体管或者N型晶体管。
在本申请一个可选地实施例中，与移位寄存器EM-(n)对应的子像素行Pixel(n)电连接至移位寄存器EM-(n)的第二信号输出端。
本申请实施中，“移位寄存器EM-(n)”为第一栅极驱动子电路中与显示区域控制单元3电连接，并向显示区域控制单元3输出栅极启动信号的移位寄存器。显示区域控制单元3用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的栅极启动信号的通断。
可选地，当第一显示区域1和第二显示区域2共同发挥显示功能时，第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行Pixel(n)接收由该移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号，并进行相应的显示。当第一显示区域1进行显示，而第二显示区域2不进行显示时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)接收由该移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号，进行相应的显示。第二显示区域2停止接收该移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号，并停止进行相应的显示。
在本申请一个可选的实施例中，显示区域控制单元3包括：第一晶体管TFT1、第二晶体管TFT2、分屏显示控制信号端V1、半屏控制信号端V2和显示区域调整信号端V3。
第一晶体管TFT1的第一极作为显示区域控制单元3的信号输入端，第一晶体管TFT1的控制极与分屏显示控制信号端V1电连接；第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的控制极与半屏控制信号端V2电连接，第一晶体管TFT1和第二晶体管TFT2各自的第二极共同作为显示区域控制单元3的信号输出端。
在本申请实施例中，移位寄存器EM-(n)的第二信号输出端分别与第一晶体管TFT1的第一极电连接、以及与该移位寄存器EM-(n)对应的子像素行Pixel(n)电连接。第一晶体管TFT1的第二极分别与第二栅极驱动子电路中的第一个移位寄存器EM-(n+1)的信号输入端和第二晶体管TFT2的第二极电连接。
当第一晶体管TFT1导通时，由移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号向第二栅极驱动子电路输出的路径导通。则第二栅极驱动子电路与第一栅极驱动子电路各自对应的各子像素行均根据 栅极启动信号进行显示。
当第一晶体管TFT1关闭时，由移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号向第二栅极驱动子电路输出的路径断开。则第二栅极驱动子电路不再根据该移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号进行显示，但该移位寄存器EM-(n)的第二信号输出端和与之对应的子像素行Pixel(n)之间的电连接状态不变，与之对应的子像素行Pixel(n)继续根据该移位寄存器EM-(n)的第二信号输出端输出的栅极启动信号进行显示。本申请实施例中，与该移位寄存器EM-(n)对应的子像素行Pixel(n)和该移位寄存器EM-(n)之间的电连接关系不再受显示区域控制单元3的控制。第一显示区域1进行显示时，与该移位寄存器EM-(n)对应的子像素行Pixel(n)也进行显示。
第一晶体管TFT1的导通和关闭状态由与第一晶体管TFT1的控制极电连接的分屏显示控制信号端V1控制。可选地，当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于高电平的第二信号时，第一晶体管TFT1关闭；当分屏显示控制信号端V1向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第一晶体管TFT1导通。控制第一晶体管TFT1导通或关闭的信号的高低电平取决于第一晶体管的类型。可选地，第一晶体管TFT1可为P型晶体管或者N型晶体管。
第二晶体管TFT2的第一极与显示区域调整信号端V3电连接，第二晶体管TFT2的第二极与第一晶体管TFT1的第二极以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)的第一极电连接。当第二显示区域2不再进行显示时、或者第一晶体管TFT1关闭时，第二晶体管TFT2导通，将显示区域调整信号端V3输出的处于高电平的关闭显示信号输出至第二栅极驱动子电路，则第二显示区域2停止显示。
在多区域显示阶段，移位寄存器EM-(n)的第二信号输出端向与之对应的子像素行输出的信号EOUT1、通过显示区域控制单元3向第二栅极驱动子电路的第一个移位寄存器EM-(n+1)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2的波形，如图8所示。可知， 在多区域显示阶段，第一显示区域1和第二显示区域2均进行显示，信号EOUT1、信号EOUT1-1和信号EOUT2的波形基本相同，则第一显示区域中的各子像素行和第二显示区域中的各子像素行之间接收的信号波形差异被较大程度的降低。
在局部显示阶段，移位寄存器EM-(n)的第二信号输出端向与之对应的子像素行输出的信号EOUT1、通过显示区域控制单元3向第二栅极驱动子电路的第一个移位寄存器EM-(n+1)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2的波形如图9所示。可知，在局部显示阶段中，第二显示区域2不进行显示，第二显示区域2未接收到移位寄存器EM-(n)输出的信号，则对应的EOUT1-1无有效波形显示。第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行Pixel(n+1)输出的信号EOUT2为显示区域调整信号端V3输出的关闭显示信号，在该实施例中关闭显示信号为高电平信号。
或者，当第一显示区域1不再进行显示，而第二显示区域2进行显示时，第一晶体管TFT1关闭，第二晶体管TFT2导通，显示区域调整信号端V3输出的栅极启动信号输出至第二栅极驱动子电路，则第二栅极驱动子电路对应的子像素行进行显示。
第二晶体管TFT2的导通和关闭状态由与第二晶体管TFT2的控制极电连接的半屏控制信号端V2控制。可选地，当半屏控制信号端V2向第二晶体管TFT2的控制极输出处于高电平的第二信号时，第二晶体管TFT2关闭；当半屏控制信号端V2向第一晶体管TFT1的控制极输出处于低电平的第二信号时，第二晶体管TFT2导通。控制第二晶体管TFT2导通或关闭的信号的高低电平取决于第二晶体管的类型。可选地，第二晶体管TFT2可为P型晶体管或者N型晶体管。
本申请实施例中的分屏显示控制信号端V1、半屏控制信号端V2、显示区域调整信号端V3中的任一项或者几项，可仅为一个用于传输相应的信号的线路，不包含产生该相应的信号的信号源。也可包括用于传输相应的信号的线路和产生该相应的信号的信号源。
可选地，当本申请实施例中的显示装置为可折叠的显示装置时，分 屏显示控制信号端V1的信号输出状态由对显示装置的折叠、展平操作进行触发。具体地，当第一显示区域1和第二显示区域2的相对位置关系为使得显示装置被折叠时，分屏显示控制信号端V1向第一晶体管TFT1的控制极输出使得TFT1关闭的第二信号；当第一显示区域1和第二显示区域2的相对位置关系为使得显示装置被展平时，分屏显示控制信号端V1向第一晶体管TFT1的控制极输出使得TFT1导通的第一控制信号。
可选地，当本申请实施例中的显示装置为可折叠的显示装置时，半屏控制信号端V2的信号输出状态由对显示装置的折叠、展平操作进行触发。具体地，当第一显示区域1和第二显示区域2的相对位置关系为使得显示装置被展平时，半屏控制信号端V2向第二晶体管TFT2的控制极输出使得TFT2关闭的第二信号；当第一显示区域1和第二显示区域2的相对位置关系为使得显示装置被折叠时，半屏控制信号端V2向第二晶体管TFT2的控制极输出使得TFT2导通的第一控制信号。
在本申请一个可选的实施例中，当本申请实施例中的显示装置为可折叠的显示装置时，显示区域调整信号端V3的信号输出状态也可由对显示装置的折叠、展平操作进行触发。
在本申请实施例中，第二栅极驱动子电路中，每个移位寄存器的第二信号输出端用于电连接至对应的子像素行；
和/或，第一栅极驱动子电路中，除了一个移位寄存器EM-(n)以外的其他移位寄存器的第二信号输出端用于电连接至对应的子像素行。
本申请实施例中的栅极驱动电路中，第二显示区域2对应的第二栅极驱动子电路中的各移位寄存器均具有相同的结构及连接关系。可选地，第一显示区域1对应的第一栅极驱动子电路中，除移位寄存器EM-(n)以外的其他各移位寄存器均具有相同的结构及连接关系；并且除移位寄存器EM-(n)以外的其他各移位寄存器与第二显示区域2对应的第二栅极驱动子电路中的各移位寄存器的结构及连接关系相同。可选地，第一显示区域1和第二显示区域2分别对应的第一栅极驱动子电路和第二栅极驱动子电路中的各移位寄存器均具有相同的结构及连接关系。
在本申请一个可选地实施例中，如图11所示，在栅极驱动电路中， 第一栅极驱动子电路包括依次电连接的M个级联的第一移位寄存器EM(1)～EM(M)，第二栅极驱动子电路包括依次电连接的N个级联的第二移位寄存器EM(n+1)～EM(n+N)，所述M、N分别为大于或等于2的正整数。
第一栅极驱动子电路的输入端与栅极启动信号端STV电连接，并且所述第一栅极驱动子电路的多个输出端与显示装置的第一显示区域的多个子像素行电连接，用于输出扫描信号并根据所述扫描信号控制所述第一显示区域进行显示。
显示区域控制单元的输入端连接所述第一栅极驱动子电路的多个输出端中的一个输出端，用于接收所述第一栅极驱动子电路输出的扫描信号，所述显示区域控制单元的控制端与分屏控制信号端连接，用于接收所述分屏控制信号端输出的分屏控制信号，所述显示区域控制单元的输出端用于根据所述分屏控制信号而输出或不输出所述扫描信号。第二栅极驱动子电路的输入端与所述显示区域控制单元的输出端电连接，所述第二栅极驱动子电路的多个输出端与显示装置的第二显示区域的多个子像素行电连接，用于根据接收是否接收到扫描信号，控制所述第二显示区域的显示状态。
当第一显示区域1和第二显示区域2共同发挥显示功能时，即在全屏显示阶段，与第一栅极驱动子电路对应的第一显示区域的子像素行接收由该第一栅极驱动子电路输出的扫描信号，并进行相应的显示。分屏控制信号端接收第一控制信号，使得显示区域控制单元的输出端根据所述分屏控制信号而输出扫描信号。与第二栅极驱动子电路对应的第二显示区域的子像素行根据接收到的扫描信号进行相应的显示。
当第一显示区域1进行显示，而第二显示区域2不进行显示时，即在分屏显示阶段，与第一栅极驱动子电路对应的第一显示区域的子像素行接收由该第一栅极驱动子电路输出的扫描信号，并进行相应的显示。分屏控制信号端接收第二控制信号，使得显示区域控制单元的输出端根据所述分屏控制信号而不输出扫描信号。与第二栅极驱动子电路对应的第二显示区域的子像素行由于未接收到扫描信号，不进行显示。
在本申请一个可选地实施例中，如图11所示，显示区域控制单元 包括：第一晶体管TFT1。
第一晶体管TFT1的第一极作为显示区域控制单元3的输入端，与第一栅极驱动子电路的一个输出端电连接，第一晶体管TFT1的控制极与所述分屏控制信号端电连接，第一晶体管TFT1的第二极作为所述显示区域控制单元的输出端。
显示区域控制单元被配置为在全屏显示阶段接收所述分屏控制信号端输出的第一控制信号而在输出端输出所述第一栅极驱动子电路的一个输出端输出的扫描信号，在分屏显示阶段接收所述分屏控制信号端输出的第二控制信号而不在输出端输出扫描信号。
在本申请实施例中，移位寄存器EM-(n)的信号输出端与第一晶体管TFT1的第一极电连接，移位寄存器EM-(n+1)的信号输入端与第一晶体管TFT1的第二极电连接。
当第一晶体管TFT1导通时，由移位寄存器EM-(n)的信号输出端输出的扫描信号向第二栅极驱动子电路输出的路径导通。则第二栅极驱动子电路根据接收的扫描信号，驱动与第二栅极驱动子电路对应的第二显示区域的子像素行进行相应的显示。
当第一晶体管TFT1关闭时，由移位寄存器EM-(n)的信号输出端输出的扫描信号向第二栅极驱动子电路的路径断开。则第二栅极驱动子电路未接收到扫描信号，不再根据扫描信号驱动与第二栅极驱动子电路对应的第二显示区域的子像素行进行相应的显示。
第一晶体管TFT1的导通和关闭状态，由与第一晶体管TFT1的控制极电连接的分屏控制信号端V1控制。可选地，当分屏控制信号端V1向第一晶体管TFT1的控制极输出处于高电平的第二信号时，第一晶体管TFT1关闭；当分屏控制信号端V1向第一晶体管TFT1的控制极输出处于低电平的第一控制信号时，第一晶体管TFT1导通。控制第一晶体管TFT1导通或关闭的信号的高低电平取决于第一晶体管的类型。
本申请实施例中的分屏控制信号端V1可仅为一个用于传输相应的信号的线路，不包含产生该相应的信号的信号源。也可包括用于传输相应的信号的线路和产生该相应的信号的信号源。
在本申请实施例中，显示区域控制单元3还包括电容C，电容C的 两端分别与显示区域控制单元3的输入端和输出端电连接。电容C用于调整通过第一晶体管TFT1的信号的持续性。
本领域技术人员可以理解，第一移位寄存器、第二移位寄存器以及显示区域控制单元3的各用于输出信号、输入信号的端的数量、布置方式、连接关系可根据实际要求进行设计。前述各实施例中的各用于输出信号、输入信号的端的数量、布置方式、连接关系仅作为本申请实施例提供的栅极驱动电路的一种示例。可适应地调整本申请实施例提供的栅极驱动电路中的移位寄存器以及显示区域控制单元3的各端的数量、布置方式、连接关系，适应地调整后获得的技术方案仍然属于本申请实施例的保护范围。
本申请实施例还提供了一种显示装置。如图5-7和图11所示，该显示装置包括第一显示区域1、第二显示区域2，以及前述各实施例中的栅极驱动电路。
栅极驱动电路中的第一栅极驱动子电路与第一显示区域1中的各子像素行电连接。
栅极驱动电路中的显示区域控制单元3电连接在第一栅极驱动子电路和第二栅极驱动子电路之间。
栅极驱动电路中的第二栅极驱动子电路与第二显示区域2中的各子像素行电连接。
本申请实施例提供的显示装置，与前面的各实施例具有相同的发明构思及相同的有益效果，该显示装置中未详细示出的内容可参照前面的各实施例，在此不再赘述。
在本申请的实施例中，显示装置还可包括驱动控制电路，用于提供栅极启动信号和分屏控制信号。
本申请实施例还提供了一种显示控制方法。如图13所述，显示控制方法1300可以应用于前述各实施例中的栅极驱动电路。该方法包括，首先确定显示装置的显示状态，即是处于全屏显示阶段还是处于分屏显示阶段。
如果是在全屏显示阶段，则如步骤S1310所示，例如驱动控制电路向栅极启动信号端提供栅极启动信号，使得第一栅极驱动子电路根据栅 极启动信号控制第一显示区域1进行显示，并向分屏控制信号端提供第一控制信号，以使得显示区域控制单元3将第一栅极驱动子电路的一个输出端输出的扫描信号传输到第二栅极驱动子电路的输入端，第二栅极驱动子电路根据扫描信号控制第二显示区域2进行显示。
如果是在局部显示阶段，则如步骤S1320所示，例如驱动控制电路向栅极启动信号端提供栅极启动信号，使得第一栅极驱动子电路根据栅极启动信号控制第一显示区域1进行显示，并向分屏控制信号端提供第一控制信号，并向分屏控制信号端提供第二控制信号，显示区域控制单元3断开第一栅极驱动子电路和第二栅极驱动子电路之间的电连接，不将第一栅极驱动子电路的一个输出端输出的扫描信号传输到第二栅极驱动子电路的输入端，使得第二显示区域2停止显示。
在全屏显示阶段中，至少显示装置的第一显示区域1和第二显示区域2处于图像显示状态，用于画面输出。本阶段中，栅极启动信号端STV将栅极启动信号输出至第一栅极驱动子电路，第一栅极驱动子电路根据接收到的栅极启动信号，向与第一栅极驱动子电路对应的各子像素行输出扫描信号，该与第一栅极驱动子电路对应的各子像素行根据扫描信号进行图像显示。并且，在显示区域控制单元3中用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的信号通断的部分导通的情况下，第一栅极驱动子电路将扫描信号输出至显示区域控制单元3，显示区域控制单元3再将该扫描信号输出至第二栅极驱动子电路。第二栅极驱动子电路根据接收的扫描信号，输出扫描信号至与第二栅极驱动子电路对应的各子像素行，该与第二栅极驱动子电路对应的各子像素行根据扫描信号进行图像显示。则，本申请实施例中的第一显示区域1和第二显示区域2均根据同一栅极启动信号端STV输出的栅极启动信号进行显示，较大程度地降低了由于信号差异引起的两个显示区域之间的显示状况差异。
在本申请一个可选的实施例中，栅极驱动电路中的显示区域控制单元3将第一栅极驱动子电路的栅极启动信号输出至栅极驱动电路中的第二栅极驱动子电路，包括：
显示区域控制单元3中的第一晶体管TFT1根据控制极接收到的源自分屏显示控制信号端V1的第一控制信号导通。
显示区域控制单元3中的第二晶体管TFT2根据控制极接收到的源自半屏控制信号端V2的第二信号断开。
栅极启动信号依次通过第一栅极驱动子电路、第一晶体管TFT1输出至第二栅极驱动子电路的信号输入端。
本申请实施例中，当第一晶体管TFT1导通时，由栅极信号模块EM-(n)输出的栅极启动信号向第二栅极驱动子电路以及向与该栅极信号模块EM-(n)对应的子像素行输出的路径导通。第二栅极驱动子电路和与该栅极信号模块EM-(n)对应的子像素行根据该栅极信号模块EM-(n)输出的栅极启动信号进行显示。第二晶体管TFT2的断开状态，使得显示区域调整信号端V3和第二栅极驱动子电路之间的电连接断开，显示区域调整信号端V3的信号将不会输出至第二栅极驱动子电路。
可选地，分屏控制信号端V1、半屏控制信号端V2和显示区域调整信号端V3各自的信号输出状况如图10所示。分屏显示控制信号端V1输出处于低电平的第一控制信号，半屏控制信号端V2输出处于高电平的第二信号。显示区域调整信号端V3输出的信号不作限制，可为低电平信号或者高电平信号，如图10的虚线部分所示；也可不输出信号。
可选地，在局部显示阶段中，第一显示区域1进行显示，第二显示区域2不进行显示。在显示区域控制单元3中用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的信号通断的部分断开，栅极启动信号端STV将栅极启动信号输出至第一栅极驱动子电路，第一栅极驱动子电路将接收到的栅极启动信号输出至与第一栅极驱动子电路对应的各子像素行，与第一栅极驱动子电路对应的各子像素行根据栅极启动信号端STV输出的栅极启动信号进行图像显示。显示区域控制单元3断开第二栅极驱动子电路从第一栅极驱动子电路接收栅极启动信号的电路，第二栅极驱动子电路停止从第一栅极驱动子电路接收栅极启动信号。则，第二栅极驱动子电路不再根据栅极启动信号控制与第二栅极驱动子电路对应的各子像素行的显示状态。
在本申请一个可选的实施例中，显示区域控制单元断开第一栅极驱动子电路和第二栅极驱动子电路之间的电连接，包括：
显示区域控制单元中的第一晶体管TFT1根据控制极接收到的源自 分屏显示控制信号端V1的第二信号断开。
本申请实施例中，第一晶体管TFT1在分屏显示控制信号端V1的控制下导通或者断开。第一晶体管TFT1的导通和断开操作，至少用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的栅极启动信号的通断。可选地，第二信号为高电平信号。
在本申请一个可选的实施例中，显示区域控制单元3断开第一栅极驱动子电路和第二栅极驱动子电路之间的电连接，使得第二显示区域2停止显示之后，还包括：
显示区域控制单元3向第二栅极驱动子电路输出关闭显示信号，第二栅极驱动子电路根据关闭显示信号控制第二显示区域2停止显示。
在局部显示阶段，移位寄存器EM-(n)向与之对应的子像素行输出的信号EOUT1、向第二栅极驱动子电路的第一个移位寄存器EM-(n+1)输出的信号EOUT1-1、以及第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行输出的信号EOUT2的波形如图9所示。可知，在局部显示阶段中，第二显示区域2不进行显示，第二显示区域2未接收到移位寄存器EM-(n)输出的栅极启动信号，对应的EOUT1-1无有效波形显示。第二栅极驱动子电路的第一个移位寄存器EM-(n+1)向与之对应的子像素行输出的信号EOUT2为显示区域调整信号端V3输出的关闭显示信号，此时关闭显示信号为高电平信号。
在本申请一个可选的实施例中，显示控制方法还包括，在局部显示阶段，显示区域控制单元3断开第一栅极驱动子电路和第二栅极驱动子电路之间的电连接，并输出源自显示区域调整信号端V3的栅极启动信号，同时第一栅极驱动子电路通过栅极启动信号端STV接收关闭显示信号，使得第二栅极驱动子电路根据源自显示区域调整信号端V3的栅极启动信号控制第二显示区域2进行显示，且第一栅极驱动子电路根据关闭显示信号控制第一显示区域1停止显示。
本申请实施例中，当第一显示区域1不再进行显示，而第二显示区域2进行显示时，第一晶体管TFT1关闭，第二晶体管TFT2导通，显示区域调整信号端V3输出的栅极启动信号输出至第二栅极驱动子电路，第二栅极驱动子电路进行显示。或者，显示区域调整信号端V3输出的 栅极启动信号输出至第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行，则第二栅极驱动子电路和与该移位寄存器EM-(n)对应的子像素行进行显示。第一显示区域1停止显示。
在本申请一个可选的实施例中，显示区域控制单元3向第二栅极驱动子电路输出栅极启动信号，包括：
显示区域控制单元3中的第二晶体管TFT2根据控制极接收到的源自半屏控制信号端V2的第一控制信号导通。
显示区域调整信号端V3的栅极启动信号依次通过第二晶体管TFT2的第一极、第二极，并输出至第二栅极驱动子电路的信号输入端。
在本申请一个可选的实施例中，栅极驱动电路中的显示区域控制单元3将第一栅极驱动子电路的扫描信号输出至栅极驱动电路中的第二栅极驱动子电路，包括：
显示区域控制单元3中的第一晶体管TFT1根据控制极接收到的源自分屏控制信号端V1的第一控制信号导通。
扫描信号依次通过第一栅极驱动子电路、第一晶体管TFT1输出至第二栅极驱动子电路的输入端。
本申请实施例中，当第一晶体管TFT1导通时，由移位寄存器EM-(n)输出的扫描信号向第二栅极驱动子电路输出的路径导通。第二栅极驱动子电路根据该移位寄存器EM-(n)输出的扫描信号控制与第二栅极驱动子电路对应的子像素行进行显示。
可选地，分屏显示控制信号端V1的信号输出状况如图12所示。分屏显示控制信号端V1输出处于低电平的第一控制信号。
可选地，在局部显示阶段中，第一显示区域1进行显示，第二显示区域2不进行显示。在显示区域控制单元3中用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的信号通断的部分断开，栅极启动信号端STV将栅极启动信号输出至第一栅极驱动子电路，第一栅极驱动子电路将接收到的栅极启动信号输出至与第一栅极驱动子电路对应的各子像素行，与第一栅极驱动子电路对应的各子像素行根据栅极启动信号端STV输出的栅极启动信号进行图像显示。显示区域控制单元3断开第二栅极驱动子电路从第一栅极驱动子电路接收栅极启动信号的电路，第二 栅极驱动子电路停止从第一栅极驱动子电路接收栅极启动信号。则，第二栅极驱动子电路不再根据栅极启动信号控制与第二栅极驱动子电路对应的各子像素行的显示状态。
在本申请一个可选的实施例中，显示区域控制单元断开第一栅极驱动子电路和第二栅极驱动子电路之间的电连接，包括：
显示区域控制单元中的第一晶体管TFT1根据控制极接收到的源自分屏显示控制信号端V1的第二控制信号断开。
本申请实施例中，第一晶体管TFT1在分屏显示控制信号端V1的控制下导通或者断开。第一晶体管TFT1的导通和断开操作，至少用于控制第一栅极驱动子电路和第二栅极驱动子电路之间的栅极启动信号的通断。可选地，第二控制信号为高电平信号。
在本申请一个可选的实施例中，显示装置还包括第三显示区域。则本申请中各实施例的显示控制方法还可以应用于该第三显示区域和与第三显示区域具备显示配合关系的其他显示区域之间。则本申请中各实施例的显示控制方法中的在多区域显示阶段的相关技术方案，不仅仅局限于显示装置具有第一显示区域1和第二显示区域2的情形，还可应用于显示装置具备更多个显示区域的情形。
应用本申请实施例提供的像素驱动电路和像素驱动方法，至少可以实现如下有益效果：
1)采用本申请实施例提供的栅极驱动电路、显示装置及显示控制方法，至少在相邻的两个显示区域之间建立栅极启动信号的承接关系，则至少在相邻的显示区域之间，第一显示区域中的栅极启动信号能够在一定条件下输出至第二显示区域中，使得第一显示区域和第二显示区域能够在同一个栅极启动信号的控制下进行显示，至少能够减小相邻的显示区域之间由于接收到的栅极启动信号的差异而导致的显示差异。
2)在本申请实施例提供的栅极驱动电路、显示装置及显示控制方法，能够使得显示装置的任意相邻的两行子像素通过相同来源的栅极启动信号进行控制，则相邻的两个显示区域同时显示时，不会因为栅极启动信号的波形差异引起相邻的两个显示区域之间产生“分屏”的现象。
3)在本申请实施例提供的栅极驱动电路、显示装置及显示控制方法，在不需要进行显示的显示区域中，通过栅极启动信号端或者显示区域控制单元，向该不需要进行显示的区域输出关闭显示信号，使得该不需要进行显示的显示区域停止显示。避免影响其他需要进行显示的显示区域的显示效果。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，其可以以其他的顺序执行。而且，附图的流程图中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，其执行顺序也不必然是依次进行，而是可以与其他步骤或者其他步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (7)

  1. 一种栅极驱动电路，包括：
    第一栅极驱动子电路，所述第一栅极驱动子电路的输入端与栅极启动信号端电连接，所述第一栅极驱动子电路的多个输出端与显示装置的第一显示区域的多个子像素行电连接，用于输出扫描信号并根据所述扫描信号控制所述第一显示区域进行显示；
    显示区域控制单元，所述显示区域控制单元的输入端连接所述第一栅极驱动子电路的多个输出端中的一个输出端，用于接收所述第一栅极驱动子电路输出的扫描信号，所述显示区域控制单元的控制端与分屏控制信号端连接，用于接收所述分屏控制信号端输出的分屏控制信号，所述显示区域控制单元的输出端用于根据所述分屏控制信号而输出或不输出所述扫描信号；以及
    第二栅极驱动子电路，所述第二栅极驱动子电路的输入端与所述显示区域控制单元的输出端电连接，所述第二栅极驱动子电路的多个输出端与显示装置的第二显示区域的多个子像素行电连接，用于根据接收是否接收到扫描信号，控制所述第二显示区域的显示状态。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述显示区域控制单元包括：第一晶体管；
    所述第一晶体管的第一极作为所述显示区域控制单元的输入端，与所述第一栅极驱动子电路的一个输出端电连接，所述第一晶体管的控制极与所述分屏控制信号端电连接，所述第一晶体管的第二极作为所述显示区域控制单元的输出端，
    所述显示区域控制单元被配置为在全屏显示阶段接收所述分屏控制信号端输出的第一控制信号而在输出端输出所述第一栅极驱动子电路的一个输出端输出的扫描信号，在分屏显示阶段接收所述分屏控制信号端输出的第二控制信号而不在输出端输出所述扫描信号。
  3. 根据权利要求1或2所述的栅极驱动电路，其中，所述显示区 域控制单元还包括电容；
    所述电容的两端分别与所述显示区域控制单元的输入端和输出端电连接。
  4. 根据权利要求1至3任一项所述的栅极驱动电路，其中，所述第一栅极驱动子电路包括M个级联的第一移位寄存器，所述第二栅极驱动子电路包括N个级联的第二移位寄存器，所述M、N分别为大于或等于2的正整数，
    第1级第一移位寄存器的信号输入端连接所述栅极启动信号端，第M级第一移位寄存器的输出端连接所述显示区域控制单元的输入端，第一个第二移位寄存器的信号输入端连接所述显示区域控制单元的输出端。
  5. 一种显示装置，包括第一显示区域、第二显示区域、以及如权利要求1至4中任一项所述的栅极驱动电路；
    所述栅极驱动电路中的第一栅极驱动子电路与所述第一显示区域中的各子像素行电连接；
    所述栅极驱动电路中的显示区域控制单元电连接在所述第一栅极驱动子电路和所述第二栅极驱动子电路之间；
    所述栅极驱动电路中的第二栅极驱动子电路与所述第二显示区域中的各子像素行电连接。
  6. 根据权利要求5所述的显示装置，还包括：驱动控制电路，用于提供所述栅极启动信号和所述分屏控制信号。
  7. 一种显示控制方法，应用于如权利要求1至4中任一项所述的栅极驱动电路，包括：
    在全屏显示阶段，向所述分屏控制信号端提供第一控制信号，以使得所述显示区域控制单元将所述第一栅极驱动子电路的一个输出端输出的扫描信号传输到所述第二栅极驱动子电路的输入端；以及
    在分屏显示阶段，向所述分屏控制信号端提供第二控制信号，以使得所述显示区域控制单元不将所述第一栅极驱动子电路的一个输出端输出的扫描信号传输到所述第二栅极驱动子电路的输入端。
PCT/CN2020/092932 2019-05-31 2020-05-28 栅极驱动电路、显示装置及显示控制方法 WO2020239028A1 (zh)

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