WO2020238313A1 - Display substrate for ultrasonic fingerprint recognition, manufacturing method therefor, and display device - Google Patents

Display substrate for ultrasonic fingerprint recognition, manufacturing method therefor, and display device Download PDF

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Publication number
WO2020238313A1
WO2020238313A1 PCT/CN2020/077869 CN2020077869W WO2020238313A1 WO 2020238313 A1 WO2020238313 A1 WO 2020238313A1 CN 2020077869 W CN2020077869 W CN 2020077869W WO 2020238313 A1 WO2020238313 A1 WO 2020238313A1
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WIPO (PCT)
Prior art keywords
electrode
layer
electrically connected
base substrate
film layer
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PCT/CN2020/077869
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French (fr)
Chinese (zh)
Inventor
邸云萍
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京东方科技集团股份有限公司
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Publication of WO2020238313A1 publication Critical patent/WO2020238313A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06VIMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12Fingerprints or palmprints
    • G06V40/13Sensors therefor
    • G06V40/1318Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/1201Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65OLEDs integrated with inorganic image sensors

Definitions

  • the embodiments of the present disclosure relate to a display substrate for ultrasonic fingerprint recognition, a manufacturing method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • the current ultrasonic fingerprint recognition device is prepared by a semiconductor process with a silicon wafer as a substrate, and the other is prepared by a low-temperature polysilicon process with a glass as a substrate.
  • the embodiments of the present disclosure provide a display substrate for ultrasonic fingerprint identification, a manufacturing method thereof, and a display device, so as to solve the problem that the existing display substrate can only realize non-display area key-press fingerprint identification by external bonding.
  • a display substrate for ultrasonic fingerprint recognition including a base substrate and a plurality of pixel units arranged on the base substrate, each of the pixel units including:
  • Light emitting device the light emitting device includes:
  • a driving circuit which is arranged on a side of the light-emitting unit close to the base substrate and configured to be electrically connected to the light-emitting unit;
  • the fingerprint recognition device includes an ultrasonic fingerprint recognition sensor, the ultrasonic fingerprint recognition sensor includes a piezoelectric film layer, the piezoelectric film layer is located between the light-emitting unit and the drive circuit and extends across the For each pixel unit, the light emitting unit is configured to penetrate the piezoelectric film layer and is electrically connected to the driving circuit.
  • the ultrasonic fingerprint recognition sensor further includes a driving electrode and a receiving electrode, and the driving electrode is located on a side of the piezoelectric film layer away from the base substrate and configured to face the display substrate.
  • the display side sends out an ultrasonic signal
  • the receiving electrode is located on a side of the piezoelectric film layer close to the base substrate and is configured to receive the ultrasonic signal reflected by the fingerprint.
  • the ultrasonic fingerprint recognition sensor further includes an extraction electrode, and the extraction electrode and the receiving electrode are located on the same side of the piezoelectric film layer and configured to be electrically connected to the driving electrode.
  • the electrode penetrates the piezoelectric film layer and is electrically connected to the lead electrode.
  • the fingerprint identification device further includes a processing circuit located between the receiving electrode and the base substrate and electrically connected to the receiving electrode, and the processing circuit is configured to receive and Processing the electrical signal from the receiving electrode.
  • the light-emitting unit includes an anode, an organic light-emitting functional layer, and a cathode
  • the anode is located on a side of the piezoelectric film layer away from the base substrate
  • the organic light-emitting functional layer is located on the The side of the anode away from the base substrate
  • the cathode is located on the side of the organic light-emitting function layer away from the base substrate.
  • the anode and the drive electrode are both located on and in contact with the piezoelectric film layer, and the anode penetrates the piezoelectric film layer and is electrically connected to the drive circuit.
  • the driving circuit includes: a first active layer disposed on the base substrate; a first insulating layer covering the first active layer; and disposed on the first insulating layer A first gate electrode; a second insulating layer covering the first gate electrode; and a first drain electrode and a first source electrode provided on the second insulating layer, wherein the first drain electrode and the The first source electrodes are respectively electrically connected to the doped regions in the first active layer through via holes, and the anode of the light-emitting unit is configured to penetrate the piezoelectric film layer and is electrically connected to the first drain electrode.
  • the driving circuit further includes: a third insulating layer covering the first drain electrode and the first source electrode; a second connecting electrode disposed on the third insulating layer, the The second connection electrode is electrically connected to the first drain electrode through a via hole; a flat layer covering the second connection electrode; a first protective layer disposed on the flat layer; disposed on the first protective layer
  • the fourth connection electrode is electrically connected to the second connection electrode through a via hole, wherein the anode of the light-emitting unit is configured to penetrate the piezoelectric film layer and the fourth connection electrode Electric connection.
  • the fingerprint identification device further includes a processing circuit located between the receiving electrode and the base substrate and electrically connected to the receiving electrode, and the processing circuit is configured to receive and Processing the electrical signal from the receiving electrode.
  • the processing circuit includes: a second active layer disposed on the base substrate, the first insulating layer further covers the second active layer; Layer on the second gate electrode, the second insulating layer also covers the second gate electrode; and the second drain electrode, the first connection electrode and the second source electrode provided on the second insulating layer, so The second drain electrode and the second source electrode are respectively electrically connected to the doped region in the second active layer through via holes, and the first connection electrode is electrically connected to the second gate electrode through the via holes.
  • the three insulating layers also cover the second drain electrode, the first connection electrode, and the second source electrode, wherein the receiving electrode is disposed on the third insulating layer, and the receiving electrode is connected to the third insulating layer through a via hole.
  • the first connecting electrode is electrically connected.
  • the processing circuit further includes: a third connection electrode disposed on the third insulating layer, the third connection electrode is electrically connected to the first connection electrode through a via hole, and the flat The layer also covers the third connecting electrode; the receiving electrode provided on the first protective layer, the receiving electrode is electrically connected to the third connecting electrode through a via hole.
  • a display device including the above-mentioned display substrate for ultrasonic fingerprint recognition.
  • the display device includes an organic light emitting diode display device.
  • a manufacturing method of a display substrate for ultrasonic fingerprint recognition including:
  • the base substrate including a plurality of pixel regions
  • the driving circuit Forming a driving circuit on a side of the light emitting unit in each of the pixel regions close to the base substrate, the driving circuit being configured to be electrically connected to the light emitting unit;
  • a piezoelectric thin film layer is formed between the light emitting unit and the driving circuit in each pixel area, the piezoelectric thin film layer extends across each pixel unit, and the light emitting unit is configured to penetrate through the The piezoelectric film layer is electrically connected to the driving circuit.
  • FIG. 1 is a plan view of a display substrate according to an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of the structure of a display substrate according to an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of the structure of the display substrate of the embodiment of the disclosure after an active layer pattern is formed on the base substrate;
  • FIG. 4 is a schematic diagram of the structure after forming the first gate electrode pattern in the display substrate of the embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a structure after forming a second gate electrode pattern in the display substrate of an embodiment of the disclosure
  • FIG. 6 is a schematic diagram of the structure after forming source and drain electrode patterns in the display substrate of the embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of the structure after forming connection electrodes in the display substrate of the embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a structure after receiving electrodes are formed in a display substrate according to an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a structure after forming a piezoelectric thin film layer in a display substrate according to an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a structure after forming driving electrodes and anodes in the display substrate of the embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of a structure after forming a pixel definition layer in a display substrate according to an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of a structure after forming a light-emitting layer and a cathode in a display substrate according to another embodiment of the disclosure.
  • FIG. 13 is a schematic diagram of a structure after forming a first gate electrode pattern in a display substrate according to another embodiment of the disclosure.
  • FIG. 14 is a schematic diagram of a structure after forming a second gate electrode pattern in a display substrate according to still another embodiment of the disclosure.
  • FIG. 15 is a flowchart of a manufacturing method of a display substrate according to an embodiment of the disclosure.
  • Ultrasonic waves have the ability to penetrate materials and generate echoes of different sizes depending on the material. That is, when ultrasonic waves reach the surface of different materials, the reflected ultrasonic energy and the distance traveled are different, and fingerprint identification is performed accordingly. Therefore, the ultrasonic fingerprint recognition technology uses the difference in acoustic impedance between the skin and the air to distinguish the location of the fingerprint ridges and valleys, so as to conduct a deeper analysis and sampling of the fingerprints, and even penetrate under the skin surface to identify the unique three-dimensional fingerprints. feature. Compared with capacitive fingerprint recognition devices, ultrasonic fingerprint recognition performance is better, for example, it has the advantages of waterproof and sweat proof and high recognition accuracy.
  • the ultrasonic fingerprint identification device of this structure can only be installed on the cover of the display substrate in a bonding manner. It not only belongs to the way of attaching outside the display screen, but also can only realize the non-display area button fingerprint recognition function.
  • the embodiments of the present disclosure provide a display substrate for ultrasonic fingerprint recognition, a manufacturing method thereof, and a display device.
  • a display substrate for ultrasonic fingerprint recognition which includes a base substrate and a plurality of pixel units arranged on the base substrate.
  • Each of the pixel units includes a light-emitting device, and the light-emitting device includes a light-emitting unit and a driving circuit.
  • the driving circuit is arranged on a side of the light emitting unit close to the base substrate and is configured to be electrically connected to the light emitting unit.
  • Each pixel unit also includes a fingerprint recognition device.
  • the fingerprint identification device includes an ultrasonic fingerprint identification sensor, and the ultrasonic fingerprint identification sensor includes a piezoelectric film layer. The piezoelectric film layer is located between the light-emitting unit and the drive circuit and extends across each pixel unit, and the light-emitting unit is configured to penetrate the piezoelectric film layer and be electrically connected to the drive circuit.
  • the display substrate of the above-mentioned embodiment of the present disclosure covers the entire pixel unit with the piezoelectric film layer, which not only realizes the display device with embedded fingerprint recognition function, but also realizes the fingerprint recognition function in the display area.
  • FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure.
  • the display substrate includes a base substrate 10 and a plurality of pixel units 100 arranged on the base substrate 10 and arranged in an array.
  • Each pixel unit 100 includes a light emitting device 11 and a fingerprint recognition device 12, and the light emitting device 11 and the fingerprint recognition device 12 are formed on a base substrate 10.
  • the light emitting device 11 includes a light emitting unit 13 and a driving circuit 14.
  • the fingerprint identification device 12 includes an ultrasonic fingerprint identification sensor 15 for forming fingerprint electrical signals.
  • the ultrasonic fingerprint recognition sensor 15 includes a piezoelectric film layer 37 located between the light emitting unit 13 and the driving circuit 14 and extending across the pixel unit to cover the entire pixel unit 100.
  • the light-emitting unit 13 penetrates the piezoelectric film layer 37 and is electrically connected to the driving circuit 14.
  • the fingerprint function can be implemented in the display area, thereby solving the existing problems.
  • the display substrate can only realize problems such as non-display area key-press fingerprint recognition by using other methods. It can be seen that the piezoelectric film layer covers the entire pixel unit, which not only realizes the display device with embedded fingerprint recognition function, but also realizes the fingerprint recognition function in the display area.
  • the ultrasonic fingerprint recognition sensor 15 further includes a driving electrode 38 and a receiving electrode 34.
  • the driving electrode 38 is located on the side of the piezoelectric film layer 37 away from the base substrate 10 and is configured to emit an ultrasonic signal to the display side of the display substrate.
  • the receiving electrode 34 is located on the side of the piezoelectric film layer 37 close to the base substrate 10 and is configured to receive the ultrasonic signal reflected by the fingerprint located on the display side.
  • the receiving electrode 34 and the driving electrode 38 share the piezoelectric film layer 37, and the driving electrode 38 drives the piezoelectric film layer 37 to vibrate and emit an ultrasonic signal, which is emitted toward the display side of the display substrate.
  • the ultrasonic signal is reflected by the receiving electrode 34 after encountering the fingerprint.
  • the receiving electrode 34 receives the reflected ultrasonic signal, and then forms an electrical signal for identifying the fingerprint through the piezoelectric film layer 37.
  • the ultrasonic fingerprint recognition sensor 15 further includes a lead electrode 35 and a first cathode 43.
  • the lead electrode 35 is located under the piezoelectric film layer 37, and the first cathode 43 is formed on the driving electrode 38.
  • the first cathode 43 and the second cathode 42 described below are arranged in the same layer.
  • the first cathode 43 and the second cathode 42 are formed in the same film forming process.
  • the first cathode 43 and the second cathode 42 are spaced apart from each other so that the first cathode 43 and the second cathode 42 are insulated from each other.
  • the driving electrode 38 is formed on the piezoelectric film layer 37, and the driving electrode 38 penetrates the piezoelectric film layer 37 and is electrically connected to the lead electrode 35. There is no overlapping area between the orthographic projection of the lead electrode 35 on the base substrate 10 and the orthographic projection of the receiving electrode 34 on the base substrate 10, so that the lead electrode will not interfere with the pair of receiving electrodes 34 Reception of ultrasonic signals.
  • the light-emitting unit 13 includes an anode 39 formed on the piezoelectric thin film layer 37, a second cathode 42 formed on the anode 39 and formed on the organic light-emitting functional layer 41.
  • the anode 39 and the driving electrode 38 are in the same layer, that is, the anode 39 and the driving electrode 38 are both located on the piezoelectric film layer 37 and in contact with the piezoelectric film layer 37.
  • the anode 39 penetrates the piezoelectric film layer 37 and is electrically connected to the drive circuit 14.
  • the organic light emitting function layer 41 includes an organic light emitting layer, and may also include at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.
  • the fingerprint identification device further includes a processing circuit 16 located between the receiving electrode 34 and the base substrate 10 and electrically connected to the receiving electrode 34, and the processing circuit 16 is configured as The electrical signal from the receiving electrode 34 is received and processed.
  • the active layer of the display substrate is prepared by a complementary metal-oxide-semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process.
  • the driving circuit 14 includes a first thin film transistor
  • the processing circuit 16 includes a second thin film transistor.
  • the first thin film transistor is a P-type thin film transistor
  • the second thin film transistor is an N-type thin film transistor.
  • the first thin film transistor includes a first active layer 17, a first gate electrode 20, a first drain electrode 23, a first source electrode 24, a second connection electrode 29 and a fourth connection electrode 33.
  • the second thin film transistor includes a second active layer 18, a second gate electrode 21, a second drain electrode 25, a first connection electrode 26, a second source electrode 27, a third connection electrode 30, and a receiving electrode 34.
  • the driving circuit 14 includes a first active layer 17 disposed on the base substrate 10 and a first insulating layer 19 covering the first active layer 17.
  • the driving circuit further includes a first gate electrode 20 provided on the first insulating layer 19 and a second insulating layer 22 covering the first gate electrode 20.
  • the driving circuit further includes a first drain electrode 23 and a first source electrode 24 disposed on the second insulating layer 22.
  • the first drain electrode 23 and the first source electrode 24 are respectively electrically connected to the doped regions in the first active layer 17 through via holes.
  • the first active layer 17 includes a channel region and two heavily doped regions.
  • the anode 39 of the light emitting unit 13 is configured to penetrate the piezoelectric film layer 37 and is electrically connected to the first drain electrode 23.
  • the driving circuit 14 further includes: a third insulating layer 28 covering the first drain electrode 23 and the first source electrode 24; and The second connection electrode 29 on the third insulating layer 28.
  • the second connection electrode 29 is electrically connected to the first drain electrode 23 through a via hole.
  • the driving circuit further includes: a flat layer 31 covering the second connection electrode 29; a first protective layer 32 disposed on the flat layer 31; and a first protective layer 32 disposed on the first protective layer 32
  • the fourth connection electrode 33 is electrically connected to the second connection electrode 29 through a via hole.
  • the anode 39 of the light-emitting unit 13 is configured to penetrate through the piezoelectric film layer 37 and be electrically connected to the fourth connection electrode 33.
  • the processing circuit 16 includes a second active layer 18 disposed on the base substrate 10, and the first insulating layer 19 also covers the second active layer 18. .
  • the processing circuit further includes a second gate electrode 21 disposed on the first insulating layer 19, and the second insulating layer 22 also covers the second gate electrode 21.
  • the processing circuit further includes a second drain electrode 25, a first connection electrode 26, and a second source electrode 27 provided on the second insulating layer 22.
  • the second drain electrode 25 and the second source electrode 27 are electrically connected to the doped regions in the second active layer 18 through via holes, respectively.
  • the second active layer 18 includes a channel region, a lightly doped region, and a heavily doped region.
  • the two heavily doped regions are located on both sides of the channel region, and the lightly doped region is located in each heavily doped region.
  • the first connection electrode 26 is electrically connected to the second gate electrode 21 through a via hole
  • the third insulating layer 28 also covers the second drain electrode 25 and the first connection electrode. 26 and the second source electrode 27.
  • the receiving electrode 34 is disposed on the third insulating layer 28, and the receiving electrode 34 is electrically connected to the first connecting electrode 26 through a via hole.
  • the processing circuit 16 further includes: a third connecting electrode 30 disposed on the third insulating layer 28, and the third connecting electrode 30 is connected to the third insulating layer 28 through a via hole.
  • the first connection electrode 26 is electrically connected, and the flat layer 31 also covers the third connection electrode 30.
  • the processing circuit further includes the receiving electrode 34 disposed on the first protective layer 32, and the receiving electrode 34 is electrically connected to the third connecting electrode 30 through a via hole.
  • a barrier layer 101 may be further provided on the base substrate 10 to block impurities or water vapor from the base substrate. Both the light emitting device 11 and the fingerprint recognition device 12 are formed on the barrier layer 101.
  • the display substrate further includes an encapsulation layer 44 covering the second cathode 42 and the first cathode 43, for example, the encapsulation layer is a cover plate.
  • the material of the base substrate 10 includes an ultrasonic absorbing material.
  • the base substrate 10 can absorb the reverse sound waves emitted by the ultrasonic fingerprint recognition sensor 15, so that the ultrasonic fingerprint recognition sensor 15 does not need to be equipped with a special reverse ultrasonic wave.
  • the absorbing layer simplifies the manufacturing process of the ultrasonic fingerprint identification sensor 15.
  • the working principle of the ultrasonic fingerprint recognition sensor is: input AC voltage to the driving electrode 38, the piezoelectric film layer 37 of the fingerprint recognition sensor will generate ultrasonic waves under the inverse piezoelectric effect, and the ultrasonic waves are transmitted to the finger.
  • the ridges and valleys of the fingerprint of the finger reflect ultrasonic waves back to the piezoelectric film layer 37, and the piezoelectric film layer 37 generates fingerprint electrical signals under the positive piezoelectric effect.
  • the processing circuit 16 is connected to the fingerprint identification sensor, receives the fingerprint electrical signal from the fingerprint identification sensor, and processes the fingerprint electrical signal to identify the fingerprint.
  • a manufacturing method of a display substrate for ultrasonic fingerprint recognition including:
  • the base substrate including a plurality of pixel regions
  • a piezoelectric thin film layer is formed between the light emitting unit and the driving circuit in each pixel area, the piezoelectric thin film layer extends across each pixel unit, and the light emitting unit is configured to penetrate through the The piezoelectric film layer is electrically connected to the driving circuit.
  • the piezoelectric film layer covers the entire pixel unit, which not only realizes the display device with embedded fingerprint recognition function, but also realizes the fingerprint recognition function in the display area.
  • the "patterning process" in this embodiment includes the processes of depositing a film layer, coating photoresist, mask exposure, developing, etching, stripping the photoresist, etc.
  • the method of forming a thin film includes but not It is limited to conventional film-making processes such as evaporation, deposition, coating, and coating.
  • a method for preparing a display substrate includes:
  • Forming the base substrate and the active layer pattern includes: first coating a layer of flexible material on the glass carrier, curing it into a film to form the base substrate 10; then depositing a layer of barrier film on the base substrate 10 to form a covering The barrier layer 101 of the base substrate 10 is patterned. Then, a polysilicon film is formed on the barrier layer 101, and the polysilicon film is patterned through a patterning process to form two active layer patterns disposed on the barrier layer 101. Finally, the two active layer patterns are respectively subjected to ion implantation treatment of PMOS threshold voltage adjustment and NMOS threshold voltage adjustment to form the first active layer 17 and the second active layer 18, as shown in FIG. 3.
  • Forming the first gate electrode pattern includes: sequentially depositing a first insulating film and a first metal film on the base substrate 10 on which the aforementioned pattern is formed, thereby forming a pattern covering the first active layer 17 and the second active layer 18 The first insulating layer 19; however, the first metal film is patterned by a patterning process to form a first gate electrode 20 disposed on the first insulating layer 19, and the first gate electrode 20 is located above the first active layer 17.
  • the first active layer 17 is heavily doped with PMOS ion implantation, so that the first active layer 17 includes a channel region and two heavily doped regions, where the channel region corresponds to In the first gate electrode 20, heavily doped regions are formed on both sides of the central region.
  • the second active layer 18 is shielded and protected by the first metal thin film pattern provided on the first insulating layer 19, as shown in FIG. 4.
  • Forming the second gate electrode pattern includes: patterning the first metal thin film disposed above the second active layer 18 through a patterning process on the base substrate 10 on which the aforementioned pattern is formed, to form a first insulating layer 19
  • Two second gate electrodes 21 are located above the second active layer 18. Then, using the two second gate electrodes 21 as shields, the second active layer 18 is implanted with lightly doped NMOS and heavily doped NMOS, so that the second active layer 18 includes the channel region and two located in the channel region. Two lightly doped regions and two heavily doped regions on the side, the channel region corresponds to each second gate electrode 21, and the lightly doped region is located between the heavily doped region and the channel region, as shown in FIG. 5.
  • Forming the source and drain electrode patterns includes: depositing a second insulating film on the first gate electrode 20 and the second gate electrode 21 on the base substrate 10 on which the aforementioned pattern is formed, so as to cover the first gate electrode 20 and the second gate electrode 21 In the second insulating layer 22, the first via holes exposing the heavily doped regions on both sides of the first active layer 17 are sequentially opened in the second insulating layer 22 through a patterning process, and the heavy on both sides of the second active layer 18 is exposed. The second via hole in the doped region and the third via hole exposing one of the second gate electrodes 21.
  • a second metal film is deposited on the base substrate with the aforementioned pattern, and the second metal film is patterned through a patterning process to form a first drain electrode 23, a first source electrode 24, and a second insulating layer 22.
  • the two drain electrodes 25, the first connection electrode 26 and the second source electrode 27, the first drain electrode 23 and the first source electrode 24 are respectively connected to the heavily doped regions on both sides of the first active layer 17 through first via holes,
  • the second drain electrode 25 and the second source electrode 27 are respectively connected to the heavily doped regions on both sides of the second active layer 18 through the second via hole, and the first connection electrode 26 is connected to the second gate electrode 21 through the third via hole.
  • One of the gate electrodes is connected as shown in Figure 6.
  • Forming the connection electrode pattern includes: depositing a third insulating film on the base substrate 10 formed with the aforementioned pattern to cover the first drain electrode 23, the first source electrode 24, the second drain electrode 25, the first connection electrode 26, and the second drain electrode.
  • a fourth via hole exposing the first drain electrode 23 and a fifth via hole exposing the first connection electrode 26 are formed on the third insulating layer 28 through a patterning process.
  • a third metal film is deposited on the base substrate with the aforementioned pattern, and the third metal film is patterned through a patterning process to form the second connection electrode 29 and the third connection electrode 30 on the third insulating layer 28.
  • the second connection electrode 29 is connected to the first drain electrode 23 through the fourth via hole
  • the third connection electrode 30 is connected to the first connection electrode 26 through the fifth via hole, as shown in FIG. 7.
  • Forming the receiving electrode pattern includes: coating a flat film on the base substrate forming the aforementioned pattern, and then depositing a first protective film to form a flat layer 31 covering the second connection electrode 29 and the third connection electrode 30, and setting The first protective layer 32 on the flat layer 31. Then, a sixth via hole exposing the second connection electrode 29 and a seventh via hole exposing the third connection electrode 30 are opened on the first protection layer 32 and the flat layer 31 through a patterning process.
  • a fourth metal film is deposited on the base substrate with the aforementioned pattern, and the fourth metal film is patterned through a patterning process to form a fourth connection electrode 33, a receiving electrode 34, and a lead electrode 35 on the first protective layer 32
  • the fourth connection electrode 33 is connected to the second connection electrode 29 through the sixth via hole
  • the receiving electrode 34 is connected to the third connection electrode 30 through the seventh via hole.
  • the first active layer 17, the first gate electrode 20, the first drain electrode 23, the first source electrode 24, the second connection electrode 29, and the fourth connection electrode 33 form a first thin film transistor.
  • the second active layer 18, the second gate electrode 21, the second drain electrode 25, the first connection electrode 26, the second source electrode 27, the third connection electrode 30 and the receiving electrode 34 form a second thin film transistor, as shown in FIG. Show.
  • Forming the piezoelectric thin film layer includes: forming a second protective layer 36 covering the fourth connecting electrode 33, the receiving electrode 34 and the lead electrode 35 on the base substrate 10 formed with the aforementioned pattern, and forming a covering on the second protective layer 36
  • the piezoelectric film layer 37 of the second protective layer 36 is then opened on the piezoelectric film layer 37 and the second protective layer 36 through a patterning process to open an eighth via hole exposing the fourth connection electrode 33 and an eighth via hole exposing the lead electrode 35
  • the ninth via is shown in Figure 9.
  • Forming driving electrodes and anode patterns includes: depositing a fifth metal film on the base substrate 10 where the aforementioned pattern is formed, patterning the fifth metal film through a patterning process, and forming a driving electrode 38 on the piezoelectric film layer 37. Subsequently, a sixth metal film is deposited, and the sixth metal film is patterned through a patterning process to form an anode 39. The anode 39 is connected to the fourth connecting electrode 33 through the eighth via hole, and the driving electrode 38 is connected to the lead electrode 35 through the ninth via hole. , As shown in Figure 10.
  • Forming the pixel defining layer includes: forming a pixel defining layer 40 exposing the anode 39 and the driving electrode 38 on the base substrate 10 formed with the aforementioned pattern, as shown in FIG. 11.
  • Forming the organic light-emitting layer and the cathode includes: forming an organic light-emitting functional layer 41 in the opening of the pixel defining layer 40 on the base substrate 10 formed with the aforementioned pattern, the organic light-emitting functional layer 41 is connected to the anode 39, and then forming a driving electrode
  • the first cathode 43 connected to 38 forms a second cathode 42 connected to the organic light-emitting functional layer 41.
  • the anode 39, the pixel definition layer 40, the organic light emitting function layer 41 and the second cathode 42 form the light emitting unit 13;
  • the receiving electrode 34, the piezoelectric film layer 37, the driving electrode 38 and the first cathode 43 form the ultrasonic fingerprint recognition sensor 15, as shown in the figure 12 shown.
  • the anode 39 and the driving electrode 38 are in the same layer, the anode 39 penetrates the piezoelectric film layer 37 and is connected to the fourth connection electrode 33; the driving electrode 38 penetrates the piezoelectric film layer 37 and is connected to the extraction electrode 35.
  • Forming the encapsulation layer includes: forming the encapsulation layer 44 on the second cathode 42 and the first cathode 43.
  • the driving electrode 38 and the receiving electrode 35 in the fingerprint recognition sensor 15 are respectively driven by separate IC chips.
  • the light-emitting device is driven by GOA and driven by a separate IC chip.
  • the IC chip of the fingerprint identification device and the IC chip of the light-emitting device are independent IC chips.
  • this embodiment not only realizes the OLED display device with embedded fingerprint identification function, but also realizes the fingerprint identification function in the display area.
  • the manufacturing method of this embodiment can be realized by using existing mature manufacturing equipment, has little improvement to the existing process, and is well compatible with the existing manufacturing process, so it has low manufacturing cost, easy process realization, and production efficiency. High and good product rate, etc., have good application prospects.
  • FIG. 13 is a schematic structural diagram of another display substrate according to an embodiment of the disclosure.
  • the active layer of each thin film transistor in the display substrate uses N-channel metal-oxide-semiconductor (Negative Channel Metal Oxide Semiconductor, NMOS).
  • NMOS N-channel metal-oxide-semiconductor
  • the display substrate of this embodiment includes a base substrate 210, and a light-emitting device 211 and a fingerprint identification device 212 formed on the base substrate 210.
  • the display substrate shown in FIG. 13 is basically the same as the display substrate of FIG. 2 described above. The difference is that when the first gate electrode pattern is formed on the display substrate of FIG. 3, the first gate electrode 220 is used as a shield for the first active
  • the layer 217 is lightly doped NMOS and heavily doped NMOS ion implantation, so that the first active layer 217 includes a channel region, an N-type lightly doped region, and an N-type heavily doped region.
  • the N-type lightly doped region is located in the N-type region. Between the heavily doped region and the channel region.
  • FIG. 14 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.
  • the active layer of each thin film transistor of the display substrate uses P-channel metal-oxide-semiconductor (Positive Channel Metal Oxide Semiconductor, PMOS).
  • PMOS P-channel metal-oxide-semiconductor
  • the display substrate of this embodiment includes a base substrate 310, and a light-emitting device 311 and a fingerprint identification device 312 on the base substrate 310.
  • the display substrate of FIG. 14 is basically the same as the display substrate of FIG. 2, except that when the second gate electrode pattern is formed on the display substrate of FIG. 14, two second gate electrodes 321 are used as shields to protect the second active layer. 318 performs heavily doped PMOS ion implantation, so that the second active layer 318 includes a heavily doped P-type region.
  • a display device including the display substrate of any of the above embodiments is also provided.
  • the display device is, for example, an organic light emitting diode display device.

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Abstract

A display substrate for ultrasonic fingerprint recognition, a manufacturing method therefor, and a display device. The display substrate comprises a base substrate (10) and a plurality of pixel units; each of the pixel units comprises a light-emitting device (11), the light-emitting device (11) comprising a light-emitting unit (13) and a drive circuit (14), the drive circuit (14) being configured to be electrically connected to the light-emitting unit (13); and each of the pixel units further comprises a fingerprint recognition device (12). The fingerprint recognition device (12) comprises an ultrasonic fingerprint recognition sensor (15), the ultrasonic fingerprint recognition sensor (15) comprises a piezoelectric thin film layer (37), the piezoelectric film layer (37) is located between the light-emitting unit (13) and the drive circuit (14) and extends across each pixel unit, the light-emitting unit (13) is configured to penetrate through the piezoelectric thin film layer (37) and to be electrically connected to the drive circuit (14). Said display substrate enables the piezoelectric thin film layer (37) to cover the whole pixel unit, thereby realizing a fingerprint recognition function in a display area.

Description

用于超声波指纹识别的显示基板及其制造方法和显示装置Display substrate for ultrasonic fingerprint identification, manufacturing method thereof and display device
相关申请的交叉引用Cross references to related applications
本申请基于并且要求于2019年5月24日递交、名称为“显示基板及其制备方法”的中国专利申请第201910437896.2号的优先权,在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。This application is based on and claims the priority of the Chinese patent application No. 201910437896.2 filed on May 24, 2019, titled "Display Substrate and Its Preparation Method", and the contents of the above Chinese patent application are quoted here in full as this application a part of.
技术领域Technical field
本公开实施例涉及一种用于超声波指纹识别的显示基板及其制造方法和显示装置。The embodiments of the present disclosure relate to a display substrate for ultrasonic fingerprint recognition, a manufacturing method thereof, and a display device.
背景技术Background technique
有机发光二极管显示装置(Organic Light Emitting Diode,OLED)是未来显示产品的发展趋势,具有视角宽、响应速度快、亮度高、对比度高、色彩鲜艳、重量轻、厚度薄、功耗低等一系列优点。目前,有机发光二极管显示装置已经开始应用于手机屏幕。Organic Light Emitting Diode (OLED) is the development trend of future display products, featuring wide viewing angles, fast response speed, high brightness, high contrast, bright colors, light weight, thin thickness, low power consumption, etc. advantage. Currently, organic light emitting diode display devices have begun to be applied to mobile phone screens.
目前的超声波指纹识别器件,一种是以硅晶圆为衬底的半导体工艺制程制备,另一种是以玻璃为衬底的低温多晶硅工艺制程制备。The current ultrasonic fingerprint recognition device is prepared by a semiconductor process with a silicon wafer as a substrate, and the other is prepared by a low-temperature polysilicon process with a glass as a substrate.
发明内容Summary of the invention
本公开实施例提供一种用于超声波指纹识别的显示基板及其制造方法和显示装置,以解决现有显示基板只能以外贴合方式实现非显示区按键式指纹识别等问题。The embodiments of the present disclosure provide a display substrate for ultrasonic fingerprint identification, a manufacturing method thereof, and a display device, so as to solve the problem that the existing display substrate can only realize non-display area key-press fingerprint identification by external bonding.
根据本公开的第一方面,提供一种用于超声波指纹识别的显示基板,包括衬底基板以及设置在所述衬底基板上的多个像素单元,每个所述像素单元包括:According to a first aspect of the present disclosure, there is provided a display substrate for ultrasonic fingerprint recognition, including a base substrate and a plurality of pixel units arranged on the base substrate, each of the pixel units including:
发光装置,所述发光装置包括:Light emitting device, the light emitting device includes:
发光单元;Light-emitting unit
驱动电路,设置在所述发光单元的靠近所述衬底基板的一侧并且配置为与所述发光单元电连接;A driving circuit, which is arranged on a side of the light-emitting unit close to the base substrate and configured to be electrically connected to the light-emitting unit;
指纹识别装置,所述指纹识别装置包括超声波指纹识别传感器,所述超声波指纹识别传感器包括压电薄膜层,所述压电薄膜层位于所述发光单元和所述驱动电路之间并且延伸跨过该每个像素单元,所述发光单元配置为贯穿所述压电薄膜层并且与所述驱动电路电连接。A fingerprint recognition device, the fingerprint recognition device includes an ultrasonic fingerprint recognition sensor, the ultrasonic fingerprint recognition sensor includes a piezoelectric film layer, the piezoelectric film layer is located between the light-emitting unit and the drive circuit and extends across the For each pixel unit, the light emitting unit is configured to penetrate the piezoelectric film layer and is electrically connected to the driving circuit.
至少一些实施例中,所述超声波指纹识别传感器还包括驱动电极和接收电极,所述驱动电极位于所述压电薄膜层的远离所述衬底基板的一侧并且配置为向所述显示基板的显示侧发出超声波信号,所述接收电极位于所述压电薄膜层的靠近所述衬底基板的一侧并且配置为接收被指纹反射回来的超声波信号。In at least some embodiments, the ultrasonic fingerprint recognition sensor further includes a driving electrode and a receiving electrode, and the driving electrode is located on a side of the piezoelectric film layer away from the base substrate and configured to face the display substrate. The display side sends out an ultrasonic signal, and the receiving electrode is located on a side of the piezoelectric film layer close to the base substrate and is configured to receive the ultrasonic signal reflected by the fingerprint.
至少一些实施例中,所述超声波指纹识别传感器还包括引出电极,所述引出电极和所述接收电极位于所述压电薄膜层的同一侧并且配置为与所述驱动电极电连接,所述驱动电极贯穿所述压电薄膜层与所述引出电极电连接。In at least some embodiments, the ultrasonic fingerprint recognition sensor further includes an extraction electrode, and the extraction electrode and the receiving electrode are located on the same side of the piezoelectric film layer and configured to be electrically connected to the driving electrode. The electrode penetrates the piezoelectric film layer and is electrically connected to the lead electrode.
至少一些实施例中,所述引出电极在所述衬底基板上的正投影与所述接收电极在所述衬底基板上的正投影之间没有重叠区域。In at least some embodiments, there is no overlap area between the orthographic projection of the extraction electrode on the base substrate and the orthographic projection of the receiving electrode on the base substrate.
至少一些实施例中,所述指纹识别装置还包括处理电路,所述处理电路位于所述接收电极与所述衬底基板之间并且与所述接收电极电连接,所述处理电路配置为接收并且处理来自所述接收电极的电信号。In at least some embodiments, the fingerprint identification device further includes a processing circuit located between the receiving electrode and the base substrate and electrically connected to the receiving electrode, and the processing circuit is configured to receive and Processing the electrical signal from the receiving electrode.
至少一些实施例中,所述发光单元包括阳极、有机发光功能层和阴极,所述阳极位于所述压电薄膜层的远离所述衬底基板的一侧,所述有机发光功能层位于所述阳极的远离所述衬底基板的一侧,所述阴极位于所述有机发光功能层的远离所述衬底基板的一侧。In at least some embodiments, the light-emitting unit includes an anode, an organic light-emitting functional layer, and a cathode, the anode is located on a side of the piezoelectric film layer away from the base substrate, and the organic light-emitting functional layer is located on the The side of the anode away from the base substrate, and the cathode is located on the side of the organic light-emitting function layer away from the base substrate.
至少一些实施例中,所述阳极与所述驱动电极均位于所述压电薄膜层上且与该压电薄膜层接触,所述阳极贯穿所述压电薄膜层与所述驱动电路电连接。In at least some embodiments, the anode and the drive electrode are both located on and in contact with the piezoelectric film layer, and the anode penetrates the piezoelectric film layer and is electrically connected to the drive circuit.
至少一些实施例中,所述驱动电路包括:设置在所述衬底基板上的第一有源层;覆盖所述第一有源层的第一绝缘层;设置在所述第一绝缘层上的第一栅电极;覆盖所述第一栅电极的第二绝缘层;和设置在所述第二绝缘层上的第一漏电极和第一源电极,其中所述第一漏电极和所述第一源电极分别通过过孔与所述第一有源层内的掺杂区电连接,所述发光单元的阳极配置为贯穿所述压电薄膜层并且与所述第一漏电极电连接。In at least some embodiments, the driving circuit includes: a first active layer disposed on the base substrate; a first insulating layer covering the first active layer; and disposed on the first insulating layer A first gate electrode; a second insulating layer covering the first gate electrode; and a first drain electrode and a first source electrode provided on the second insulating layer, wherein the first drain electrode and the The first source electrodes are respectively electrically connected to the doped regions in the first active layer through via holes, and the anode of the light-emitting unit is configured to penetrate the piezoelectric film layer and is electrically connected to the first drain electrode.
至少一些实施例中,所述驱动电路还包括:覆盖所述第一漏电极和所述第一源电极的第三绝缘层;设置在所述第三绝缘层上的第二连接电极,所述第二连接电极通过过孔与所述第一漏电极电连接;覆盖所述第二连接电极的平坦层;设置在所述平坦层上的第一保护层;设置在所述第一保护层上的第四连接电极,所述第四连接电极通过过孔与所述第二连接电极电连接,其中所述发光单元的所述阳极配置为贯穿所述压电薄膜层与所述第四连接电极电连接。In at least some embodiments, the driving circuit further includes: a third insulating layer covering the first drain electrode and the first source electrode; a second connecting electrode disposed on the third insulating layer, the The second connection electrode is electrically connected to the first drain electrode through a via hole; a flat layer covering the second connection electrode; a first protective layer disposed on the flat layer; disposed on the first protective layer The fourth connection electrode is electrically connected to the second connection electrode through a via hole, wherein the anode of the light-emitting unit is configured to penetrate the piezoelectric film layer and the fourth connection electrode Electric connection.
至少一些实施例中,所述指纹识别装置还包括处理电路,所述处理电路位于所述接收电极与所述衬底基板之间并且与所述接收电极电连接,所述处理电路配置为接收并且处理来自所述接收电极的电信号。In at least some embodiments, the fingerprint identification device further includes a processing circuit located between the receiving electrode and the base substrate and electrically connected to the receiving electrode, and the processing circuit is configured to receive and Processing the electrical signal from the receiving electrode.
至少一些实施例中,所述处理电路包括:设置在所述衬底基板上的第二有源层,所述第一绝缘层还覆盖所述第二有源层;设置在所述第一绝缘层上的第二栅电极,所述第二绝缘层还覆盖所述第二栅电极;和设置在所述第二绝缘层上的第二漏电极、第一连接电极和第二源电极,所述第二漏电极和所述第二源电极分别通过过孔与第二有源层内的掺杂区电连接,所述第一连接电极通过过孔与第二栅电极电连接,所述第三绝缘层还覆盖所述第二漏电极、所述第一连接电极和所述第二源电极,其中,所述接收电极设置在所述第三绝缘层上,所述接收电极通过过孔与所述第一连接电极电连接。In at least some embodiments, the processing circuit includes: a second active layer disposed on the base substrate, the first insulating layer further covers the second active layer; Layer on the second gate electrode, the second insulating layer also covers the second gate electrode; and the second drain electrode, the first connection electrode and the second source electrode provided on the second insulating layer, so The second drain electrode and the second source electrode are respectively electrically connected to the doped region in the second active layer through via holes, and the first connection electrode is electrically connected to the second gate electrode through the via holes. The three insulating layers also cover the second drain electrode, the first connection electrode, and the second source electrode, wherein the receiving electrode is disposed on the third insulating layer, and the receiving electrode is connected to the third insulating layer through a via hole. The first connecting electrode is electrically connected.
至少一些实施例中,所述处理电路还包括:设置在所述第三绝缘层上的第三连接电极,所述第三连接电极通过过孔与所述第一连接电极电连接,所述平坦层还覆盖所述第三连接电极;设置在所述第一保护层上的所述接收电极,所述接收电极通过过孔与所述第三连接电极电连接。In at least some embodiments, the processing circuit further includes: a third connection electrode disposed on the third insulating layer, the third connection electrode is electrically connected to the first connection electrode through a via hole, and the flat The layer also covers the third connecting electrode; the receiving electrode provided on the first protective layer, the receiving electrode is electrically connected to the third connecting electrode through a via hole.
至少一些实施例中,所述衬底基板的材料包括超声波吸收材料。In at least some embodiments, the material of the base substrate includes an ultrasonic absorbing material.
根据本公开的第二方面,提供一种显示装置,包括上述的用于超声波指纹识别的显示基板。According to a second aspect of the present disclosure, there is provided a display device including the above-mentioned display substrate for ultrasonic fingerprint recognition.
至少一些实施例中,所述显示装置包括有机发光二极管显示装置。In at least some embodiments, the display device includes an organic light emitting diode display device.
根据本公开的第三方面,提供一种用于超声波指纹识别的显示基板的制造方法,包括:According to a third aspect of the present disclosure, there is provided a manufacturing method of a display substrate for ultrasonic fingerprint recognition, including:
提供衬底基板,所述衬底基板包括多个像素区;Providing a base substrate, the base substrate including a plurality of pixel regions;
在每个所述像素区中形成发光单元;Forming a light emitting unit in each of the pixel regions;
在每个所述像素区中的所述发光单元的靠近所述衬底基板的一侧形成驱动电路,所述驱动电路配置为与所述发光单元电连接;以及Forming a driving circuit on a side of the light emitting unit in each of the pixel regions close to the base substrate, the driving circuit being configured to be electrically connected to the light emitting unit; and
在每个所述像素区中的所述发光单元和所述驱动电路之间形成压电薄膜层,所述压电薄膜层延伸跨过该每个像素单元,所述发光单元配置为贯穿所述压电薄膜层并且与所述驱动电路电连接。A piezoelectric thin film layer is formed between the light emitting unit and the driving circuit in each pixel area, the piezoelectric thin film layer extends across each pixel unit, and the light emitting unit is configured to penetrate through the The piezoelectric film layer is electrically connected to the driving circuit.
附图说明Description of the drawings
为了更清楚地说明本公开实施例的技术方案,下面将对实施例的附图作简单地介绍,显而易见地,下面描述中的附图仅仅涉及本公开的一些实施例,而非对本公开的限制。In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .
图1为本公开实施例显示基板的平面图;FIG. 1 is a plan view of a display substrate according to an embodiment of the disclosure;
图2为本公开实施例的显示基板的结构示意图;2 is a schematic diagram of the structure of a display substrate according to an embodiment of the disclosure;
图3为本公开实施例的显示基板中在衬底基板上形成有源层图案后的结构示意图;3 is a schematic diagram of the structure of the display substrate of the embodiment of the disclosure after an active layer pattern is formed on the base substrate;
图4为本公开实施例的显示基板中形成第一栅电极图案后的结构示意图;4 is a schematic diagram of the structure after forming the first gate electrode pattern in the display substrate of the embodiment of the disclosure;
图5为本公开实施例的显示基板中形成第二栅电极图案后的结构示意图;FIG. 5 is a schematic diagram of a structure after forming a second gate electrode pattern in the display substrate of an embodiment of the disclosure;
图6为本公开实施例的显示基板中形成源漏电极图案后的结构示意图;6 is a schematic diagram of the structure after forming source and drain electrode patterns in the display substrate of the embodiment of the disclosure;
图7为本公开实施例的显示基板中形成连接电极后的结构示意图;FIG. 7 is a schematic diagram of the structure after forming connection electrodes in the display substrate of the embodiment of the disclosure; FIG.
图8为本公开实施例的显示基板中形成接收电极后的结构示意图;FIG. 8 is a schematic diagram of a structure after receiving electrodes are formed in a display substrate according to an embodiment of the disclosure; FIG.
图9为本公开实施例的显示基板中形成压电薄膜层后的结构示意图;FIG. 9 is a schematic diagram of a structure after forming a piezoelectric thin film layer in a display substrate according to an embodiment of the disclosure;
图10为本公开实施例的显示基板中形成驱动电极和阳极后的结构示意图;FIG. 10 is a schematic diagram of a structure after forming driving electrodes and anodes in the display substrate of the embodiment of the disclosure;
图11为本公开实施例的显示基板中形成像素定义层后的结构示意图;FIG. 11 is a schematic diagram of a structure after forming a pixel definition layer in a display substrate according to an embodiment of the disclosure;
图12为本公开另一实施例的显示基板中形成发光层和阴极后的结构示意图;12 is a schematic diagram of a structure after forming a light-emitting layer and a cathode in a display substrate according to another embodiment of the disclosure;
图13为本公开另一实施例的显示基板中形成第一栅电极图案后的结构示意图;FIG. 13 is a schematic diagram of a structure after forming a first gate electrode pattern in a display substrate according to another embodiment of the disclosure;
图14为本公开再一实施例的显示基板中形成第二栅电极图案后的结构示意图;FIG. 14 is a schematic diagram of a structure after forming a second gate electrode pattern in a display substrate according to still another embodiment of the disclosure;
图15为本公开实施例的显示基板的制造方法的流程图。FIG. 15 is a flowchart of a manufacturing method of a display substrate according to an embodiment of the disclosure.
具体实施方式Detailed ways
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.
除非另作定义,此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同,并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。Unless otherwise defined, the technical terms or scientific terms used herein shall be the ordinary meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the specification and claims of the patent application of this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. "Include" or "include" and other similar words mean that the elements or items before "include" or "include" now cover the elements or items listed after "include" or "include" and their equivalents, and do not exclude others Components or objects. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to indicate the relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.
超声波具有穿透材料的能力,且随材料的不同产生大小不同的回波。也就是,超声波到达不同材质表面时,被反射回的超声波能量及历经的路程不同,据此来进行指纹识别。因此,超声波指纹识别技术利用皮肤与空气对于声波阻抗的差异,可以区分指纹脊与谷所在的位置,从而对指纹进行更深入的分析采样,甚至能渗透到皮肤表面之下识别出指纹独特的三维特征。相比电容式指纹识别器件,超声波指纹识别性能更优,例如具有防水防汗、识别精度高等优点。Ultrasonic waves have the ability to penetrate materials and generate echoes of different sizes depending on the material. That is, when ultrasonic waves reach the surface of different materials, the reflected ultrasonic energy and the distance traveled are different, and fingerprint identification is performed accordingly. Therefore, the ultrasonic fingerprint recognition technology uses the difference in acoustic impedance between the skin and the air to distinguish the location of the fingerprint ridges and valleys, so as to conduct a deeper analysis and sampling of the fingerprints, and even penetrate under the skin surface to identify the unique three-dimensional fingerprints. feature. Compared with capacitive fingerprint recognition devices, ultrasonic fingerprint recognition performance is better, for example, it has the advantages of waterproof and sweat proof and high recognition accuracy.
目前的超声波指纹识别器件有两种制备方法,一种是以硅晶圆为衬底利用半导体工艺制程制备,另一种是以玻璃为衬底利用低温多晶硅工艺制程制备。但上述两种指纹识别器件存在以下问题:由于器件尺寸小,厚度大,具有刚性衬底基板,因此该结构形式的超声波指纹识别器件只能以贴合的方式设置在显示基板的盖板上,不仅属于显示屏外贴合方式,而且仅能够实现非显示区按键式指纹识别功能。There are currently two preparation methods for ultrasonic fingerprint recognition devices, one is prepared by using a silicon wafer as a substrate using a semiconductor process, and the other is prepared by using a glass as a substrate using a low-temperature polysilicon process. However, the above two types of fingerprint identification devices have the following problems: due to their small size, large thickness, and rigid substrate, the ultrasonic fingerprint identification device of this structure can only be installed on the cover of the display substrate in a bonding manner. It not only belongs to the way of attaching outside the display screen, but also can only realize the non-display area button fingerprint recognition function.
本公开实施例提供一种用于超声波指纹识别的显示基板及其制造方法和显示装置。The embodiments of the present disclosure provide a display substrate for ultrasonic fingerprint recognition, a manufacturing method thereof, and a display device.
根据本公开实施例,提供一种用于超声波指纹识别的显示基板,包括衬底基板以及设置在所述衬底基板上的多个像素单元。每个所述像素单元包括:发光装置,所述发光装置包括发光单元和驱动电路。驱动电路设置在所述发光单元的靠近所述衬底基板的一侧并且配置为与所述发光单元电连接。每个像素单元还包括指纹识别装置。所述指纹识别装置包括超声波指纹识别传感器,所述超声波指纹识别传感器包括压电薄膜层。所述压电薄膜层位于所述发光单元和所述驱动电路之间并且延伸跨过该每个像素单元,所述发光单元配置为贯穿所述压电薄膜层并且与所述驱动电路电连接。According to an embodiment of the present disclosure, a display substrate for ultrasonic fingerprint recognition is provided, which includes a base substrate and a plurality of pixel units arranged on the base substrate. Each of the pixel units includes a light-emitting device, and the light-emitting device includes a light-emitting unit and a driving circuit. The driving circuit is arranged on a side of the light emitting unit close to the base substrate and is configured to be electrically connected to the light emitting unit. Each pixel unit also includes a fingerprint recognition device. The fingerprint identification device includes an ultrasonic fingerprint identification sensor, and the ultrasonic fingerprint identification sensor includes a piezoelectric film layer. The piezoelectric film layer is located between the light-emitting unit and the drive circuit and extends across each pixel unit, and the light-emitting unit is configured to penetrate the piezoelectric film layer and be electrically connected to the drive circuit.
本公开上述实施例的显示基板将压电薄膜层覆盖整个像素单元,不仅实现了在嵌入指纹识别功能的显示装置,而且实现了在显示区的指纹识别功能。The display substrate of the above-mentioned embodiment of the present disclosure covers the entire pixel unit with the piezoelectric film layer, which not only realizes the display device with embedded fingerprint recognition function, but also realizes the fingerprint recognition function in the display area.
图1为本公开实施例显示基板的结构示意图;图2为本公开实施例的显示基板的结构示意图。如图1和图2所示,显示基板包括衬底基板10以及设置在衬底基板10上、阵列排布的多个像素单元100。每个像素单元100包括发光装置11和指纹识别装置12,发光装置11和指纹识别装置12形成在衬底基板10上。发光装置11包括发光单元13和驱动电路14。指纹识别装置12包括用于形成指纹电信号的超声波指纹识别传感器15。超声波指纹识别传感器15包括压电薄膜层37,压电薄膜层37位于发光单元13和驱动电路14之间,并延伸跨过像素单元从而覆盖整个像素单元100。发光单元13贯穿压电薄膜层37并且与驱动电路14电连接。FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure; FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure. As shown in FIGS. 1 and 2, the display substrate includes a base substrate 10 and a plurality of pixel units 100 arranged on the base substrate 10 and arranged in an array. Each pixel unit 100 includes a light emitting device 11 and a fingerprint recognition device 12, and the light emitting device 11 and the fingerprint recognition device 12 are formed on a base substrate 10. The light emitting device 11 includes a light emitting unit 13 and a driving circuit 14. The fingerprint identification device 12 includes an ultrasonic fingerprint identification sensor 15 for forming fingerprint electrical signals. The ultrasonic fingerprint recognition sensor 15 includes a piezoelectric film layer 37 located between the light emitting unit 13 and the driving circuit 14 and extending across the pixel unit to cover the entire pixel unit 100. The light-emitting unit 13 penetrates the piezoelectric film layer 37 and is electrically connected to the driving circuit 14.
本公开上述实施例的显示基板中,由于多个像素单元设置在衬底基板的显示区中,压电薄膜层也位于显示区中,因此,可以在显示区中实现指纹功能,从而解决现有显示基板只能以外贴合方式实现非显示区按键式指纹识别等问题。由此可见,压电薄膜层覆盖整个像素单元,不仅实现了嵌入指纹识别功能的显示装置,而且实现了在显示区的指纹识别功能。In the display substrate of the above-mentioned embodiment of the present disclosure, since a plurality of pixel units are arranged in the display area of the base substrate, and the piezoelectric film layer is also located in the display area, the fingerprint function can be implemented in the display area, thereby solving the existing problems. The display substrate can only realize problems such as non-display area key-press fingerprint recognition by using other methods. It can be seen that the piezoelectric film layer covers the entire pixel unit, which not only realizes the display device with embedded fingerprint recognition function, but also realizes the fingerprint recognition function in the display area.
例如,如图2所示,超声波指纹识别传感器15还包括驱动电极38和接收电极34。驱动电极38位于压电薄膜层37的远离衬底基板10的一侧并且配置为向显示基板的显示侧发出超声波信号。接收电极34位于所述压电薄膜层37的靠近衬底基板10的一侧并且配 置为接收被位于显示侧的指纹反射回来的超声波信号。For example, as shown in FIG. 2, the ultrasonic fingerprint recognition sensor 15 further includes a driving electrode 38 and a receiving electrode 34. The driving electrode 38 is located on the side of the piezoelectric film layer 37 away from the base substrate 10 and is configured to emit an ultrasonic signal to the display side of the display substrate. The receiving electrode 34 is located on the side of the piezoelectric film layer 37 close to the base substrate 10 and is configured to receive the ultrasonic signal reflected by the fingerprint located on the display side.
在超声波指纹识别传感器15工作时,接收电极34和驱动电极38共用压电薄膜层37,驱动电极38驱动压电薄膜层37振动发出超声波信号,超声波信号朝着显示基板的显示侧的方向发射,超声波信号遇到指纹后反射被接收电极34接收,接收电极34接收反射回来的超声波信号,再通过压电薄膜层37形成用于识别指纹的电信号。When the ultrasonic fingerprint recognition sensor 15 is working, the receiving electrode 34 and the driving electrode 38 share the piezoelectric film layer 37, and the driving electrode 38 drives the piezoelectric film layer 37 to vibrate and emit an ultrasonic signal, which is emitted toward the display side of the display substrate. The ultrasonic signal is reflected by the receiving electrode 34 after encountering the fingerprint. The receiving electrode 34 receives the reflected ultrasonic signal, and then forms an electrical signal for identifying the fingerprint through the piezoelectric film layer 37.
例如,如图2所示,超声波指纹识别传感器15还包括引出电极35和第一阴极43。引出电极35位于压电薄膜层37之下,第一阴极43形成于驱动电极38之上。第一阴极43和下面将要描述的第二阴极42为同层设置。进一步地,至少一个示例中,第一阴极43和第二阴极42在同一成膜工艺中形成。为了避免二者信号干扰,如图2所示,第一阴极43和第二阴极42彼此间隔以使第一阴极43和第二阴极42之间彼此绝缘。驱动电极38形成于压电薄膜层37之上,驱动电极38贯穿压电薄膜层37与引出电极35电连接。所述引出电极35在所述衬底基板10上的正投影与所述接收电极34在所述衬底基板10上的正投影之间没有重叠区域,这样,引出电极不会干扰接收电极34对超声波信号的接收。For example, as shown in FIG. 2, the ultrasonic fingerprint recognition sensor 15 further includes a lead electrode 35 and a first cathode 43. The lead electrode 35 is located under the piezoelectric film layer 37, and the first cathode 43 is formed on the driving electrode 38. The first cathode 43 and the second cathode 42 described below are arranged in the same layer. Further, in at least one example, the first cathode 43 and the second cathode 42 are formed in the same film forming process. To avoid signal interference between the two, as shown in FIG. 2, the first cathode 43 and the second cathode 42 are spaced apart from each other so that the first cathode 43 and the second cathode 42 are insulated from each other. The driving electrode 38 is formed on the piezoelectric film layer 37, and the driving electrode 38 penetrates the piezoelectric film layer 37 and is electrically connected to the lead electrode 35. There is no overlapping area between the orthographic projection of the lead electrode 35 on the base substrate 10 and the orthographic projection of the receiving electrode 34 on the base substrate 10, so that the lead electrode will not interfere with the pair of receiving electrodes 34 Reception of ultrasonic signals.
例如,如图2所示,发光单元13包括形成于压电薄膜层37之上的阳极39、形成于阳极39之上的以及形成于有机发光功能层41之上的第二阴极42。阳极39与驱动电极38同层,即阳极39与驱动电极38均位于所述压电薄膜层37上且与该压电薄膜层37接触。阳极39贯穿压电薄膜层37与驱动电路14电连接。进一步,至少一个示例中,有机发光功能层41包括有机发光层,并且还可以包括空穴注入层、空穴传输层、电子注入层和电子传输层中的至少一层。For example, as shown in FIG. 2, the light-emitting unit 13 includes an anode 39 formed on the piezoelectric thin film layer 37, a second cathode 42 formed on the anode 39 and formed on the organic light-emitting functional layer 41. The anode 39 and the driving electrode 38 are in the same layer, that is, the anode 39 and the driving electrode 38 are both located on the piezoelectric film layer 37 and in contact with the piezoelectric film layer 37. The anode 39 penetrates the piezoelectric film layer 37 and is electrically connected to the drive circuit 14. Further, in at least one example, the organic light emitting function layer 41 includes an organic light emitting layer, and may also include at least one of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.
例如,所述指纹识别装置还包括处理电路16,所述处理电路16位于所述接收电极34与所述衬底基板10之间并且与所述接收电极34电连接,所述处理电路16配置为接收并且处理来自所述接收电极34的电信号。For example, the fingerprint identification device further includes a processing circuit 16 located between the receiving electrode 34 and the base substrate 10 and electrically connected to the receiving electrode 34, and the processing circuit 16 is configured as The electrical signal from the receiving electrode 34 is received and processed.
例如,如图2所示,该显示基板的有源层采用互补金属-氧化物-半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺制备而成。例如,驱动电路14包括第一薄膜晶体管,处理电路16包括第二薄膜晶体管,第一薄膜晶体管为P型薄膜晶体管,第二薄膜晶体管为N型薄膜晶体管。例如,如图8所示,第一薄膜晶体管包括第一有源层17、第一栅电极20、第一漏电极23、第一源电极24、第二连接电极29以及第四连接电极33。第二薄膜晶体管包括第二有源层18、第二栅电极21、第二漏电极25、第一连接电极26、第二源电极27、第三连接电极30和接收电极34。For example, as shown in FIG. 2, the active layer of the display substrate is prepared by a complementary metal-oxide-semiconductor (Complementary Metal Oxide Semiconductor, CMOS) process. For example, the driving circuit 14 includes a first thin film transistor, and the processing circuit 16 includes a second thin film transistor. The first thin film transistor is a P-type thin film transistor, and the second thin film transistor is an N-type thin film transistor. For example, as shown in FIG. 8, the first thin film transistor includes a first active layer 17, a first gate electrode 20, a first drain electrode 23, a first source electrode 24, a second connection electrode 29 and a fourth connection electrode 33. The second thin film transistor includes a second active layer 18, a second gate electrode 21, a second drain electrode 25, a first connection electrode 26, a second source electrode 27, a third connection electrode 30, and a receiving electrode 34.
例如,如图2至图6所示,所述驱动电路14包括设置在所述衬底基板10上的第一有源层17和覆盖所述第一有源层17的第一绝缘层19。例如,驱动电路还包括设置在所述第 一绝缘层19上的第一栅电极20和覆盖所述第一栅电极20的第二绝缘层22。例如,驱动电路还包括设置在22所述第二绝缘层上的第一漏电极23和第一源电极24。如图6所示,所述第一漏电极23和所述第一源电极24分别通过过孔与所述第一有源层17内的掺杂区电连接。至少一个示例中,第一有源层17包括沟道区和两个重掺杂区。至少一个示例中,所述发光单元13的阳极39配置为贯穿所述压电薄膜层37并且与所述第一漏电极23电连接。For example, as shown in FIGS. 2 to 6, the driving circuit 14 includes a first active layer 17 disposed on the base substrate 10 and a first insulating layer 19 covering the first active layer 17. For example, the driving circuit further includes a first gate electrode 20 provided on the first insulating layer 19 and a second insulating layer 22 covering the first gate electrode 20. For example, the driving circuit further includes a first drain electrode 23 and a first source electrode 24 disposed on the second insulating layer 22. As shown in FIG. 6, the first drain electrode 23 and the first source electrode 24 are respectively electrically connected to the doped regions in the first active layer 17 through via holes. In at least one example, the first active layer 17 includes a channel region and two heavily doped regions. In at least one example, the anode 39 of the light emitting unit 13 is configured to penetrate the piezoelectric film layer 37 and is electrically connected to the first drain electrode 23.
进一步地,如图7至图8所示,例如,所述驱动电路14还包括:覆盖所述第一漏电极23和所述第一源电极24的第三绝缘层28;以及设置在所述第三绝缘层28上的第二连接电极29。例如,所述第二连接电极29通过过孔与所述第一漏电极23电连接。如图8所示,驱动电路还包括:覆盖所述第二连接电极29的平坦层31;设置在所述平坦层31上的第一保护层32;和设置在所述第一保护层32上的第四连接电极33。例如,所述第四连接电极33通过过孔与所述第二连接电极29电连接。至少一个示例中,所述发光单元13的所述阳极39配置为贯穿所述压电薄膜层37与所述第四连接电极33电连接。Further, as shown in FIGS. 7 to 8, for example, the driving circuit 14 further includes: a third insulating layer 28 covering the first drain electrode 23 and the first source electrode 24; and The second connection electrode 29 on the third insulating layer 28. For example, the second connection electrode 29 is electrically connected to the first drain electrode 23 through a via hole. As shown in FIG. 8, the driving circuit further includes: a flat layer 31 covering the second connection electrode 29; a first protective layer 32 disposed on the flat layer 31; and a first protective layer 32 disposed on the first protective layer 32 The fourth connection electrode 33. For example, the fourth connection electrode 33 is electrically connected to the second connection electrode 29 through a via hole. In at least one example, the anode 39 of the light-emitting unit 13 is configured to penetrate through the piezoelectric film layer 37 and be electrically connected to the fourth connection electrode 33.
例如,再参照图3至图5,所述处理电路16包括设置在所述衬底基板10上的第二有源层18,所述第一绝缘层19还覆盖所述第二有源层18。例如,处理电路还包括设置在所述第一绝缘层19上的第二栅电极21,所述第二绝缘层22还覆盖所述第二栅电极21。例如,如图6所示,处理电路还包括设置在所述第二绝缘层22上的第二漏电极25、第一连接电极26和第二源电极27。例如,所述第二漏电极25和所述第二源电极27分别通过过孔与第二有源层18内的掺杂区电连接。至少一个示例中,第二有源层18包括沟道区、轻掺杂区和重掺杂区,两个重掺杂区位于沟道区的两侧,轻掺杂区位于每个重掺杂区和沟道区之间。例如,如图7所示,所述第一连接电极26通过过孔与第二栅电极21电连接,所述第三绝缘层28还覆盖所述第二漏电极25、所述第一连接电极26和所述第二源电极27。例如,如图8所示,所述接收电极34设置在所述第三绝缘层28上,所述接收电极34通过过孔与所述第一连接电极26电连接。For example, referring to FIGS. 3 to 5 again, the processing circuit 16 includes a second active layer 18 disposed on the base substrate 10, and the first insulating layer 19 also covers the second active layer 18. . For example, the processing circuit further includes a second gate electrode 21 disposed on the first insulating layer 19, and the second insulating layer 22 also covers the second gate electrode 21. For example, as shown in FIG. 6, the processing circuit further includes a second drain electrode 25, a first connection electrode 26, and a second source electrode 27 provided on the second insulating layer 22. For example, the second drain electrode 25 and the second source electrode 27 are electrically connected to the doped regions in the second active layer 18 through via holes, respectively. In at least one example, the second active layer 18 includes a channel region, a lightly doped region, and a heavily doped region. The two heavily doped regions are located on both sides of the channel region, and the lightly doped region is located in each heavily doped region. Between the region and the channel region. For example, as shown in FIG. 7, the first connection electrode 26 is electrically connected to the second gate electrode 21 through a via hole, and the third insulating layer 28 also covers the second drain electrode 25 and the first connection electrode. 26 and the second source electrode 27. For example, as shown in FIG. 8, the receiving electrode 34 is disposed on the third insulating layer 28, and the receiving electrode 34 is electrically connected to the first connecting electrode 26 through a via hole.
进一步地,例如,如图7和图8所示,处理电路16还包括:设置在所述第三绝缘层28上的第三连接电极30,所述第三连接电极30通过过孔与所述第一连接电极26电连接,所述平坦层31还覆盖所述第三连接电极30。例如,处理电路还包括设置在所述第一保护层32上的所述接收电极34,所述接收电极34通过过孔与所述第三连接电极30电连接。Further, for example, as shown in FIGS. 7 and 8, the processing circuit 16 further includes: a third connecting electrode 30 disposed on the third insulating layer 28, and the third connecting electrode 30 is connected to the third insulating layer 28 through a via hole. The first connection electrode 26 is electrically connected, and the flat layer 31 also covers the third connection electrode 30. For example, the processing circuit further includes the receiving electrode 34 disposed on the first protective layer 32, and the receiving electrode 34 is electrically connected to the third connecting electrode 30 through a via hole.
例如,如图2和图3所示,衬底基板10上还可设有阻挡层101,用于阻挡来自衬底基板的杂质或水汽。发光装置11和指纹识别装置12均形成于阻挡层101上。For example, as shown in FIGS. 2 and 3, a barrier layer 101 may be further provided on the base substrate 10 to block impurities or water vapor from the base substrate. Both the light emitting device 11 and the fingerprint recognition device 12 are formed on the barrier layer 101.
例如,如图2所示,显示基板还包括覆盖所述第二阴极42和第一阴极43的封装层44, 例如该封装层为盖板。For example, as shown in FIG. 2, the display substrate further includes an encapsulation layer 44 covering the second cathode 42 and the first cathode 43, for example, the encapsulation layer is a cover plate.
至少一些实施例中,衬底基板10的材料包括超声波吸收材料,这样,衬底基板10能够吸收超声波指纹识别传感器15发出的反向声波,使超声波指纹识别传感器15不需要设置专门的反向超声波的吸收层,简化了超声波指纹识别传感器15的制备工艺。In at least some embodiments, the material of the base substrate 10 includes an ultrasonic absorbing material. In this way, the base substrate 10 can absorb the reverse sound waves emitted by the ultrasonic fingerprint recognition sensor 15, so that the ultrasonic fingerprint recognition sensor 15 does not need to be equipped with a special reverse ultrasonic wave. The absorbing layer simplifies the manufacturing process of the ultrasonic fingerprint identification sensor 15.
上述实施例中,超声波指纹识别传感器的工作原理为:向驱动电极38输入AC电压,指纹识别传感器的压电薄膜层37会在逆压电效应下产生超声波,超声波传递到手指。手指指纹的脊与谷将超声波反射回压电薄膜层37,压电薄膜层会37在正向压电效应下产生指纹电信号。处理电路16与指纹识别传感器连接,从指纹识别传感器接收该指纹电信号,并对指纹电信号进行处理,从而辨识指纹。In the above embodiment, the working principle of the ultrasonic fingerprint recognition sensor is: input AC voltage to the driving electrode 38, the piezoelectric film layer 37 of the fingerprint recognition sensor will generate ultrasonic waves under the inverse piezoelectric effect, and the ultrasonic waves are transmitted to the finger. The ridges and valleys of the fingerprint of the finger reflect ultrasonic waves back to the piezoelectric film layer 37, and the piezoelectric film layer 37 generates fingerprint electrical signals under the positive piezoelectric effect. The processing circuit 16 is connected to the fingerprint identification sensor, receives the fingerprint electrical signal from the fingerprint identification sensor, and processes the fingerprint electrical signal to identify the fingerprint.
根据本公开实施例,如图15所示,还提供一种用于超声波指纹识别的显示基板的制造方法,包括:According to an embodiment of the present disclosure, as shown in FIG. 15, there is also provided a manufacturing method of a display substrate for ultrasonic fingerprint recognition, including:
提供衬底基板,所述衬底基板包括多个像素区;Providing a base substrate, the base substrate including a plurality of pixel regions;
在每个所述像素区中形成发光单元;Forming a light emitting unit in each of the pixel regions;
在每个所述像素区中的所述发光单元的靠近所述衬底基板的一侧形成驱动电路,所述驱动电路配置为与所述发光单元电连接;以及Forming a drive circuit on a side of the light emitting unit in each of the pixel regions close to the base substrate, the drive circuit being configured to be electrically connected to the light emitting unit; and
在每个所述像素区中的所述发光单元和所述驱动电路之间形成压电薄膜层,所述压电薄膜层延伸跨过该每个像素单元,所述发光单元配置为贯穿所述压电薄膜层并且与所述驱动电路电连接。A piezoelectric thin film layer is formed between the light emitting unit and the driving circuit in each pixel area, the piezoelectric thin film layer extends across each pixel unit, and the light emitting unit is configured to penetrate through the The piezoelectric film layer is electrically connected to the driving circuit.
本公开上述实施例的制造方法中,压电薄膜层覆盖整个像素单元,不仅实现了在嵌入指纹识别功能的显示装置,而且实现了在显示区的指纹识别功能。In the manufacturing method of the foregoing embodiment of the present disclosure, the piezoelectric film layer covers the entire pixel unit, which not only realizes the display device with embedded fingerprint recognition function, but also realizes the fingerprint recognition function in the display area.
下面通过一示例描述显示基板的制造方法的具体过程。本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理,本实施例中,形成薄膜的方法包括但不限于蒸镀、沉积、涂覆、涂布等常规的制膜工艺。The following describes the specific process of the manufacturing method of the display substrate through an example. The "patterning process" in this embodiment includes the processes of depositing a film layer, coating photoresist, mask exposure, developing, etching, stripping the photoresist, etc. In this embodiment, the method of forming a thin film includes but not It is limited to conventional film-making processes such as evaporation, deposition, coating, and coating.
图3至图12是本公开实施例的显示基板的制造方法的各步骤结构示意图。参照图3至图12,在一个示例中,显示基板的制备方法包括:3 to 12 are schematic diagrams of each step of the manufacturing method of the display substrate of the embodiment of the present disclosure. Referring to FIGS. 3 to 12, in an example, a method for preparing a display substrate includes:
(1)形成衬底基板和有源层图案。形成衬底基板和有源层图案包括:先在玻璃载板上涂布一层柔性材料,固化成膜,形成衬底基板10;随后在衬底基板10上沉积一层阻挡薄膜,形成覆盖整个衬底基板10的阻挡层101图案。然后,在阻挡层101上面形成多晶硅薄膜,通过构图工艺对多晶硅薄膜进行构图,形成设置在阻挡层101上的两个有源层图案。最后,分别对两个有源层图案进行PMOS阈值电压调节和NMOS阈值电压调节的离子注入处理,形成第一有源层17和第二有源层18,如图3所示。(1) Form the base substrate and the active layer pattern. Forming the base substrate and the active layer pattern includes: first coating a layer of flexible material on the glass carrier, curing it into a film to form the base substrate 10; then depositing a layer of barrier film on the base substrate 10 to form a covering The barrier layer 101 of the base substrate 10 is patterned. Then, a polysilicon film is formed on the barrier layer 101, and the polysilicon film is patterned through a patterning process to form two active layer patterns disposed on the barrier layer 101. Finally, the two active layer patterns are respectively subjected to ion implantation treatment of PMOS threshold voltage adjustment and NMOS threshold voltage adjustment to form the first active layer 17 and the second active layer 18, as shown in FIG. 3.
(2)形成第一栅电极图案。形成第一栅电极图案包括:在形成前述图案的衬底基板10上,依次沉积第一绝缘薄膜和第一金属薄膜,由此形成覆盖第一有源层17和第二有源层18图案的第一绝缘层19;然而,通过构图工艺对第一金属薄膜进行构图,形成设置在第一绝缘层19上的第一栅电极20,第一栅电极20位于第一有源层17的上方。然后,以第一栅电极20为遮挡,对第一有源层17进行PMOS重掺杂离子注入,使第一有源层17包括沟道区和两个重掺杂区,其中沟道区对应于第一栅电极20,在该中心区两侧形成重掺杂区。同时第二有源层18因设置在第一绝缘层19上的第一金属薄膜图形被遮挡保护,如图4所示。(2) Form the first gate electrode pattern. Forming the first gate electrode pattern includes: sequentially depositing a first insulating film and a first metal film on the base substrate 10 on which the aforementioned pattern is formed, thereby forming a pattern covering the first active layer 17 and the second active layer 18 The first insulating layer 19; however, the first metal film is patterned by a patterning process to form a first gate electrode 20 disposed on the first insulating layer 19, and the first gate electrode 20 is located above the first active layer 17. Then, using the first gate electrode 20 as a shield, the first active layer 17 is heavily doped with PMOS ion implantation, so that the first active layer 17 includes a channel region and two heavily doped regions, where the channel region corresponds to In the first gate electrode 20, heavily doped regions are formed on both sides of the central region. At the same time, the second active layer 18 is shielded and protected by the first metal thin film pattern provided on the first insulating layer 19, as shown in FIG. 4.
(3)形成第二栅电极图案。形成第二栅电极图案包括:在形成前述图案的衬底基板10上,通过构图工艺对设置在第二有源层18上方的第一金属薄膜进行构图,形成设置在第一绝缘层19上的两个第二栅电极21,其位于第二有源层18的上方。然后,以两个第二栅电极21为遮挡,对第二有源层18进行NMOS轻掺杂和NMOS重掺杂离子注入,使第二有源层18包括沟道区和位于沟道区两侧的两个轻掺杂区和两个重掺杂区,沟道区对应每个第二栅电极21,轻掺杂区位于重掺杂区与沟道区之间,如图5所示。(3) Form the second gate electrode pattern. Forming the second gate electrode pattern includes: patterning the first metal thin film disposed above the second active layer 18 through a patterning process on the base substrate 10 on which the aforementioned pattern is formed, to form a first insulating layer 19 Two second gate electrodes 21 are located above the second active layer 18. Then, using the two second gate electrodes 21 as shields, the second active layer 18 is implanted with lightly doped NMOS and heavily doped NMOS, so that the second active layer 18 includes the channel region and two located in the channel region. Two lightly doped regions and two heavily doped regions on the side, the channel region corresponds to each second gate electrode 21, and the lightly doped region is located between the heavily doped region and the channel region, as shown in FIG. 5.
(4)形成源漏电极图案。形成源漏电极图案包括:在形成前述图案的衬底基板10上,在第一栅电极20和第二栅电极21上沉积第二绝缘薄膜,形成覆盖第一栅电极20和第二栅电极21的第二绝缘层22,通过构图工艺在第二绝缘层22内依次开设暴露出第一有源层17两侧重掺杂区的第一过孔、暴露出第二有源层18两侧的重掺杂区的第二过孔以及暴露出第二栅电极21中的一个栅电极的第三过孔。随后,在形成前述图案的衬底基板上,沉积第二金属薄膜,通过构图工艺对第二金属薄膜进行构图,在第二绝缘层22上形成第一漏电极23、第一源电极24、第二漏电极25、第一连接电极26和第二源电极27,第一漏电极23和第一源电极24分别通过第一过孔与第一有源层17两侧的重掺杂区连接,第二漏电极25和第二源电极27分别通过第二过孔与第二有源层18两侧的重掺杂区连接,第一连接电极26通过第三过孔与第二栅电极21中的一个栅电极连接,如图6所示。(4) Form source and drain electrode patterns. Forming the source and drain electrode patterns includes: depositing a second insulating film on the first gate electrode 20 and the second gate electrode 21 on the base substrate 10 on which the aforementioned pattern is formed, so as to cover the first gate electrode 20 and the second gate electrode 21 In the second insulating layer 22, the first via holes exposing the heavily doped regions on both sides of the first active layer 17 are sequentially opened in the second insulating layer 22 through a patterning process, and the heavy on both sides of the second active layer 18 is exposed. The second via hole in the doped region and the third via hole exposing one of the second gate electrodes 21. Subsequently, a second metal film is deposited on the base substrate with the aforementioned pattern, and the second metal film is patterned through a patterning process to form a first drain electrode 23, a first source electrode 24, and a second insulating layer 22. The two drain electrodes 25, the first connection electrode 26 and the second source electrode 27, the first drain electrode 23 and the first source electrode 24 are respectively connected to the heavily doped regions on both sides of the first active layer 17 through first via holes, The second drain electrode 25 and the second source electrode 27 are respectively connected to the heavily doped regions on both sides of the second active layer 18 through the second via hole, and the first connection electrode 26 is connected to the second gate electrode 21 through the third via hole. One of the gate electrodes is connected as shown in Figure 6.
(5)形成连接电极图案。形成连接电极图案包括:在形成前述图案的衬底基板10上,沉积第三绝缘薄膜,形成覆盖第一漏电极23、第一源电极24、第二漏电极25、第一连接电极26和第二源电极27的第三绝缘层28,通过构图工艺在第三绝缘层28上形成暴露出第一漏电极23的第四过孔以及暴露出第一连接电极26的第五过孔。随后,在形成前述图案的衬底基板上,沉积第三金属薄膜,通过构图工艺对第三金属薄膜进行构图,在第三绝缘层28上形成第二连接电极29和第三连接电极30。第二连接电极29通过第四过孔与第一漏电极23连接,第三连接电极30通过第五过孔与第一连接电极26连接,如图7所示。(5) Form connection electrode patterns. Forming the connection electrode pattern includes: depositing a third insulating film on the base substrate 10 formed with the aforementioned pattern to cover the first drain electrode 23, the first source electrode 24, the second drain electrode 25, the first connection electrode 26, and the second drain electrode. In the third insulating layer 28 of the two source electrodes 27, a fourth via hole exposing the first drain electrode 23 and a fifth via hole exposing the first connection electrode 26 are formed on the third insulating layer 28 through a patterning process. Subsequently, a third metal film is deposited on the base substrate with the aforementioned pattern, and the third metal film is patterned through a patterning process to form the second connection electrode 29 and the third connection electrode 30 on the third insulating layer 28. The second connection electrode 29 is connected to the first drain electrode 23 through the fourth via hole, and the third connection electrode 30 is connected to the first connection electrode 26 through the fifth via hole, as shown in FIG. 7.
(5)形成接收电极图案。形成接收电极图案包括:在形成前述图案的衬底基板上,先涂覆一层平坦薄膜,然后沉积第一保护薄膜,形成覆盖第二连接电极29和第三连接电极30的平坦层31以及设置在平坦层31上的第一保护层32。然后,通过构图工艺对第一保护层32和平坦层31上开设暴露出第二连接电极29的第六过孔和暴露出第三连接电极30的第七过孔。随后,在形成前述图案的衬底基板上,沉积第四金属薄膜,通过构图工艺对第四金属薄膜进行构图,在第一保护层32上形成第四连接电极33、接收电极34和引出电极35,第四连接电极33通过第六过孔与第二连接电极29连接,接收电极34通过第七过孔与第三连接电极30连接。例如,第一有源层17、第一栅电极20、第一漏电极23、第一源电极24、第二连接电极29以及第四连接电极33形成第一薄膜晶体管。第二有源层18、第二栅电极21、第二漏电极25、第一连接电极26、第二源电极27、第三连接电极30和接收电极34形成第二薄膜晶体管,如图8所示。(5) Form the receiving electrode pattern. Forming the receiving electrode pattern includes: coating a flat film on the base substrate forming the aforementioned pattern, and then depositing a first protective film to form a flat layer 31 covering the second connection electrode 29 and the third connection electrode 30, and setting The first protective layer 32 on the flat layer 31. Then, a sixth via hole exposing the second connection electrode 29 and a seventh via hole exposing the third connection electrode 30 are opened on the first protection layer 32 and the flat layer 31 through a patterning process. Subsequently, a fourth metal film is deposited on the base substrate with the aforementioned pattern, and the fourth metal film is patterned through a patterning process to form a fourth connection electrode 33, a receiving electrode 34, and a lead electrode 35 on the first protective layer 32 The fourth connection electrode 33 is connected to the second connection electrode 29 through the sixth via hole, and the receiving electrode 34 is connected to the third connection electrode 30 through the seventh via hole. For example, the first active layer 17, the first gate electrode 20, the first drain electrode 23, the first source electrode 24, the second connection electrode 29, and the fourth connection electrode 33 form a first thin film transistor. The second active layer 18, the second gate electrode 21, the second drain electrode 25, the first connection electrode 26, the second source electrode 27, the third connection electrode 30 and the receiving electrode 34 form a second thin film transistor, as shown in FIG. Show.
(6)形成压电薄膜层。形成压电薄膜层包括:在形成前述图案的衬底基板10上,先形成覆盖第四连接电极33、接收电极34以及引出电极35的第二保护层36,在第二保护层36上形成覆盖第二保护层36的压电薄膜层37,然后通过构图工艺在压电薄膜层37和第二保护层36上开设出暴露出第四连接电极33的第八过孔和暴露出引出电极35的第九过孔,如图9所示。(6) Forming a piezoelectric film layer. Forming the piezoelectric thin film layer includes: forming a second protective layer 36 covering the fourth connecting electrode 33, the receiving electrode 34 and the lead electrode 35 on the base substrate 10 formed with the aforementioned pattern, and forming a covering on the second protective layer 36 The piezoelectric film layer 37 of the second protective layer 36 is then opened on the piezoelectric film layer 37 and the second protective layer 36 through a patterning process to open an eighth via hole exposing the fourth connection electrode 33 and an eighth via hole exposing the lead electrode 35 The ninth via is shown in Figure 9.
(7)形成驱动电极和阳极图案。形成驱动电极和阳极图案包括:在形成前述图案的衬底基板10上,沉积第五金属薄膜,通过构图工艺对第五金属薄膜进行构图,在压电薄膜层37上形成驱动电极38。随后沉积第六金属薄膜,通过构图工艺对第六金属薄膜进行构图,形成阳极39,阳极39通过第八过孔与第四连接电极33连接,驱动电极38通过第九过孔与引出电极35连接,如图10所示。(7) Forming driving electrodes and anode patterns. Forming the driving electrode and anode pattern includes: depositing a fifth metal film on the base substrate 10 where the aforementioned pattern is formed, patterning the fifth metal film through a patterning process, and forming a driving electrode 38 on the piezoelectric film layer 37. Subsequently, a sixth metal film is deposited, and the sixth metal film is patterned through a patterning process to form an anode 39. The anode 39 is connected to the fourth connecting electrode 33 through the eighth via hole, and the driving electrode 38 is connected to the lead electrode 35 through the ninth via hole. , As shown in Figure 10.
(8)形成像素定义层。形成像素定义层包括:在形成前述图案的衬底基板10上,形成暴露出阳极39和驱动电极38的像素定义层40,如图11所示。(8) Form a pixel definition layer. Forming the pixel defining layer includes: forming a pixel defining layer 40 exposing the anode 39 and the driving electrode 38 on the base substrate 10 formed with the aforementioned pattern, as shown in FIG. 11.
(9)形成有机发光功能层和阴极。形成有机发光层和阴极包括:在形成前述图案的衬底基板10上,在像素定义层40的开口内形成有机发光功能层41,有机发光功能层41与阳极39连接,然后,形成与驱动电极38连接的第一阴极43,形成与有机发光功能层41连接的第二阴极42。阳极39、像素定义层40、有机发光功能层41和第二阴极42形成发光单元13;接收电极34、压电薄膜层37、驱动电极38和第一阴极43形成超声波指纹识别传感器15,如图12所示。(9) Form an organic light-emitting functional layer and a cathode. Forming the organic light-emitting layer and the cathode includes: forming an organic light-emitting functional layer 41 in the opening of the pixel defining layer 40 on the base substrate 10 formed with the aforementioned pattern, the organic light-emitting functional layer 41 is connected to the anode 39, and then forming a driving electrode The first cathode 43 connected to 38 forms a second cathode 42 connected to the organic light-emitting functional layer 41. The anode 39, the pixel definition layer 40, the organic light emitting function layer 41 and the second cathode 42 form the light emitting unit 13; the receiving electrode 34, the piezoelectric film layer 37, the driving electrode 38 and the first cathode 43 form the ultrasonic fingerprint recognition sensor 15, as shown in the figure 12 shown.
例如,阳极39与驱动电极38同层,阳极39贯穿压电薄膜层37与第四连接电极33连接;驱动电极38贯穿压电薄膜层37与引出电极35连接。For example, the anode 39 and the driving electrode 38 are in the same layer, the anode 39 penetrates the piezoelectric film layer 37 and is connected to the fourth connection electrode 33; the driving electrode 38 penetrates the piezoelectric film layer 37 and is connected to the extraction electrode 35.
(10)形成封装层。形成封装层包括:在第二阴极42和第一阴极43上形成封装层44。(10) Form an encapsulation layer. Forming the encapsulation layer includes: forming the encapsulation layer 44 on the second cathode 42 and the first cathode 43.
上述实施例中,指纹识别传感器15中的驱动电极38以及接收电极35分别通过单独的IC芯片驱动。发光装置采用GOA驱动,由单独的IC芯片驱动。指纹识别装置的IC芯片与发光装置的IC芯片为互相独立的IC芯片。In the above-mentioned embodiment, the driving electrode 38 and the receiving electrode 35 in the fingerprint recognition sensor 15 are respectively driven by separate IC chips. The light-emitting device is driven by GOA and driven by a separate IC chip. The IC chip of the fingerprint identification device and the IC chip of the light-emitting device are independent IC chips.
通过本实施例上述制造方法可以看出,本实施例通过将指纹识别装置12集成到显示基板中,不仅实现了嵌入指纹识别功能的OLED显示装置,而且实现了在显示区的指纹识别功能。It can be seen from the above manufacturing method of this embodiment that by integrating the fingerprint identification device 12 into the display substrate, this embodiment not only realizes the OLED display device with embedded fingerprint identification function, but also realizes the fingerprint identification function in the display area.
此外,本实施例的制造方法利用现有成熟的制备设备即可实现,对现有工艺改进较小,能够很好地与现有制备工艺兼容,因此具有制作成本低、易于工艺实现、生产效率高和良品率高等优,具有良好的应用前景。In addition, the manufacturing method of this embodiment can be realized by using existing mature manufacturing equipment, has little improvement to the existing process, and is well compatible with the existing manufacturing process, so it has low manufacturing cost, easy process realization, and production efficiency. High and good product rate, etc., have good application prospects.
图13为本公开实施例的另一显示基板的结构示意图。该显示基板中每个薄膜晶体管的有源层均采用N沟道金属-氧化物-半导体(Negative Channel Metal Oxide Semiconductor,NMOS)。FIG. 13 is a schematic structural diagram of another display substrate according to an embodiment of the disclosure. The active layer of each thin film transistor in the display substrate uses N-channel metal-oxide-semiconductor (Negative Channel Metal Oxide Semiconductor, NMOS).
如图13所示,本实施例的显示基板包括衬底基板210,以及在衬底基板210上形成的发光装置211和指纹识别装置212。图13所示的显示基板与前述图2的显示基板基本相同,所不同的是,图3的显示基板在形成第一栅电极图案时,以第一栅电极220为遮挡,对第一有源层217进行NMOS轻掺杂和NMOS重掺杂离子注入,使第一有源层217包括沟道区、N型轻掺杂区和N型重掺杂区,N型轻掺杂区位于N型重掺杂区与沟道区之间。As shown in FIG. 13, the display substrate of this embodiment includes a base substrate 210, and a light-emitting device 211 and a fingerprint identification device 212 formed on the base substrate 210. The display substrate shown in FIG. 13 is basically the same as the display substrate of FIG. 2 described above. The difference is that when the first gate electrode pattern is formed on the display substrate of FIG. 3, the first gate electrode 220 is used as a shield for the first active The layer 217 is lightly doped NMOS and heavily doped NMOS ion implantation, so that the first active layer 217 includes a channel region, an N-type lightly doped region, and an N-type heavily doped region. The N-type lightly doped region is located in the N-type region. Between the heavily doped region and the channel region.
图14为本公开再一实施例的显示基板的结构示意图。该显示基板的每个薄膜晶体管的有源层均采用P沟道金属-氧化物-半导体(Positive Channel Metal Oxide Semiconductor,PMOS)。FIG. 14 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure. The active layer of each thin film transistor of the display substrate uses P-channel metal-oxide-semiconductor (Positive Channel Metal Oxide Semiconductor, PMOS).
如图14所示,本实施例的显示基板包括衬底基板310,以及在衬底基板310上的发光装置311和指纹识别装置312。图14的显示基板与图2的显示基板基本相同,所不同的是,图14的显示基板在形成第二栅电极图案时,以两个第二栅电极321为遮挡,对第二有源层318进行PMOS重掺杂离子注入,使第二有源层318包括形成P型重掺杂区。As shown in FIG. 14, the display substrate of this embodiment includes a base substrate 310, and a light-emitting device 311 and a fingerprint identification device 312 on the base substrate 310. The display substrate of FIG. 14 is basically the same as the display substrate of FIG. 2, except that when the second gate electrode pattern is formed on the display substrate of FIG. 14, two second gate electrodes 321 are used as shields to protect the second active layer. 318 performs heavily doped PMOS ion implantation, so that the second active layer 318 includes a heavily doped P-type region.
根据本公开实施例,还提供一种包括以上任一实施例的显示基板的显示装置。该显示装置例如为有机发光二极管显示装置。According to an embodiment of the present disclosure, a display device including the display substrate of any of the above embodiments is also provided. The display device is, for example, an organic light emitting diode display device.
本文中,有以下几点需要说明:In this article, the following points need to be explained:
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构,其他结构可参考通常设计。(1) The drawings of the embodiments of the present disclosure only refer to the structures related to the embodiments of the present disclosure, and other structures can refer to the usual design.
(2)为了清晰起见,在用于描述本公开的实施例的附图中,层或区域的厚度被放大或 缩小,即这些附图并非按照实际的比例绘制。(2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions are enlarged or reduced, that is, these drawings are not drawn according to actual scale.
(3)在不冲突的情况下,本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。(3) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
以上所述仅是本公开的示范性实施方式,而非用于限制本公开的保护范围,本公开的保护范围由所附的权利要求确定。The above are only exemplary implementations of the present disclosure, and are not used to limit the protection scope of the present disclosure, which is determined by the appended claims.

Claims (16)

  1. 一种用于超声波指纹识别的显示基板,包括衬底基板以及设置在所述衬底基板上的多个像素单元,每个所述像素单元包括:A display substrate used for ultrasonic fingerprint identification includes a base substrate and a plurality of pixel units arranged on the base substrate, each of the pixel units includes:
    发光装置,所述发光装置包括:Light emitting device, the light emitting device includes:
    发光单元;Light-emitting unit
    驱动电路,设置在所述发光单元的靠近所述衬底基板的一侧并且配置为与所述发光单元电连接;A driving circuit, which is arranged on a side of the light-emitting unit close to the base substrate and is configured to be electrically connected to the light-emitting unit;
    指纹识别装置,所述指纹识别装置包括超声波指纹识别传感器,所述超声波指纹识别传感器包括压电薄膜层,所述压电薄膜层位于所述发光单元和所述驱动电路之间并且延伸跨过该每个像素单元,所述发光单元配置为贯穿所述压电薄膜层并且与所述驱动电路电连接。A fingerprint recognition device, the fingerprint recognition device includes an ultrasonic fingerprint recognition sensor, the ultrasonic fingerprint recognition sensor includes a piezoelectric film layer, the piezoelectric film layer is located between the light-emitting unit and the drive circuit and extends across the For each pixel unit, the light emitting unit is configured to penetrate the piezoelectric film layer and is electrically connected to the driving circuit.
  2. 根据权利要求1所述的显示基板,其中所述超声波指纹识别传感器还包括驱动电极和接收电极,所述驱动电极位于所述压电薄膜层的远离所述衬底基板的一侧并且配置为向所述显示基板的显示侧发出超声波信号,所述接收电极位于所述压电薄膜层的靠近所述衬底基板的一侧并且配置为接收被指纹反射回来的超声波信号。The display substrate according to claim 1, wherein the ultrasonic fingerprint recognition sensor further comprises a driving electrode and a receiving electrode, the driving electrode is located on a side of the piezoelectric film layer away from the base substrate and is configured to face The display side of the display substrate emits an ultrasonic signal, and the receiving electrode is located on a side of the piezoelectric film layer close to the base substrate and is configured to receive the ultrasonic signal reflected by the fingerprint.
  3. 根据权利要求2所述的显示基板,其中所述超声波指纹识别传感器还包括引出电极,所述引出电极和所述接收电极位于所述压电薄膜层的同一侧并且配置为与所述驱动电极电连接,所述驱动电极贯穿所述压电薄膜层与所述引出电极电连接。The display substrate according to claim 2, wherein the ultrasonic fingerprint recognition sensor further comprises an extraction electrode, and the extraction electrode and the receiving electrode are located on the same side of the piezoelectric film layer and configured to be electrically connected to the driving electrode. Connected, the driving electrode penetrates the piezoelectric film layer and is electrically connected to the lead electrode.
  4. 根据权利要求3所述的显示基板,其中所述引出电极在所述衬底基板上的正投影与所述接收电极在所述衬底基板上的正投影之间没有重叠区域。3. The display substrate of claim 3, wherein there is no overlapping area between the orthographic projection of the extraction electrode on the base substrate and the orthographic projection of the receiving electrode on the base substrate.
  5. 根据权利要求2至4任一项所述的显示基板,其中所述指纹识别装置还包括处理电路,所述处理电路位于所述接收电极与所述衬底基板之间并且与所述接收电极电连接,所述处理电路配置为接收并且处理来自所述接收电极的电信号。The display substrate according to any one of claims 2 to 4, wherein the fingerprint identification device further comprises a processing circuit located between the receiving electrode and the base substrate and electrically connected to the receiving electrode Connected, the processing circuit is configured to receive and process the electrical signal from the receiving electrode.
  6. 根据权利要求1至5任一项所述的显示基板,其中所述发光单元包括阳极、有机发光功能层和阴极,所述阳极位于所述压电薄膜层的远离所述衬底基板的一侧,所述有机发光功能层位于所述阳极的远离所述衬底基板的一侧,所述阴极位于所述有机发光功能层的远离所述衬底基板的一侧。The display substrate according to any one of claims 1 to 5, wherein the light-emitting unit comprises an anode, an organic light-emitting function layer, and a cathode, and the anode is located on a side of the piezoelectric thin film layer away from the base substrate The organic light-emitting function layer is located on the side of the anode away from the base substrate, and the cathode is located on the side of the organic light-emitting function layer away from the base substrate.
  7. 根据权利要求6所述的显示基板,其中所述阳极与所述驱动电极均位于所述压电薄膜层上且与该压电薄膜层接触,所述阳极贯穿所述压电薄膜层与所述驱动电路电连接。7. The display substrate of claim 6, wherein the anode and the driving electrode are both located on and in contact with the piezoelectric film layer, and the anode penetrates the piezoelectric film layer and the piezoelectric film layer. The drive circuit is electrically connected.
  8. 根据权利要求1至7任一项所述的显示基板,其中所述驱动电路包括:8. The display substrate according to any one of claims 1 to 7, wherein the driving circuit comprises:
    设置在所述衬底基板上的第一有源层;A first active layer provided on the base substrate;
    覆盖所述第一有源层的第一绝缘层;A first insulating layer covering the first active layer;
    设置在所述第一绝缘层上的第一栅电极;A first gate electrode provided on the first insulating layer;
    覆盖所述第一栅电极的第二绝缘层;和A second insulating layer covering the first gate electrode; and
    设置在所述第二绝缘层上的第一漏电极和第一源电极,A first drain electrode and a first source electrode provided on the second insulating layer,
    其中所述第一漏电极和所述第一源电极分别通过过孔与所述第一有源层内的掺杂区电连接,所述发光单元的阳极配置为贯穿所述压电薄膜层并且与所述第一漏电极电连接。The first drain electrode and the first source electrode are respectively electrically connected to the doped region in the first active layer through via holes, and the anode of the light-emitting unit is configured to penetrate the piezoelectric film layer and It is electrically connected to the first drain electrode.
  9. 根据权利要求8所述的显示基板,其中所述驱动电路还包括:The display substrate according to claim 8, wherein the driving circuit further comprises:
    覆盖所述第一漏电极和所述第一源电极的第三绝缘层;A third insulating layer covering the first drain electrode and the first source electrode;
    设置在所述第三绝缘层上的第二连接电极,所述第二连接电极通过过孔与所述第一漏电极电连接;A second connection electrode provided on the third insulating layer, the second connection electrode being electrically connected to the first drain electrode through a via;
    覆盖所述第二连接电极的平坦层;A flat layer covering the second connection electrode;
    设置在所述平坦层上的第一保护层;A first protective layer provided on the flat layer;
    设置在所述第一保护层上的第四连接电极,所述第四连接电极通过过孔与所述第二连接电极电连接,A fourth connection electrode disposed on the first protection layer, the fourth connection electrode is electrically connected to the second connection electrode through a via hole,
    其中所述发光单元的所述阳极配置为贯穿所述压电薄膜层与所述第四连接电极电连接。The anode of the light-emitting unit is configured to penetrate the piezoelectric film layer and be electrically connected to the fourth connecting electrode.
  10. 根据权利要求9所述的显示基板,其中所述指纹识别装置还包括处理电路,所述处理电路位于所述接收电极与所述衬底基板之间并且与所述接收电极电连接,所述处理电路配置为接收并且处理来自所述接收电极的电信号。The display substrate according to claim 9, wherein the fingerprint identification device further comprises a processing circuit located between the receiving electrode and the base substrate and electrically connected to the receiving electrode, the processing circuit The circuit is configured to receive and process the electrical signal from the receiving electrode.
  11. 根据权利要求10所述的显示基板,其中所述处理电路包括:The display substrate according to claim 10, wherein the processing circuit comprises:
    设置在所述衬底基板上的第二有源层,所述第一绝缘层还覆盖所述第二有源层;A second active layer provided on the base substrate, the first insulating layer also covering the second active layer;
    设置在所述第一绝缘层上的第二栅电极,所述第二绝缘层还覆盖所述第二栅电极;和A second gate electrode provided on the first insulating layer, the second insulating layer also covering the second gate electrode; and
    设置在所述第二绝缘层上的第二漏电极、第一连接电极和第二源电极,所述第二漏电极和所述第二源电极分别通过过孔与第二有源层内的掺杂区电连接,所述第一连接电极通过过孔与第二栅电极电连接,所述第三绝缘层还覆盖所述第二漏电极、所述第一连接电极和所述第二源电极,The second drain electrode, the first connection electrode and the second source electrode are arranged on the second insulating layer, and the second drain electrode and the second source electrode pass through the via hole and the second active layer. The doped region is electrically connected, the first connection electrode is electrically connected to the second gate electrode through a via hole, and the third insulating layer also covers the second drain electrode, the first connection electrode and the second source electrode,
    其中,所述接收电极设置在所述第三绝缘层上,所述接收电极通过过孔与所述第一连接电极电连接。Wherein, the receiving electrode is disposed on the third insulating layer, and the receiving electrode is electrically connected to the first connecting electrode through a via hole.
  12. 根据权利要求11所述的显示基板,其中所述处理电路还包括:The display substrate according to claim 11, wherein the processing circuit further comprises:
    设置在所述第三绝缘层上的第三连接电极,所述第三连接电极通过过孔与所述第一连接电极电连接,所述平坦层还覆盖所述第三连接电极;A third connection electrode disposed on the third insulating layer, the third connection electrode is electrically connected to the first connection electrode through a via hole, and the flat layer also covers the third connection electrode;
    设置在所述第一保护层上的所述接收电极,所述接收电极通过过孔与所述第三连接电极电连接。The receiving electrode provided on the first protective layer is electrically connected to the third connecting electrode through a via hole.
  13. 根据权利要求1至12任一项所述的显示基板,其中所述衬底基板的材料包括超声波吸收材料。The display substrate according to any one of claims 1 to 12, wherein the material of the base substrate includes an ultrasonic absorbing material.
  14. 一种显示装置,包括权利要求1至13任一项所述的用于超声波指纹识别的显示基板。A display device, comprising the display substrate for ultrasonic fingerprint identification according to any one of claims 1 to 13.
  15. 根据权利要求14所述的显示装置,其中所述显示装置包括有机发光二极管显示装置。The display device according to claim 14, wherein the display device comprises an organic light emitting diode display device.
  16. 一种用于超声波指纹识别的显示基板的制造方法,包括:A manufacturing method of a display substrate for ultrasonic fingerprint recognition, including:
    提供衬底基板,所述衬底基板包括多个像素区;Providing a base substrate, the base substrate including a plurality of pixel regions;
    在每个所述像素区中形成发光单元;Forming a light emitting unit in each of the pixel regions;
    在每个所述像素区中的所述发光单元的靠近所述衬底基板的一侧形成驱动电路,所述驱动电路配置为与所述发光单元电连接;以及Forming a drive circuit on a side of the light emitting unit in each of the pixel regions close to the base substrate, the drive circuit being configured to be electrically connected to the light emitting unit; and
    在每个所述像素区中的所述发光单元和所述驱动电路之间形成压电薄膜层,所述压电薄膜层延伸跨过该每个像素单元,所述发光单元配置为贯穿所述压电薄膜层并且与所述驱动电路电连接。A piezoelectric film layer is formed between the light emitting unit and the driving circuit in each pixel area, the piezoelectric film layer extends across each pixel unit, and the light emitting unit is configured to penetrate through the The piezoelectric film layer is electrically connected to the driving circuit.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113327953A (en) * 2021-05-11 2021-08-31 武汉华星光电技术有限公司 Display panel
US20240036670A1 (en) * 2021-12-07 2024-02-01 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and mobile terminal

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109993156B (en) * 2019-04-24 2022-09-06 京东方科技集团股份有限公司 Ultrasonic fingerprint identification panel and display device
CN110112202B (en) * 2019-05-24 2021-04-30 京东方科技集团股份有限公司 Display substrate and preparation method thereof
US11657638B2 (en) * 2019-09-27 2023-05-23 Boe Technology Group Co., Ltd. Ultrasonic fingerprint sensor apparatus, method of operating ultrasonic fingerprint sensor apparatus, and method of fabricating ultrasonic fingerprint sensor apparatus
US11997891B2 (en) 2020-03-24 2024-05-28 Boe Technology Group Co., Ltd. Display substrate, fabricating method thereof and display panel
CN114628610B (en) * 2020-03-25 2023-09-12 京东方科技集团股份有限公司 Display substrate and display device
CN111524461A (en) * 2020-04-27 2020-08-11 武汉华星光电半导体显示技术有限公司 Display module and preparation method thereof
KR102675926B1 (en) * 2020-06-30 2024-06-17 엘지디스플레이 주식회사 Display apparatus
CN111814712B (en) * 2020-07-15 2024-07-16 京东方科技集团股份有限公司 Line recognition device and display equipment
CN111799388B (en) * 2020-08-24 2023-05-19 京东方科技集团股份有限公司 Display backboard, manufacturing method thereof and display device
CN114531921A (en) * 2020-08-31 2022-05-24 京东方科技集团股份有限公司 Display substrate, preparation method thereof and display device
CN112038380B (en) * 2020-09-08 2023-04-07 京东方科技集团股份有限公司 Display substrate and display device
CN112633166B (en) * 2020-12-23 2022-12-09 厦门天马微电子有限公司 Ultrasonic fingerprint identification module, display module and electronic equipment
CN112701149B (en) * 2020-12-29 2022-08-02 湖北长江新型显示产业创新中心有限公司 Display panel and display device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11212002A (en) * 1998-01-23 1999-08-06 Seiko Epson Corp Spatial optical modulator and projection type display device
CN107402662A (en) * 2016-05-18 2017-11-28 株式会社日本显示器 Display device
CN207254707U (en) * 2017-04-14 2018-04-20 杭州士兰微电子股份有限公司 Ultrasonic transducer and ultrasonic fingerprint sensor
CN108899353A (en) * 2018-07-26 2018-11-27 京东方科技集团股份有限公司 Oled display substrate and preparation method thereof, display device
CN109492460A (en) * 2017-09-12 2019-03-19 南昌欧菲生物识别技术有限公司 Display module and electronic device
CN110112202A (en) * 2019-05-24 2019-08-09 京东方科技集团股份有限公司 Display base plate and preparation method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9262003B2 (en) * 2013-11-04 2016-02-16 Qualcomm Incorporated Piezoelectric force sensing array
CN106446817B (en) * 2016-09-18 2018-03-20 京东方科技集团股份有限公司 Fingerprint recognition device, touch display panel and fingerprint recognition device driving method
KR102295068B1 (en) * 2017-03-31 2021-08-31 삼성디스플레이 주식회사 Display device and method of driving the display device
CN107425038B (en) * 2017-06-09 2020-01-21 武汉天马微电子有限公司 Organic light-emitting display panel, manufacturing method thereof and electronic device
MY191624A (en) * 2017-09-29 2022-07-04 Silterra Malaysia Sdn Bhd Monolithic integration of pmut on cmos
CN108052930B (en) * 2018-01-02 2022-06-21 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof, display panel and display device
CN109244108B (en) * 2018-08-29 2020-11-03 京东方科技集团股份有限公司 OLED display substrate, manufacturing method thereof and OLED display device
CN109614963B (en) * 2019-01-28 2023-08-29 京东方科技集团股份有限公司 Fingerprint identification structure and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11212002A (en) * 1998-01-23 1999-08-06 Seiko Epson Corp Spatial optical modulator and projection type display device
CN107402662A (en) * 2016-05-18 2017-11-28 株式会社日本显示器 Display device
CN207254707U (en) * 2017-04-14 2018-04-20 杭州士兰微电子股份有限公司 Ultrasonic transducer and ultrasonic fingerprint sensor
CN109492460A (en) * 2017-09-12 2019-03-19 南昌欧菲生物识别技术有限公司 Display module and electronic device
CN108899353A (en) * 2018-07-26 2018-11-27 京东方科技集团股份有限公司 Oled display substrate and preparation method thereof, display device
CN110112202A (en) * 2019-05-24 2019-08-09 京东方科技集团股份有限公司 Display base plate and preparation method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113327953A (en) * 2021-05-11 2021-08-31 武汉华星光电技术有限公司 Display panel
US12087080B2 (en) 2021-05-11 2024-09-10 Wuhan China Star Optoelectronics Technology Co., Ltd. Display panel
US20240036670A1 (en) * 2021-12-07 2024-02-01 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and mobile terminal
US12026331B2 (en) * 2021-12-07 2024-07-02 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Display panel and mobile terminal

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