WO2020237717A1 - SOI器件的kink电流计算方法及装置 - Google Patents

SOI器件的kink电流计算方法及装置 Download PDF

Info

Publication number
WO2020237717A1
WO2020237717A1 PCT/CN2019/090565 CN2019090565W WO2020237717A1 WO 2020237717 A1 WO2020237717 A1 WO 2020237717A1 CN 2019090565 W CN2019090565 W CN 2019090565W WO 2020237717 A1 WO2020237717 A1 WO 2020237717A1
Authority
WO
WIPO (PCT)
Prior art keywords
channel
soi device
long
soi
gate voltages
Prior art date
Application number
PCT/CN2019/090565
Other languages
English (en)
French (fr)
Inventor
王明湘
陈言言
张冬利
王槐生
Original Assignee
苏州大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 苏州大学 filed Critical 苏州大学
Priority to US16/959,633 priority Critical patent/US11442097B2/en
Publication of WO2020237717A1 publication Critical patent/WO2020237717A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G01R31/2623—Circuits therefor for testing field effect transistors, i.e. FET's for measuring break-down voltage therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2637—Circuits therefor for testing other individual devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/10—Noise analysis or noise optimisation

Definitions

  • This application relates to the technical field of semiconductor devices, and in particular to a method and device for calculating kink current of SOI devices.
  • Silicon on Insulator refers to a silicon transistor structure built on an insulator substrate. SOI devices are similar in structure to MOSFETs, and they are both field-effect devices, but SOI devices are fabricated on an insulating substrate unlike MOSFETs on a semiconductor substrate. Broadly speaking, “Silicon” represents the channel layer of SOI devices, which can be not only single crystal silicon, but also amorphous silicon, polycrystalline silicon, oxide semiconductors, organic semiconductors, etc.; “Insulator” represents the insulating layer lining of SOI devices The bottom can be insulating materials such as glass, quartz, or a silicon substrate covered with a thin SiO 2 layer.
  • the existing kink current calculation methods for SOI devices include:
  • the multiplication factor M is obtained by integrating the collision ionization rate in the drain depletion zone along the depletion zone.
  • the relationship between kink current and multiplication factor M is:
  • I Dsat is the saturation current of the drain terminal
  • M is the multiplication factor
  • the multiplying factor M in method 2 relies on an empirical formula, which is a semi-empirical model and cannot be well applied to the output characteristic curve under the conditions of various gate voltages V gs .
  • the embodiments of the present application provide a method and apparatus for calculating kink current of SOI devices to solve the problem of large errors in the method of calculating kink current of SOI devices in the prior art.
  • the method includes:
  • the kink current of the SOI device is calculated.
  • obtaining the parasitic transistor function factor of the SOI device specifically includes:
  • the channel length and the carrier diffusion length in the body region of the SOI device are obtained, and the parasitic transistor action factor of the SOI device is calculated according to the channel length and the carrier diffusion length in the body region.
  • the parasitic transistor action factor of the SOI device and the channel length of the SOI device and the carrier diffusion length in the body region are in a hyperbolic secant dependence
  • the parasitic transistor action factor is:
  • L is the channel length of the SOI device
  • L b is the carrier diffusion length in the body region of the SOI device.
  • the impact ionization factor of the SOI device is an interpolation related to the threshold electric field F I , the width of the depletion region I d , the drain voltage V D and the drain saturation voltage of the SOI device for impact ionization of the SOI device Function V Dse index correlation;
  • the impact ionization factor is:
  • the impact ionization factor of the SOI device is related to the voltage parameter V k related to the SOI device kink effect, the drain terminal voltage V D, and the drain terminal saturation voltage related interpolation function V Dse index;
  • the impact ionization factor is:
  • the method for calculating the kink current I kink of the SOI device is:
  • C is the parameter related to the material and geometric size of the SOI device
  • L is the channel length of the SOI device
  • V D is the drain voltage of the SOI device
  • V Dse is the interpolation function related to the drain saturation voltage
  • F I is the occurrence of the SOI device.
  • L b is the carrier diffusion length in the body region of the SOI device
  • I Dsat is the saturation current of the drain terminal of the SOI device
  • the kink current I kink calculation method of the SOI device is:
  • C k is the parameter related to the material and geometric size of the SOI device
  • L is the channel length of the SOI device
  • V D is the drain voltage of the SOI device
  • V Dse is the interpolation function related to the drain saturation voltage
  • V k is the SOI device
  • L b is the carrier diffusion length in the body region of the SOI device
  • I Dsat is the saturation current at the drain of the SOI device.
  • the method further includes the steps:
  • the method also includes the steps:
  • the method also includes the steps:
  • the method further includes the steps:
  • the threshold electric fields for collision and ionization of the long-channel SOI devices under multiple gate voltages are respectively averaged to obtain the preliminary simulations of the threshold electric fields F I of the multiple long-channel SOI devices in formula (1). Combined value; and/or,
  • the C parameter extraction step is repeated to obtain the fitting value of the C parameter in the formula (1) under the multiple gate voltages of the multiple long-channel devices.
  • the method further includes the steps:
  • the multiple V k of a long-channel SOI device under multiple gate voltages According to the drain current I D and the drain saturation current I Dsat of the multiple long-channel SOI devices under multiple gate voltages , and the function of V k as the slope in the long-channel SOI device, the multiple V k of a long-channel SOI device under multiple gate voltages; preferably,
  • the method also includes the steps:
  • V k the carrier diffusion lengths L b and C k in the body region of the multiple long-channel SOI devices under multiple gate voltages as the slope and ln(2C k ) as a function of the intercept.
  • it further includes:
  • An embodiment of the present application also provides a kink current calculation device for an SOI device, including:
  • the acquisition module is used to acquire the impact ionization factor, parasitic transistor action factor, and drain saturation current of the SOI device respectively;
  • the calculation module is used to calculate the kink current of the SOI device according to the impact ionization factor, the parasitic transistor action factor, and the drain saturation current.
  • An embodiment of the present application also provides a kink current calculation device for an SOI device, including:
  • the memory is arranged to store computer executable instructions, and the processor executes the executable instructions to implement the kink current calculation method of the SOI device as described above.
  • the calculated kink current of the SOI device is more accurate, and Without introducing any empirical parameters, it has a good fitting effect under different grid voltages; at the same time, the parameters used in the calculation method are easy to extract and are suitable for circuit simulation.
  • Figure 1 is a schematic diagram of the kink current in an SOI device
  • Figure 2 is a schematic diagram of Jacunski et al. using the RPI model for fitting in the background art
  • Figure 3 is a schematic diagram of the applicant using the RPI model for fitting
  • FIG. 10 is a schematic structural diagram of a device provided by an embodiment of this application.
  • FIG. 11 is a block diagram of a kink current calculation device of an SOI device provided by an embodiment of the application.
  • the method includes:
  • the drain terminal of the SOI device When the drain terminal of the SOI device is biased at a large voltage, a large number of electron-hole pairs are generated by collision ionization in the drain depletion region, which is enhanced by the parasitic transistor effect, and additional positive feedback occurs in the body region. Therefore, by adding the impact ionization factor and the parasitic transistor action factor in the kink current calculation of the SOI device, the two influencing factors that affect the kink current in the SOI device can be better explained, making the calculated kink current of the SOI device more accurate.
  • the channel length of the SOI device and the carrier diffusion length in the body region can be obtained, and the parasitic transistor action factor of the SOI device can be calculated according to the channel length and the carrier diffusion length in the body region, and SOI
  • the parasitic transistor effect factor of the device has a hyperbolic secant dependence on the channel length of the SOI device and the carrier diffusion length in the body region.
  • the carrier diffusion length in the body region corresponds to the electron diffusion length; accordingly, if the N-type SOI device is shown For devices, the carrier diffusion length in the body region corresponds to the hole diffusion length.
  • the parasitic transistor action factor of the SOI device is:
  • L is the channel length of the SOI device
  • L b is the carrier diffusion length in the body region of the SOI device.
  • the impact ionization factor of the SOI device is related to the threshold electric field F I for the impact ionization of the SOI device, the depletion region width l d , the drain voltage V D and the drain saturation voltage related interpolation function V Dse index.
  • the impact ionization factor is:
  • the impact ionization factor of the SOI device is related to the SOI device's voltage parameter V k related to the kink effect, the drain terminal voltage V D, and the drain terminal saturation voltage related interpolation function V Dse index;
  • the impact ionization factor is:
  • the kink current I kink calculation method of SOI device is:
  • C is the parameter related to the material and geometric size of the SOI device
  • L is the channel length of the SOI device
  • V D is the drain voltage of the SOI device
  • V Dse is the interpolation function related to the drain saturation voltage (in the linear region close to the drain).
  • V D is close to the drain terminal saturation voltage V Dsat in the saturation region
  • l d is the width of the depletion region of the SOI device
  • F I is the threshold electric field for collision ionization of the SOI device
  • L b is the carriers in the body of the SOI device Diffusion length
  • I Dsat is the saturation current at the drain of the SOI device
  • sech(x) is the hyperbolic secant function
  • the channel length L is much larger than the carrier diffusion length L b in the body region, so:
  • the kink current calculation method of the above SOI device can be changed to:
  • the kink current and the channel length L of the SOI device can be further approximated as an exponential dependence, and the SOI device kink current calculation method is all based on Physical parameters do not involve empirical parameters, making it more accurate and reliable.
  • the aforementioned C parameter may be
  • I 0 is the reverse saturation current of the SOI device
  • ⁇ b is the carrier lifetime in the body region
  • A is the area of the collision ionization zone
  • E I is the threshold energy for collision ionization
  • n i is the intrinsic carrier concentration.
  • the expression of the drain saturation current I Dsat of the SOI device is:
  • W is the width of the SOI device
  • L is the channel length of the SOI device
  • l d is the width of the depletion region
  • ⁇ eff is the effective channel mobility
  • C ox is the gate oxide capacitance per unit area
  • V Dse is a drain saturation
  • E sat is the characteristic electric field of the velocity saturation effect
  • V GT is the effective gate voltage.
  • the expression of the drain saturation current I Dsat of the SOI device may also be:
  • ⁇ FET is the field effect mobility
  • C ox is the gate oxide capacitance per unit area
  • W is the width of the SOI device
  • L is the channel length of the SOI device
  • V GS is the gate terminal voltage
  • V t is the threshold voltage
  • ⁇ sat is Parameters related to pinch-off of the drain end.
  • the method further includes a parameter extraction and fitting step of the threshold electric field F I, a parameter extraction and fitting step of the carrier diffusion length L b in the body region, and a C parameter extraction and fitting step.
  • the above steps are all based on a group of polysilicon thin film transistors with the same width W but different channel lengths L. specifically,
  • the multiple The threshold electric field for collision and ionization of long-channel SOI devices under multiple gate voltages According to the drain current I D and the drain saturation current I Dsat of multiple long-channel SOI devices under multiple gate voltages , and the function of the threshold electric field F I as the slope in the long-channel SOI device, the multiple The threshold electric field for collision and ionization of long-channel SOI devices under multiple gate voltages.
  • the channel length L is much larger than the carrier diffusion length L b in the body region, so
  • I kink I D -I Dsat . Equation (1) can be transformed into
  • the carrier diffusion length in the body region of the multiple long-channel SOI devices under multiple gate voltages is calculated.
  • the formula (1) can be transformed into
  • the slope of the Y ⁇ L curve is Using the threshold electric field for collision and ionization of multiple long-channel SOI devices extracted in step S101 under multiple gate voltages, find the average value of the same SOI device under different gate voltages, and substitute them into the above equations. The carrier diffusion length of multiple long-channel SOI devices in the body region under multiple gate voltages is obtained.
  • the threshold electric fields of the long-channel SOI devices undergoing collision and ionization under multiple gate voltages are respectively averaged, and the threshold electric fields F I of the multiple long-channel SOI devices in the formula (1) are obtained. Preliminary fitting value.
  • the obtained preliminary fitting value of the C parameter is substituted into equation (1), and according to the average value of the carrier diffusion length of the multiple long-channel SOI devices in the body region under multiple gate voltages, it is determined that each SOI device is in multiple
  • the threshold electric field at which collision ionization occurs under the gate voltage is used as the fitting value of the threshold electric field F I of each long-channel SOI device in formula (1);
  • the above-mentioned C parameter extraction step is repeated to obtain the fitting value of the C parameter in formula (1) for the multiple long-channel devices under multiple gate voltages.
  • the threshold electric field F I obtained by fitting has a linear dependence on the channel length L, and the kink current of other SOI devices of the same process and the same width can be calculated based on this.
  • the technical solution of the present application may also include the threshold electric field F I , the carrier diffusion length L b in the body region, and the fitting values of the three parameters C obtained in the above steps. Enter the equation (1), and iterate the steps of parameter extraction and parameter fitting mentioned above for many times to obtain the threshold electric field F I , the carrier diffusion length L b in the body region, and the three parameters of C in the equation (1) In this case, the fitting value of the satisfactory fitting effect is further approximated, and this embodiment should still fall within the concept of this application.
  • Aspect ratio 10/25 ⁇ m, 10/20 ⁇ m, 10/15 ⁇ m and 10/10 ⁇ m.
  • V gs -3.5, -4, -4.5, -5V.
  • the fitted value of the carrier diffusion length L b in the body region (here the carrier diffusion length refers to the electron diffusion length) (because the extracted value of L b under different gate voltages is close, the average value is taken as the value of L b Fitting values) are as follows:
  • the same set of C values can be used for SOI devices with different aspect ratios, and C has a linear dependence on the gate voltage V gs , and the carrier diffusion length L b uses a fixed fitting value, the threshold The electric field F I is also the same at different gate voltages. Specifically, the relationship between the threshold electric field F I and the channel length L is shown in Figure 5.
  • F I k 1 ⁇ L+b 1
  • F I k 1 ⁇ L+b 1
  • k 1 -6 ⁇ 10 7 V/cm 2
  • b 1 3.6 ⁇ 10 5 V/cm
  • MILC N-type metal-induced lateral crystallization process
  • Aspect ratio 10/25 ⁇ m, 10/20 ⁇ m, 10/15 ⁇ m and 10/10 ⁇ m.
  • V gs 11, 12, 13, 14V.
  • the kink current calculation method provided by the present invention is extremely effective in both the low defect density excimer laser annealing (ELA) and the high defect density metal induced lateral crystallization (MILC) devices. Good fitting effect. Similarly, there is also a good fitting effect on partially depleted SOI devices with fewer defective states, which will not be repeated here.
  • the kink current I kink calculation method of SOI device is:
  • C k is a parameter related to the material and geometric dimensions of the SOI device
  • L is the channel length of the SOI device
  • V D is the drain voltage of the SOI device
  • V Dse is the interpolation function related to the drain saturation voltage (close to the drain in the linear region).
  • the terminal voltage V D is close to the drain terminal saturation voltage V Dsat in the saturation region.
  • V k is the voltage parameter related to the kink effect of the SOI device
  • L b is the carrier diffusion length in the body region of the SOI device
  • I Dsat is the drain of the SOI device.
  • Terminal saturation current, sech(x) is hyperbolic secant function
  • the channel length L is much larger than the carrier diffusion length L b in the body region, so:
  • the kink current calculation method of the above SOI device can be changed to:
  • the kink current and the channel length L of the SOI device can be further approximated as an exponential dependence, and the SOI device kink current calculation method is all based on physical Parameters do not involve experience parameters, more accurate and reliable.
  • the selection of the drain saturation current I Dsat of the SOI device can refer to the first embodiment, which will not be repeated here.
  • the method further includes a parameter extraction and fitting step of V k, a parameter extraction and fitting step of the carrier diffusion length L b in the body region, and a parameter extraction and fitting step of C k .
  • the above steps are all based on a group of polysilicon thin film transistors with the same width W but different channel lengths L. specifically,
  • the multiple Long-channel SOI device V k According to the drain current I D and the drain saturation current I Dsat of the multiple long-channel SOI devices under multiple gate voltages , and the function of the threshold electric field V k as the slope in the long-channel SOI device, the multiple Long-channel SOI device V k at multiple gate voltages.
  • the channel length L is much larger than the carrier diffusion length L b in the body region, so
  • I kink I D -I Dsat . Equation (2) can be transformed into
  • V k is the slope can be determined in a plurality of the plurality of gate voltages V k long channel SOI devices.
  • V k the carrier diffusion lengths L b and C k in the body region of the multiple long-channel SOI devices under multiple gate voltages as the slope and ln(2C k ) as a function of the intercept.
  • the formula (2) can be transformed into
  • the slope of the Y ⁇ L curve is The intercept is ln(2C k ).
  • S204 averaging the carrier diffusion length in the body region of the multiple long-channel SOI devices under multiple gate voltages to obtain a fitted value of the carrier diffusion length L b in the body region in formula (2).
  • the fitted values of the three parameters V k , the carrier diffusion length L b in the body region, and C k can be obtained.
  • the L b and C k obtained by the fitting are kept constant, and V k has a certain linear dependence on the channel length L and the gate voltage V g . Based on this, the kink current of other SOI devices of the same process and the same width can be calculated.
  • the fitting values of the three parameters V k , carrier diffusion length L b in the body region, and C k can be further brought into equation (2) , And iterate the steps of parameter extraction and parameter fitting mentioned above for many times to obtain the three parameters of V k , carrier diffusion length L b in the body region, and C k .
  • equation (2) the satisfactory fitting effect is further approximated The fitted value.
  • Aspect ratio 10/25 ⁇ m, 10/20 ⁇ m, 10/15 ⁇ m and 10/10 ⁇ m.
  • V gs -3.5, -4, -4.5, -5V.
  • Fig. 10 is a schematic structural diagram of a device according to an exemplary embodiment. Please refer to Figure 10.
  • the device includes a processor, internal bus, network interface, memory, and non-volatile memory. Of course, it may also include hardware required for other services.
  • the processor reads the corresponding computer program from the non-volatile memory to the memory and then runs it to form the kink current calculation device of the SOI device on the logical level.
  • one or more embodiments of this specification do not exclude other implementations, such as logic devices or a combination of software and hardware, etc., which means that the execution body of the following processing flow is not limited to each
  • the logic unit can also be hardware or logic devices.
  • the kink current calculation device of the SOI device includes an acquisition module 301 and a calculation module 302.
  • the obtaining module 301 is used to obtain the impact ionization factor, the parasitic transistor action factor, and the drain saturation current of the SOI device; the calculation module 302 is used to obtain the impact ionization factor, the parasitic transistor action factor, and the drain saturation current Calculate the kink current of the SOI device.
  • the kink current calculation device of the SOI device substantially corresponds to the kink current calculation method of the SOI device mentioned in the above-mentioned embodiment, and will not be repeated here.
  • a typical implementation device is a computer.
  • the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.
  • the computer includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.
  • processors CPU
  • input/output interfaces network interfaces
  • memory volatile and non-volatile memory
  • the memory may include non-permanent memory in computer readable media, random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). Memory is an example of computer readable media.
  • RAM random access memory
  • ROM read-only memory
  • flash RAM flash memory
  • Computer-readable media include permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology.
  • the information can be computer-readable instructions, data structures, program modules, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc (DVD) or other optical storage, Magnetic cassettes, magnetic disk storage, quantum memory, graphene-based storage media or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices. According to the definition in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.
  • first, second, third, etc. may be used in one or more embodiments of this specification to describe various information, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other.
  • first information may also be referred to as second information, and similarly, the second information may also be referred to as first information.
  • word “if” as used herein can be interpreted as "when” or “when” or "in response to determination”.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本申请公开了一种SOI器件的kink电流计算方法和装置，用以解决现有技术中kink电流计算不精准，不适合电路仿真的问题。该方法包括：分别获取SOI器件的碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流；根据碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流，计算SOI器件的kink电流。

Description

SOI器件的kink电流计算方法及装置 技术领域
本申请涉及半导体器件技术领域，尤其涉及一种SOI器件的kink电流计算方法及装置。
背景技术
绝缘层上硅(Silicon on Insulator，SOI)是指硅晶体管结构做在绝缘体衬底上。SOI器件与MOSFET结构类似，都属于场效应器件，但SOI器件制作于绝缘衬底上而不像MOSFET制作于半导体衬底上。广泛来说，“Silicon”代表SOI器件的沟道层，其不仅仅可以为单晶硅，也可以是非晶硅、多晶硅、氧化物半导体、有机半导体等；“Insulator”代表SOI器件的绝缘层衬底，可以为玻璃、石英或是覆盖薄SiO 2层的硅衬底等绝缘材料。当SOI器件漏端偏置在一足够大电压时，其输出曲线会出现电流突增的现象，即kink效应，这部分多出的电流称为kink电流，ΔI kink，如图1所示。一个准确的、基于物理的kink电流解析模型对于电路设计和仿真是非常关键的。
现有的SOI器件的kink电流计算方法包括：
①基于浮体效应，把背沟道中所有的电流成分都考虑进去，但涉及的模型参数较多，电流形式较复杂，不适合用于电路仿真。
②通过计算倍增因子M来建模，比如RPI模型。在Jacunski等人的工作中，通过将漏端耗尽区内的碰撞离化率沿着耗尽区进行积分得到倍增因子M。其中，kink电流与倍增因子M之间的关系是：
I kink＝M·I Dsat
其中I Dsat是漏端饱和电流，M为倍增因子。
倍增因子M的表达式是：
Figure PCTCN2019090565-appb-000001
其中L kink和m kink都为经验参数，L为沟道长度，V D为漏端所加电压，V kink是kink效应发生时的漏端电压，V GT＝V GS-V T为有效栅电压(V GS为栅压，V T为阈值电压)，α sat是与漏端夹断有关的参数。
方法②中的倍增因子M依赖于经验公式，是一个半经验化的模型，不能很好地适用于多种栅压V gs条件下的输出特性曲线。如图2所示，实验对象为P型多晶硅薄膜晶体管，五条输出特性曲线由下至上分别对应于栅压V gs＝-2，-4，-6，-8，-10V。本申请人在使用此模型进行拟合时，也发现了同样的缺点，如图3所示，实验对象为P型多晶硅薄膜晶体管，四条输出特性曲线由下至上分别对应于栅压V gs＝-3.5，-4，-4.5，-5V。
因此，如何准确对SOI器件的kink电流进行建模计算是当前亟需解决的问题。
发明内容
本申请实施例提供一种SOI器件的kink电流计算方法和装置，用以解决现有技术中SOI器件的kink电流计算方法误差较大的问题，所述方法包括：
分别获取SOI器件的碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流；
根据所述碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流，计算所述SOI器件的kink电流。
一实施例中，获取所述SOI器件的寄生晶体管作用因子具体包括：
获取所述SOI器件的沟道长度以及体区内载流子扩散长度，并根据所述沟道长度以及体区内载流子扩散长度计算所述SOI器件的寄生晶体管作用因子。
一实施例中，所述SOI器件的寄生晶体管作用因子与所述SOI器件的沟道长度以及体区内载流子扩散长度为双曲正割依赖关系；
优选地，所述寄生晶体管作用因子为：
Figure PCTCN2019090565-appb-000002
其中L为SOI器件的沟道长度，L b为SOI器件的体区内载流子扩散长度。
一实施例中，所述SOI器件的碰撞离化作用因子与所述SOI器件发生碰撞离化的阈值电场F I、耗尽区宽度I d、漏端电压V D以及漏端饱和电压相关的插值函数V Dse指数相关；
优选地，所述碰撞离化作用因子为：
Figure PCTCN2019090565-appb-000003
或，所述SOI器件的碰撞离化作用因子与所述SOI器件kink效应相关的电压参数V k、漏端电压V D以及漏端饱和电压相关的插值函数V Dse指数相关；
优选地，所述碰撞离化作用因子为：
Figure PCTCN2019090565-appb-000004
一实施例中，所述SOI器件的kink电流I kink计算方法为：
Figure PCTCN2019090565-appb-000005
其中，C是与SOI器件材料和几何尺寸相关参数，L为SOI器件的沟道长度，V D为SOI器件漏端电压，V Dse为漏端饱和电压相关的插值函数，F I为SOI器件发生碰撞离化的阈值电场，L b为SOI器件体区内载流子扩散长度，I Dsat为SOI器件漏端饱和电流；或，
所述SOI器件的kink电流I kink计算方法为：
Figure PCTCN2019090565-appb-000006
其中，C k是与SOI器件材料和几何尺寸相关参数，L为SOI器件的沟道长度，V D为SOI器件漏端电压，V Dse为漏端饱和电压相关的插值函数，V k为SOI器件与kink效应相关的电压参数，L b为SOI器件体区内载流子扩散长度，I Dsat 为SOI器件漏端饱和电流。
一实施例中，所述方法还包括步骤：
阈值电场F I的参数提取：
获取多个宽度相同但沟道长度不同的长沟道SOI器件在多个栅压下的漏端电流I D以及漏端饱和电流I Dsat；
利用式(1)建立长沟道SOI器件中，以阈值电场F I为斜率的函数；
根据所述多个长沟道SOI器件在多个栅压下的漏端电流I D和漏端饱和电流I Dsat，以及长沟道SOI器件中以阈值电场F I为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下发生碰撞离化的阈值电场；优选地，
所述方法还包括步骤：
体区内载流子扩散长度L b的参数提取：
利用式(1)建立长沟道SOI器件中以
Figure PCTCN2019090565-appb-000007
为斜率的函数；
计算各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值；
根据所述各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值，以及长沟道SOI器件中以
Figure PCTCN2019090565-appb-000008
为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下的体区内载流子扩散长度；优选地，
所述方法还包括步骤：
C参数的提取：
计算所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值；
根据所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值，以及所述各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值，计算所述多个长沟道SOI器件在多个栅压下式(1)的C参数。
一实施例中，所述方法还包括步骤：
将所述各长沟道SOI器件在多个栅压下发生碰撞离化的阈值电场分别求均值，分别获得所述多个长沟道SOI器件在式(1)中阈值电场F I的初步拟合值；和/或，
将所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度求均值，获得式(1)中体区内载流子扩散长度L b的拟合值；和/或，
将所述多个长沟道SOI器件在多个栅压下C参数的均值作为式(1)中C参数的初步拟合值；
以所述C参数的初步拟合值代入式(1)，并根据所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值，确定各SOI器件在多个栅压下发生碰撞离化的阈值电场，作为各长沟道SOI器件在式(1)中阈值电场F I的拟合值；
重复所述C参数提取步骤，得到所述多个长沟道器件在多个栅压下在式(1)中C参数的拟合值。
一实施例中，所述方法还包括步骤：
参数V k的提取：
获取多个宽度相同但沟道长度不同的长沟道SOI器件在多个栅压下的漏端电流I D以及漏端饱和电流I Dsat；
利用式(2)建立长沟道SOI器件中，以V k为斜率的函数；
根据所述多个长沟道SOI器件在多个栅压下的漏端电流I D和漏端饱和电流I Dsat，以及长沟道SOI器件中以V k为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下的V k；优选地，
所述方法还包括步骤：
体区内载流子扩散长度L b和C k的参数提取：
利用式(2)建立长沟道器件中以
Figure PCTCN2019090565-appb-000009
为斜率、ln(2C k)为截距的函数；
计算各长沟道SOI器件在多个栅压下V k的均值；
根据各长沟道SOI器件在多个栅压下V k的均值，以及长沟道SOI器件中以
Figure PCTCN2019090565-appb-000010
为斜率、ln(2C k)为截距的函数，计算所述多个长沟道SOI器件在多个栅压下的体区内载流子扩散长度L b和C k。
一实施例中，还包括：
将所述多个长沟道SOI器件在多个栅压下的C k求均值，获得式(2)中C k的拟合值；和/或，
将所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度求均值，获得式(2)中体区内载流子扩散长度L b的拟合值；和/或，
将所述多个长沟道SOI器件在多个栅压下C k、L b的均值代入式(2)，分别获得所述多个长沟道SOI器件在多个栅压下在式(2)中V k的拟合值。
本申请实施例还提供一种SOI器件的kink电流计算装置，包括：
获取模块，用于分别获取SOI器件的碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流；
计算模块，用于根据所述碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流，计算所述SOI器件的kink电流。
本申请实施例还提供一种SOI器件的kink电流计算设备，包括：
处理器；以及
被安排成存储计算机可执行指令的存储器，所述处理器通过运行所述可执行指令以实现如上所述的SOI器件的kink电流计算方法。
本申请实施例中，通过在计算SOI器件的kink电流时考虑碰撞离化作用因子、寄生晶体管作用因子两个影响SOI器件中kink电流的因素，使得计算得到的SOI器件的kink电流更加准确，且不引入任何经验参数，在不同栅压下都具有较好的拟合效果；同时，该计算方法中使用的参数易于提取，适用于电路仿真。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为SOI器件中kink电流的示意图；
图2为背景技术中Jacunski等人利用RPI模型进行拟合时的示意图；
图3为本申请人利用RPI模型进行拟合时的示意图；
图4为本申请一实施例提供的SOI器件的电流计算方法的流程图；
图5为本申请实验例1中F I拟合值与沟道长度L的关系示意图；
图6为本申请实验例1中C拟合值与栅压V gs的关系示意图；
图7为本申请实验例1中多个SOI器件在多个栅压下的kink电流拟合示意图；
图8为本申请实验例2中多个SOI器件在多个栅压下的kink电流拟合示意图；
图9为本申请实验例3中多个SOI器件在多个栅压下的kink电流拟合示意图；
图10为本申请一实施例提供的设备的结构示意图；
图11为本申请一实施例提供的SOI器件的kink电流计算装置的模块图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请具体实施例及相应的附图对本申请技术方案进行清楚、完整地描述。显然，所描述的实施例仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
参图4，介绍本发明SOI器件的kink电流计算方法的一实施方式。在本 实施方式中，该方法包括：
S10、分别获取SOI器件的碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流。
当SOI器件的漏端偏置在大电压时，漏端耗尽区内碰撞离化产生大量的电子空穴对，并且由寄生晶体管效应而增强，在体区内发生附加的正反馈作用。因此，通过在SOI器件的kink电流计算中加入碰撞离化作用因子和寄生晶体管作用因子，可以较好地阐述影响SOI器件中kink电流的两个影响因素，使得计算得到的SOI器件的kink电流更加准确。
具体地，可以是通过获取SOI器件的沟道长度以及体区内载流子扩散长度，并根据该沟道长度以及体区内载流子扩散长度计算SOI器件的寄生晶体管作用因子，并且，SOI器件的寄生晶体管作用因子与SOI器件的沟道长度以及体区内载流子扩散长度为双曲正割依赖关系。
需要说明的是，在下述的各实施例中：如果示出的是P型SOI器件，则体区内的载流子扩散长度对应为电子扩散长度；相应地，如果示出的是N型SOI器件，则体区内的载流子扩散长度对应为空穴扩散长度。
一实施例中，该SOI器件的寄生晶体管作用因子为：
Figure PCTCN2019090565-appb-000011
其中L为SOI器件的沟道长度，L b为SOI器件的体区内载流子扩散长度。
SOI器件的碰撞离化作用因子与SOI器件发生碰撞离化的阈值电场F I、耗尽区宽度l d、漏端电压V D以及漏端饱和电压相关的插值函数V Dse指数相关。
一实施例中，该碰撞离化作用因子为：
Figure PCTCN2019090565-appb-000012
又或者，SOI器件的碰撞离化作用因子与SOI器件与kink效应相关的电压参数V k、漏端电压V D以及漏端饱和电压相关的插值函数V Dse指数相关；
一实施例中，该碰撞离化作用因子为：
Figure PCTCN2019090565-appb-000013
S20、根据所述碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流，计算所述SOI器件的kink电流。
以下将分别通过不同的实施例来阐述步骤S20中SOI器件kink电流I kink的计算方法。
实施例一
SOI器件的kink电流I kink计算方法为：
Figure PCTCN2019090565-appb-000014
其中，C是与SOI器件材料和几何尺寸相关参数，L为SOI器件的沟道长度，V D为SOI器件漏端电压，V Dse为漏端饱和电压相关的插值函数(在线性区接近漏端电压V D，在饱和区接近漏端饱和电压V Dsat)，l d为SOI器件耗尽区宽度，F I为SOI器件发生碰撞离化的阈值电场，L b为SOI器件体区内载流子扩散长度，I Dsat为SOI器件漏端饱和电流，sech(x)为双曲正割函数
Figure PCTCN2019090565-appb-000015
特别地，对于长沟道SOI器件，沟道长度L远大于体区内载流子扩散长度L b，故：
Figure PCTCN2019090565-appb-000016
所以上述SOI器件的kink电流计算方法可以变化为：
Figure PCTCN2019090565-appb-000017
可以看出，本发明实施例的SOI器件kink电流计算方法中，kink电流与SOI器件的沟道长度L是可以进一步地近似为指数依赖关系，且该SOI器件kink电流计算方法中，全部是基于物理参数而不涉及经验参数，更加准确可靠。
一实施例中，上述的C参数可以是
Figure PCTCN2019090565-appb-000018
其中I 0为SOI器件反向饱和电流，τ b为体区内载流子寿命，A为碰撞离化区的面积，E I为发生碰撞离化的阈值能量，n i为本征载流子浓度。需要说明的是，这里的C参数的表达式只是一示范性的说明，在后续的C参数的拟合步骤中，实质上并不需要依赖上述的I 0、τ b、A、E I、n i确定C参数，因此在不同的实施例中，C参数可以选择性地进行不同的物理定义。
一实施例中，SOI器件的漏端饱和电流I Dsat的表达式为：
Figure PCTCN2019090565-appb-000019
其中，W为SOI器件的宽度，L为SOI器件沟道长度，l d为耗尽区宽度，μ eff为沟道有效迁移率，C ox为单位面积栅氧电容，V Dse为一漏端饱和电压相关的插值函数，在线性区接近V D，在饱和区接近V Dsat，E sat为速度饱和效应的特征电场，V GT为有效栅压。
又一实施例中，SOI器件的漏端饱和电流I Dsat的表达式还可以为：
Figure PCTCN2019090565-appb-000020
其中，μ FET为场效应迁移率，C ox为单位面积栅氧电容，W为SOI器件的宽度，L为SOI器件沟道长度，V GS为栅端电压，V t为阈值电压，α sat是与漏端夹断有关的参数。
可以理解的是，上述只是示范性地给出了SOI器件中两种漏端饱和电流I Dsat的计算方式而并非对本发明的限制，在更多的实施例中，本领域技术人员可以根据实际仿真需要而选择不同的漏端饱和电流模型，这些变换的实施例仍应当属于本发明的保护范围之内。
在本实施方式中，该方法还包括阈值电场F I的参数提取和拟合步骤、体区内载流子扩散长度L b的参数提取和拟合步骤、以及C参数的提取和拟合步骤。示范性地，上述的步骤都基于一组宽度W相同、但沟道长度L不同的多晶硅 薄膜晶体管。具体地，
S101、阈值电场F I的参数提取步骤：
获取多个宽度相同但沟道长度不同的长沟道SOI器件在多个栅压下的漏端电流I D以及漏端饱和电流I Dsat；
利用式(1)建立长沟道SOI器件中，以阈值电场F I为斜率的函数；
根据多个长沟道SOI器件在多个栅压下的漏端电流I D和漏端饱和电流I Dsat，以及长沟道SOI器件中以阈值电场F I为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下发生碰撞离化的阈值电场。
一实施例中，由于对于长沟道器件，沟道长度L远大于体区内载流子扩散长度L b，所以
Figure PCTCN2019090565-appb-000021
其中I kink＝I D-I Dsat。式(1)可变形为
Figure PCTCN2019090565-appb-000022
令
Figure PCTCN2019090565-appb-000023
画出lny～x的曲线，F I为斜率，可以求出多个长沟道SOI器件的在多个栅压下发生碰撞离化的阈值电场。
S102、体区内载流子扩散长度L b的参数提取步骤：
利用式(1)建立长沟道SOI器件中以
Figure PCTCN2019090565-appb-000024
为斜率的函数；
计算各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值；
根据各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值，以及长沟道SOI器件中以
Figure PCTCN2019090565-appb-000025
为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度。
一实施例中，式(1)可变形为
Figure PCTCN2019090565-appb-000026
令
Figure PCTCN2019090565-appb-000027
Y～L的曲线中斜率为
Figure PCTCN2019090565-appb-000028
用步骤S101中提取出的多个长沟道SOI器件在多个栅压下发生碰撞离化的阈值电场，求其在同一SOI器件、不同栅压下的平均值，分别代入上式，即可得到多个长沟道SOI器件在多个栅压下体区内载流子扩散长度。
S103、C参数的提取步骤：
计算所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值；
根据所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值，以及所述各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值，计算所述多个长沟道SOI器件在多个栅压下式(1)的C参数。
S104、将所述各长沟道SOI器件在多个栅压下发生碰撞离化的阈值电场分别求均值，分别获得所述多个长沟道SOI器件在式(1)中阈值电场F I的初步拟合值。
S105、将所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度求均值，获得式(1)中体区内载流子扩散长度L b的拟合值。
S106、将所述多个长沟道SOI器件在多个栅压下C参数的均值作为式(1)中C参数的初步拟合值；
以获得的C参数的初步拟合值代入式(1)，并根据所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值，确定各SOI器件在多个栅压下发生碰撞离化的阈值电场，作为各长沟道SOI器件在式(1)中阈值电场F I的拟合值；
重复上述C参数提取步骤，得到所述多个长沟道器件在多个栅压下在式(1)中C参数的拟合值。
如此，可以得到阈值电场F I、体区内载流子扩散长度L b、以及C三个参数的拟合值。拟合得到的阈值电场F I与沟道长度L有线性依赖关系，据此可以 计算同一工艺、相同宽度的其他SOI器件的kink电流。
当然，在更多的实施例中，本申请的技术方案还可以包括将上述步骤得到的阈值电场F I、体区内载流子扩散长度L b、以及C三个参数的拟合值再次带入式(1)中，并多次迭代上述的参数提取及参数拟合的步骤，以获得阈值电场F I、体区内载流子扩散长度L b、以及C三个参数在式(1)中进一步逼近满意拟合效果的拟合值，这种实施例仍应当属于本申请的构思之内。
以下提供两个具体的实验例，对本实施例的SOI器件的kink电流计算方法做进一步说明。
实验例1
器件类型：P型准分子激光退火工艺的多晶硅薄膜晶体管。
宽长比：10/25μm、10/20μm、10/15μm和10/10μm。
栅压：V gs＝-3.5，-4，-4.5，-5V。
阈值电场F I的拟合值如下表：
Figure PCTCN2019090565-appb-000029
体区内载流子扩散长度L b(这里的载流子扩散长度指的是电子扩散长度)的拟合值(由于不同栅压下L b的提取值接近，故以其均值作为L b的拟合值)如下表：
V gs(V) L b(μm)拟合值
-3.5 4.5
-4 4.5
-4.5 4.5
-5 4.5
C参数的拟合值如下表：
Figure PCTCN2019090565-appb-000030
从本实验例可以看出，对于不同宽长比的SOI器件可以使用同一组C值，且C与栅压V gs有线性依赖关系，载流子扩散长度L b用一固定拟合值，阈值电场F I在不同栅压时也相同。具体地，阈值电场F I与沟道长度L的关系如图5，F I与沟道长度L的关系可以用一参数方程来描述，F I＝k 1·L+b 1，对于P型准分子激光退火工艺的多晶硅薄膜晶体管，k 1＝-6×10 7V/cm 2，b 1＝3.6×10 5V/cm；C与栅压V gs的关系如图6，C与栅压V gs的关系也可用线性参数方程来描述，C＝k 2·V gs+b 2，对于P型准分子激光退火工艺的多晶硅薄膜晶体管，k 2＝0.068cm/V 2，b 2＝0.44cm/V。配合参照图7(其中漏端电流大小与栅压V gs正相关，四条输出特性曲线由下至上分别对应于栅压V gs＝-3.5，-4，-4.5，-5V)，可以看出本发明的SOI器件kink电流计算方法中，拟合出的kink电流大小与实验测量数据高度接近，具有较好的拟合效果。
实验例2
器件类型：N型金属诱导横向结晶工艺(MILC)的多晶硅薄膜晶体管(体区内载流子扩散长度指的是空穴扩散长度)。
宽长比：10/25μm、10/20μm、10/15μm和10/10μm。
栅压：V gs＝11、12、13、14V。
类似的，配合参照图8(其中漏端电流大小与栅压V gs正相关，四条输出特性曲线由下至上分别对应于栅压V gs＝11、12、13、14V)，可以看出拟合出的 kink电流大小与实验测量数据高度接近，具有较好的拟合效果。
通过上述实验例，可以看出本发明提供的kink电流计算方法在低缺陷密度的准分子激光退火(ELA)和高缺陷密度的金属诱导横向结晶(MILC)这两种工艺的器件上都有极好的拟合效果，同样，在缺陷态更少的部分耗尽SOI器件上也有很好的拟合效果，在此不再赘述。
实施例二
SOI器件的kink电流I kink计算方法为：
Figure PCTCN2019090565-appb-000031
其中，C k是与SOI器件材料和几何尺寸相关参数，L为SOI器件的沟道长度，V D为SOI器件漏端电压，V Dse为漏端饱和电压相关的插值函数(在线性区接近漏端电压V D，在饱和区接近漏端饱和电压V Dsat)，V k为SOI器件与kink效应相关的电压参数，L b为SOI器件体区内载流子扩散长度，I Dsat为SOI器件漏端饱和电流，sech(x)为双曲正割函数
Figure PCTCN2019090565-appb-000032
特别地，对于长沟道SOI器件，沟道长度L远大于体区内载流子扩散长度L b，故：
Figure PCTCN2019090565-appb-000033
所以上述SOI器件的kink电流计算方法可以变化为：
Figure PCTCN2019090565-appb-000034
可以看出，本发明实施例的SOI器件kink电流计算方法中，kink电流与SOI器件的沟道长度L可以进一步地近似为指数依赖关系，且该SOI器件kink电流计算方法中，全部是基于物理参数而不涉及经验参数，更加准确可靠。
其中，SOI器件的漏端饱和电流I Dsat的选择可以参考实施例一，在此不再赘述。
在本实施方式中，该方法还包括V k的参数提取和拟合步骤、体区内载流子扩散长度L b的参数提取和拟合步骤、以及C k的参数提取和拟合步骤。示范性地，上述的步骤都基于一组宽度W相同、但沟道长度L不同的多晶硅薄膜晶体管。具体地，
S201、参数V k提取步骤：
获取多个宽度相同但沟道长度不同的长沟道SOI器件在多个栅压下的漏端电流I D以及漏端饱和电流I Dsat；
利用式(2)建立长沟道SOI器件中，以V k为斜率的函数；
根据多个长沟道SOI器件在多个栅压下的漏端电流I D和漏端饱和电流I Dsat，以及长沟道SOI器件中以阈值电场V k为斜率的函数，计算所述多个长沟道SOI器件在多个栅压的V k。
一实施例中，由于对于长沟道器件，沟道长度L远大于体区内载流子扩散长度L b，所以
Figure PCTCN2019090565-appb-000035
其中I kink＝I D-I Dsat。式(2)可变形为
Figure PCTCN2019090565-appb-000036
令
Figure PCTCN2019090565-appb-000037
画出lny～x的曲线，V k为斜率，可以求出多个长沟道SOI器件的在多个栅压下的V k。
需要说明的是，在上述式(2)的变形中，由于
Figure PCTCN2019090565-appb-000038
中的
Figure PCTCN2019090565-appb-000039
是对数项，与
Figure PCTCN2019090565-appb-000040
相比是缓变项，在提取斜率时可以忽略。
S202、体区内载流子扩散长度L b和C k的参数提取步骤：
利用式(2)建立长沟道SOI器件中以
Figure PCTCN2019090565-appb-000041
为斜率、ln(2C k)为截距的函数；
计算各长沟道SOI器件在多个栅压下V k的均值；
根据各长沟道SOI器件在多个栅压下V k的均值，以及长沟道SOI器件中以
Figure PCTCN2019090565-appb-000042
为斜率、ln(2C k)为截距的函数，计算所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度L b和C k。
一实施例中，式(2)可变形为
Figure PCTCN2019090565-appb-000043
令
Figure PCTCN2019090565-appb-000044
Y～L的曲线中斜率为
Figure PCTCN2019090565-appb-000045
截距为ln(2C k)，用步骤S201中提取出的多个长沟道SOI器件在多个栅压下的V k，求其在同一SOI器件、不同栅压下的平均值，分别代入上式，即可得到多个长沟道SOI器件在在多个栅压下体区内载流子扩散长度L b和C k。
S203、将所述多个长沟道SOI器件在多个栅压下的C k求均值，获得式(2)中C k的拟合值。
S204、将所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度求均值，获得式(2)中体区内载流子扩散长度L b的拟合值。
S205、将所述多个长沟道SOI器件在多个栅压下C k、L b的均值代入式(2)，分别获得所述多个长沟道SOI器件在多个栅压下在式(2)中V k的拟合值。
如此，可以得到V k、体区内载流子扩散长度L b、以及C k三个参数的拟合值。拟合得到的L b和C k保持为常数，V k与沟道长度L、栅压V g有一定的线性依赖关系，据此可以计算同一工艺、相同宽度的其他SOI器件的kink电流。
与上一实施例类似地，本实施例中也可以通过将得到的V k、体区内载流子扩散长度L b、以及C k三个参数的拟合值进一步带入式(2)中，并多次迭代上述的参数提取及参数拟合的步骤，以获得V k、体区内载流子扩散长度L b、以及C k三个参数在式(2)中进一步逼近满意拟合效果的拟合值。
以下提供一个具体的实验例，对本实施例的SOI器件的kink电流计算方 法做进一步说明。
实验例3
器件类型：P型准分子激光退火工艺的多晶硅薄膜晶体管(体区内载流子扩散长度指的是电子扩散长度)。
宽长比：10/25μm、10/20μm、10/15μm和10/10μm。
栅压：V gs＝-3.5，-4，-4.5，-5V。
最终的参数拟合值如下表：
Figure PCTCN2019090565-appb-000046
从本实验例可以看出，L b和C k为常数，V k与栅压V gs以及沟道长度L有一定的线性依赖关系，具体地用一参数方程来表示：V k＝V k0+a·V gs+b·L，对于P型准分子激光退火工艺的多晶硅薄膜晶体管，V k0＝52.2V，a＝-1.7，b＝-8×10 3V/cm。配合参照图9(其中漏端电流大小与栅压V gs正相关，四条输出特性曲线由下至上分别对应于栅压V gs＝-3.5，-4，-4.5，-5V)，可以看出本发明的SOI器件kink电流计算方法中，拟合出的kink电流大小与实验测量数据高度接近，具有较好的拟合效果。
图10是一示例性实施例提供的一种设备的示意结构图。请参考图10，在硬件层面，该设备包括处理器、内部总线、网络接口、内存以及非易失性存储器，当然还可能包括其他业务所需要的硬件。处理器从非易失性存储器中读取对应的计算机程序到内存中然后运行，在逻辑层面上形成SOI器件的kink电流计算装置。当然，除了软件实现方式之外，本说明书一个或多个实施例并不排除其他实现方式，比如逻辑器件抑或软硬件结合的方式等等，也就是说以下处理流程的执行主体并不限定于各个逻辑单元，也可以是硬件或逻辑器件。
请参考图11，在软件实施方式中，该SOI器件的kink电流计算装置，包括获取模块301和计算模块302。
获取模块301用于分别获取SOI器件的碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流；计算模块302用于根据所述碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流，计算所述SOI器件的kink电流。
由于软件的实施方式中，该SOI器件的kink电流计算装置实质上与上述实施例中提及的SOI器件的kink电流计算方法彼此对应，在此不再赘述。
上述实施例阐明的系统、装置、模块或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机，计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。
在一个典型的配置中，计算机包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带、磁盘存储、量子存储器、基于石墨烯的存储介质或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂 存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
上述对本说明书特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作或步骤可以按照不同于实施例中的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序才能实现期望的结果。在某些实施方式中，多任务处理和并行处理也是可以的或者可能是有利的。
在本说明书一个或多个实施例使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本说明书一个或多个实施例。在本说明书一个或多个实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本说明书一个或多个实施例可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本说明书一个或多个实施例范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在......时”或“当......时”或“响应于确定”。
以上所述仅为本说明书一个或多个实施例的较佳实施例而已，并不用以限制本说明书一个或多个实施例，凡在本说明书一个或多个实施例的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本说明书一个或多个 实施例保护的范围之内。

Claims (10)

  1. 一种SOI器件的kink电流计算方法，其特征在于，包括：
    分别获取SOI器件的碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流；
    根据所述碰撞离化作用因子、寄生晶体管作用因子、以及漏端饱和电流，计算所述SOI器件的kink电流。
  2. 如权利要求1所述的方法，其特征在于，获取所述SOI器件的寄生晶体管作用因子具体包括：
    获取所述SOI器件的沟道长度以及体区内载流子扩散长度，并根据所述沟道长度以及体区内载流子扩散长度计算所述SOI器件的寄生晶体管作用因子。
  3. 如权利要求2所述的方法，其特征在于，所述SOI器件的寄生晶体管作用因子与所述SOI器件的沟道长度以及体区内载流子扩散长度为双曲正割依赖关系；
    优选地，所述寄生晶体管作用因子为：
    Figure PCTCN2019090565-appb-100001
    其中L为SOI器件的沟道长度，L b为SOI器件体区内载流子扩散长度。
  4. 如权利要求1所述的方法，其特征在于，所述SOI器件的碰撞离化作用因子与所述SOI器件发生碰撞离化的阈值电场F I、耗尽区宽度l d、漏端电压V D以及漏端饱和电压相关的插值函数V Dse指数相关；
    优选地，所述碰撞离化作用因子为：
    Figure PCTCN2019090565-appb-100002
    或，所述SOI器件的碰撞离化作用因子与所述SOI器件kink效应相关的电压参数V k、漏端电压V D以及漏端饱和电压相关的插值函数V Dse指数相关；
    优选地，所述碰撞离化作用因子为：
    Figure PCTCN2019090565-appb-100003
  5. 如权利要求1至4任一项所述的方法，其特征在于，所述SOI器件的kink电流I kink计算方法为：
    Figure PCTCN2019090565-appb-100004
    其中，C是与SOI器件材料和几何尺寸相关参数，L为SOI器件的沟道长度，V D为SOI器件漏端电压，V Dse为漏端饱和电压相关的插值函数，l d为SOI器件耗尽区宽度，F I为SOI器件发生碰撞离化的阈值电场，L b为SOI器件体区内载流子扩散长度，I Dsat为SOI器件漏端饱和电流；或，
    所述SOI器件的kink电流I kink计算方法为：
    Figure PCTCN2019090565-appb-100005
    其中，C k是与SOI器件材料和几何尺寸相关参数，L为SOI器件的沟道长度，V D为SOI器件漏端电压，V Dse为漏端饱和电压相关的插值函数，V k为与kink效应相关的电压参数，L b为SOI器件体区内载流子扩散长度，I Dsat为SOI器件漏端饱和电流。
  6. 如权利要求5所述的方法，其特征在于，所述方法还包括步骤：
    阈值电场F I的参数提取：
    获取多个宽度相同但沟道长度不同的长沟道SOI器件在多个栅压下的漏端电流I D以及漏端饱和电流I Dsat；
    利用式(1)建立长沟道SOI器件中，以阈值电场F I为斜率的函数；
    根据所述多个长沟道SOI器件在多个栅压下的漏端电流I D和漏端饱和电流I Dsat，以及长沟道SOI器件中以阈值电场F I为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下发生碰撞离化的阈值电场；优选地，
    所述方法还包括步骤：
    体区内载流子扩散长度L b的参数提取：
    利用式(1)建立长沟道SOI器件中以
    Figure PCTCN2019090565-appb-100006
    为斜率的函数；
    计算各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值；
    根据所述各长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值，以及长沟道SOI器件中以
    Figure PCTCN2019090565-appb-100007
    为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下的体区内载流子扩散长度；优选地，
    所述方法还包括步骤：
    C参数的提取：
    计算所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值；
    根据所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值，以及所述各个长沟道SOI器件在多个栅压下分别发生碰撞离化的阈值电场的均值，计算所述多个长沟道SOI器件在多个栅压下式(1)的C参数。
  7. 如权利要求6所述的方法，其特征在于，所述方法还包括步骤：
    将各长沟道SOI器件在所述多个栅压下发生碰撞离化的阈值电场分别求均值，分别获得各长沟道SOI器件在式(1)中阈值电场F I的初步拟合值；和/或，
    将所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度求均值，获得式(1)中体区内载流子扩散长度L b的拟合值；和/或，
    将所述多个长沟道SOI器件在多个栅压下C参数的均值作为式(1)中C参数的初步拟合值；
    以所述C参数的初步拟合值代入式(1)，并根据所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度的均值，确定各SOI器件在多个栅压下发生碰撞离化的阈值电场，作为各长沟道SOI器件在式(1)中阈值电场F I的拟合值；
    重复所述C参数提取步骤，得到所述多个长沟道器件在多个栅压下在式(1)中C参数的拟合值。
  8. 如权利要求5所述的方法，其特征在于，所述方法还包括步骤：
    参数V k的提取：
    获取多个宽度相同但沟道长度不同的长沟道SOI器件在多个栅压下的漏端电流I D以及漏端饱和电流I Dsat；
    利用式(2)建立长沟道SOI器件中，以V k为斜率的函数；
    根据所述多个长沟道SOI器件在多个栅压下的漏端电流I D和漏端饱和电流I Dsat，以及长沟道SOI器件中以V k为斜率的函数，计算所述多个长沟道SOI器件在多个栅压下的V k；优选地，
    所述方法还包括步骤：
    体区内载流子扩散长度L b和C k的参数提取：
    利用式(2)建立长沟道器件中以
    Figure PCTCN2019090565-appb-100008
    为斜率、ln(2C k)为截距的函数；
    计算各长沟道SOI器件在多个栅压下V k的均值；
    根据各长沟道SOI器件在多个栅压下V k的均值，以及长沟道SOI器件中以
    Figure PCTCN2019090565-appb-100009
    为斜率、ln(2C k)为截距的函数，计算所述多个长沟道SOI器件在多个栅压下的体区内载流子扩散长度L b和C k。
  9. 如权利要求8所述的方法，其特征在于，还包括：
    将所述多个长沟道SOI器件在多个栅压下的C k求均值，获得式(2)中C k的拟合值；和/或，
    将所述多个长沟道SOI器件在多个栅压下体区内载流子扩散长度求均值，获得式(2)中体区内载流子扩散长度L b的拟合值；和/或，
    将所述多个长沟道SOI器件在多个栅压下C k、体区内载流子扩散长度L b的均值代入式(2)，分别获得所述多个长沟道SOI器件在多个栅压下在式(2) 中V k的拟合值。
  10. 一种电子设备，其特征在于，包括：
    处理器；以及
    被安排成存储计算机可执行指令的存储器，所述处理器通过运行所述可执行指令以实现如权利要求1-9中任一项所述的SOI器件的kink电流计算方法。
PCT/CN2019/090565 2019-05-31 2019-06-10 SOI器件的kink电流计算方法及装置 WO2020237717A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/959,633 US11442097B2 (en) 2019-05-31 2019-06-10 Method and apparatus for calculating kink current of SOI device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910467871.7 2019-05-31
CN201910467871.7A CN110210123B (zh) 2019-05-31 2019-05-31 SOI器件的kink电流计算方法及装置

Publications (1)

Publication Number Publication Date
WO2020237717A1 true WO2020237717A1 (zh) 2020-12-03

Family

ID=67789871

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/090565 WO2020237717A1 (zh) 2019-05-31 2019-06-10 SOI器件的kink电流计算方法及装置

Country Status (3)

Country Link
US (1) US11442097B2 (zh)
CN (1) CN110210123B (zh)
WO (1) WO2020237717A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111291480A (zh) * 2020-01-21 2020-06-16 中国科学院微电子研究所 一种mos器件剂量率模型的建模方法和装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920093A (en) * 1997-04-07 1999-07-06 Motorola, Inc. SOI FET having gate sub-regions conforming to t-shape
TW554522B (en) * 2001-02-20 2003-09-21 Hau-Ran Yang Using SOI kink effect to build a single-transistor DRAM
CN107315673A (zh) * 2017-06-29 2017-11-03 努比亚技术有限公司 功耗监测方法、移动终端及计算机可读存储介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3504212B2 (ja) * 2000-04-04 2004-03-08 シャープ株式会社 Ｓｏｉ構造の半導体装置
CN101840458B (zh) * 2010-05-20 2012-06-27 清华大学 载流子迁移率的提取方法
US9741857B2 (en) * 2015-08-07 2017-08-22 Ahmad Tarakji Approach for an area-efficient and scalable CMOS performance based on advanced Silicon-On-Insulator (SOI), Silicon-On-Sapphire (SOS) and Silicon-On-Nothing (SON) technologies
US10714623B2 (en) * 2015-08-07 2020-07-14 Ahmad Houssam Tarakji Approach for an area-efficient and scalable CMOS performance based on advanced silicon-on-insulator (SOI), silicon-on-sapphire (SOS) and silicon-on-nothing (SON) technologies
CN106446395B (zh) * 2016-09-20 2019-06-21 电子科技大学 一种nmos总剂量辐照效应的解析建模方法
CN108416115B (zh) * 2018-02-09 2022-12-20 复旦大学 氮化镓基大功率高电子迁移率晶体管沟道电流计算方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920093A (en) * 1997-04-07 1999-07-06 Motorola, Inc. SOI FET having gate sub-regions conforming to t-shape
TW554522B (en) * 2001-02-20 2003-09-21 Hau-Ran Yang Using SOI kink effect to build a single-transistor DRAM
CN107315673A (zh) * 2017-06-29 2017-11-03 努比亚技术有限公司 功耗监测方法、移动终端及计算机可读存储介质

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MOHAMMAD KAIFI ET AL.: "Kink Model for SOI MOSFET", 13 February 2012 (2012-02-13), XP032115127, DOI: 20200213201546 *

Also Published As

Publication number Publication date
CN110210123A (zh) 2019-09-06
US11442097B2 (en) 2022-09-13
US20210405107A1 (en) 2021-12-30
CN110210123B (zh) 2023-07-21

Similar Documents

Publication Publication Date Title
Zhang et al. Extremely high-gain source-gated transistors
Duncan et al. Full-band Monte Carlo investigation of hot carrier trends in the scaling of metal-oxide-semiconductor field-effect transistors
US10585136B2 (en) Method of characterizing and modeling leakage statistics and threshold voltage for ensemble devices
Li et al. High-frequency characteristic fluctuations of nano-MOSFET circuit induced by random dopants
WO2020237717A1 (zh) SOI器件的kink电流计算方法及装置
US20030200071A1 (en) Simulation method
Zhou et al. Rigorous surface-potential solution for undoped symmetric double-gate MOSFETs considering both electrons and holes at quasi nonequilibrium
Tsuji et al. Efficient simulation model for amorphous In-Ga-Zn-O thin-film transistors
Yuehui et al. Impact of Process Variability on Threshold Voltage in Vertically-Stacked Nanosheet TFET
Chatzikyriakou et al. A systematic method for simulating total ionizing dose effects using the finite elements method
US9209167B2 (en) Determining threshold voltage variations in field effect transistors
Li et al. Discrete-dopant-induced timing fluctuation and suppression in nanoscale CMOS circuit
Roy et al. Effect of back oxide thickness of FDSOI on SRAM performance
Sil et al. On the performance of hafnium-oxide-based negative capacitance FinFETs, with and without a spacer
Badaroglu et al. More Moore landscape for system readiness-ITRS2. 0 requirements
JP2013080847A (ja) 表面ポテンシャルのシミュレーション装置及び表面ポテンシャルのシミュレーションプログラム
Watabe et al. Statistical evaluation of process damage using an arrayed test pattern in a large number of MOSFETs
Mukherjee et al. U shaped vertical gate bulk MOSFET for area minimization
Saha et al. Analytical modeling and performance characterization of a double gate MOSFET with dielectric pockets incorporating work function engineered binary metal alloy gate electrode for subdued SCEs
Panigrahi et al. Impact of non‐uniformly doped double‐gate junctionless transistor on the performance of 6T‐SRAM bitcell
Watabe et al. A simple test structure for evaluating the variability in key characteristics of a large number of mosfets
Xi et al. The influence of channel width on total ionizing dose responses of the 130 nm H-gate partially depleted SOI NMOSFETs
Kola et al. Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors
Li et al. Random-work-function-induced characteristic fluctuation in 16-nm-gate bulk and SOI FinFETs
Aneesh et al. Comparative Analysis of Single Event Transients in InGaAs-OI/Bulk/BOI FinFETs for SET-Tolerant InGaAs/Ge-OI Complementary FinFET Circuits

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19931172

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19931172

Country of ref document: EP

Kind code of ref document: A1