WO2020237635A1 - 接口组件、芯片及电子设备 - Google Patents

接口组件、芯片及电子设备 Download PDF

Info

Publication number
WO2020237635A1
WO2020237635A1 PCT/CN2019/089562 CN2019089562W WO2020237635A1 WO 2020237635 A1 WO2020237635 A1 WO 2020237635A1 CN 2019089562 W CN2019089562 W CN 2019089562W WO 2020237635 A1 WO2020237635 A1 WO 2020237635A1
Authority
WO
WIPO (PCT)
Prior art keywords
control
usb
usb transceiver
control circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/089562
Other languages
English (en)
French (fr)
Inventor
鲁灯
曾涛
郑科
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201980078223.0A priority Critical patent/CN113168207B/zh
Priority to PCT/CN2019/089562 priority patent/WO2020237635A1/zh
Publication of WO2020237635A1 publication Critical patent/WO2020237635A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of electronic equipment, and more specifically to interface components, chips and electronic equipment.
  • USB universal serial bus
  • USB transceiver is not connected to an external device is handled as the USB interface is in the idle state.
  • the power consumption of a USB interface will be more than 10 milliwatts (mW) .
  • the USB interface will generate greater power consumption.
  • This application provides interface components, chips and electronic equipment, which can reduce the power consumption of the USB interface.
  • the present application provides an interface component, which includes: a universal serial bus USB host controller, a USB transceiver, a control circuit, and a first signal switching circuit, wherein the USB host controls The USB transceiver and the control circuit are connected to the USB transceiver through the first signal switching circuit; the control circuit is used to control the first signal switching when the USB transceiver is not connected to an external device The circuit communicates the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state.
  • the interface component in the above technical solution also adds a control circuit, and the source of the USB transceiver control signal can be switched through the first signal switching circuit.
  • the USB transceiver can be controlled by the USB host controller in some cases, and the USB transceiver can be controlled by the control circuit in other cases.
  • the control circuit may control the first signal switching circuit to connect the connection between the control circuit and the USB transceiver, so that the control circuit The USB transceiver is controlled to enter a low power consumption state, so that the power consumption of the USB interface can be reduced.
  • control circuit is further configured to control the USB transceiver to exit the low power consumption state when the USB transceiver is connected to an external device; the control circuit further After the USB transceiver exits the low power consumption state, control the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver, and connect to the USB host controller The connection with the USB transceiver.
  • the interface component further includes a second signal switching circuit, and the USB transceiver and the control circuit are connected to the USB host controller through the second signal switching circuit;
  • the control circuit is also used to control the second signal switching circuit to connect the control circuit and the USB host controller when the USB transceiver is not connected to an external device.
  • the interface component further includes a detection circuit connected to the control circuit and the USB transceiver; the detection circuit is used to detect whether the USB transceiver is Connect an external device and transmit the detection result to the control circuit; the control circuit is specifically configured to control the USB transceiver to enter the USB transceiver when the detection result indicates that the USB transceiver is not connected to an external device Low power consumption state.
  • the control circuit includes a control register, a status register, an interrupt circuit, and a central processing unit CPU; the status register is used to store the detection result of the detection circuit and pass the interrupt circuit Report the detection result to the CPU; the CPU is configured to perform at least one of the following operations when the detection result indicates that the USB transceiver is not connected to an external device: by configuring the control register The first control signal controls the first signal switching circuit to connect the control circuit and the USB transceiver; configure the second control signal in the control register to control the USB transceiver to enter the The low power consumption state; by configuring the third control signal in the control register to control the second signal switching circuit to connect the connection between the control circuit and the USB host controller.
  • the CPU is further configured to perform at least one of the following operations when the detection result indicates that the USB transceiver is connected to an external device: by configuring the control register in the The second control signal controls the USB transceiver to exit the low power consumption state; after the USB transceiver exits the low power consumption state, the first control signal that configures the control register controls all The first signal switching circuit disconnects the connection between the control circuit and the USB transceiver, and connects the connection between the USB host controller and the USB transceiver.
  • the above technical solution adopts software implementation to control the signal switching unit, and the cost is low.
  • the control circuit includes a control register, a status register, and a control logic circuit; the status register is used to store the detection result of the detection circuit; the control logic circuit is used in the If the detection result indicates that the USB transceiver is not connected to an external device, perform at least one of the following operations: control the first signal switching circuit to connect the control circuit and the USB transceiver; control The USB transceiver enters the low power consumption state; the second signal switching circuit is controlled to communicate the connection between the control circuit and the USB host controller.
  • the above technical solution realizes the control of the signal switching circuit through the logic circuit, which can reduce the complexity of the software compared with the way of realizing by software.
  • control logic circuit is further configured to perform at least one of the following operations when the detection result indicates that an external device is connected to the USB transceiver: control the USB transceiver After the USB transceiver exits the low power consumption state, the first signal switching circuit is controlled to disconnect the connection between the control circuit and the USB transceiver, and Connect the connection between the USB host controller and the USB transceiver.
  • the above technical solution realizes the control of the signal switching circuit through the logic circuit, which can reduce the complexity of the software compared with the way of realizing by software.
  • the first signal switching circuit includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal.
  • the first input terminal and the first control terminal Are respectively connected to the control circuit, the second input terminal is connected to the USB host controller, the first output terminal is connected to the USB transceiver;
  • the second signal switching circuit includes a third input terminal, A fourth input terminal, a second output terminal and a second control terminal, the third input terminal and the second control terminal are respectively connected to the control circuit, and the fourth input terminal is connected to the USB transceiver;
  • the second output terminal is connected to the USB host controller;
  • the control circuit is specifically configured to control the first control terminal through the first control terminal when the USB transceiver is not connected to an external device.
  • the signal switching circuit communicates the connection between the control circuit and the USB transceiver, and, through the second control terminal, controls the second signal switching circuit to communicate between the control circuit and the USB host controller
  • the control circuit is specifically also used to control the first signal switching circuit to disconnect the control circuit and the control circuit through the first control terminal when an external device is connected to the USB transceiver
  • the detection circuit includes a filter, and the filter is connected to the control circuit and the USB transceiver for detecting whether an external device is connected to the USB transceiver.
  • the phase-locked loop PLL circuit of the USB transceiver when the USB transceiver is in the low power consumption state, the phase-locked loop PLL circuit of the USB transceiver is in a closed state.
  • the PLL circuit Since the PLL circuit is a high-power device in the USB transceiver, the PLL circuit is turned off.
  • the system clock signal with lower power consumption (or no additional power consumption) can be used instead to ensure the normal operation of the USB host controller. This can reduce the power consumption of the USB interface.
  • the present application provides a control method, which is applied to an interface component, and the interface component includes a universal serial bus USB host controller, a USB transceiver, a control circuit, and a first signal switching circuit, wherein The USB host controller and the control circuit are connected to the USB transceiver through the first signal switching circuit, and the method includes: when the USB transceiver is not connected to an external device, the controlling The circuit controls the first signal switching circuit to connect the connection between the control circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state.
  • the method further includes: when the USB transceiver is connected to an external device, the control circuit controls the USB transceiver to exit the low power consumption state; After the transceiver exits the low power consumption state, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver, and connects the USB host controller to the USB Describe the connection between USB transceivers.
  • the interface component further includes a second signal switching circuit
  • the USB transceiver and the control circuit are connected to the USB host controller through the second signal switching circuit
  • the The method further includes: when the USB transceiver is not connected to an external device, the control circuit controls the second signal switching circuit to connect the control circuit and the USB host controller.
  • the interface component further includes a detection circuit connected to the control circuit and the USB transceiver
  • the method further includes: the control circuit receives the detection circuit
  • the transmitted detection result is used to indicate whether an external device is connected to the USB transceiver; when the USB transceiver is not connected to an external device, the control circuit controls the first signal switching circuit to communicate
  • the connection between the control circuit and the USB transceiver so that the control circuit controls the USB transceiver to enter a low power consumption state includes: when the detection result indicates that the USB transceiver is not connected to an external device
  • the control circuit controls the first signal switching circuit to connect the connection between the control circuit and the USB transceiver, and controls the USB transceiver to enter the low power consumption state.
  • the first signal switching circuit includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal.
  • the first input terminal and the first control terminal Are respectively connected to the control circuit, the second input terminal is connected to the USB host controller, the first output terminal is connected to the USB transceiver;
  • the second signal switching circuit includes a third input terminal, A fourth input terminal, a second output terminal and a second control terminal, the third input terminal and the second control terminal are respectively connected to the control circuit, and the fourth input terminal is connected to the USB transceiver;
  • the second output terminal is connected to the USB host controller; when the USB transceiver is not connected to an external device, the control circuit controls the first signal switching circuit to connect the control circuit and the USB
  • the connection between the transceivers includes: when the USB transceiver is not connected to an external device, the control circuit controls the first signal switching circuit to connect the control circuit and the control circuit through the first control terminal.
  • connection between the USB transceivers, and, through the second control terminal, the second signal switching circuit is controlled to communicate the connection between the control circuit and the USB host controller;
  • the control circuit is in the When an external device is connected to the USB transceiver, the first signal switching circuit is controlled through the first control terminal to disconnect the connection between the control circuit and the USB transceiver, and through the first control terminal, A control terminal and the second control terminal communicate with the connection between the USB host controller and the USB transceiver.
  • the detection circuit includes a filter, and the filter is connected to the control circuit and the USB transceiver for detecting whether an external device is connected to the USB transceiver.
  • the phase-locked loop PLL circuit of the USB transceiver when the USB transceiver is in the low power consumption state, the phase-locked loop PLL circuit of the USB transceiver is in a closed state.
  • the present application provides a chip that includes a processor and an interface component as described in the first aspect or any one of the possible implementation manners of the first aspect.
  • the present application provides an electronic device that includes a processor, a memory, and an interface component as described in the first aspect or any one of the possible implementation manners of the first aspect.
  • Fig. 1 is a schematic structural diagram of a USB system to which the technical solutions of the embodiments of the present application can be applied.
  • Figure 2 is a schematic structural diagram of an interface component of an embodiment of the present application.
  • Fig. 3 is a schematic diagram of the signal flow of the interface component of the embodiment of the present application.
  • Fig. 4 is a schematic diagram of another signal flow of the interface component of the embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of a control circuit of an embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of another control circuit of an embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of MUX.
  • FIG. 8 is a schematic structural diagram of an interface component provided by another embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an interface component provided by another embodiment of the present application.
  • the technical solutions of the embodiments of the present application can be applied to various devices or products that need to reduce interface power consumption, as long as the device or product performs data transmission with external devices through the USB interface.
  • PCs PCs, tablets, set-top boxes, TVs, etc.
  • the technical solutions of the embodiments of the present application can also be applied to other types of interface systems, such as high definition multimedia interface (HDMI), external serial advanced technology attachment, E-SATA) interface, video graphics array (video graphics array, VGA) interface, etc.
  • HDMI high definition multimedia interface
  • E-SATA external serial advanced technology attachment
  • VGA video graphics array
  • This application uses a USB interface as an example to describe the technical solution of this application.
  • the embodiment of the present application does not specifically limit the type of the USB interface, for example, it may be Micro-USB, Mini-USB, Sub-USB, USB-type C, etc.
  • Fig. 1 is a schematic structural diagram of a USB system to which the technical solutions of the embodiments of the present application can be applied.
  • the USB host controller 101 is connected to the memory 114 via the system bus 115 (for example, double data rate synchronous dynamic random access memory (DDR SDRAM), central processing unit ,
  • the CPU 1041 is connected to the USB transceiver 102.
  • the USB host controller 101 After the USB host controller 101 receives the task issued by the CPU 1041, it reads or writes data between the memory 104 and the external device 106 through the USB transceiver 102.
  • the external device 106 is connected to the USB transceiver 102.
  • USB transceivers More in the state where the USB device is not connected, and the USB transceiver is not connected to the USB device, it is usually handled as the USB host controller and the USB transceiver in the idle state, rather than entering the suspended state.
  • the power consumption of a USB interface will be more than 10 milliwatts (mW). In this scenario, the USB interface will generate greater power consumption. Therefore, the embodiment of the present application is based on the interface component 200 and provides a low-power solution for the scenario where the USB transceiver is not connected to the USB device.
  • FIG. 2 is a schematic structural diagram of an interface component of an embodiment of the present application.
  • the interface component 200 includes a USB host controller 201, a USB transceiver 202, a control circuit 204, and a first signal switching circuit 205-1.
  • the USB host controller 201 and the USB transceiver 202 can respectively correspond to the USB host controller 101 and the USB transceiver 102 in FIG. 1.
  • the USB host controller 201 and the control circuit 204 are connected to the USB transceiver 202 through the first signal switching circuit 205-1.
  • the control circuit 204 and the first signal switching circuit 205-1 are added between the USB host controller 201 and the USB transceiver 202.
  • USB host controller 201 such as enhanced host controller interface (EHCI) host controller, universal host controller interface (UHCI) host controller, open Host control interface (open host controller interface, OHCI) host controller, etc.
  • EHCI enhanced host controller interface
  • UHCI universal host controller interface
  • OHCI open host controller interface
  • USB transceiver 202 for example, a USB2.0 transceiver macrocell interface (UTMI) transceiver.
  • UTMI USB2.0 transceiver macrocell interface
  • the control circuit 204 is used to control the first signal switching circuit 205-1 to connect the connection between the control circuit 204 and the USB transceiver 202 when the USB transceiver 202 is not connected to an external device, so that the control circuit 204 controls the USB transceiver 202 enters a low power consumption state.
  • the connection between the communication control circuit 204 and the USB transceiver 202 may be the signal transmission/reception between the two.
  • the control signal sent by the control circuit 204 can reach the USB transceiver 202, thereby changing the USB transceiver 202. 202 status.
  • the USB transceiver 202 is in a low power consumption state, at least part of the circuits are turned off to save power consumption, for example, the low power consumption state is a suspended state.
  • the phase-locked loop PLL circuit of the USB transceiver 202 is turned off.
  • the USB transceiver 202 is in a low power consumption state when no external device is connected, and the USB host controller 201 is in a non-low power state. Therefore, in order to make the USB host controller 201 work normally, when the USB transceiver 202 is in a low power consumption state, the USB host controller 201 can be connected to the system clock signal.
  • the USB transceiver 202 when the USB transceiver 202 is connected to an external device, the USB transceiver 202 is controlled by the USB host controller 201 and is in a state of high power consumption for data transmission; the USB transceiver 202 is not connected to an external device In the case of a device, the USB transceiver 202 is controlled by the control circuit 204 to enter a low power consumption state, such as a low power consumption state, thereby reducing the power consumption of the USB interface.
  • a low power consumption state such as a low power consumption state
  • the first signal switching circuit 205-1 of the embodiment of the present application can switch according to whether the USB transceiver 202 is connected to an external device.
  • the first signal switching circuit 205-1 may be controlled by the control circuit 204.
  • the control circuit 204 controls the first signal switching circuit 205-1 to communicate with the USB host when the USB transceiver 202 is connected to an external device.
  • the connection between the USB transceiver 201 and the USB transceiver 202 controls the first signal switching circuit 205-1 to connect the connection control circuit 204 to the USB transceiver 202.
  • the interface component implemented in this application may also have more control circuits, for example, two control circuits or more than two control circuits. Accordingly, the first signal switching circuit 205-1 in the embodiment of the present application may also Switch to more channels of signals, for example, 3 channels or more than 3 channels, etc.
  • the first signal switching circuit 205-1 can switch between 3 signals as an example, for example, the first signal switching circuit 205-1 is connected to the USB host When the controller 201 is connected to the USB transceiver, the USB transceiver is in the idle state; when the first signal switching circuit 205-1 connects the connection between the control circuit 204-1 and the USB transceiver 202, the USB transceiver is in Low power consumption state; when the first signal switching circuit 205-1 connects the connection between the control circuit 204-2 and the USB transceiver 202, the USB transceiver is in an idle state and a state other than the low power consumption state.
  • the interface component has a control circuit 204, and the first signal switching circuit 205-1 can switch between two signals as an example for description.
  • control circuit 204 is also used to control the USB transceiver 202 to exit the low power consumption state when the USB transceiver 202 is connected to an external device.
  • control circuit can control the USB transceiver 202 to exit the low power consumption state when an external device is inserted on the USB transceiver 202.
  • control circuit 204 is also configured to control the first signal switching circuit 205-1 to disconnect the control circuit 204 and the USB transceiver 202 after the USB transceiver 202 exits the low power consumption state, and connect to the USB The connection between the host controller 201 and the USB transceiver 202.
  • the USB transceiver 202 when the USB transceiver 202 is not connected to an external device, the USB transceiver 202 is switched to a low power consumption state, and The USB host controller 201 is in an idle state, not a low-power state.
  • USB transceiver 202 when the USB transceiver 202 is connected to an external device, in order to avoid various inconsistencies caused by the inconsistency between the USB transceiver 202 and the USB host controller 201 .
  • the problem is that you need to restore the USB transceiver 202 to the normal state first, for example, turn on the circuit that was turned off in the low-power state, so that the USB transceiver 202 returns to the normal state, and then connect the USB host controller to the USB transceiver. Signal connection.
  • the first signal switching circuit 205-1 connects the connection between the control circuit 204 and the USB transceiver 202, the signal sent by the USB host controller 201 to the USB transceiver 202 is disconnected;
  • a signal switching circuit 205-1 connects the connection between the USB host controller 201 and the USB transceiver 202, the signal sent by the control circuit 204 to the USB transceiver 202 is disconnected. This can avoid interference between signals.
  • the interface assembly 200 further includes a second signal switching circuit 205-2.
  • the USB transceiver 202 and the control circuit 204 are connected to the USB host controller 201 through the second signal switching circuit 205-2.
  • the signal source of the input signal of the USB host controller 201 can be changed by the second signal switching circuit 205-2.
  • the control circuit 204 is also used to control the second signal switching circuit 205-2 to connect the connection between the control circuit 204 and the USB host controller 201 when the USB transceiver 202 is not connected to an external device.
  • control signals of the first signal switching circuit 205-1 and the second signal switching circuit 205-2 may be the same control signal, or different control signals may be used.
  • the USB controller when the USB transceiver is connected to the USB device, the USB device is in a state of high power consumption for data transmission, and when the USB transceiver is not connected to the USB device, the USB controller can be controlled The circuit control enters a low power consumption state, such as a low power consumption state, thereby reducing the power consumption of the USB interface.
  • the interface component 200 of the embodiment of the present application further includes a detection circuit 203, which is connected to the USB transceiver 202 and the control circuit 204, for detecting whether the USB transceiver 202 is connected to an external device, and sending the detection result to
  • the control circuit 204 controls the single circuit 204 to control the first signal switching circuit 205-1, the second signal switching circuit 205-2, and the USB transceiver 202 according to the detection result.
  • the detection result of the detection circuit can be expressed by the state value of the bit position or the high and low level of the output signal of the detection circuit. As an example, it is represented by two bits, one of which indicates whether an external device is connected, and one bit indicates whether the connection status has changed.
  • the state value of the two bits when the state value of the two bits is 00, it means that the USB transceiver 202 is always in the state of not connecting an external device; when the state value of the two bits is 01, it means that no external device is connected and the state has changed, that is Say that the external device on the USB transceiver 202 is unplugged; when the state value of the two bits is 10, it means that an external device is connected and the state has not changed, that is, the USB transceiver 202 is always connected to the external device; when the two bits are When the status value of is 11, it indicates that an external device is connected and the status has changed, that is, the external device is inserted into the USB transceiver 202.
  • the detection circuit 203 receives the first signal 310 from the USB transceiver 202, and the first signal 310 indicates that the USB transceiver 202 is not connected to an external device. Next, a second signal 307 is generated.
  • the second signal 307 is used to indicate to the control circuit 204 that the USB transceiver 202 is not connected to an external device; after receiving the second signal 307, the control circuit 204 controls the first signal switching circuit 205-1 to turn off Open the connection between the USB host controller 201 and the USB transceiver 202, and connect the connection between the control circuit 204 and the USB transceiver 202, so that the second control signal 311 sent by the control circuit 204 reaches the USB transceiver 202; and control The second signal switching circuit 205-2 disconnects the connection between the USB host controller 201 and the USB transceiver 202, and connects the connection between the control circuit 204 and the USB host controller 201; the USB transceiver 202 receives the second control After the signal 311, the low power consumption state is entered.
  • the detection circuit 203 For the case where the USB transceiver 202 is connected to an external device, as shown in FIG. 4, the detection circuit 203 generates a third signal 412 when the first signal 310 indicates that the USB transceiver 202 is connected to the external device, and the third signal 412 is used to The control circuit 204 instructs the USB transceiver 202 to connect to the external device; after receiving the third signal 412, the control circuit 204 sends a fourth signal to the USB transceiver 202 when the signal between the control circuit 204 and the USB transceiver 202 is connected.
  • the USB host controller 201 and the USB transceiver 202 use the signals from the control circuit 204 by default. In other words, if the USB transceiver 202 is not connected to an external device from beginning to end, the USB transceiver 202 can always be in a low power consumption state. In this way, the power consumption can also be reduced for USB ports that have never been used.
  • the embodiment of the present application does not specifically limit the form of the aforementioned control circuit 204, as long as it can realize the aforementioned functions.
  • the control circuit 204 includes a control register 204-4, a status register 204-1, an interrupt circuit 204-2, and a CPU 204-3.
  • the status register 204-1 is used to store the detection result of the detection circuit 203, and report the detection result to the CPU 204-3 through the interrupt circuit 204-2.
  • the CPU 204-3 is configured to perform at least one of the following operations when the detection result indicates that the USB transceiver 202 is not connected to an external device:
  • the first signal switching circuit 205-1 is controlled to connect the connection between the control circuit 204 and the USB transceiver 202; by configuring the second control signal in the control register 204-4 The control signal 311 controls the USB transceiver 202 to enter a low power consumption state; by configuring the third control signal in the control register 204-4, the second signal switching circuit 205-2 is controlled to connect the control circuit 204 and the USB host controller 201 the connection between.
  • the CPU 204-3 is further configured to perform at least one of the following operations when the detection result indicates that the USB transceiver 202 is connected to an external device:
  • the USB transceiver 202 is controlled to exit the low power state by the second control signal 311 in the configuration control register 204-4; after the USB transceiver 202 exits the low power state, it is controlled by the first control signal in the configuration control register 204-4
  • the first signal switching circuit 205-1 disconnects the connection between the control circuit 204 and the USB transceiver 202, and connects the connection between the USB host controller 201 and the USB transceiver 202.
  • the status register 204-1 is used to report the first signal to the CPU 204-3 through the interrupt circuit 204-2 after receiving the second signal 307 from the detection circuit 203 An interrupt event.
  • the first interrupt event is that the USB transceiver 202 is not connected to an external device (for example, when the external device is unplugged).
  • the CPU 204-3 is used to configure the control register 204-4 according to the first interrupt event to control the register 204-4 controls the first signal switching circuit 205-1 to disconnect the connection between the USB host controller 201 and the USB transceiver 202, and connects the connection between the control circuit 204 and the USB transceiver 202, so that the control circuit 204 sends the first signal
  • the second control signal 311 reaches the USB transceiver 202; and controls the second signal switching circuit 205-2 to disconnect the connection between the USB host controller 201 and the USB transceiver 202, and connect the control circuit 204 to the USB host controller 201 Connected; the USB transceiver 202 enters a low power consumption state after receiving the second control signal 311.
  • the status register 204-1 is used to report the second interrupt event to the CPU 204-3 through the interrupt circuit 204-2 after receiving the third signal 412 from the detection circuit 203.
  • the first interrupt event is when the USB transceiver 202 is connected to an external device (for example, when the external device is plugged in), the CPU 204-3 is used to configure the control register 204-4 according to the second interrupt event, so that the control circuit 204 and the USB transceiver
  • the fourth control signal 413 is sent to the USB transceiver 202; the USB transceiver 202 exits the low power consumption state after receiving the fourth control signal 413; the control circuit 204 is in the USB transceiver 202
  • the first signal switching circuit 205-1 is controlled to disconnect the connection between the control circuit 204 and the USB transceiver, and connect the connection between the USB host controller 201 and the USB transceiver 202.
  • control circuit 204 includes a control register 204-6, a status register 204-5, and a control logic circuit 204-7.
  • the status register 204-5 is used to store the detection result of the detection circuit 203;
  • the control logic circuit 204-7 is used to perform at least one of the following operations when the detection result indicates that the USB transceiver 202 is not connected to an external device:
  • the control logic circuit 204-7 is further configured to perform at least one of the following operations when the detection result indicates that an external device is connected to the USB transceiver 202:
  • the status register 204-5 is used to generate a fourth signal after receiving the second signal 307 from the detection circuit 203, and the control logic circuit 204-7 is used to After receiving the fourth signal, control the first signal switching circuit 205-1 to connect the connection between the control logic circuit 204-7 and the USB transceiver 202, and control the connection between the register 204-6 and the USB transceiver 202, and control The second signal switching circuit 205-2 communicates the connection between the control register 204-6 and the USB host controller 201, so as to control the USB transceiver 202 to enter a low power consumption state.
  • the status register 204-5 is used to generate the fifth signal after receiving the third signal 412 from the detection circuit, and the control logic circuit 204-7 is used to generate the fifth signal after receiving the fifth signal.
  • the USB transceiver 202 is controlled to exit the low power consumption state, and after the USB transceiver 202 exits the low power consumption state, the first signal switching circuit 205-1 is controlled to connect the connection between the USB host controller 201 and the USB transceiver 202, The second signal switching circuit 205-2 is controlled to connect the connection between the USB transceiver 202 and the USB host controller 201.
  • control circuit 204 can also be implemented entirely by software programming, or entirely implemented by hardware, or implemented by a combination of software and hardware, which is not specifically limited in the embodiment of the present application.
  • the application does not specifically limit the form of the first signal switching circuit 205-1.
  • the first signal switching circuit 205-1 may be implemented by one or more multiplexers (MUX).
  • the first signal switching circuit 205-1 includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal. The first input terminal and the first control terminal are respectively connected to the control circuit 204.
  • the second input terminal is connected to the USB transceiver 202, and the first output terminal is connected to the USB host controller 201.
  • the control circuit 204 controls the first signal switching circuit 205-1 to connect the connection between the control circuit 204 and the USB transceiver 202 through the first control terminal; when the USB transceiver is When an external device is connected to 202, the first signal switching circuit 205-1 is controlled through the first control terminal to disconnect the connection between the control circuit 204 and the USB transceiver 202, and the USB host controller 201 is connected to the USB transceiver. 202 signal.
  • the second signal switching circuit 205-2 can be implemented by one or more MUXs.
  • the second signal switching circuit 205-2 includes a third input terminal, a fourth input terminal, a second output terminal, and a second control terminal.
  • the third input terminal and the second control terminal are respectively connected to the control circuit 204.
  • the four input terminals are connected to the USB host controller 201, and the second output terminal is connected to the USB transceiver 202.
  • the control circuit 204 can control the second signal switching circuit 205-2 to connect the connection between the control circuit 204 and the USB host controller 201 by controlling the second control terminal;
  • the second signal switching circuit 205-2 is controlled to disconnect the connection between the control circuit 204 and the USB host controller 201, and the USB transceiver 202 is connected to The signal of the USB host controller 201.
  • Fig. 7 is a schematic structural diagram of MUX.
  • the MUX has two input terminals A and B, an output terminal D, and a control terminal C.
  • the input terminals A and B may correspond to the first input terminal, the second input terminal, or the third input terminal, the fourth input terminal, and the output terminal D may correspond to the first output terminal or the second output above.
  • the control terminal C can correspond to the first control terminal or the second control terminal above.
  • the implementation of the MUX in the embodiment of the present application is not specifically limited.
  • it can be implemented using software programming, can also be implemented by hardware, or can be implemented by a combination of software and hardware.
  • the embodiment of the present application does not specifically limit the form of the detection circuit 203, as long as it can detect whether the USB transceiver 202 is connected to an external device.
  • the detection circuit 203 may be a filter.
  • the present application does not specifically limit the implementation of the detection circuit. For example, it can be implemented by software programming, can also be implemented by hardware, or can be implemented by a combination of software and hardware.
  • FIG. 8 is a schematic structural diagram of an interface component provided by another embodiment of the present application.
  • the USB host controller 801 in FIG. 8 may correspond to the above host controller 201, and the USB2.0 transceiver macrocell interface physical layer (UTMI physical layer, UTMI PHY) 802 may correspond to the above USB transceiver 202,
  • the control circuit 804 (including the interrupt circuit 8042, CSR 8041 and CPU 8043) can correspond to the control circuit 204 above, 10 MUXs can correspond to the signal switching circuit 205 above, and the filter 803 can correspond to the detection circuit above. 203.
  • EHCI host controller and UTMI PHY the interface standard between EHCI host controller (ie logical layer) and UTMI PHY (ie physical layer) is UTMI, and the signal description between EHCI host controller and UTMI PHY is as follows:
  • utmi_linestate Corresponding to 1 and 11, it is used to feed back the signal of the USB bus connection.
  • the phase locked loop (PLL) inside UTMI PHY 802 the phase locked loop inside UTMI PHY 802 )
  • the clock source is turned off, but the utmi_linestate signal can be directly reflected by the combinational logic circuit. That is to say, after the UTMI PHY 802 enters the low power consumption state, the utmi_linestate signal can still transmit the connection status of the external device.
  • utmi_hostdisconnect Corresponding to 2 and 12, used to feed back whether UTMI PHY 802 is a disconnected signal.
  • utmi_suspendm Corresponding to 3 and 13, the signal used to control whether UTMI PHY 802 is in standby (that is, suspended state), low level is effective;
  • utmi_xcvselect[1:0] Corresponding to 4 and 14, the signal used to control whether UTMI PHY 802 selects the high-speed channel;
  • utmi_termselect Corresponding to 5 and 15, a signal used to control whether UTMI PHY 802 is connected to a high-speed resistor;
  • utmi_opmode[1:0] Corresponding to 6 and 16, the signal used to control whether UTMI PHY 802 works in the normal encoding mode;
  • utmi_rx Corresponding to 7 and 17, used for UTMI PHY 802 to send data received from an external device to the USB host controller 801;
  • utmi_tx Corresponding to 8 and 18, used for UTMI PHY 802 to send data received from the USB host controller 801 to an external device;
  • clk_utmi Corresponding to 9 and 19, the working clock signal of UTMI PHY 802, from UTMI PHY 802 to the USB host controller 801 via clock gating 816, 60 MHz, the clock stops in the suspended state;
  • clk_free Corresponding to 10 and 20, the working clock signal of UTMI PHY 802, from UTMI PHY 802 to the USB host controller 801 via clock gating 817, 60 MHz, the clock does not stop in the suspended state.
  • some incremental circuit designs are made between the EHCI host controller and the UTMI PHY to implement the above-mentioned solution. Specifically, set MUX 805-1, 805-2, and 805-7 between utmi_linestate, utmi_hostdisconnect, and utmi_rx, respectively, and set them between utmi_suspendm, utmi_rcvselect[1:0], utmi_termselect, utmi_opmode[1:0], and utmi_tx.
  • MUX 805-9 and 805-10 between clk_utmi and clk_free.
  • MUX 805-1, 805-2 and 805-7 The output terminal is connected to the USB host controller 801, the control terminal is connected to the control register 804-4, and the two input terminals are respectively connected to the control register 804-4 and UTMI PHY 802, MUX 805-3, 805-4, 805-5 and 805
  • the output terminal of -6 is connected to the USB transceiver 802, the control terminal is connected to the control register 804-4, and the two input terminals are respectively connected to the control register 804-4 and the USB host controller 801, the output of MUX 805-9 and 805-10
  • the terminal is connected to the USB host controller 801, the control terminal is connected to the control register 804-4, and the two input terminals are respectively connected to the system clock signal 818 and UTMI PHY 802; the utmi_linestate signal from UTMI PHY 802 is used as the input of MUX
  • control terminal ie, select signal
  • control terminal of each MUX in FIG. 8 is not shown. In fact, the control terminal of each MUX is connected to the control register 804-4.
  • the initial setting of the interface component 800 is the default value.
  • the specific configuration is shown in Figure 8.
  • the input of utmi_termselect is 1, and the input of clk_free/clk_utmi is the system clock signal (clk_from_crg) 818. That is, in the initial state, the control circuit 804 controls the connection state between the USB host controller 801 and the UTMI PHY 802. When no external device is plugged into the UTMI PHY 802, the control circuit 804 (or software) controls the connection between the USB host controller 801 and the UTMI PHY 802 to be disconnected through the MUX.
  • the control circuit 804 controls the UTMI PHY 802 to communicate with the USB host controller 801.
  • the utmi_terselect of the USB host controller 801 is connected to the utmi_terselect of the UTMI PHY 802, and the USB host controller 801
  • the clk_free/clk_utmi of UTMI is connected to clk_free/clk_utmi of UTMI PHY 802.
  • the interface component 800 returns to the normal mode.
  • the interface component 800 detects whether the UTMI PHY 802 is connected to an external device through the filter 803.
  • the filter 803 is configured to use the utmi_linestate signal to detect whether the UTMI PHY 802 is connected to an external device.
  • the filter 803 detects that utmi_linestate[1:0] is equal to 2'b00 and the duration is greater than x milliseconds, it means that the external device pulls out the UTMI PHY 802;
  • the filter 803 detects that utmi_linestate[1:0] is not equal to 2'b00 and the duration is greater than y milliseconds (ms)
  • the external device is inserted UTMI PHY 802.
  • x it should be understood that for the selection of x, it should be ensured that when an external device is inserted into UTMI PHY 802, according to the USB protocol, utmi_linestate must last at least 3ms to ensure that the external device is connected stably, so x is at least greater than 3ms. Further consider that if x is selected too large, the detection time will be very long. Therefore, preferably, the default value of x can be 10ms, and x can be configured by a register.
  • the USB bus will not have a situation where utmi_linestate with a duration greater than y milliseconds is not equal to 2'b00.
  • y is at least 0.25ms. If the value of y is too small, it is easy to be interfered by external glitches, while the value of y becomes larger, which will make the detection time longer. Therefore, preferably, the default value of y may be 10ms, and y may be configured by a register. In this way, the solution of the embodiment of the present application can ensure the reliability of plug detection and reduce false detection.
  • the main workflow of the interface component 800 is described below.
  • the connection state between the USB host controller 801 and the UTMI PHY 802 is the default value and is in a disconnected state.
  • the control circuit 804 controls clk_free/clk_utmi to be clk_from_crg, utmi_suspendm is 0, etc., and UTMI PHY 802 enters a standby state (or a low power consumption state). If no external device has been inserted into UTMI PHY 802, UTMI PHY 802 will always be in a low power consumption state.
  • the filter 803 detects the insertion of the external device, the status register 804-1 stores the connection status, and reports the interrupt event of the external device insertion to the CPU 804-3 through the interrupt circuit 804-2.
  • the software receives an interrupt event, it sets utmi_suspendm to 1 through the control register 804-4 to let UTMI PHY 802 exit the standby state, and after UTMI PHY 802 exits the standby state, set the signal connection between the USB host controller 801 and UTMI PHY 802 .
  • USB host controller 801 and UTMI PHY 802 When connecting the signal between the USB host controller 801 and UTMI PHY 802, first control the clk_free/clk_utmi between the USB host controller 801 and UTMI PHY 802, and then control the connection of other signals. After completion, the USB host controller 801 and UTMI The PHY 802 enters the normal connection state, and the normal working process thereafter is the same as the prior art.
  • the filter 803 detects that the external device is pulled out, the status register 804-1 stores the connection status, and reports the interruption of the external device pull out to the CPU 804-3 through the interrupt circuit 804-2 Event, when the software receives an interrupt event, it first controls the signal between the USB host controller 801 and UTMI PHY 802 (for example, clk_free, clk_utmi, etc.) to be disconnected through the control register 804-4, and then sets utmi_suspend to 0 to enable UTMI PHY 802 enters the standby mode, that is, it returns to the low power consumption state.
  • the software receives an interrupt event, it first controls the signal between the USB host controller 801 and UTMI PHY 802 (for example, clk_free, clk_utmi, etc.) to be disconnected through the control register 804-4, and then sets utmi_suspend to 0 to enable UTMI PHY 802 enters the standby mode, that
  • FIG. 9 is a schematic structural diagram of an interface component provided by another embodiment of the present application.
  • the control circuit 904 of FIG. 9 includes a control register 904-6, a state register 904-5, and a control logic circuit 904-7, where the control logic circuit 904-7 includes a state machine. As shown in FIG. 9, the control terminal of each MUX is connected to the control logic circuit 904-7.
  • the difference between the interface component 800 and the interface component 900 is that the interface component 800 has an interrupt design and requires software to cooperate with logic to implement the above processing flow.
  • the CPU 804-3 controls the UTMI PHY 802 to enter or exit the low state according to the specific event after receiving the interrupt event.
  • the power consumption state, and in the interface component 900, these operations are completed by the control logic circuit 904-7.
  • the interface component 900 slightly increases the complexity of the logic circuit, in exchange for the benefit of not requiring software participation and avoiding increased software maintenance overhead.
  • control logic circuit 904-7 can adopt existing basic functional modules.
  • the structure and functions of other parts of the interface component 900 (for example, the USB host controller 901, the UTMI PHY 902, the filter 903, etc.), and the workflow of the interface component 900 can be referred to the related description of FIG. 8 and will not be repeated here.
  • the technical solution of the embodiment of the present application makes up for the insufficient consideration of the low power consumption scenario of the USB 2.0 protocol.
  • configuring the UTMI PHY in the suspended state can significantly reduce the overall power consumption of the USB interface component.
  • the area of the UTMI PHY is about 10 times that of the USB host controller. Reducing the power consumption of the PHY can significantly reduce the overall power consumption of the USB.
  • the measured data of the 28nm process is as follows: if the UTMI PHY does not enter the low power state, the power consumption of the USB interface component is about 15 milliwatts (mW); if the UTMI PHY enters the low power state , The power consumption of USB interface components is about 0.5mW, saving more than 96% of power consumption.
  • the embodiment of the present application also provides a control method.
  • the method is applied to an interface component, the interface component includes a universal serial bus USB host controller, a USB transceiver, a control circuit, and a first signal switching circuit, wherein the USB host controller and the control circuit pass The first signal switching circuit is connected to the USB transceiver, and the method includes: when the USB transceiver is not connected to an external device, the control circuit controls the first signal switching circuit to communicate with the control The connection between the circuit and the USB transceiver, so that the control circuit controls the USB transceiver to enter a low power consumption state.
  • the method further includes: when the USB transceiver is connected to an external device, the control circuit controls the USB transceiver to exit the low power consumption state; After the low power consumption state, the control circuit controls the first signal switching circuit to disconnect the connection between the control circuit and the USB transceiver, and connects the USB host controller and the USB transceiver. The connection between.
  • the interface component further includes a second signal switching circuit
  • the USB transceiver and the control circuit are connected to the USB host controller through the second signal switching circuit
  • the method further includes: When the USB transceiver is not connected to an external device, the control circuit controls the second signal switching circuit to communicate the connection between the control circuit and the USB host controller.
  • the interface component further includes a detection circuit connected to the control circuit and the USB transceiver
  • the method further includes: the control circuit receives the detection result transmitted by the detection circuit, The detection result is used to indicate whether an external device is connected to the USB transceiver; when the USB transceiver is not connected to an external device, the control circuit controls the first signal switching circuit to connect the control circuit and The connection between the USB transceivers so that the control circuit controls the USB transceiver to enter a low power consumption state includes: when the detection result indicates that the USB transceiver is not connected to an external device, controlling The first signal switching circuit communicates the connection between the control circuit and the USB transceiver, and controls the USB transceiver to enter the low power consumption state.
  • the first signal switching circuit includes a first input terminal, a second input terminal, a first output terminal, and a first control terminal.
  • the first input terminal, the first control terminal and the control terminal are respectively Circuit connection, the second input terminal is connected to the USB host controller, the first output terminal is connected to the USB transceiver;
  • the second signal switching circuit includes a third input terminal, a fourth input terminal, The second output terminal and the second control terminal, the third input terminal and the second control terminal are respectively connected to the control circuit, the fourth input terminal is connected to the USB transceiver, the second output Terminal is connected to the USB host controller; when the USB transceiver is not connected to an external device, the control circuit controls the first signal switching circuit to connect the control circuit and the USB transceiver Connecting, including: the control circuit controls the first signal switching circuit to communicate between the control circuit and the USB transceiver through the first control terminal when the USB transceiver is not connected to an external device And, through the second control terminal, the second signal switching circuit is controlled to communicate the connection between the control
  • the detection circuit includes a filter, and the filter is connected to the control circuit and the USB transceiver for detecting whether an external device is connected to the USB transceiver.
  • the phase-locked loop PLL circuit of the USB transceiver is in the off state.
  • At least one of means one of the listed items or any combination thereof, for example, “at least one of A, B, and C” means: exist alone A, B alone exists, C alone exists, A and B exist at the same time, A and C exist at the same time, B and C exist at the same time, and there are six cases of A, B and C at the same time.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program code .

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Power Sources (AREA)

Abstract

接口组件(200)、芯片和电子设备，包括：USB主机控制器(201)、USB收发器(202)、控制电路(204)和第一信号切换电路(205-1)，其中，USB主机控制器(201)和控制电路(204)通过第一信号切换电路(205-1)与USB收发器(202)相连；控制电路(204)，用于在USB收发器(202)未连接外部设备的情况下，控制第一信号切换电路(205-1)连通控制电路(204)与USB收发器(202)之间的连接，以使得控制电路(204)控制USB收发器(202)进入低功耗状态。上述技术方案中的接口组件(200)除包括USB主机控制器(201)以外还增加了控制电路(204)，可以通过第一信号切换电路(205-1)切换USB收发器(202)控制信号的来源，当信号来源为控制电路(204)时，控制电路(204)可以控制USB收发器(202)进入低功耗状态，从而可以降低USB接口的功耗。

Description

接口组件、芯片及电子设备 技术领域
本申请涉及电子设备领域，并且更具体地涉及接口组件、芯片及电子设备。
背景技术
现有的通用串行总线(universal serial bus，USB)接口的低功耗方案都是针对USB收发器连接外部设备的场景。但在个人电脑(personal computer，PC)、平板电脑、机顶盒、电视等产品的实际使用场景中，USB收发器更多处于未连接外部设备的状态。
对于USB收发器未连接外部设备的场景则是按照USB接口处于空闲态处理的，以典型的28纳米(nm)工艺的芯片为例，一个USB接口的功耗将在10毫瓦(mW)以上。在此场景下，USB接口则会产生较大的功耗。
发明内容
本申请提供接口组件、芯片和电子设备，可以降低USB接口的功耗。
第一方面，本申请提供了一种接口组件，所述接口组件包括：包括：通用串行总线USB主机控制器、USB收发器、控制电路和第一信号切换电路，其中，所述USB主机控制器和所述控制电路通过所述第一信号切换电路与所述USB收发器相连；所述控制电路，用于在所述USB收发器未连接外部设备的情况下，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态。
上述技术方案中的接口组件除包括USB主机控制器以外还增加了控制电路，可以通过第一信号切换电路切换USB收发器控制信号的来源。也就是说，在一些情况下USB收发器可以由USB主机控制器控制，在另一些情况下USB收发器可以由控制电路控制。并且具体地在所述USB收发器未连接外部设备的情况下，控制电路可以控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态，从而可以降低USB接口的功耗。
并且上述技术方案并未改变USB相关协议，可以避免引入USB兼容性问题。
在一种可能的实现方式中，所述控制电路，还用于在所述USB收发器连接外部设备的情况下，控制所述USB收发器退出所述低功耗状态；所述控制电路，还用于在所述USB收发器退出所述低功耗状态之后，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
在一种可能的实现方式中，所述接口组件还包括第二信号切换电路，所述USB收发器和所述控制电路通过所述第二信号切换电路与所述USB主机控制器相连；所述控制电路，还用于在所述USB收发器未连接外部设备的情况下，控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
在一种可能的实现方式中，所述接口组件还包括检测电路，所述检测电路与所述控制电路以及所述USB收发器相连；所述检测电路，用于检测所述USB收发器上是否连接外部设备，并向所述控制电路传输检测结果；所述控制电路，具体用于在所述检测结果指示所述USB收发器未连接外部设备的情况下，控制所述USB收发器进入所述低功耗状态。
在一种可能的实现方式中，所述控制电路包括控制寄存器、状态寄存器、中断电路和中央处理单元CPU；所述状态寄存器，用于存储所述检测电路的检测结果，并通过所述中断电路向所述CPU上报所述检测结果；所述CPU，用于在所述检测结果指示所述USB收发器未连接外部设备的情况下，执行以下操作中的至少一个：通过配置所述控制寄存器中的第一控制信号，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接；通过配置所述控制寄存器中的第二控制信号控制所述USB收发器进入所述低功耗状态；通过配置所述控制寄存器中的第三控制信号控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
在一种可能的实现方式中，所述CPU，还用于在所述检测结果指示所述USB收发器连接外部设备的情况下，执行以下操作中的至少一个：通过配置所述控制寄存器中的所述第二控制信号控制所述USB收发器退出所述低功耗状态；在所述USB收发器退出所述低功耗状态之后，通过配置所述控制寄存器的所述第一控制信号控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
上述技术方案采用软件实现的方式对信号切换单元进行控制，成本较低。
在一种可能的实现方式中，所述控制电路包括控制寄存器、状态寄存器和控制逻辑电路；所述状态寄存器，用于存储所述检测电路的检测结果；所述控制逻辑电路，用于在所述检测结果指示所述USB收发器未连接外部设备的情况下，执行以下操作中的至少一个：控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接；控制所述USB收发器进入所述低功耗状态；控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
上述技术方案通过逻辑电路实现对信号切换电路的控制，相比于采用软件实现的方式，可以降低软件的复杂度。
在一种可能的实现方式中，所述控制逻辑电路，还用于在所述检测结果指示所述USB收发器上连接外部设备的情况下，执行以下操作中的至少一个：控制所述USB收发器退出所述低功耗状态；在所述USB收发器退出所述低功耗状态之后，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
上述技术方案通过逻辑电路实现对信号切换电路的控制，相比于采用软件实现的方式，可以降低软件的复杂度。
在一种可能的实现方式中，所述第一信号切换电路包括第一输入端、第二输入端、第一输出端以及第一控制端，所述第一输入端、所述第一控制端分别与所述控制电路连接，所述第二输入端与所述USB主机控制器连接，所述第一输出端与所述USB收发器连接；所述第二信号切换电路包括第三输入端、第四输入端、第二输出端以及第二控制端，所述第三输入端、所述第二控制端分别与所述控制电路连接，所述第四输入端与所述USB收 发器连接，所述第二输出端与所述USB主机控制器连接；所述控制电路，具体用于在所述USB收发器未连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以及，通过所述第二控制端，控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接；所述控制电路，具体还用于当所述USB收发器上连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，以及通过所述第一控制端和所述第二控制端连通所述USB主机控制器与所述USB收发器之间的连接。
在一种可能的实现方式中，所述检测电路包括滤波器，所述滤波器与所述控制电路以及所述USB收发器相连，用于检测所述USB收发器上是否连接外部设备。
在一种可能的实现方式中，当所述USB收发器处于所述低功耗状态时，所述USB收发器的锁相环PLL电路处于关闭状态。
由于PLL电路是USB收发器中的高功耗器件，将PLL电路关闭。可以改用功耗较低(或者说不产生额外功耗)系统时钟信号来保证USB主机控制器的正常工作。这样可以使USB接口功耗降低。
第二方面，本申请供了一种控制方法，所述方法应用于接口组件中，所述接口组件包括通用串行总线USB主机控制器、USB收发器、控制电路和第一信号切换电路，其中，所述USB主机控制器和所述控制电路通过所述第一信号切换电路与所述USB收发器相连，所述方法包括：在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态。
在一种可能的实现方式中，所述方法还包括：在所述USB收发器连接外部设备的情况下，所述控制电路控制所述USB收发器退出所述低功耗状态；在所述USB收发器退出所述低功耗状态之后，所述控制电路控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
在一种可能的实现方式中，所述接口组件还包括第二信号切换电路，所述USB收发器和所述控制电路通过所述第二信号切换电路与所述USB主机控制器相连，所述方法还包括：在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
在一种可能的实现方式中，所述接口组件还包括检测电路，所述检测电路与所述控制电路以及所述USB收发器相连，所述方法还包括：所述控制电路接收所述检测电路传送的检测结果，所述检测结果用于指示所述USB收发器上是否连接外部设备；在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态，包括：在所述检测结果指示所述USB收发器未连接外部设备的情况下，所述控制电路控制控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，并控制所述USB收发器进入所述低功耗状态。
在一种可能的实现方式中，所述第一信号切换电路包括第一输入端、第二输入端、第一输出端以及第一控制端，所述第一输入端、所述第一控制端分别与所述控制电路连接， 所述第二输入端与所述USB主机控制器连接，所述第一输出端与所述USB收发器连接；所述第二信号切换电路包括第三输入端、第四输入端、第二输出端以及第二控制端，所述第三输入端、所述第二控制端分别与所述控制电路连接，所述第四输入端与所述USB收发器连接，所述第二输出端与所述USB主机控制器连接；在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，包括：所述控制电路在所述USB收发器未连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以及，通过所述第二控制端，控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接；所述控制电路在所述USB收发器上连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，以及通过所述第一控制端和所述第二控制端连通所述USB主机控制器与所述USB收发器之间的连接。
在一种可能的实现方式中，所述检测电路包括滤波器，所述滤波器与所述控制电路以及所述USB收发器相连，用于检测所述USB收发器上是否连接外部设备。
在一种可能的实现方式中，当所述USB收发器处于所述低功耗状态时，所述USB收发器的锁相环PLL电路处于关闭状态。
第三方面，本申请提供了一种芯片，所述芯片包括处理器以及如第一方面或第一方面的任意一种可能的实现方式中所述的接口组件。
第四方面，本申请提供了一种电子设备，所述电子设备包括处理器、存储器以及如第一方面或第一方面的任意一种可能的实现方式中所述的接口组件。
附图说明
图1是可以应用本申请实施例的技术方案的USB系统的示意性结构图。
图2是本申请实施例的接口组件的示意性结构图。
图3是本申请实施例的接口组件的信号流向的示意图。
图4是本申请实施例的接口组件的另一信号流向的示意图。
图5是本申请实施例的控制电路的示意性结构图。
图6是本申请实施例的另一控制电路的示意性结构图。
图7是MUX的示意性结构图。
图8是本申请另一实施例提供的接口组件的示意性结构图。
图9是本申请又一实施例提供的接口组件的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例的技术方案可以应用于各种需要降低接口功耗的设备或产品中，只要该设备或产品中通过USB接口与外部设备进行数据传输即可。例如，PC、平板电脑、机顶盒、电视等。可以理解地，本申请实施例的技术方案同样可以应用于其他类型的接口系统中，例如高清晰度多媒体接口(high definition multimedia interface，HDMI)、外部串行高技术配置(external serial advanced technology attachment，E-SATA)接口、视频图像阵列 (video graphics array，VGA)接口等。本申请以USB接口为例，对本申请的技术方案进行描述。
本申请实施例对USB接口的类型不作具体限定，例如可以是Micro-USB、Mini-USB、Sub-USB、USB-type C等。
图1是可以应用本申请实施例的技术方案的USB系统的示意性结构图。如图1所示，USB主机控制器101通过系统总线115连接到存储器114(例如，双倍速率同步动态随机存储器(double data rate synchronous dynamic random access memory，DDR SDRAM)、中央处理单元(central processing unit，CPU)1041和USB收发器102相连，USB主机控制器101在接收到CPU 1041下发的任务后，通过USB收发器102实现存储器104与外部设备106之间的数据的读出或写入，其中外部设备106与USB收发器102连接。
现有的USB接口的低功耗方案都是针对USB收发器连接USB设备的场景，但在个人电脑(personal computer，PC)、平板电脑、机顶盒、电视等产品的实际使用场景中，USB收发器更多处于未连接USB设备的状态，而对于USB收发器未连接USB设备的情况，通常按照USB主机控制器和USB收发器处于空闲态处理，而非进入挂起状态。以典型的28纳米(nm)工艺的芯片为例，一个USB接口的功耗将在10毫瓦(mW)以上。在此场景下，USB接口则会产生较大的功耗。因此，本申请实施例基于接口组件200，提供了针对USB收发器未连接USB设备的场景的低功耗方案。
图2是本申请实施例的接口组件的示意性结构图。如图2所示，接口组件200包括USB主机控制器201、USB收发器202、控制电路204和第一信号切换电路205-1。USB主机控制器201、USB收发器202分别可与图1中的USB主机控制器101、USB收发器102对应。
其中，USB主机控制器201和控制电路204通过第一信号切换电路205-1与USB收发器202相连。也就是说，在USB主机控制器201与USB收发器202之间增加了控制电路204与第一信号切换电路205-1。
本申请实施例对USB主机控制器201的类型不作具体限定，例如增强主机控制接口(enhanced host controller interface，EHCI)主机控制器、通用主机控制接口(universal host controller interface，UHCI)主机控制器、开放主机控制接口(open host controller interface，OHCI)主机控制器等。
本申请实施例对USB收发器202的类型不作具体限定，例如USB2.0收发器宏单元接口(USB2.0transceiver macrocell interface，UTMI)收发器等。
控制电路204用于在USB收发器202未连接外部设备的情况下，控制第一信号切换电路205-1连通控制电路204与USB收发器202之间的连接，以使得控制电路204控制USB收发器202进入低功耗状态。其中，连通控制电路204与USB收发器202之间的连接可以是连通二者之间的信号发送/接收。
具体地，在第一信号切换电路205-1连通控制电路204和USB收发器202之间的连接的情况下，控制电路204的发出的控制信号就可以到达USB收发器202，从而改变USB收发器202的状态。可选地，USB收发器202处于低功耗状态时，关闭至少部分电路以节省功耗，例如，低功耗状态为挂起状态。可选地，当USB收发器202处于低功耗状态时，USB收发器202的锁相环PLL电路关闭。由于在不改变现有的USB协议的情况下，在本 申请实施例的技术方案中，USB收发器202在未连接外部设备时，处于低功耗状态，而USB主机控制器201处于非低功耗状态，因此，为了使USB主机控制器201正常工作，在USB收发器202处于低功耗状态时，可以使USB主机控制器201连接到系统时钟信号。
也就是说，在USB收发器202连接外部设备的情况下，USB收发器202由USB主机控制器201控制，处于功耗较高的状态，以待进行数据传输；在USB收发器202未连接外部设备的情况下，USB收发器202由控制电路204控制进入功耗较低的状态，例如低功耗状态，从而降低USB接口的功耗。
本申请实施例的第一信号切换电路205-1可以根据USB收发器202是否连接外部设备进行切换。作为一个示例，第一信号切换电路205-1可以由控制电路204控制，具体地，控制电路204在USB收发器202连接外部设备的情况下，控制第一信号切换电路205-1连通USB主机控制器201与USB收发器202之间的连接，在USB收发器202未连接外部设备的情况下，控制第一信号切换电路205-1连通控制电路204向USB收发器202之间的连接。
可以理解地，本申请实施的接口组件还可以有更多控制电路，例如，两个控制电路或者两个以上的控制电路，相应地，本申请实施例的第一信号切换电路205-1也可以进行更多路的信号的切换，例如，3路或者大于3路等。以接口组件具有两个控制电路204-1和204-2，第一信号切换电路205-1可以进行3路信号之间的切换为例，例如，在第一信号切换电路205-1连通USB主机控制器201与USB收发器之间的连接时，USB收发器处于空闲态；在第一信号切换电路205-1连通控制电路204-1与USB收发器202之间的连接时，USB收发器处于低功耗状态；在第一信号切换电路205-1连通控制电路204-2与USB收发器202之间的连接时，USB收发器处于空闲态和低功耗状态以外的其他状态。下面为了描述方便，以接口组件具有1控制电路204，第一信号切换电路205-1可以进行两路信号之间的切换为例进行描述。
可选地，控制电路204还用于在USB收发器202连接外部设备的情况下，控制USB收发器202退出低功耗状态。例如，控制电路可以在USB收发器202上有外部设备插入时，控制USB收发器202退出低功耗状态。
可选地，控制电路204，还用于在USB收发器202退出低功耗状态之后，控制第一信号切换电路205-1断开控制电路204与USB收发器202之间的连接，并连通USB主机控制器201与USB收发器202之间的连接。
也就是说，在不改变现有的USB协议的情况下，在本申请实施例的技术方案中，USB收发器202在未连接外部设备时，将USB收发器202切换到了低功耗状态，而USB主机控制器201处于空闲状态，而非低功耗状态，因此，在USB收发器202连接了外部设备时，为了避免由于USB收发器202和USB主机控制器201所处状态不一致导致的各种问题，需要先使USB收发器202恢复到正常状态，例如，开启在低功耗状态关闭的电路等，使得USB收发器202恢复到正常状态，再导通USB主机控制器与USB收发器之间的信号连接。
可以理解地，当第一信号切换电路205-1连通控制电路204与USB收发器202之间的连接的情况下，USB主机控制器201向USB收发器202发送的信号是断开的；当第一信号切换电路205-1连通USB主机控制器201与USB收发器202之间的连接的情况下， 控制电路204向USB收发器202发送的信号是断开的。这样可以避免信号之间的干扰。
可选地，接口组件200还包括第二信号切换电路205-2。USB收发器202和控制电路204通过第二信号切换电路205-2与USB主机控制器201相连。也就是说，可以第二信号切换电路205-2改变USB主机控制器201的输入信号的信号来源。控制电路204还用于在USB收发器202未连接外部设备的情况下，控制第二信号切换电路205-2连通控制电路204与USB主机控制器201之间的连接。
需要说明的是，第一信号切换电路205-1和第二信号切换电路205-2的控制信号可以为同一个控制信号，也可以是使用不同的控制信号。
也就是说，在USB收发器连接USB设备的情况下，由USB设备处于功耗较高的状态，以待进行数据传输，而在USB收发器没有连接USB设备的情况下，USB控制器可由控制电路控制进入功耗较低的状态，例如低功耗状态，从而降低USB接口的功耗。
可选地，本申请实施例的接口组件200还包括检测电路203，检测电路203与USB收发器202、控制电路204相连，用于检测USB收发器202是否连接外部设备，并将检测结果发送给控制电路204，以便控制单电路204根据检测结果对第一信号切换电路205-1、第二信号切换电路205-2和USB收发器202进行控制。
检测电路的检测结果可以用比特位的状态值或者检测电路输出信号的高低电平来表示。作为一个示例，用两个比特表示，其中一个比特表示是否有外部设备连接，一个比特位表示连接状态是否有变化。例如，当两个比特的状态值为00时，表示USB收发器202一直处于未连接外部设备的状态；当两个比特的状态值为01时，表示无外部设备连接并且状态发生改变，也就是说USB收发器202上的外部设备拔出；当两个比特的状态值为10时，表示有外部设备连接并且状态未发生改变，也就是说USB收发器202一直连接外部设备；当两个比特的状态值为11时，表示有外部设备连接并且状态发生改变，也就是说USB收发器202上插入外部设备。
下面结合图3和图4对接口组件200的信号流进行描述。
对于USB收发器202未连接外部设备的情况，如图3所示，检测电路203接收来自USB收发器202的第一信号310，并在第一信号310指示USB收发器202未连接外部设备的情况下，生成第二信号307，第二信号307用于向控制电路204指示USB收发器202未连接外部设备；控制电路204在接收到第二信号307之后，控制第一信号切换电路205-1断开USB主机控制器201与USB收发器202之间的连接，并连通控制电路204与USB收发器202之间的连接，使得控制电路204发出的第二控制信号311到达USB收发器202；并且控制第二信号切换电路205-2断开USB主机控制器201与USB收发器202之间的连接，连通控制电路204与USB主机控制器201之间的连接；USB收发器202在接收到第二控制信号311之后，进入低功耗状态。
对于USB收发器202连接外部设备的情况，如图4所示，检测电路203在第一信号310指示USB收发器202连接外部设备的情况下，生成第三信号412，第三信号412用于向控制电路204指示USB收发器202连接外部设备；控制电路204在接收到第三信号412之后，在控制电路204与USB收发器202之间的信号连通的情况下，向USB收发器202发送第四控制信号413；USB收发器202在接收到第四控制信号413之后，退出低功耗状态；控制电路204在USB收发器202退出低功耗状态之后，控制第一信号切换电路205-1 断开控制电路204与USB收发器之间的连接，并连通USB主机控制器201与USB收发器202之间的连接。
此外，在系统初始化的时候，USB主机控制器201和USB收发器202默认使用来自控制电路204的信号。也就是说，如果USB收发器202从始至终未连接外部设备，USB收发器202可以一直处于低功耗状态。这样，对于从未使用过的USB接口，同样可以降低功耗。
应理解，在切换USB收发器202和USB主机控制器201的信号来源的时候，控制电路204中用于控制第一信号切换电路205-1和第二信号切换电路205-2的信号始终保持连接。
本申请实施例对上述控制电路204的形式不作具体限定，只要其能够实现上文所述的功能即可。
作为一个示例，如图5所示，控制电路204包括控制寄存器204-4、状态寄存器204-1、中断电路204-2和CPU 204-3。状态寄存器204-1用于存储检测电路203的检测结果，并通过中断电路204-2向CPU 204-3上报所述检测结果。CPU 204-3用于在检测结果指示USB收发器202未连接外部设备的情况下，执行以下操作中的至少一个：
通过配置控制寄存器204-4中的第一控制信号，控制第一信号切换电路205-1连通控制电路204与USB收发器202之间的连接；通过配置所述控制寄存器204-4中的第二控制信号311，控制USB收发器202进入低功耗状态；通过配置所述控制寄存器204-4中的第三控制信号，控制第二信号切换电路205-2连通控制电路204与USB主机控制器201之间的连接。
CPU 204-3还用于在检测结果指示USB收发器202连接外部设备的情况下，执行以下操作中的至少一个：
通过配置控制寄存器204-4中的第二控制信号311控制USB收发器202退出低功耗状态；在USB收发器202退出低功耗状态之后，通过配置控制寄存器204-4的第一控制信号控制第一信号切换电路205-1断开控制电路204与USB收发器202之间的连接，并连通USB主机控制器201与USB收发器202之间的连接。
具体地，对于USB收发器202未连接外部设备的情况，状态寄存器204-1用于在接收到来自检测电路203的第二信号307之后，通过中断电路204-2向CPU 204-3上报第一中断事件，该第一中断事件为USB收发器202未连接外部设备(例如，在外部设备拔出时)，CPU 204-3用于根据第一中断事件，配置控制寄存器204-4，以便控制寄存器204-4控制第一信号切换电路205-1断开USB主机控制器201与USB收发器202之间的连接，连通控制电路204与USB收发器202之间的连接，使得控制电路204发出的第二控制信号311到达USB收发器202；并且控制第二信号切换电路205-2断开USB主机控制器201与USB收发器202之间的连接，连通控制电路204与USB主机控制器201之间的连接；USB收发器202在接收到第二控制信号311之后，进入低功耗状态。
对于外部设备插入USB收发器202的情况，状态寄存器204-1用于在接收到来自检测电路203的第三信号412之后，通过中断电路204-2向CPU 204-3上报第二中断事件，该第一中断事件为USB收发器202连接外部设备(例如，在外部设备插入时)，CPU 204-3用于根据第二中断事件，配置控制寄存器204-4，以便在控制电路204与USB收发器202 之间的信号连通的情况下，向USB收发器202发送第四控制信号413；USB收发器202在接收到第四控制信号413之后，退出低功耗状态；控制电路204在USB收发器202退出低功耗状态之后，控制第一信号切换电路205-1断开控制电路204与USB收发器之间的连接，并连通USB主机控制器201与USB收发器202之间的连接。
作为另外一个示例，如图6所示，控制电路204包括控制寄存器204-6、状态寄存器204-5和控制逻辑电路204-7。状态寄存器204-5用于存储检测电路203的检测结果；控制逻辑电路204-7用于在检测结果指示USB收发器202未连接外部设备的情况下，执行以下操作中的至少一个：
控制第一信号切换电路205-1连通控制电路204与USB收发器202之间的连接；控制USB收发器202进入低功耗状态；控制第二信号切换电路205-2连通控制电路204与USB主机控制器201之间的连接。
控制逻辑电路204-7还用于在检测结果指示USB收发器202上连接外部设备的情况下，执行以下操作中的至少一个：
控制USB收发器202退出所述低功耗状态；在USB收发器202退出低功耗状态之后，控制第一信号切换电路205-1断开控制电路204与USB收发器202之间的连接，并连通USB主机控制器201与USB收发器202之间的连接。
具体地，对于USB收发器202未连接外部设备的情况，状态寄存器204-5用于在接收到来自检测电路203的第二信号307之后，生成第四信号，控制逻辑电路204-7用于在接收到第四信号之后，控制第一信号切换电路205-1连通控制逻辑电路204-7与USB收发器202之间的连接，以及控制寄存器204-6与USB收发器202之间的连接，控制第二信号切换电路205-2连通控制寄存器204-6与USB主机控制器201之间的连接，以便控制USB收发器202进入低功耗状态。
对于外部设备插入USB收发器202的情况，状态寄存器204-5用于在接收到来自检测电路的第三信号412之后，生成第五信号，控制逻辑电路204-7用于在接收到第五信号之后，控制USB收发器202退出低功耗状态，在USB收发器202退出低功耗状态后，控制第一信号切换电路205-1连通USB主机控制器201与USB收发器202之间的连接，控制第二信号切换电路205-2连通USB收发器202与USB主机控制器201之间的连接。
可以理解地，控制电路204也可以完全使用软件编程实现，或者完全通过硬件实现，或者通过软硬件结合的方式实现，本申请实施例对此不作具体限定。
本申请对第一信号切换电路205-1的形式不作具体限定。作为一个示例，第一信号切换电路205-1可以由一个或者多个复用器(multiplexer，MUX)实现。可选地，第一信号切换电路205-1包括第一输入端、第二输入端、第一输出端以及第一控制端，第一输入端、第一控制端分别与控制电路204连接，第二输入端与USB收发器202连接，第一输出端与USB主机控制器201连接。控制电路204在所述USB收发器未连接外部设备的情况下，通过第一控制端，控制第一信号切换电路205-1连通控制电路204与USB收发器202之间的连接；当USB收发器202上连接外部设备的情况下，通过第一控制端，控制第一信号切换电路205-1断开控制电路204与USB收发器202之间的连接，连通USB主机控制器201发向USB收发器202的信号。
同样，第二信号切换电路205-2可以由一个或者多个MUX实现。可选地，第二信号 切换电路205-2包括第三输入端、第四输入端、第二输出端以及第二控制端，第三输入端、第二控制端分别与控制电路204连接，第四输入端与USB主机控制器201连接，第二输出端与USB收发器202连接。控制电路204在所述USB收发器未连接外部设备的情况下，可以通过控制第二控制端，控制第二信号切换电路205-2连通控制电路204与USB主机控制器201之间的连接；当USB收发器202上连接外部设备的情况下，通过第二控制端，控制第二信号切换电路205-2断开控制电路204与USB主机控制器201之间的连接，连通USB收发器202发向USB主机控制器201的信号。
图7是MUX的示意性结构图。如图7所示，MUX具有两个输入端A和B、一个输出端D，以及一个控制端C。输入端A和B分别可以对应于上文的第一输入端、第二输入端，或第三输入端、第四输入端，输出端D可以对应于上文的第一输出端或第二输出端，控制端C可以对应于上文的第一控制端或第二控制端。控制电路204通过控制端C，可以实现输出端D＝输入端A或输出端D＝输入端B，从而实现信号切换。
应理解，本申请实施例MUX的实现方式不作具体限定，例如可以使用软件编程实现，也可以通过硬件实现，或者通过软硬件结合的方式实现。
本申请实施例对检测电路203的形式不作具体限定，只要其能实现检测USB收发器202是否连接外部设备即可。例如，检测电路203可以是滤波器。本申请对检测电路的实现方式不作具体限定，例如可以使用软件编程实现，也可以通过硬件实现，或者通过软硬件结合的方式实现。
下面结合具体地例子，对本申请实施例的技术方案进行详细描述。
图8是本申请另一实施例提供的接口组件的示意性结构图。图8中的USB主机控制器801可以对应于上文的主机控制器201，USB2.0收发器宏单元接口物理层(UTMI physical layer，UTMI PHY)802可以对应于上文的USB收发器202，控制电路804(包括中断电路8042、CSR 8041和CPU 8043)可以对应于上文的控制电路204，10个MUX可以对应于上文的信号切换电路205，滤波器803可以对应于上文的检测电路203。
以EHCI主机控制器和UTMI PHY为例，EHCI主机控制器(即逻辑层)与UTMI PHY(即物理层)之间的接口标准为UTMI，EHCI主机控制器和UTMI PHY之间的信号描述如下：
utmi_linestate：对应于1和11，用于反馈USB总线连接情况的信号，根据UTMI接口协议，当UTMI PHY 802进入挂起(suspend)状态时，UTMI PHY 802内部的锁相环(phase locked loop，PLL)时钟源关闭，但utmi_linestate信号可以通过组合逻辑电路直接反应得到，也就是说，UTMI PHY 802进入低功耗状态后，utmi_linestate信号仍然能够传递外部设备的连接情况。
utmi_hostdisconnect：对应于2和12，用于反馈UTMI PHY 802是否为断连的信号。
utmi_suspendm：对应于3和13，用于控制UTMI PHY 802是否待机(即挂起状态)的信号，低电平有效；
utmi_xcvselect[1:0]：对应于4和14，用于控制UTMI PHY 802是否选择高速通道的信号；
utmi_termselect：对应于5和15，用于控制UTMI PHY 802是否连接高速电阻的信号；
utmi_opmode[1:0]：对应于6和16，用于控制UTMI PHY 802是否工作在正常编码模 式的信号；
utmi_rx：对应于7和17，用于UTMI PHY 802向USB主机控制器801发送从外部设备接收的数据；
utmi_tx：对应于8和18，用于UTMI PHY 802向外部设备发送从USB主机控制器801接收的数据；
clk_utmi：对应于9和19，UTMI PHY 802的工作时钟信号，从UTMI PHY 802经由时钟门控816连接至USB主机控制器801，60MHz，挂起状态下停钟；
clk_free：对应于10和20，UTMI PHY 802的工作时钟信号，从UTMI PHY 802经由时钟门控817连接至USB主机控制器801，60MHz，挂起状态下不停钟。
如图8所示，本申请实施例在EHCI主机控制器和UTMI PHY之间做一些增量电路设计，以实现上文所述的方案。具体地，在utmi_linestate，utmi_hostdisconnect，utmi_rx，之间分别设置MUX 805-1、805-2和805-7，在utmi_suspendm，utmi_rcvselect[1:0]，utmi_termselect，utmi_opmode[1:0]，utmi_tx之间分别设置MUX 805-3、805-4、805-5和805-6，在clk_utmi，clk_free之间分别设置MUX 805-9和805-10，其中，MUX 805-1、805-2和805-7的输出端连接USB主机控制器801，控制端连接控制寄存器804-4，以及两个输入端分别连接至控制寄存器804-4和UTMI PHY 802，MUX 805-3、805-4、805-5和805-6的输出端连接USB收发器802，控制端连接控制寄存器804-4，以及两个输入端分别连接至控制寄存器804-4和USB主机控制器801，MUX 805-9和805-10的输出端连接USB主机控制器801，控制端连接控制寄存器804-4，以及两个输入端分别连接至系统时钟信号818和UTMI PHY 802；来自UTMI PHY 802的utmi_linestate信号除了作为MUX 805-1的输入，还作为滤波器803的输入，以便在UTMI PHY 802由控制电路804控制时，让状态寄存器804-1可以获知UTMI PHY 802是否连接外部设备，其中滤波器803为连接状态检测滤波器，用于防止连接状态误检测；中断电路804-2可以是电平触发的一个中断信号线，可以信号保持高电平触发中断。
需要说明的是，图8中的每个MUX的控制端(即选择(select)信号)连接均未示出，实际上每个MUX的控制端均连接到控制寄存器804-4。
接口组件800的初始设置为默认值，具体配置如图8所示，例如，utmi_termselect输入为1，clk_free/clk_utmi等输入为系统时钟信号(clk_from_crg)818，也就是说，初始状态下，由控制电路804控制USB主机控制器801和UTMI PHY 802之间连接状态。在UTMI PHY 802上没有外部设备插上时，控制电路804(或称软件)通过MUX控制USB主机控制器801和UTMI PHY 802之间的连接断开。在UTMI PHY 802上有外部设备插上时，控制电路804再控制UTMI PHY 802和USB主机控制器801连通，例如，USB主机控制器801的utmi_terselect连接到UTMI PHY 802的utmi_terselect，USB主机控制器801的clk_free/clk_utmi连接到UTMI PHY 802的clk_free/clk_utmi等，此时接口组件800恢复了正常模式。
接口组件800通过滤波器803检测UTMI PHY 802是否连接外部设备。具体地，滤波器803被配置为利用utmi_linestate信号检测UTMI PHY 802是否连接外部设备。更具体地，在UTMI PHY 802的当前状态为未连接外部设备的情况下，如果滤波器803检测到utmi_linestate[1:0]等于2’b00，且持续时间大于x毫秒，说明外部设备拔出UTMI PHY 802； 在UTMI PHY 802的当前状态为连接外部设备的情况下，如果滤波器803检测到utmi_linestate[1:0]不等于2’b00，且持续时间大于y毫秒(ms)，说明外部设备插入UTMI PHY 802。
应理解，对于x的选取，应保证在有外部设备插入UTMI PHY 802的情况下，根据USB协议规定，utmi_linestate至少要持续3ms，才足以保证外部设备稳定连接上，所以x至少大于3ms。进一步考虑到如果x选取过大，会使得检测时间很长。因此，优选地，x的默认值可为10ms，且x可以由寄存器配置。同理，对于y的选取，应保证在没有外部设备插入UTMI PHY 802的情况下，USB总线不会出现持续时间大于y毫秒的utmi_linestate不等于2’b00的情况。按照USB2.0协议，y至少是0.25ms。y的值过小，容易受到外部毛刺的干扰，而y的值变大，会使检测时间变长。因此，优选地，y的默认值可为10ms，且y可以由寄存器配置。这样，本申请实施例的方案可以保证插拔检测的可靠性，降低误检测。
下面描述接口组件800的主要工作流程。
1、初始化
系统初始化时候，USB主机控制器801和UTMI PHY 802之间的连接状态为默认值，处于非连通状态。例如，控制电路804控制clk_free/clk_utmi为clk_from_crg，utmi_suspendm为0等，UTMI PHY 802进入待机状态(或称低功耗状态)。如果一直没有外部设备插入UTMI PHY 802，则UTMI PHY 802将一直处于低功耗状态。
2、设备插入
当有外部设备插入UTMI PHY 802的时候，滤波器803检测到外部设备插入，状态寄存器804-1存储连接状态，并通过中断电路804-2向CPU 804-3上报外部设备插入的中断事件，这时候软件收到中断事件，通过控制寄存器804-4设置utmi_suspendm为1，让UTMI PHY 802退出待机状态，待UTMI PHY 802退出待机状态之后，设置USB主机控制器801和UTMI PHY 802之间的信号连通。连通USB主机控制器801和UTMI PHY 802之间的信号时，先控制连通USB主机控制器801和UTMI PHY 802之间的clk_free/clk_utmi，后控制其他信号连通，完成之后USB主机控制器801和UTMI PHY 802则进入正常连接状态，之后的正常工作流程即与现有技术相同。
3、设备拔出
当有外部设备拔出UTMI PHY 802的时候，滤波器803检测到外部设备拔出，状态寄存器804-1存储连接状态，并通过中断电路804-2向CPU 804-3上报外部设备拔出的中断事件，这时候软件收到中断事件，先通过控制寄存器804-4控制USB主机控制器801和UTMI PHY 802之间的信号(例如，clk_free，clk_utmi等)断开，然后设置utmi_suspend为0，使UTMI PHY 802进入待机模式，即恢复到低功耗状态。
图9是本申请另一实施例提供的接口组件的示意性结构图。图9控制电路904包括控制寄存器904-6、状态寄存器904-5和控制逻辑电路904-7，其中控制逻辑电路904-7包括状态机。如图9所示，各MUX的控制端连接控制逻辑电路904-7。
接口组件800和接口组件900的不同之处在于接口组件800有中断设计，需要软件配合逻辑实现上述处理流程，例如CPU 804-3在收到中断事件之后根据具体事件控制UTMI PHY 802进入或退出低功耗状态，而在接口组件900中，这些操作由控制逻辑电路904-7 完成。接口组件900稍微增加了逻辑电路复杂度，换取的好处是不需要软件参与，避免增加软件的维护开销。
可选地，控制逻辑电路904-7可以采用现有的基本功能模块。
接口组件900的其他部分(例如，USB主机控制器901、UTMI PHY 902、滤波器903等)的结构和功能，以及接口组件900的工作流程可以参见图8的相关描述，在此不再赘述。
本申请实施例的技术方案，弥补了USB2.0协议的低功耗场景的考虑不足。在接口组件在未连接外部设备的情况下，将UTMI PHY配置为挂起状态，可以显著降低USB接口组件的整体功耗。以一个典型的28纳米(nm)工艺的芯片为例，UTMI PHY的面积约是USB主机控制器的10倍，降低PHY的功耗可以显著降低USB的整体功耗。对于USB接口组件不接外部设备的场景，28nm工艺的实测数据如下：如果UTMI PHY不进入低功耗状态，USB接口组件的功耗约15毫瓦(mW)；如果UTMI PHY进入低功耗状态，USB接口组件的功耗约0.5mW，节省功耗96％以上。
本申请实施例还提供了一种控制方法。所述方法应用于接口组件中，所述接口组件包括通用串行总线USB主机控制器、USB收发器、控制电路和第一信号切换电路，其中，所述USB主机控制器和所述控制电路通过所述第一信号切换电路与所述USB收发器相连，所述方法包括：在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态。
可选地，所述方法还包括：在所述USB收发器连接外部设备的情况下，所述控制电路控制所述USB收发器退出所述低功耗状态；在所述USB收发器退出所述低功耗状态之后，所述控制电路控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
可选地，所述接口组件还包括第二信号切换电路，所述USB收发器和所述控制电路通过所述第二信号切换电路与所述USB主机控制器相连，所述方法还包括：在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
可选地，所述接口组件还包括检测电路，所述检测电路与所述控制电路以及所述USB收发器相连，所述方法还包括：所述控制电路接收所述检测电路传送的检测结果，所述检测结果用于指示所述USB收发器上是否连接外部设备；在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态，包括：在所述检测结果指示所述USB收发器未连接外部设备的情况下，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，并控制所述USB收发器进入所述低功耗状态。
可选地，所述第一信号切换电路包括第一输入端、第二输入端、第一输出端以及第一控制端，所述第一输入端、所述第一控制端分别与所述控制电路连接，所述第二输入端与所述USB主机控制器连接，所述第一输出端与所述USB收发器连接；所述第二信号切换电路包括第三输入端、第四输入端、第二输出端以及第二控制端，所述第三输入端、所述 第二控制端分别与所述控制电路连接，所述第四输入端与所述USB收发器连接，所述第二输出端与所述USB主机控制器连接；在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，包括：所述控制电路在所述USB收发器未连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以及，通过所述第二控制端，控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接；所述控制电路在所述USB收发器上连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，以及通过所述第一控制端和所述第二控制端连通所述USB主机控制器与所述USB收发器之间的连接。
可选地，所述检测电路包括滤波器，所述滤波器与所述控制电路以及所述USB收发器相连，用于检测所述USB收发器上是否连接外部设备。
可选地，当所述USB收发器处于所述低功耗状态时，所述USB收发器的锁相环PLL电路处于关闭状态。
需要注意的是，本申请实施例中的“……中的至少一个”表示所列出的各项之一或其任意组合，例如，“A、B和C中的至少一个”表示：单独存在A，单独存在B，单独存在C，同时存在A和B，同时存在A和C，同时存在B和C，同时存在A、B和C这六种情况。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计 算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种接口组件，其特征在于，包括：通用串行总线USB主机控制器、USB收发器、控制电路和第一信号切换电路，其中，所述USB主机控制器和所述控制电路通过所述第一信号切换电路与所述USB收发器相连；
    所述控制电路，用于在所述USB收发器未连接外部设备的情况下，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态。
  2. 根据权利要求1所述的接口组件，其特征在于，
    所述控制电路，还用于在所述USB收发器连接外部设备的情况下，控制所述USB收发器退出所述低功耗状态；
    所述控制电路，还用于在所述USB收发器退出所述低功耗状态之后，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
  3. 根据权利要求1或2所述的接口组件，其特征在于，所述接口组件还包括第二信号切换电路，所述USB收发器和所述控制电路通过所述第二信号切换电路与所述USB主机控制器相连；
    所述控制电路，还用于在所述USB收发器未连接外部设备的情况下，控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
  4. 根据权利要求1至3中任一项所述的接口组件，其特征在于，所述接口组件还包括检测电路，所述检测电路与所述控制电路以及所述USB收发器相连；
    所述检测电路，用于检测所述USB收发器上是否连接外部设备，并向所述控制电路传输检测结果；
    所述控制电路，具体用于在所述检测结果指示所述USB收发器未连接外部设备的情况下，控制所述USB收发器进入所述低功耗状态。
  5. 根据权利要求4所述的接口组件，其特征在于，所述控制电路包括控制寄存器、状态寄存器、中断电路和中央处理单元CPU；
    所述状态寄存器，用于存储所述检测电路的检测结果，并通过所述中断电路向所述CPU上报所述检测结果；
    所述CPU，用于在所述检测结果指示所述USB收发器未连接外部设备的情况下，执行以下操作中的至少一个：
    通过配置所述控制寄存器中的第一控制信号，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接；
    通过配置所述控制寄存器中的第二控制信号控制所述USB收发器进入所述低功耗状态；
    通过配置所述控制寄存器中的第三控制信号控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
  6. 根据权利要求5所述的接口组件，其特征在于，所述CPU，还用于在所述检测结 果指示所述USB收发器连接外部设备的情况下，执行以下操作中的至少一个：
    通过配置所述控制寄存器中的所述第二控制信号控制所述USB收发器退出所述低功耗状态；
    在所述USB收发器退出所述低功耗状态之后，通过配置所述控制寄存器的所述第一控制信号控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
  7. 根据权利要求4所述的接口组件，其特征在于，所述控制电路包括控制寄存器、状态寄存器和控制逻辑电路；
    所述状态寄存器，用于存储所述检测电路的检测结果；
    所述控制逻辑电路，用于在所述检测结果指示所述USB收发器未连接外部设备的情况下，执行以下操作中的至少一个：
    控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接；
    控制所述USB收发器进入所述低功耗状态；
    控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
  8. 根据权利要求7所述的接口组件，其特征在于，所述控制逻辑电路，还用于在所述检测结果指示所述USB收发器上连接外部设备的情况下，执行以下操作中的至少一个：
    控制所述USB收发器退出所述低功耗状态；
    在所述USB收发器退出所述低功耗状态之后，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
  9. 根据权利要求3至8中任一项所述的接口组件，其特征在于，
    所述第一信号切换电路包括第一输入端、第二输入端、第一输出端以及第一控制端，所述第一输入端、所述第一控制端分别与所述控制电路连接，所述第二输入端与所述USB主机控制器连接，所述第一输出端与所述USB收发器连接；
    所述第二信号切换电路包括第三输入端、第四输入端、第二输出端以及第二控制端，所述第三输入端、所述第二控制端分别与所述控制电路连接，所述第四输入端与所述USB收发器连接，所述第二输出端与所述USB主机控制器连接；
    所述控制电路，具体用于在所述USB收发器未连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以及，通过所述第二控制端，控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接；
    所述控制电路，具体还用于当所述USB收发器上连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，以及通过所述第一控制端和所述第二控制端连通所述USB主机控制器与所述USB收发器之间的连接。
  10. 根据权利要求4至9中任一项所述的接口组件，其特征在于，所述检测电路包括滤波器，所述滤波器与所述控制电路以及所述USB收发器相连，用于检测所述USB收发器上是否连接外部设备。
  11. 根据权利要求1至10中的任一项所述接口组件，其特征在于，当所述USB收发 器处于所述低功耗状态时，所述USB收发器的锁相环PLL电路处于关闭状态。
  12. 一种芯片，其特征在于，包括处理器以及如权利要求1至11中任一项所述的接口组件。
  13. 一种电子设备，其特征在于，包括处理器、存储器以及如权利要求1至11中任一项所述的接口组件。
  14. 一种控制方法，其特征在于，应用于接口组件中，所述接口组件包括通用串行总线USB主机控制器、USB收发器、控制电路和第一信号切换电路，其中，所述USB主机控制器和所述控制电路通过所述第一信号切换电路与所述USB收发器相连，所述方法包括：
    在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态。
  15. 根据权利要求14所述的方法，其特征在于，所述方法还包括：
    在所述USB收发器连接外部设备的情况下，所述控制电路控制所述USB收发器退出所述低功耗状态；
    在所述USB收发器退出所述低功耗状态之后，所述控制电路控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，并连通所述USB主机控制器与所述USB收发器之间的连接。
  16. 根据权利要求14或15所述的方法，其特征在于，所述接口组件还包括第二信号切换电路，所述USB收发器和所述控制电路通过所述第二信号切换电路与所述USB主机控制器相连，所述方法还包括：
    在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接。
  17. 根据权利要求14至16中任一项所述的方法，其特征在于，所述接口组件还包括检测电路，所述检测电路与所述控制电路以及所述USB收发器相连，所述方法还包括：
    所述控制电路接收所述检测电路传送的检测结果，所述检测结果用于指示所述USB收发器上是否连接外部设备；
    在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以使得所述控制电路控制所述USB收发器进入低功耗状态，包括：
    在所述检测结果指示所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，并控制所述USB收发器进入所述低功耗状态。
  18. 根据权利要求16或17所述的方法，其特征在于，
    所述第一信号切换电路包括第一输入端、第二输入端、第一输出端以及第一控制端，所述第一输入端、所述第一控制端分别与所述控制电路连接，所述第二输入端与所述USB主机控制器连接，所述第一输出端与所述USB收发器连接；
    所述第二信号切换电路包括第三输入端、第四输入端、第二输出端以及第二控制端，所述第三输入端、所述第二控制端分别与所述控制电路连接，所述第四输入端与所述USB 收发器连接，所述第二输出端与所述USB主机控制器连接；
    在所述USB收发器未连接外部设备的情况下，所述控制电路控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，包括：
    所述控制电路在所述USB收发器未连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路连通所述控制电路与所述USB收发器之间的连接，以及，通过所述第二控制端，控制所述第二信号切换电路连通所述控制电路与所述USB主机控制器之间的连接；
    所述控制电路在所述USB收发器上连接外部设备的情况下，通过所述第一控制端，控制所述第一信号切换电路断开所述控制电路与所述USB收发器之间的连接，以及通过所述第一控制端和所述第二控制端连通所述USB主机控制器与所述USB收发器之间的连接。
  19. 根据权利要求17或18所述的方法，其特征在于，所述检测电路包括滤波器，所述滤波器与所述控制电路以及所述USB收发器相连，用于检测所述USB收发器上是否连接外部设备。
  20. 根据权利要求14至19中的任一项所述方法，其特征在于，当所述USB收发器处于所述低功耗状态时，所述USB收发器的锁相环PLL电路处于关闭状态。
PCT/CN2019/089562 2019-05-31 2019-05-31 接口组件、芯片及电子设备 Ceased WO2020237635A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980078223.0A CN113168207B (zh) 2019-05-31 2019-05-31 接口组件、芯片及电子设备
PCT/CN2019/089562 WO2020237635A1 (zh) 2019-05-31 2019-05-31 接口组件、芯片及电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/089562 WO2020237635A1 (zh) 2019-05-31 2019-05-31 接口组件、芯片及电子设备

Publications (1)

Publication Number Publication Date
WO2020237635A1 true WO2020237635A1 (zh) 2020-12-03

Family

ID=73551947

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/089562 Ceased WO2020237635A1 (zh) 2019-05-31 2019-05-31 接口组件、芯片及电子设备

Country Status (2)

Country Link
CN (1) CN113168207B (zh)
WO (1) WO2020237635A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116866111A (zh) * 2023-08-24 2023-10-10 珠海格力电器股份有限公司 一种can总线的接线控制装置、方法和汽车

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114356815B (zh) * 2021-12-09 2024-12-03 青岛信芯微电子科技股份有限公司 一种usb控制器、芯片、显示设备和控制方法
CN114564099B (zh) * 2022-01-20 2024-06-04 珠海亿智电子科技有限公司 一种降低usb传输功耗的方法及电子装置
CN120743085B (zh) * 2025-09-03 2026-01-27 厦门紫光展锐科技有限公司 一种基于通信行为预测的usb低功耗控制方法及系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101997963A (zh) * 2009-08-31 2011-03-30 英华达股份有限公司 可携式通讯装置的电源管理方法以及系统
US20150143138A1 (en) * 2013-11-21 2015-05-21 Genesys Logic, Inc. System for detecting universal serial bus (usb) device and method thereof
CN104882155A (zh) * 2015-04-30 2015-09-02 厦门睿联创信息科技有限公司 低功耗防丢安全优盘
CN105095132A (zh) * 2014-04-30 2015-11-25 名硕电脑(苏州)有限公司 可自动切换通用串行总线主从设备模式的电子装置及其操作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010015318A (ja) * 2008-07-02 2010-01-21 Toshiba Corp Ｕｓｂホストコントローラ、情報処理装置及びプログラム
KR101329014B1 (ko) * 2008-10-30 2013-11-12 삼성전자주식회사 휴대단말에서 스위칭 회로의 모드 제어 방법 및 장치
US20130067258A1 (en) * 2010-05-20 2013-03-14 Toshiaki Furuya Data processor and electronic control unit
CN102821444B (zh) * 2011-06-08 2017-10-10 中兴通讯股份有限公司 自动功耗控制方法及系统
CN107967049A (zh) * 2017-10-18 2018-04-27 珠海全志科技股份有限公司 一种基于usb协议降低芯片功耗的实现方法
CN108563537A (zh) * 2018-03-13 2018-09-21 珠海慧联科技有限公司 一种usb主从检测装置和方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101997963A (zh) * 2009-08-31 2011-03-30 英华达股份有限公司 可携式通讯装置的电源管理方法以及系统
US20150143138A1 (en) * 2013-11-21 2015-05-21 Genesys Logic, Inc. System for detecting universal serial bus (usb) device and method thereof
CN105095132A (zh) * 2014-04-30 2015-11-25 名硕电脑(苏州)有限公司 可自动切换通用串行总线主从设备模式的电子装置及其操作方法
CN104882155A (zh) * 2015-04-30 2015-09-02 厦门睿联创信息科技有限公司 低功耗防丢安全优盘

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116866111A (zh) * 2023-08-24 2023-10-10 珠海格力电器股份有限公司 一种can总线的接线控制装置、方法和汽车

Also Published As

Publication number Publication date
CN113168207A (zh) 2021-07-23
CN113168207B (zh) 2025-01-03

Similar Documents

Publication Publication Date Title
WO2020237635A1 (zh) 接口组件、芯片及电子设备
TWI416909B (zh) 通用序列匯流排及乙太網路控制器組合裝置
US8683091B2 (en) Device disconnect detection
TWI628545B (zh) 計算裝置、通用序列匯流排埠以及操作通用序列匯流排的方法
US7193442B2 (en) USB 1.1 for USB OTG implementation
EP2912831B1 (en) Ethernet over usb interfaces with full-duplex differential pairs
US11347669B2 (en) Equalization time configuration method, chip, and communications system
US20140006653A1 (en) Device connect detection
CN101369948B (zh) 一种实现低功耗的通信系统
US10394309B2 (en) Power gated communication controller
US6715019B1 (en) Bus reset management by a primary controller card of multiple controller cards
CN209072526U (zh) 以太网交换装置
CN114661646A (zh) 串口转接控制电路
CN109039955A (zh) 一种基于光纤通道的存储系统
TWI818834B (zh) 微控制器及應用其之序列周邊介面系統
CN216249232U (zh) 一种视频高速采集与处理电路结构
US20060050731A1 (en) High-speed IEEE 1394 link interface
KR20250042841A (ko) 데이터 통신 인터페이스를 위한 입력-출력 전압 제어
CN209265223U (zh) 一种支持二次开发的串/并转化的接口处理板卡
CN223712163U (zh) 接口集成电路及接口集成设备
TW442721B (en) Adaptive power-down clock control
CN111624915A (zh) 一种上位机通过串口唤醒微控制器的方法
CN223155476U (zh) 多源异构的末端数据处理系统及电子设备
CN120614717A (zh) 基于usb协议的5g模组和下载口自适应系统
CN115915581A (zh) 一种主控电路板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19930503

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19930503

Country of ref document: EP

Kind code of ref document: A1

WWG Wipo information: grant in national office

Ref document number: 201980078223.0

Country of ref document: CN