WO2020237503A1 - 一种电容检测电路、电容检测方法、触控芯片以及电子设备 - Google Patents

一种电容检测电路、电容检测方法、触控芯片以及电子设备 Download PDF

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Publication number
WO2020237503A1
WO2020237503A1 PCT/CN2019/088819 CN2019088819W WO2020237503A1 WO 2020237503 A1 WO2020237503 A1 WO 2020237503A1 CN 2019088819 W CN2019088819 W CN 2019088819W WO 2020237503 A1 WO2020237503 A1 WO 2020237503A1
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WIPO (PCT)
Prior art keywords
cancellation
capacitor
switch unit
voltage
capacitance
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PCT/CN2019/088819
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English (en)
French (fr)
Inventor
蒋宏
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201980000896.4A priority Critical patent/CN112313611B/zh
Priority to EP19920628.5A priority patent/EP3770738B1/en
Priority to PCT/CN2019/088819 priority patent/WO2020237503A1/zh
Priority to US17/060,028 priority patent/US11206019B2/en
Publication of WO2020237503A1 publication Critical patent/WO2020237503A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • H03K17/9622—Capacitive touch switches using a plurality of detectors, e.g. keyboard
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/96071—Capacitive touch switches characterised by the detection principle
    • H03K2217/960725—Charge-transfer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/960735—Capacitive touch switches characterised by circuit details
    • H03K2217/96074—Switched capacitor

Definitions

  • This application relates to the field of touch technology, and in particular to a capacitance detection circuit, a capacitance detection method, a touch chip and an electronic device.
  • the principle is to detect the capacitance formed between the electrode and the system ground, which is called self-capacitance detection.
  • the capacitance formed between the detection electrode and the system ground has a basis Electric capacity or initial electric capacity.
  • the capacitance between the detection electrode and the system ground will increase. By detecting the change in the capacitance, the user's related touch operation can be judged.
  • the existing self-capacitance detection technology needs to offset the basic capacitance first, and then perform self-capacitance detection. Due to the large channel base capacitance of the flexible screen, the current cancellation method requires a huge capacitance, resulting in a huge chip area, and because capacitive touch often requires tens or hundreds of channels, the current basic capacitance cancellation method is not only costly. The chip size is severely exceeded and has no great practical value.
  • one of the technical problems solved by the embodiments of the present application is to provide a capacitance detection circuit, a touch chip and an electronic device to overcome the above-mentioned defects in the prior art.
  • An embodiment of the application provides a capacitance detection circuit, which includes: a control module, a charge transfer module, a processing module, a driving module, and a cancellation module, the control module is used to control the driving module to charge a capacitor to be measured;
  • the cancellation module is used to perform M times of charge cancellation processing on the capacitor under test;
  • the charge transfer module is used to perform conversion processing on the charge of the capacitor under test after the M times of charge cancellation processing to generate an output voltage;
  • the processing module is used to determine the capacitance change of the capacitance to be measured according to the output voltage.
  • the embodiment of the application provides a capacitance detection method applied to a capacitance detection circuit, which includes: controlling a driving module to charge a capacitor to be measured; controlling a cancellation module to charge a cancellation capacitor; The measured capacitance is subjected to M charge cancellation processing; the charge transfer module is controlled to transform the charge of the capacitance under test after the M times of charge cancellation processing to generate an output voltage; and based on the output voltage, the control processing module determines the to-be-measured The capacitance change of the capacitor.
  • An embodiment of the present application provides a touch control chip including: the capacitance detection circuit described in any embodiment of the present application.
  • An embodiment of the present application provides an electronic device, which includes the touch chip described in any embodiment of the present application.
  • the capacitance detection circuit includes: a control module, a charge transfer module, a processing module, a driving module, and a cancellation module
  • the control module is used to control the driving module to charge the capacitor to be measured
  • the cancellation module is used for charging the cancellation capacitor and performing M times of charge cancellation processing on the capacitance to be measured
  • the charge transfer module is used for canceling the charge of the capacitance to be measured after the M times of charge cancellation processing Perform conversion processing to generate an output voltage
  • the processing module is used to determine the capacitance change of the capacitance to be measured according to the output voltage.
  • FIG. 1 is a schematic structural diagram of a capacitive touch system according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of the structure of a capacitance detection circuit according to an embodiment of the present application.
  • FIG. 3 is a timing diagram of the capacitance detection circuit in FIG. 2 according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application.
  • FIG. 5 is a timing diagram of the capacitance detection circuit in FIG. 4 according to another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application.
  • FIG. 7 is a timing diagram of the capacitance detection circuit in FIG. 6 according to another embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application.
  • FIG. 9 is a timing diagram of the capacitance detection circuit in FIG. 8 according to another embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application.
  • FIG. 11 is a timing diagram of the capacitance detection circuit in FIG. 10 according to another embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application.
  • FIG. 13 is a timing diagram of the capacitance detection circuit in FIG. 12 according to another embodiment of the present application.
  • FIG. 14 is a flowchart of a method for canceling a capacitance to be measured according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a capacitive touch system according to an embodiment of the application; as shown in FIG. 1, it includes a touch sensor 101, a touch chip 102 and a host 103.
  • the touch sensor 101 has a two-layer structure, including a driving channel Tx and a sensing channel Rx. In this embodiment, there are 5 driving channels and 5 sensing channels, respectively. Their basic capacitance to the system ground is denoted as C1 ⁇ C5 and C6 ⁇ C10.
  • the touch chip 102 scans each channel, including the capacitance of each drive channel and each sensing channel to system ground, and calculates the capacitance change of each channel to system ground .
  • the capacitance of the channel where the finger approaches or touches the system ground will increase.
  • the capacitance between the finger and the driving channel Tx is Cd
  • the capacitance between the finger and the sensing channel Rx is Cs.
  • the capacitance of the driving channel Tx2 to the system ground will become C2+Cd
  • the capacitance of the sensing channel Rx3 to the system ground Will become C8+Cs.
  • the touch chip 102 detects that the capacitance of the driving channel Tx2 and the sensing channel Rx3 to the system ground will increase, while the capacitance of the other channels to the system ground is unchanged or approximately unchanged or smaller, so it can be calculated that the touch position is driving At the position where the channel Tx2 and the sensing channel Rx3 intersect, the coordinates at the position are sent to the host 103 to implement various functions of touch operation.
  • the channels are named as driving channels and sensing channels in this case, those skilled in the art can understand that in the self-capacitance detection mode, whether it is a driving channel or a sensing channel, a single channel is the receiving touch chip 102
  • the output drive signal channel is also the channel used to output the induction signal, which is different from the drive channel only responsible for receiving the drive signal and the induction channel only responsible for outputting the induction signal in the mutual capacitance mode.
  • the capacitance detection circuit is specifically configured on the above-mentioned touch chip 102 in FIG. 1. Therefore, it can be understood that the above-mentioned touch chip 102 includes the capacitance detection circuit described in the following embodiments.
  • the capacitance detection circuit includes: a control module 112, a drive module 122, a cancellation module 132, a charge transfer module 142, and a processing module 152.
  • the drive module 122, the cancellation module 132, and the charge transfer module 142 are specifically configured in the front-end circuit .
  • the control module 112 is used to control the driving module 122 to charge the capacitance to be measured, and the cancellation module is used to perform M charge cancellation processing on the capacitance to be measured, so that the cancellation capacitance is Perform charge cancellation processing; the charge transfer module 142 is used to transform the charge of the capacitor under test after the charge cancellation processing to generate an output voltage; the processing module 152 is used to determine the output voltage (Vout) The capacitance change before and after the capacitance to be measured is affected by the external electric field.
  • the driving module 122 includes a first switch unit K1 (a single switch is taken as an example), and the control module 112 is further used to control the first switch unit K1 to be in a closed state to make the driving The module 122 performs charging processing on the capacitor Cx to be measured. Further, when the first switch unit K1 is in the closed state, the first terminal of the capacitor Cx to be measured is electrically connected to the first voltage (Vcc), the second terminal is electrically connected to the second voltage to ground, and the first voltage is high. In the second voltage. In this embodiment, V CC is a positive supply voltage.
  • the cancellation module 132 includes a second switch unit K2 (take a single switch as an example) and a third switch unit K3 (take a single switch as an example), wherein the second switch unit K2 is connected to one end of the cancellation capacitor Cc, and the third switch unit K3 is connected to the other end of the cancellation capacitor.
  • the second switch unit K2 and the third switch unit K3 can be in different closed states, so as to realize the pair of the cancellation capacitor in the cancellation module.
  • the capacitance to be measured undergoes M times of charge cancellation processing.
  • the control module 112 controls the second switch unit and the third switch unit to be in the first closed state and The second closed state is switched back and forth M times, so that the cancellation capacitor cancels the charge of the capacitance under test.
  • the cancellation module charges the cancellation capacitor
  • the second switch unit K2 and the third switch unit K3 are in the first closed state
  • the first end of the cancellation capacitor Cc The second switch unit K2 is electrically connected to a third voltage (-Vcc)
  • the second end of the cancellation capacitor Cc is electrically connected to a fourth voltage (Vcc) through the third switch unit K3, and the fourth voltage is higher than all The third voltage.
  • the absolute value of the fourth voltage may be equal to the absolute value of the third voltage.
  • the control module 112 controls when the second switch unit K2 and the third switch unit K3 are in the second closed state, the cancellation capacitor Cc
  • the first end of the capacitor Cx is electrically connected to the first end of the capacitor Cx to be tested, and the second end of the cancellation capacitor Cc is electrically connected to a fifth voltage (-Vcc) that is lower than the capacitor Cx to be tested.
  • the second terminal is electrically connected to a second voltage (GND).
  • -Vcc is a negative supply voltage.
  • the control module 112 controls the second switch unit K2 and the third switch unit K3 to be in the first closed state and the second closed state Switch back and forth between M times. Because the amount of charge stored after the charging process of the capacitance to be measured and the cancellation capacitance are different, the value of the capacitance to be measured is much larger than the value of the cancellation capacitance, which can be switched from the charging state to the cancellation state by the control circuit , The cancellation capacitance performs M charge cancellation processing on the capacitance to be measured to realize the cancellation of the large capacitance to be measured.
  • a fourth switch unit K4 is provided between the charge transfer module 142 unit and the offset module 132 (a single switch is taken as an example).
  • the control module 112 further controls The fourth switch unit K4 is in a closed state so that the charge transfer module 142 is electrically connected to the capacitor Cx to be tested, so as to perform conversion processing on the charge of the capacitor Cx to be tested after the charge cancellation process to generate an output voltage V OUT .
  • the charge transfer module 142 is specifically a fully differential amplifier circuit. Further, the positive phase terminal of the fully differential amplifier circuit can be electrically connected to the fourth switch K4, and the negative phase terminal of the fully differential amplifier circuit is connected to the common mode The working voltage V CM is connected. In the fully differential amplifier circuit, a feedback resistor Rf and a feedback capacitor Cf are provided between the positive phase terminal and the output terminal, and between the negative phase terminal and the output terminal.
  • the first switch unit K1 and the fourth switch unit K4 are single-pole single-throw switches.
  • the second switch unit K2 and the third switch unit K3 are single-pole double-throw switches.
  • contact 1, contact 2, contact 3, and contact 4 are configured.
  • Contact 1 and contact 3 are located on the charging branch, and specifically may include contact 1 connected to -Vcc and contact 3 connected to Vcc.
  • FIG. 3 is a timing diagram of the embodiment of the application when the capacitance detection circuit in FIG. 2 is working; in the embodiment of the application, a detection cycle includes a period of t1-t4, and the detailed timing is as follows:
  • the first switch unit K1 is turned on (that is, K1 is in the closed state), the second switch unit K2 is connected to contact 1 (that is, in the first closed state), and the third switch unit K3 is connected to contact 3 (that is, in the closed state).
  • the fourth switch unit K4 is turned off, and the capacitor Cx to be measured and the offset capacitor Cc are charged simultaneously.
  • the voltage of the capacitor Cx to be measured is Vcc
  • the voltage of the cancellation capacitor Cc is -2Vcc
  • the output voltage V OUT of the charge transfer module is 0.
  • the first switch unit K1 and the fourth switch unit K4 are turned off, and the second switch unit K2 switches back and forth between the positions of contact 1 (that is, in the first closed state) and contact 2 (that is, in the second closed state) M times, at the same time, the third switch unit K3 switches back and forth between the positions of contact 3 (that is, in the first closed state) and contact 4 (that is, in the second closed state) for M times, each time the second switch unit K2 When switching from the first closed state to the second closed state at the same time as the third switch unit K3, the charge stored in Cx will be partially offset by the charge stored in Cc, repeating M times.
  • the first switch unit K1 is turned off, the second switch unit K2 is connected to contact 1 (that is, in the first closed state), and the third switch unit K3 is connected to contact 3 (that is, in the first closed state).
  • the four-switch unit K4 is turned on. According to the voltage Vx of the capacitor Cx to be tested, there are the following situations:
  • the capacitance Cx to be measured and the cancellation capacitance Cc simultaneously transfer charges to the charge transfer module until the voltage of the capacitance Cx to be measured reaches Vcm. During this process, the output voltage VOUT of the charge transfer module is a negative voltage.
  • the circuit reaches a perfect cancellation state.
  • the circuit can achieve a complete cancellation state when there is no touch, and the basic capacitance of the capacitance Cx to be measured can be completely cancelled.
  • the capacitance of the capacitance Cx to be measured becomes larger and the output voltage V OUT is entirely caused by touch. Therefore, the detection sensitivity is the highest in this state.
  • the charge transfer module will charge the capacitors Cx and Cc under test through the feedback network Rf and Cf until the voltages of Cx and Cc reach Vcm.
  • the output voltage Vout of the charge transfer module is a positive voltage.
  • the first switch unit K1 is turned off, the second switch unit K2 and the third switch unit K3 are in the first closed state, and the fourth switch unit K4 is turned off, the charge transfer module is reset, and the output voltage V OUT becomes zero.
  • Vcc*Cx-2M*Vcc*Cc Vx*Cx+M*(Vx+Vcc)*Cc.
  • the transferred charge amount ⁇ Q (V CC -V CM ) ⁇ C
  • f represents the detection frequency
  • its value is the reciprocal of a detection cycle formed by t1-t4.
  • the size of the basic capacitance Cx o of the capacitance to be measured Cx set the parameters of the cancellation capacitances Cc and M reasonably to better realize the charge cancellation processing of the capacitance to be measured by the cancellation capacitance, for example, according to the basic capacitance of the capacitance Cx to be measured
  • the size of Cx o when the output voltage is 0, set the parameters of the cancellation capacitances Cc and M, so that the circuit can achieve a complete cancellation state when there is no touch.
  • M can be any value such as 5, 10, 20, 50, etc., and the value of M can be set according to actual needs, and the value of M is not limited in this application.
  • Fig. 4 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application; as shown in Fig. 4, which is roughly the same as the above embodiment, it includes: a control module 112, a driving module 122, a cancellation module 132, a charge transfer module 142, and a processing module 152.
  • the difference from the foregoing embodiment is that when the second switch unit K2 and the third switch unit K3 are in the second closed state, the first end of the cancellation capacitor Cc and the first end of the capacitor Cx to be measured One end is electrically connected, and the second end of the cancellation capacitor Cc is electrically connected to a sixth voltage (GND), and the sixth voltage is equal to the second voltage (GND) electrically connected to the second end of the capacitor Cx under test. That is, the negative voltage -Vcc in the charging branch and the cancellation branch in Figure 2 is replaced with the system ground.
  • the arrangement of the first switch unit K1-the fourth switch unit K4 is the same as the embodiment shown in FIG. 2, and the switch action control is also the same.
  • FIG. 5 is a timing diagram of another embodiment of the application when the capacitance detection circuit in FIG. 4 is working; in the embodiment of the application, a detection cycle still includes the t1-t4 period, and the detailed timing is as follows:
  • the first switch unit K1 is turned on, the second switch unit K2 is connected to contact 1, the third switch unit K3 is connected to contact 3, and the fourth switch unit K4 is turned off.
  • the capacitance Cx to be measured and the cancellation capacitance Cc are simultaneously Recharge.
  • the voltage of the capacitor Cx to be measured is Vcc
  • the voltage of the cancellation capacitor Cc is -Vcc
  • the output voltage VOUT of the charge transfer module is 0.
  • the first switch unit K1 and the fourth switch unit K4 are turned off, and the second switch unit K2 and the third switch unit K3 switch back and forth M times in the first closed state and the second closed state at the same time, each time the second switch unit When K2 is switched from contact 1 to contact 2 and the third switch unit K3 is switched from contact 3 to contact 4, the charge stored in Cx will be partially offset by the charge stored in Cc. Repeat M times.
  • the first switch unit K1 is turned off, the second switch unit K2 and the third switch unit K3 are in the first closed state, and the fourth switch unit K4 is turned on. According to the magnitude of the Vx voltage, the following situations exist:
  • the capacitance Cx to be measured and the cancellation capacitance Cc simultaneously transfer charges to the charge transfer module until the voltage of the capacitance Cx to be measured reaches Vcm.
  • the output voltage V OUT of the charge transfer module is a negative voltage.
  • the circuit reaches a perfect cancellation state.
  • the circuit can achieve a complete cancellation state when there is no touch, and the basic capacitance of the capacitance Cx to be measured can be completely cancelled.
  • the capacitance of the capacitance Cx to be measured becomes larger and the output voltage V OUT is entirely caused by touch. Therefore, the detection sensitivity is the highest in this state.
  • the charge transfer module will charge the capacitors Cx and Cc under test through the feedback network Rf and Cf until the voltages of Cx and Cc reach Vcm.
  • the output voltage Vout of the charge transfer module is a positive voltage.
  • the fourth switch unit K4 is turned off, the charge transfer module is reset, and the output voltage V OUT becomes zero.
  • the parameters of the cancellation capacitances Cc and M can be set reasonably to better realize the charge cancellation processing of the capacitance to be measured by the cancellation capacitance.
  • M can be any value such as 5, 10, 20, 50, etc., and the value of M can be set according to actual needs, and the value of M is not limited in this application.
  • FIG. 6 is a schematic structural diagram of a capacitance detection circuit of Embodiment 6 of the present application; as shown in FIG. 6, it is roughly the same as the above-mentioned embodiment, and includes: a control module 112, a driving module 122, a cancellation module 132, a charge transfer module 142 and a processing module 152.
  • the cancellation module 132 includes a second switch unit (not including the third switch unit K3), and the control module 112 is further configured to control the second switch unit K2 to be in the first closed state and A charging branch is formed to enable the driving module 122 to charge the cancellation capacitor Cc.
  • the first end of the cancellation capacitor Cc is electrically connected to a seventh voltage (-V CC ) through the second switch unit K2, and the cancellation capacitor Cc
  • the second end of is electrically connected to an eighth voltage (GND), the seventh voltage is lower than the eighth voltage.
  • the control module 112 controls the second switch unit K2 to switch M times between the first closed state and the second closed state, so that the canceling capacitor Cc has a positive effect on the The capacitor Cx performs charge cancellation processing.
  • the second switch unit K2 is in the second closed state, the first end of the cancellation capacitor Cc is electrically connected to the first end of the capacitor Cx to be measured, and the second end of the cancellation capacitor Cc is electrically connected to the An eighth voltage (GND) is electrically connected, and the eighth voltage is equal to a second voltage (GND) electrically connected to the second end of the capacitor Cx under test.
  • FIG. 7 is a timing diagram of another embodiment of the application when the capacitance detection circuit in FIG. 6 is working; in the embodiment of the application, a detection cycle still includes the t1-t4 period, and the detailed timing is as follows:
  • the first switch unit K1 is turned on, the second switch unit K2 is connected to the contact 1, the fourth switch unit K4 is turned off, and the capacitor Cx to be measured and the offset capacitor Cc are charged simultaneously.
  • the voltage of the capacitor Cx to be measured is Vcc
  • the voltage of the cancellation capacitor Cc is -Vcc
  • the output voltage V OUT of the charge transfer module is 0.
  • the first switch unit K1 and the fourth switch unit K4 are turned off, and the second switch unit K2 switches back and forth between the positions of contact 1 and contact 2 M times, each time the second switch unit K2 switches from contact 1 to At contact 2, the charge stored by Cx will be partially offset by the charge stored by Cc, repeating M times.
  • the first switch unit K1 is turned off, the second switch unit K2 is connected to the contact 1 (that is, in the first closed state), and the fourth switch unit K4 is turned on.
  • the capacitance Cx to be measured and the cancellation capacitance Cc simultaneously transfer charges to the charge transfer module until the voltage of the capacitance Cx to be measured reaches Vcm.
  • the output voltage V OUT of the charge transfer module is a negative voltage.
  • the circuit reaches a perfect cancellation state.
  • the circuit can achieve a complete cancellation state when there is no touch, and the basic capacitance of the capacitance Cx to be measured can be completely cancelled.
  • the capacitance of the capacitance Cx to be measured becomes larger and the output voltage V OUT is entirely caused by touch. Therefore, the detection sensitivity is the highest in this state.
  • the charge transfer module will charge the capacitors Cx and Cc under test through the feedback network Rf and Cf until the voltages of Cx and Cc reach Vcm.
  • the output voltage Vout of the charge transfer module is a positive voltage.
  • the fourth switch unit K4 is turned off, the charge transfer module is reset, and the output V OUT becomes 0.
  • Vcc*Cx-M*Vcc*Cc Vx*Cx+M*Vx*Cc.
  • the parameters of the cancellation capacitances Cc and M can be set reasonably to better realize the charge cancellation processing of the capacitance to be measured by the cancellation capacitance. By setting the circuit parameters reasonably, the When the circuit can achieve a complete cancellation state.
  • M can be any value such as 5, 10, 20, 50, etc., and the value of M can be set according to actual needs, and the value of M is not limited in this application.
  • the cancellation efficiency of the cancellation circuit can be greatly improved, and the demand for the capacitance of the cancellation capacitor can be reduced, so as to better meet
  • the flexible screen needs to offset the need for a larger capacitance to be measured.
  • FIG. 8 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application; as shown in FIG. 8, the same as the above embodiment, it includes: a control module 112, a driving module 122, a cancellation module 132, a charge transfer module 142, and a processing module 152,
  • the difference from the foregoing embodiment is that the first terminal of the cancellation capacitor Cc is electrically connected to the ninth voltage (GND) through the second switch unit K2, and the second terminal of the cancellation capacitor Cc is electrically connected through the third switch unit K3.
  • FIG. 9 is a timing diagram of another embodiment of the application when the capacitance detection circuit in FIG. 8 is working; as shown in FIG. 9, a detection cycle still includes the t1-t4 period, and the detailed timing is as follows:
  • the first switch unit K1 is turned on (that is, in the closed state)
  • the second switch unit K2 is connected to the contact 1 (that is, in the first closed state)
  • the third switch unit K3 is connected to the contact 3 (that is, in the first closed state).
  • the fourth switch unit K4 is turned off, and the capacitance Cx to be measured is charged.
  • the voltage of the capacitor Cx to be measured is Vcc.
  • the first switch unit K1 is turned off
  • the fourth switch unit K4 is turned off
  • the second switch unit K2 and the third switch unit K3 switch back and forth M times in the first closed state and the second closed state at the same time.
  • the switch unit K2 and the third switch unit K3 switch from the first closed state to the second closed state
  • the charge stored in Cx will be partially offset by the charge stored in Cc, and repeat M times.
  • the first switch unit K1 is disconnected, the second switch unit K2 is connected to contact 1 (that is, in the first closed state), and the third switch unit K3 is connected to contact 3 (that is, in the first closed state).
  • the four-switch unit K4 is turned on (that is, in a closed state), and Cx is connected to the charge transfer module.
  • the capacitance Cx to be measured and the cancellation capacitance Cc simultaneously transfer charges to the charge transfer module until the voltage of the capacitance Cx to be measured reaches Vcm.
  • the output voltage V OUT of the charge transfer module is a negative voltage.
  • the circuit reaches a perfect cancellation state.
  • the circuit can achieve a complete cancellation state when there is no touch, and the basic capacitance of the capacitance Cx to be measured can be completely cancelled.
  • the capacitance of the capacitance Cx to be measured becomes larger and the output voltage VOUT is completely caused by touch. Therefore, the detection sensitivity is the highest in this state.
  • the charge transfer module will charge the test capacitor Cx and the offset capacitor Cc through the feedback network (composed of Rf and Cf) until the voltage of the test capacitor Cx and the offset capacitor Cc both reach Vcm.
  • the output voltage V OUT of the charge transfer module is a positive voltage.
  • this embodiment describes how to determine the capacitance of the cancellation capacitor Cc.
  • the capacitance to be measured Cx and the cancellation capacitance Cc will not release or absorb charges to the charge transfer module 142, or the cancellation capacitance Cc will offset the capacitance Cx to be measured to perfection, and the voltage Vout output by the charge transfer module 142 is 0V.
  • Vcc*Cx Vx*Cx+M*Vx*Cc.
  • the quantity ⁇ Q is only related to the capacitance change ⁇ C of the capacitance Cx to be measured, and has nothing to do with the basic capacitance Cx o of the capacitance Cx to be measured.
  • the voltage Vout output by the charge transfer module 142 directly reflects the capacitance change ⁇ C of the capacitance Cx to be measured.
  • the parameters of the cancellation capacitances Cc and M can be set reasonably to better realize the charge cancellation processing of the capacitance to be measured by the cancellation capacitance. By setting the parameters of the circuit reasonably, it can be used when there is no touch. The circuit can reach a state of complete cancellation.
  • M can be any value such as 5, 10, 20, 50, etc., and the value of M can be set according to actual needs, and the value of M is not limited in this application.
  • ⁇ C is generally relatively small, in order to reduce noise and improve sensitivity, it is necessary to repeat the previous three stages, namely t1, t1 and t3, and repeat N times.
  • the processing circuit will measure the output voltage Vout Then, the N results are summed according to the weight, and the voltage after the sum is output as a detection result. This method can be used for any embodiment of the present application.
  • FIG. 10 is a schematic diagram of the structure of a capacitance detection circuit of another embodiment of the present application;
  • FIG. 10 shows another structure of a capacitance detection circuit of the embodiment of the present application, which is the same as the foregoing embodiment, and includes: a control module 112, a drive module 122, and a cancellation
  • the difference between the module 132, the charge transfer module 142, and the processing module 152 is that the first end of the cancellation capacitor Cc is electrically connected to the ninth voltage (GND) through the second switch unit K2, and the cancellation capacitor
  • the second end of Cc is directly connected to the tenth voltage (GND).
  • the first end of the cancellation capacitor Cc is electrically connected to the first end of the capacitor Cx to be measured
  • the tenth voltage is equal to the second voltage (GND) electrically connected to the second end of the capacitor Cx under test.
  • Fig. 11 is a timing diagram of another embodiment of the application for the capacitance detection circuit in Fig. 10 when working; the same as the foregoing embodiment, a detection cycle still includes the period t1-t4, and the difference from the foregoing embodiment is that this embodiment
  • the capacitance detection circuit does not have a third switch unit, and does not need to control the third switch unit, and the circuit structure and circuit control are simpler.
  • FIG. 12 is a schematic structural diagram of a capacitance detection circuit according to another embodiment of the present application. As shown in FIG. 12, the same as the above embodiment, it includes: a control module 112, a driving module 122, a cancellation module 132, a charge transfer module 142, and a processing module 152.
  • the first end of the cancellation capacitor Cc passes through the second switch unit K2 is electrically connected to the ninth voltage (GND), the second end of the cancellation capacitor Cc is electrically connected to the tenth voltage (GND) through the third switch unit K3, and the second switch unit K2 and the third switch unit K3 are at In the second closed state, the first end of the cancellation capacitor Cc is electrically connected to the first end of the capacitor Cx to be measured, and the second end of the cancellation capacitor Cc is electrically connected to the sixth voltage (GND).
  • the sixth voltage is equal to the second voltage (GND) electrically connected to the second end of the capacitor Cx under test.
  • the charge transfer module 142 is provided with a feedback resistor Rf and a feedback capacitor Cf between the positive phase terminal and the output terminal or between the negative phase terminal and the output terminal.
  • the feedback resistor Rf and the feedback capacitor Cf are provided between the output terminals as an example for description.
  • FIG. 13 is a timing diagram of another embodiment of the application when the capacitance detection circuit in FIG. 12 is working; the control method is similar to that of the foregoing embodiment, and the embodiment of the application will not be described in detail.
  • the capacitance detection circuit structures of other embodiments of the present application can all adopt this single-ended charge transfer module, and this single-ended structure can reduce the use of a set of feedback resistors and capacitors, and the circuit is simpler.
  • the embodiments of the present application can simplify the circuit structure, improve the cancellation efficiency of the cancellation circuit, and reduce the demand for the capacitance of the cancellation capacitor. Even the capacitance of the smaller cancellation capacitor can cancel the basic capacitance of the larger capacitance to be measured. The capacity reduces the cost and significantly reduces the noise of each offset voltage source.
  • the cancellation circuit may not be able to completely cancel the basic capacitance of the capacitor under test, that is, The contribution of the base capacitance to the output voltage of the amplifier may not be absolutely zero. Therefore, here, the cancellation circuit cancels the basic capacitance, which may mean that the cancellation circuit completely cancels the basic capacitance, or approximately cancels the basic capacitance (for example, the cancelled capacitance of the basic capacitance reaches a certain threshold, etc.).
  • the application also provides a method for canceling the capacitance to be measured, which is applied to a capacitance detection circuit, as shown in FIG. 14, the method includes:
  • S1402 Control the cancellation module to perform charging processing on the cancellation capacitor and control the cancellation capacitor to perform M charge cancellation processing on the capacitor under test;
  • S1403 Control the charge transfer module to perform conversion processing on the charge of the capacitor to be measured after the charge cancellation process to generate an output voltage
  • control processing module determines the capacitance change before and after the capacitance to be measured is affected by the applied electric field.
  • the method includes: the driving module includes a first switching unit, and controlling the first switching unit to be in a closed state, so that the driving module performs charging processing on the capacitor to be measured.
  • the method includes: the cancellation module includes a second switch unit and a third switch unit, and controls the second switch unit and the third switch unit to be in a first closed state and form a charging branch to make the The cancellation module performs charging processing on the cancellation capacitor.
  • the method includes: controlling the second switch unit and the third switch unit to switch M times back and forth between the first closed state and the second closed state, so that the cancellation capacitance is effective for the under-test
  • the capacitor performs charge cancellation processing M times.
  • the method includes: the cancellation module includes a second switch unit, and the second switch unit is in a first closed state and forms a charging branch to enable the cancellation module to charge the cancellation capacitor.
  • the method includes: the cancellation module includes a second switch unit, and controls the second switch unit to switch M times between the first closed state and the second closed state, so that the cancellation capacitor has an impact on the capacitance to be measured. Perform charge cancellation processing.
  • the method includes: controlling the fourth switch unit to be in a closed state so that the charge transfer module is electrically connected to the capacitor to be measured, so as to convert the charge of the capacitor to be measured after the charge cancellation Generate output voltage.
  • the method includes: controlling the fourth switch unit to be in an off state to reset the charge transfer module.
  • the method includes: controlling the charge transfer module to detect N times to obtain N output voltages, and the processing module is configured to determine, based on the N output voltages, the capacitance before and after the capacitance to be measured is affected by the applied electric field. The amount of change.
  • An embodiment of the present application also provides an electronic device, which includes the touch chip described in any one of the embodiments of the present application.
  • the cancellation capacitor Cc is integrated in the touch chip
  • the smaller the cancellation capacitance the smaller the area and cost of the touch chip.
  • each switch unit of a single switch is taken as an example for description, in fact, it can also be implemented in a circuit combination structure, in which the constituent elements can have any on-off function.
  • the electronic components can form a charging branch and an offset branch, switch from the charging branch to the offset branch, and make the detection circuit enter the charge transfer state.
  • the electronic devices in the embodiments of this application exist in various forms, including but not limited to:
  • Mobile communication equipment This type of equipment is characterized by mobile communication functions, and its main goal is to provide voice and data communications.
  • Such terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones.
  • Ultra-mobile personal computer equipment This type of equipment belongs to the category of personal computers, has calculation and processing functions, and generally also has mobile Internet features.
  • Such terminals include: PDA, MID and UMPC devices, such as iPad.
  • Portable entertainment equipment This type of equipment can display and play multimedia content.
  • Such devices include: audio, video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.
  • Server A device that provides computing services.
  • the composition of a server includes a processor, hard disk, memory, system bus, etc.
  • the server is similar to a general computer architecture, but because it needs to provide highly reliable services, it is in terms of processing capacity and stability. , Reliability, security, scalability, and manageability.

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Abstract

一种电容检测电路、电容检测方法、触控芯片以及电子设备，所述电容检测电路包括：控制模块（112）、电荷转移模块（142）、处理模块（152）、驱动模块（122）以及抵消模块（132），所述控制模块（112）用于通过控制所述驱动模块（122）对待测电容进行充电处理；所述抵消模块（132）用于对所述待测电容进行M次电荷抵消处理；所述电荷转移模块（142）用于对所述M次电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块（152）用于根据所述输出电压确定所述待测电容的电容变化量。所述电容检测电路能够提升抵消电路的抵消效率，降低对抵消电容的电容量的需求，即使较小的抵消电容的电容量也能够抵消较大的待测电容的基础电容量，降低了成本，显著降低各个抵消电压源的噪声。

Description

一种电容检测电路、电容检测方法、触控芯片以及电子设备 技术领域
本申请涉及触控技术领域，尤其涉及一种电容检测电路、电容检测方法、触控芯片以及电子设备。
背景技术
对自电容检测来说，其原理是检测电极与系统地之间形成的电容，称之为自电容检测，当没有手指等导致出现外加电场时，检测电极与系统地之间形成的电容具有基础电容量或初始电容量。当手指靠近或触摸检测电极时，检测电极和系统地之间的电容量会变大，通过检测该电容的变化量，可以判断用户的相关触控操作。
在电容触控领域，柔性屏是一个重要的发展方向。当利用上述自电容原理实现电容触控检测时，由于柔性屏往往比传统电容触控屏更薄，导致检测电极相对于系统地距离更近(也就是所形成的电容的两个电极板之间距离更小)，因而该电容的基础电容量显著高于传统电容触控屏的该电容的基础电容量。当有手指触控时，自电容的变化量相对于基础电容量的比率明显低于传统电容触控屏，电容的变化量较小由此导致产生的电信号也很小，容易被电路噪声淹没而无法检测到。已有的自电容检测技术需要先抵消基础电容量，然后再进行自电容检测。由于柔性屏的通道基础电容很大，目前采用抵消方式需要巨大的电容，造成芯片面积巨大，再由于电容触控动辄需要几十或上百通道，使得现在基础电容量抵消方法除了成本高之外芯片尺寸严重超标，没有很大实用价值。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种电容检测电路、触控芯片以及电子设备，用以克服现有技术中上述缺陷。
本申请实施例提供了一种电容检测电路，其包括：控制模块、电荷转移模块、处理模块、驱动模块以及抵消模块，所述控制模块用于通过控制所述驱动模块对待测电容进行充电处理；所述抵消模块用于对所述待测电容进行M次电荷抵消处理；所述电荷转移模块用于对所述M次电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块用于根据所述输出电压确定所述待测电容的电容变化量。
本申请实施例提供了一种电容检测方法，应用于电容检测电路，其包括：控制驱动模块对待测电容进行充电处理；控制抵消模块对抵消电容进行充电处理以及控制所述抵消电容对所述待测电容进行M次电荷抵消处理；控制电荷转移模块对M次电荷抵消处理后的所述待测电容的电荷进行转化处理生成输出电压；以及根据所述输出电压，控制处理模块确定所述待测电容的电容变化量。
本申请实施例提供了一种触控芯片，包括：本申请任一实施例所述的电容检测电路。
本申请实施例提供了一种电子设备，其包括本申请任一实施例所述的触控芯片。
本申请实施例提供的技术方案中，由于电容检测电路包括：控制模块、电荷转移模块、处理模块、驱动模块以及抵消模块，所述控制模块用于通过控制所述驱动模块对待测电容进行充电处理、所述抵消模块用于对抵消电容进行充电处理以及对所述待测电容进行M次电荷抵消处理；所述电荷转移模块用于对所述M次电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块用于根据所述输出电压确定所述待测电容的电容变化量，当应用于自电容检测时，能够提升抵消电路的抵消效率，降低对抵消电容的电容量的需求，即使较小的抵消电容的电容量也能够抵消较大的待测电容的基础电容量，降低了成本，显著降低各个抵消电压源的噪声。
附图说明
图1是本申请实施例的电容触控系统结构示意图；
图2是本申请实施例的电容检测电路结构示意图；
图3是本申请实施例的针对图2中电容量检测电路工作时的时序图；
图4是本申请另一实施例的电容检测电路结构示意图；
图5是本申请另一实施例的针对图4中电容量检测电路工作时的时序图；
图6是本申请另一实施例的电容检测电路结构示意图；
图7是本申请另一实施例的针对图6中电容量检测电路工作时的时序图；
图8是本申请另一实施例的电容检测电路结构示意图；
图9是本申请另一实施例的针对图8中电容量检测电路工作时的时序图；
图10是本申请另一实施例的电容检测电路结构示意图；
图11是本申请另一实施例的针对图10中电容量检测电路工作时的时序图；
图12是本申请另一实施例的电容检测电路结构示意图；
图13是本申请另一实施例的针对图12中电容量检测电路工作时的时序图；
图14是本申请实施例的待测电容抵消方法的流程图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的部分实施例采用举例的方式进行详细的阐述。然而，本领域的普通技术人员可以理解，在各例子中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以 下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请实施例一电容触控系统结构示意图；如图1所示，其包含触控传感器101、触控芯片102和主机103。触控传感器101为双层结构，包括驱动通道Tx和感应通道Rx，在本实施例中，分别有5根驱动通道和5根感应通道，它们对系统地的基础电容量记为C1～C5和C6～C10。在进行自电容检测时，触控芯片102会扫描每一根通道，包括每一根驱动通道和每一根感应通道对系统地的电容量，并计算每一根通道对系统地的电容变化量。当手指靠近或触摸触控屏时，手指靠近或触摸位置的通道对系统地的电容量会变大。如图1所示，假如手指与驱动通道Tx之间的电容量为Cd，手指与感应通道Rx之间的电容量为Cs。例如，当手指靠近驱动通道Tx2和感应通道Rx3时，由于人体作为导体是与系统地相连的，驱动通道Tx2对系统地的电容量会变为C2+Cd，感应通道Rx3对系统地的电容量会变成C8+Cs。触控芯片102检测到驱动通道Tx2和感应通道Rx3对系统地的电容量都会变大，而其它通道对系统地的电容量不变或者近似不变或者较小，因此可计算出触摸位置在驱动通道Tx2和感应通道Rx3相交的位置，将该位置处的坐标发送主机103以实现各种功能的触控操作。值得注意的是，虽然本案中对通道分别命名为驱动通道和感应通道，但本领域技术人员可以理解，在自电容检测模式下，无论是驱动通道还是感应通道，单个通道既是接收触控芯片102输出的驱动信号的通道，也是用于输出感应信号的通道，这与互容模式下驱动通道只负责接收驱动信号而感应通道只负责输出感应信号是不同的。
本实施例中，电容检测电路具体配置在上述图1的触控芯片102上，因此，可理解上述触控芯片102包括下述实施例中所述的电容检测电路。
图2为本申请实施例电容检测电路结构示意图。如图2所示，电容检测电路包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152，驱动模块122、抵消模块132、电荷转移模块142具体配置在前端电路中。所述控制模块112用于通过控制所述驱动模块122对所述待测电容进行充电处理，所述抵消模块用于对所述待测电容进行M次电荷抵消处理，以使得抵消电容对 待测电容进行电荷抵消处理；所述电荷转移模块142用于对所述电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块152用于根据所述输出电压(Vout)确定所述待测电容被外加电场影响前后的电容变化量。
如图2所示，所述驱动模块122包括第一开关单元K1(以一个单一的开关实现为例)，所述控制模块112进一步用于控制第一开关单元K1处于闭合状态以使所述驱动模块122对所述待测电容Cx进行充电处理。进一步地，所述第一开关单元K1处于闭合状态时，所述待测电容Cx的第一端电连接第一电压(Vcc)，第二端电连接第二电压接地，所述第一电压高于所述第二电压。本实施例中，V CC为正的供电电压。
如图2所示，所述抵消模块132包括第二开关单元K2(以一个单一的开关实现为例)以及第三开关单元K3(以一个单一的开关实现为例)，其中，第二开关单元K2连接抵消电容Cc的一端，第三开关单元K3连接抵消电容的另一端，第二开关单元K2和第三开关单元K3可以处于不同的闭合状态，以实现对抵消模块中的抵消电容对所述待测电容进行M次电荷抵消处理。
具体地，当所述抵消模块132包括第二开关单元K2以及第三开关单元K3时，所述控制模块112控制所述第二开关单元和所述第三开关单元在所述第一闭合状态与第二闭合状态来回切换M次，以使所述抵消电容对所述待测电容进行电荷抵消。具体地，所述抵消模块对所述抵消电容进行充电处理时，所述第二开关单元K2、所述第三开关单元K3处于所述第一闭合状态时，所述抵消电容Cc的第一端通过所述第二开关单元K2电连接第三电压(-Vcc)，所述抵消电容Cc的第二端通过第三开关单元K3电连接第四电压(Vcc)，所述第四电压高于所述第三电压。可选的，第四电压的绝对值可以等于第三电压的绝对值。
具体地，所述抵消电容对所述待测电容进行电荷抵消处理时，控制模块112控制所述第二开关单元K2和所述第三开关单元K3处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx第一端电连接，所述抵消电容Cc的第二端与第五电压(-Vcc)电连接，所述第五电压低于所述待测电容Cx的第二端电连接的第二电压(GND)。本实施例中，-Vcc为负的供电电压。进一步地，所述抵消 电容对所述待测电容进行电荷抵消处理时，所述控制模块112控制所述第二开关单元K2和所述第三开关单元K3在第一闭合状态和第二闭合状态之间来回切换M次，由于待测电容和抵消电容经过充电处理之后存储的电荷量不同，待测电容的值远大于抵消电容的值，由此可以通过控制电路从充电状态切换到抵消状态时，抵消电容对待测电容进行M次电荷抵消处理以实现对大的待测电容的抵消。
如图2所示，在所述电荷转移模块142单元与所述抵消模块132之间设置有第四开关单元K4(以一个单一的开关实现为例)，对应地，所述控制模块112进一步控制第四开关单元K4处于闭合状态以使所述电荷转移模块142与所述待测电容Cx电连接，以对所述电荷抵消处理后所述待测电容Cx的电荷进行转化处理生成输出电压V OUT。
本实施例中，电荷转移模块142具体为全差分放大电路，进一步地，该全差分放大电路的正相端可与所述第四开关K4电连接，该全差分放大电路的负相端与共模工作电压V CM连接。在该全差分放大电路中，在其正相端与输出端之间、负相端与输出端之间均设置有反馈电阻Rf以及反馈电容Cf。
本实施例中，第一开关单元K1、第四开关单元K4为单刀单掷开关。第二开关单元K2、第三开关单元K3为单刀双掷开关，为更好的说明在抵消阶段中开关单元的切换，配置了触点1、触点2、触点3和触点4，其中触点1和触点3位于充电支路上，具体可以包括连接到-Vcc的触点1和连接到Vcc的触点3。
图3为本申请实施例针对图2中电容检测电路工作时的时序图；在本申请实施例中，一个检测周期包括t1-t4时段，详细时序如下：
t1时段，第一开关单元K1导通(即K1处于闭合状态)，第二开关单元K2接到触点1(即处于第一闭合状态)、第三开关单元K3接到触点3(即处于第一闭合状态)，第四开关单元K4关断，待测电容Cx和抵消电容Cc同时充电。t1时段结束时，待测电容Cx电压为Vcc，抵消电容Cc电压为-2Vcc，电荷转移模块的输出电压V OUT为0。此时，待测电容Cx存储的电荷量Q1＝Vcc*Cx，抵消电容Cc储存的电荷量Q2＝-2Vcc*Cc。
t2时段，第一开关单元K1、第四开关单元K4关断，第二开关单元K2在触点1(即处于第一闭合状态)和触点2(即处于第二闭合状态)的位置来回切换M次，与此同时，第三开关单元K3在触点 3(即处于第一闭合状态)和触点4(即处于第二闭合状态)的位置来回切换M次，每次第二开关单元K2和第三开关单元K3同时从第一闭合状态切换到第二闭合状态时，Cx存储的电荷会被Cc存储的电荷抵消一部分，重复M次，达到稳态后，由电荷守恒定律，有Vcc*Cx-2M*Vcc*Cc＝Vx*Cx+M*(Vx+Vcc)*Cc成立，可得待测电容Cx的电压Vx＝(Vcc*Cx-3M*Vcc*Cc)/(Cx+M*Cc)。
t3时段，第一开关单元K1关断，第二开关单元K2接到触点1(即处于第一闭合状态)、第三开关单元K3接到触点3(即处于第一闭合状态)，第四开关单元K4导通，根据待测电容Cx的电压Vx大小，存在以下几种情况：
若Vx>Vcm，待测电容Cx与抵消电容Cc同时向电荷转移模块转移电荷，直至待测电容Cx电压达到Vcm。在这个过程中，电荷转移模块的输出电压VOUT为负向的电压。
若Vx＝Vcm，则不存在待测电容Cx与抵消电容Cc向电荷转移模块转移电荷的过程，电荷转移模块的输出电压V OUT为0。此时电路达到完美抵消状态。通过合理设置电路的参数，使得在无触摸时电路能够达到完全抵消状态，能够将待测电容Cx的基础电容量完全抵消，则在有触摸时，待测电容Cx的电容量变大，输出电压V OUT完全是由触摸导致的。因此，这种状态下检测灵敏度最高。
若Vx<Vcm，电荷转移模块会通过反馈网络Rf和Cf对待测电容Cx和Cc充电，直至Cx和Cc电压达到Vcm。在这个过程中，电荷转移模块的输出电压Vout为正向的电压。
t4过程，第一开关单元K1断开，第二开关单元K2和第三开关单元K3处于第一闭合状态，且第四开关单元K4断开，电荷转移模块复位，输出电压V OUT变为0。
由上述可见，在t2时段结束时：Vcc*Cx-2M*Vcc*Cc＝Vx*Cx+M*(Vx+Vcc)*Cc。
由上述可见，t3时段结束时待测电容Cx和抵消电容Cc的电压一定为Vcm，则转移的电荷量为：
ΔQ＝Vx*Cx+M*(Vx+Vcc)*Cc
-(Vcm*Cx+M*(Vcm+Vcc)*Cc)
＝(Vcc-Vcm)*Cx—M*(3Vcc+Vcm)*Cc
根据t1-t4的时序过程，可得转移的电荷量为ΔQ＝(Vcc-Vcm)*(Cxo+ΔC)—M*(3Vcc+Vcm)*Cc，当完全抵消状态时，转移的电荷量ΔQ＝(V CC-V CM)·ΔC，并且可得输出电压的平均值为V OUT＝2ΔQ·f·R f，f表示检测频率，其数值为t1-t4构成的一个检测周期的倒数。
在完全抵消状态时，Vx＝Vcm，则有以下关系成立：
(Vcc-Vcm)*Cx o＝M*(3Vcc+Vcm)*Cc
可得抵消电容Cc的电容量为Cc＝Cx o*(Vcc-Vcm)/[M*(Vcm+3*Vcc)]，特别地，当V CC＝2V CM时，可得抵消电容Cc的电容量大小为Cc＝Cx o/(7*M)，所述抵消电容Cc的参数和M的值成反比例关系，所述M的值越大，所述抵消电容的电容值越小。根据待测电容Cx的基础电容量Cx o的大小，合理设置抵消电容Cc和M的参数，更好的实现抵消电容对待测电容进行的电荷抵消处理，例如，根据待测电容Cx的基础电容量Cx o的大小，在输出电压为0的情况下，设置抵消电容Cc和M的参数，使得在无触摸时电路能够达到完全抵消状态。
当M＝20的时候，此时Cc＝Cx o/140，可以大幅度降低抵消电容Cc的电容值大小，从而降低成本。在本申请实施例中，M可以为5、10、20、50等任意数值，可以根据实际需求设置M值，本申请对于M的取值不做限定。
图4本申请另一实施例的电容检测电路结构示意图；如图4所示，与上述实施例大致相同，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152，与上述实施例不同的是，所述第二开关单元K2和所述第三开关单元K3处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx的第一端电连接，所述抵消电容Cc的第二端与第六电压(GND)电连接，所述第六电压等于所述待测电容Cx的第二端电连接的第二电压(GND)。即上述图2中充电支路和抵消支路中的负电压-Vcc被替换为系统地。第一开关单元K1-第四开关单元K4的设置与上述图2所示实施例相同，开关动作控制也相同。
图5为本申请另一实施例针对图4中电容检测电路工作时的时序图；在本申请实施例中，一个检测周期仍然包括t1-t4时段，详细时序如下：
t1时段，第一开关单元K1导通，第二开关单元K2接到触点1、第三开关单元K3接到触点3，第四开关单元K4关断，待测电容Cx和抵消电容Cc同时充电。t1时段结束时，待测电容Cx电压为Vcc，抵消电容Cc电压为-Vcc，电荷转移模块的输出电压VOUT为0。此时，待测电容Cx存储的电荷量Q1＝Vcc*Cx，抵消电容Cc储存的电荷量Q2＝-Vcc*Cc。
t2时段，第一开关单元K1、第四开关单元K4关断，第二开关单元K2和第三开关单元K3同时在第一闭合状态和第二闭合状态来回切换M次，每次第二开关单元K2从触点1切换到触点2和第三开关单元K3从触点3切换到触点4时，Cx存储的电荷会被Cc存储的电荷抵消一部分，重复M次，达到稳态后，由电荷守恒定律，有Vcc*Cx-M*Vcc*Cc＝Vx*Cx+M*Vx*Cc成立，可得待测电容Cx的电压Vx＝Vcc(Cx-M*Cc)/(Cx+M*Cc)。
t3时段，第一开关单元K1关断，第二开关单元K2和第三开关单元K3处于第一闭合状态，第四开关单元K4导通，根据Vx电压大小，存在以下几种情况：
若Vx>Vcm，待测电容Cx与抵消电容Cc同时向电荷转移模块转移电荷，直至待测电容Cx电压达到Vcm。在这个过程中，电荷转移模块的输出电压V OUT为负向的电压。
若Vx＝Vcm，则不存在待测电容Cx与抵消电容Cc向电荷转移模块转移电荷的过程，电荷转移模块的输出电压V OUT为0。此时电路达到完美抵消状态。通过合理设置电路的参数，使得在无触摸时电路能够达到完全抵消状态，能够将待测电容Cx的基础电容量完全抵消，则在有触摸时，待测电容Cx的电容量变大，输出电压V OUT完全是由触摸导致的。因此，这种状态下检测灵敏度最高。
若Vx<Vcm，电荷转移模块会通过反馈网络Rf和Cf对待测电容Cx和Cc充电，直至Cx和Cc电压达到Vcm。在这个过程中，电荷转移模块的输出电压Vout为正向的电压。
t4过程，第四开关单元K4断开，电荷转移模块复位，输出电压V OUT变为0。
根据t1-t4的时序过程，可得转移的电荷量为ΔQ＝(Vcc-Vcm)(Cxo+ΔC)-M*(Vcm+Vcc)*Cc。当完全抵消状态时， 转移的电荷量ΔQ＝(V CC-V CM)·ΔC，在完全抵消状态时，Vx＝Vcm，则有以下关系成立：
(Vcc-Vcm)Cxo＝M*(Vcm+Vcc)*Cc
Cc＝Cx o*(Vcc-Vcm)/[M*(Vcm+Vcc)]，特别地，当V CC＝2V CM时，可得抵消电容Cc的电容量大小为Cc＝Cx o/(3*M)。根据待测电容Cx的基础电容量Cx o的大小，合理设置抵消电容Cc和M的参数，更好的实现抵消电容对待测电容进行的电荷抵消处理，通过合理设置电路的参数，使得在无触摸时电路能够达到完全抵消状态。
当M＝20的时候，此时Cc＝Cx o/60，可以大幅度降低抵消电容Cc的电容值大小，从而降低成本。在本申请实施例中，M可以为5、10、20、50等任意数值，可以根据实际需求设置M值，本申请对于M的取值不做限定。
图6本申请实施例六电容检测电路结构示意图；如图6所示，与上述实施例大致相同，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152。与上述实施例不同的是，所述抵消模块132包括第二开关单元(不包括第三开关单元K3)，所述控制模块112进一步用于控制所述第二开关单元K2处于第一闭合状态并形成充电支路以使所述驱动模块122对所述抵消电容Cc进行充电处理。当所述第二开关单元K2处于所述第一闭合状态时，所述抵消电容Cc的第一端通过所述第二开关单元K2电连接第七电压(-V CC)，所述抵消电容Cc的第二端电连接第八电压(GND)，所述第七电压低于所述第八电压。
进一步地，本实施例中，所述控制模块112控制所述第二开关单元K2在第一闭合状态和第二闭合状态之间来回切换M次，以使所述抵消电容Cc对所述待测电容Cx进行电荷抵消处理。当所述第二开关单元K2处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx的第一端电连接，所述抵消电容Cc的第二端与所述第八电压(GND)电连接，所述第八电压等于所述待测电容Cx的第二端电连接的第二电压(GND)。
图7为本申请另一实施例针对图6中电容检测电路工作时的时序图；在本申请实施例中，一个检测周期仍然包括t1-t4时段，详细时序如下：
t1时段，第一开关单元K1导通，第二开关单元K2接到触点1，第四开关单元K4关断，待测电容Cx和抵消电容Cc同时充电。t1时段结束时，待测电容Cx电压为Vcc，抵消电容Cc电压为-Vcc，电荷转移模块的输出电压V OUT为0。此时，待测电容Cx存储的电荷量Q1＝Vcc*Cx，抵消电容Cc储存的电荷量Q2＝-Vcc*Cc。
t2时段，第一开关单元K1、第四开关单元K4关断，第二开关单元K2在触点1和触点2的位置来回切换M次，每次第二开关单元K2从触点1切换到触点2时，Cx存储的电荷会被Cc存储的电荷抵消一部分，重复M次，达到稳态后，由电荷守恒定律，有Vcc*Cx-M*Vcc*Cc＝Vx*Cx+M*Vx*Cc成立，可得待测电容Cx的电压Vx＝Vcc*(Cx-M*Cc)/(Cx+M*Cc)。
t3时段，第一开关单元K1关断，第二开关单元K2接到触点1(即处于第一闭合状态)，第四开关单元K4导通，根据Vx电压大小，存在以下几种情况：
若Vx>Vcm，待测电容Cx与抵消电容Cc同时向电荷转移模块转移电荷，直至待测电容Cx电压达到Vcm。在这个过程中，电荷转移模块的输出电压V OUT为负向的电压。
若Vx＝Vcm，则不存在待测电容Cx与抵消电容Cc向电荷转移模块转移电荷的过程，电荷转移模块的输出电压V OUT为0。此时电路达到完美抵消状态。通过合理设置电路的参数，使得在无触摸时电路能够达到完全抵消状态，能够将待测电容Cx的基础电容量完全抵消，则在有触摸时，待测电容Cx的电容量变大，输出电压V OUT完全是由触摸导致的。因此，这种状态下检测灵敏度最高。
若Vx<Vcm，电荷转移模块会通过反馈网络Rf和Cf对待测电容Cx和Cc充电，直至Cx和Cc电压达到Vcm。在这个过程中，电荷转移模块的输出电压Vout为正向的电压。
t4过程，第四开关单元K4断开，电荷转移模块复位，输出V OUT变为0。
由上述可见，在t2时段结束时：
Vcc*Cx-M*Vcc*Cc＝Vx*Cx+M*Vx*Cc。
由上述可见，t3时段结束时待测电容Cx和抵消电容Cc的电压一定为VCM，则转移的电荷量为：
ΔQ＝Vx*Cx+M*Vx*Cc-(Vcm*Cx+M*Vcm*Cc)
＝(Vcc-Vcm)*Cx-M*(Vcc+Vcm)*Cc
根据t1-t4的时序过程，可得转移的电荷量为ΔQ＝(Vcc-Vcm)*(Cxo+ΔC)-M*(Vcc+Vcm)*Cc。当完全抵消状态时，转移的电荷量ΔQ＝(V CC-V CM)·ΔC，在完全抵消状态时，则有以下关系成立：
(Vcc-Vcm)*Cxo＝M*(Vcc+Vcm)*Cc
可得抵消电容Cc的电容量为Cc＝Cx o*(Vcc-Vcm)/[M*(Vcm+Vcc)]，特别地，当V CC＝2V CM时，可得抵消电容Cc的电容量大小为Cc＝Cx o/(3*M)，所述抵消电容Cc的值和M的值成反比例关系，所述M的值越大，所述抵消电容的电容值越小。根据待测电容Cx的基础电容量Cx o的大小，合理设置抵消电容Cc和M的参数，更好的实现抵消电容对待测电容进行的电荷抵消处理，通过合理设置电路的参数，使得在无触摸时电路能够达到完全抵消状态。
当M＝20的时候，此时Cc＝Cx o/60，可以大幅度降低抵消电容Cc的电容值大小，从而降低成本。在本申请实施例中，M可以为5、10、20、50等任意数值，可以根据实际需求设置M值，本申请对于M的取值不做限定。
本申请的电路控制时序图，通过控制开关在第一闭合状态和第二闭合状态来回切换M次，能够大幅度提升抵消电路的抵消效率，降低对抵消电容的电容量的需求，更好的满足柔性屏需抵消较大的待测电容的需求。
图8本申请另一实施例电容检测电路结构示意图；如图8所示，与上述实施例相同，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152，与上述实施例不同的是，所述抵消电容Cc的第一端通过所述第二开关单元K2电连接第九电压(GND)，所述抵消电容Cc的第二端通过第三开关单元K3电连接第十电压(GND)，所述第二开关单元K2和所述第三开关单元K3处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx的第一端电连接，所述抵消电容Cc的第二端与第六电压(GND)电连接，所述第六电压等于所述待测电容Cx的第二端电连接的第二电压(GND)。
图9为本申请另一实施例针对图8中电容检测电路工作时的时序图；如图9所示，一个检测周期仍然包括t1-t4时段，详细时序如下：
t1时段，第一开关单元K1导通(即处于闭合状态)，第二开关单元K2接到触点1(即处于第一闭合状态)，第三开关单元K3接到触点3(即处于第一闭合状态)，第四开关单元K4关断，待测电容Cx被充电。t1时段结束时，待测电容Cx电压为Vcc。
t2时段，第一开关单元K1关断，第四开关单元K4关断，第二开关单元K2和第三开关单元K3同时在第一闭合状态和第二闭合状态来回切换M次，每次第二开关单元K2和第三开关单元K3从第一闭合状态切换到第二闭合状态时，Cx存储的电荷会被Cc存储的电荷抵消一部分，重复M次，达到稳态后，由电荷守恒定律，有Vcc*Cx＝Vx*Cx+M*Vx*Cc成立，可得待测电容Cx的电压Vx＝Vcc*Cx/(Cx+M*Cc)。
t3时段，第一开关单元K1断开，第二开关单元K2接到触点1(即处于第一闭合状态)，第三开关单元K3接到触点3(即处于第一闭合状态)，第四开关单元K4导通(即处于闭合状态)，Cx与电荷转移模块连接。
若Vx>Vcm，待测电容Cx与抵消电容Cc同时向电荷转移模块转移电荷，直至待测电容Cx电压达到Vcm。在这个过程中，电荷转移模块的输出电压V OUT为负向的电压。
若Vx＝Vcm，则不存在待测电容Cx与抵消电容Cc向电荷转移模块转移电荷的过程，电荷转移模块的输出电压V OUT为0。此时电路达到完美抵消状态。通过合理设置电路的参数，使得在无触摸时电路能够达到完全抵消状态，能够将待测电容Cx的基础电容量完全抵消，则在有触摸时，待测电容Cx的电容量变大，输出电压VOUT完全是由触摸导致的。因此，这种状态下检测灵敏度最高。
若Vx<Vcm，电荷转移模块会通过反馈网络(Rf和Cf组成)对待测电容Cx和抵消电容Cc充电，直至待测电容Cx和抵消电容Cc的电压都达到Vcm。在这个过程中，电荷转移模块的输出电压V OUT为正向的电压。
t4时段，第一开关单元K1断开，第二开关单元K2和第三开关单元K3处于第一闭合状态，且第四开关单元K4断开，待测电容Cx和抵消电容Cc复位，电荷转移模块复位，输出电压V OUT变为0。
具体的，本实施例描述了如何确定抵消电容Cc的电容大小。当 没有手指触摸或靠近(即ΔC＝0)时，调整该抵消电容Cc的电容大小，使得该待测电容Cx的电压Vx＝Vcm，从而得到该抵消电容Cc的电容大小为Cc＝Cx*(Vcc-Vcm)/(M*Vcm)。这时，待测电容Cx和该抵消电容Cc不会对电荷转移模块142释放电荷或吸收电荷，或者说抵消电容Cc对待测电容Cx抵消达到完美，电荷转移模块142输出的电压Vout＝0V。
当手指触摸或靠近(即ΔC≠0)时，若Vx>Vcm，待测电容Cx和抵消电容Cc会对电荷转移模块142的反馈电阻Rf和电容Cf释放电荷直到待测电容Cx电压到达Vx＝Vcm，这时电荷转移模块142会输出一个负向电压Vout。若Vx<Vcm，电荷转移模块142会通过其反馈电阻Rf和电容Cf向待测电容Cx和抵消电容Cc释放电荷直到待测电容Cx电压到达Vx＝Vcm，这时电荷转移模块142会输出一个正向电压Vout。
由上述可见，在t2时段结束时：Vcc*Cx＝Vx*Cx+M*Vx*Cc。
由上述可见，t3时段结束时待测电容Cx和抵消电容Cc的电压一定为Vcm，则转移的电荷量为：
ΔQ＝Vx*Cx+M*Vx*Cc-(Vcm*Cx+M*Vcm*Cc)
＝Vcc*Cx-Vcm*Cx-M*Vcm*Cc
根据t1-t4的时序过程，可得转移的电荷量为ΔQ＝Vcc(Cxo+ΔC-Vcm*Cxo-M*Vcm*Cc。当完全抵消状态时，转移的电荷量ΔQ＝Vcc*ΔC，电荷量ΔQ只与待测电容Cx的电容变化量ΔC相关，而与待测电容Cx的基础电容Cx o无关，电荷转移模块142输出的电压Vout直接反应该待测电容的Cx的电容变化量ΔC，并且可得输出电压的平均值为V OUT＝2ΔQ·f·R f，f表示检测频率，其数值为t1-t4构成的一个检测周期的倒数。
在完全抵消状态时，Vx＝Vcm，则有以下关系成立：
Vcc*Cxo-Vx*Cxo-M*Vcm*Cc＝0
可得抵消电容Cc的电容量为Cc＝Cx o*(Vcc-Vcm)/(M*Vcm)，特别地，当V CC＝2V CM时，可得抵消电容Cc的电容量大小为Cc＝Cxo/M，所述抵消电容Cc的值和M的值成反比例关系，所述M的值越大，所述抵消电容的电容值越小。根据待测电容Cx的基础电容Cx o的大小，合理设置抵消电容Cc和M的参数，更好的实现抵消电容对待测 电容进行的电荷抵消处理，通过合理设置电路的参数，使得在无触摸时电路能够达到完全抵消状态。
当M＝20的时候，此时Cc＝Cx o/20，可以大幅度降低抵消电容Cc的电容值大小，从而降低成本。在本申请实施例中，M可以为5、10、20、50等任意数值，可以根据实际需求设置M值，本申请对于M的取值不做限定。
再有，由于△C一般比较小，为了降低噪声，提高灵敏度，需要重复前面三个阶段，即t1、t1和t3阶段，重复N次，每次在检测阶段，处理电路会把输出电压Vout测量下来，然后把N次结果按照权重求和，求和后电压作为一次检测结果输出。对于本申请任一实施例均可采用这种方法。
图10本申请另一实施例电容检测电路结构示意图；如图10所示本申请实施例的另外一种电容检测电路结构，与上述实施例相同，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152，与上述实施例不同的是，所述抵消电容Cc的第一端通过所述第二开关单元K2电连接第九电压(GND)，所述抵消电容Cc的第二端直接接第十电压(GND)，所述第二开关单元K2处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx的第一端电连接，所述第十电压等于所述待测电容Cx的第二端电连接的第二电压(GND)。
图11为本申请另一实施例针对图10中电容检测电路工作时的时序图；与上述实施例相同，一个检测周期仍然包括t1-t4时段，与上述实施例不同的是，本实施例的电容检测电路没有第三开关单元，无需对第三开关单元进行控制，电路结构和电路控制更加简单。
图12本申请另一实施例电容检测电路结构示意图。如图12所示，与上述实施例相同，其包括：控制模块112、驱动模块122、抵消模块132、电荷转移模块142以及处理模块152，抵消电容Cc的第一端通过所述第二开关单元K2电连接第九电压(GND)，所述抵消电容Cc的第二端通过第三开关单元K3电连接第十电压(GND)，所述第二开关单元K2和所述第三开关单元K3处于第二闭合状态时，所述抵消电容Cc的第一端与所述待测电容Cx的第一端电连接，所述抵消电容Cc的第二端与第六电压(GND)电连接，所述第六电压等于所述待测电容Cx的第二端电连接的第二电压(GND)。与上述实施 例不同的是，所述电荷转移模块142在其正相端与输出端之间或者负相端与输出端之间设置有反馈电阻Rf以及反馈电容Cf，图12以负相端与输出端之间设置有反馈电阻Rf以及反馈电容Cf为例进行说明。
图13为本申请另一实施例针对图12中电容检测电路工作时的时序图；与上述实施例控制方式类似，本申请实施例不再详细描述。
当然，本申请的其它实施例的电容检测电路结构均可采用这种单端电荷转移模块，此单端结构可以少用一组反馈电阻和电容，电路更加简单。
本申请实施例能够在简化电路结构的同时，提升抵消电路的抵消效率，降低对抵消电容的电容量的需求，即使较小的抵消电容的电容量也能够抵消较大的待测电容的基础电容量，降低了成本，显著降低各个抵消电压源的噪声。
应理解，在实际应用中，由于与驱动模块、抵消模块、待测电容器等相关的电压参数或电容参数等都可能存在一定的误差，可能不能使得抵消电路完全抵消待测电容器的基础电容，即基础电容对放大器的输出电压的贡献量可能不是绝对为零。因此，这里，该抵消电路抵消该基础电容，可以指抵消电路完全抵消该基础电容，或者近似地抵消该基础电容(例如该基础电容被抵消的电容量达到一定阈值等)。
本申请还提供一种待测电容抵消方法，应用于电容检测电路，如图14所示，该方法包括：
S1401，控制驱动模块对待测电容进行充电处理；
S1402，控制抵消模块对抵消电容进行充电处理以及控制所述抵消电容对所述待测电容进行M次电荷抵消处理；
S1403，控制电荷转移模块对电荷抵消处理后的所述待测电容的电荷进行转化处理生成输出电压；
S1404，根据所述输出电压，控制处理模块确定所述待测电容被外加电场影响前后的电容变化量。
可选的，该方法包括：所述驱动模块包括第一开关单元，控制第一开关单元处于闭合状态，以使驱动模块对待测电容进行充电处理。可选的，该方法包括：所述抵消模块包括第二开关单元以及第三开关单元，控制所述第二开关单元和所述第三开关单元处于第一闭合状态并形成充电支路以使所述抵消模块对所述抵消电容进行充电处理。
可选的，该方法包括：控制所述第二开关单元和所述第三开关单元在所述第一闭合状态与第二闭合状态来回切换M次，以使所述抵消电容对所述待测电容进行M次电荷抵消处理。
可选的，该方法包括：所述抵消模块包括第二开关单元，所述第二开关单元处于第一闭合状态并形成充电支路以使所述抵消模块对所述抵消电容进行充电处理。
可选的，该方法包括：所述抵消模块包括第二开关单元，控制第二开关单元在第一闭合状态与第二闭合状态来回切换M次，以使所述抵消电容对所述待测电容进行电荷抵消处理。
可选的，该方法包括：控制第四开关单元处于闭合状态以使所述电荷转移模块与所述待测电容电连接，以对所述电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压。
可选的，该方法包括：控制所述第四开关单元处于断开状态，以对所述电荷转移模块进行复位。
可选的，该方法包括：控制所述电荷转移模块检测N次，得到N个输出电压，所述处理模块用于根据所述N个输出电压确定所述待测电容被外加电场影响前后的电容变化量。
本申请实施例还提供一种电子设备，其包括本申请任一项实施例中所述的触控芯片。
在上述实施例中，考虑到抵消电容Cc是集成在触控芯片内，因此，抵消电容越小，触控芯片的面积以及成本也就随之越小。为此，在具体应用场景中，优选在可减小检测到的待测电容的基础电容量的前提下，选用具有最小电容量的抵消电容形成上述电容检测电路。
需要说明的是，上述实施例中，虽然以一个单一的开关各个开关单元为例进行说明，但是，实际上，也可以一电路组合结构的方式实现，其中组成的元件可以具有通断功能的任意电子元器件只要可以形成充电支路、抵消支路，且可实现从充电支路到抵消支路的切换，以及使得检测电路进入电荷转移状态即可。
另外，当基于互电容检测实现触控检测时，如果互电容的基础电容量比较大以至于可影响到互电容的变化率，则也可以应用本申请下述实施例的思想。
本申请实施例的电子设备以多种形式存在，包括但不限于:
(1)移动通信设备:这类设备的特点是具备移动通信功能，并且以 提供话音、数据通信为主要目标。这类终端包括:智能手机(例如iPhone)、多媒体手机、功能性手机，以及低端手机等。
(2)超移动个人计算机设备:这类设备属于个人计算机的范畴，有计算和处理功能，一般也具备移动上网特性。这类终端包括:PDA、MID和UMPC设备等，例如iPad。
(3)便携式娱乐设备:这类设备可以显示和播放多媒体内容。该类设备包括:音频、视频播放器(例如iPod)，掌上游戏机，电子书，以及智能玩具和便携式车载导航设备。
(4)服务器:提供计算服务的设备，服务器的构成包括处理器、硬盘、内存、系统总线等，服务器和通用的计算机架构类似，但是由于需要提供高可靠的服务，因此在处理能力、稳定性、可靠性、安全性、可扩展性、可管理性等方面要求较高。
(5)其他具有数据交互功能的电子装置。
至此，已经对本主题的特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作可以按照不同的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序，以实现期望的结果。在某些实施方式中，多任务处理和并行处理可以是有利的。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请 的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (34)

  1. 一种电容检测电路，其特征在于，包括：控制模块、电荷转移模块、处理模块、驱动模块以及抵消模块，所述控制模块用于通过控制所述驱动模块对待测电容进行充电处理；所述抵消模块用于对所述待测电容进行M次电荷抵消处理；所述电荷转移模块用于对所述M次电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压；所述处理模块用于根据所述输出电压确定所述待测电容的电容变化量。
  2. 根据权利要求1所述的电路，其特征在于，所述驱动模块包括第一开关单元，所述控制模块进一步用于控制第一开关单元处于闭合状态，以使所述驱动模块对所述待测电容进行充电处理。
  3. 根据权利要求2所述的电路，其特征在于，所述第一开关单元处于闭合状态时，所述待测电容的第一端电连接第一电压，第二端电连接第二电压，所述第一电压高于所述第二电压。
  4. 根据权利要求3所述的电路，其特征在于，所述第一电压由正电压源提供，所述第二电压为接地电压。
  5. 根据权利要求1-4中任意一项所述的电路，其特征在于，所述抵消模块包括抵消电容、第二开关单元以及第三开关单元，所述第二开关单元连接所述抵消电容的一端，所述第三开关单元连接所述抵消电容的另一端。
  6. 根据权利要求5所述的电路，其特征在于，所述抵消模块用于对所述待测电容进行M次电荷抵消处理包括：
    所述控制模块用于控制所述第二开关单元和所述第三开关单元处于第一闭合状态，以使所述抵消模块对所述抵消电容进行充电处理；
    所述控制模块用于控制所述第二开关单元和所述第三开关单元处于第二闭合状态，以使所述抵消电容对所述待测电容进行电荷抵消处理；以及
    所述控制模块用于控制所述第二开关单元和所述第三开关单元在所述第一闭合状态与所述第二闭合状态来回切换M次，以使所述抵消电容对所述待测电容进行M次电荷抵消处理。
  7. 根据权利要求6所述的电路，其特征在于，所述第二开关单元、所述第三开关单元处于所述第一闭合状态时，所述抵消电容 的第一端通过所述第二开关单元电连接第三电压，所述抵消电容的第二端通过第三开关单元电连接第四电压，所述第四电压高于所述第三电压；以及所述第二开关单元和所述第三开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与第五电压电连接，所述第五电压低于所述待测电容的第二端电连接的第二电压。
  8. 根据权利要求6所述的电路，其特征在于，所述第二开关单元、所述第三开关单元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第三电压，所述抵消电容的第二端通过第三开关单元电连接第四电压，所述第四电压高于所述第三电压；以及
    所述第二开关单元和所述第三开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与第六电压电连接，所述第六电压等于所述待测电容的第二端电连接的第二电压。
  9. 根据权利要求1-4中任意一项所述的电路，其特征在于，所述抵消模块包括第二开关单元，所述抵消模块用于对所述待测电容进行M次电荷抵消处理包括：
    所述控制模块用于控制所述第二开关单元处于第一闭合状态以使所述抵消模块对所述抵消电容进行充电处理；
    所述控制模块用于控制所述第二开关单元处于第二闭合状态以使所述抵消电容对所述待测电容进行电荷抵消处理；以及
    所述控制模块用于控制所述第二开关单元在所述第一闭合状态与第二闭合状态来回切换M次，以使所述抵消电容对所述待测电容进行M次电荷抵消处理。
  10. 根据权利要求9所述的电路，其特征在于，所述第二开关单元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第七电压，所述抵消电容的第二端电连接第八电压，所述第七电压低于所述第八电压；以及
    所述第二开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与所述第八电压电连接，所述第八电压等于所述待测电容的第二端电连接的第二电压。
  11. 根据权利要求9所述的电路，其特征在于，所述第二开关单 元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第九电压，所述抵消电容的第二端接第十电压，所述第九电压等于第十电压；以及
    所述第二开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与所述第八电压电连接，所述第八电压等于所述待测电容的第二端电连接的第二电压。
  12. 根据权利要求1-11中任意一项所述的电路，其特征在于，所述抵消电容的电容值和M的值与所述待测电容的大小相关，以使所述抵消电容对所述待测电容进行M次电荷抵消处理。
  13. 根据权利要求12所述的电路，其特征在于，所述抵消电容的电容值和M的值成反比例关系，所述M的值越大，所述抵消电容的电容值越小。
  14. 根据权利要求1-13中任一项所述的电路，其特征在于，还包括：第四开关单元，所述控制模块进一步用于控制所述第四开关单元处于闭合状态以使所述电荷转移模块与所述待测电容电连接，以对所述M次电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压。
  15. 根据权利要求14所述的电路，其特征在于，所述控制模块进一步用于控制所述第四开关单元处于断开状态，以对所述电荷转移模块进行复位。
  16. 根据权利要求1-15中任意一项所述的电路，其特征在于，所述控制模块用于控制电荷转移模块检测N次，得到N个输出电压，所述处理模块用于根据所述N个输出电压确定所述待测电容的电容变化量。
  17. 一种电容检测方法，应用于电容检测电路，其特征在于：
    控制驱动模块对待测电容进行充电处理；
    控制抵消模块对所述待测电容进行M次电荷抵消处理；
    控制电荷转移模块对M次电荷抵消处理后的所述待测电容的电荷进行转化处理生成输出电压；以及
    根据所述输出电压，控制处理模块确定所述待测电容的电容变化量。
  18. 根据权利要求17所述的方法，其特征在于，所述驱动模块包括第一开关单元，控制第一开关单元处于闭合状态，以使所述驱动模块对所述待测电容进行充电处理。
  19. 根据权利要求18所述的方法，其特征在于，所述第一开关单元处于闭合状态时，所述待测电容的第一端电连接第一电压，第二端电连接第二电压，所述第一电压高于所述第二电压。
  20. 根据权利要求19所述的方法，其特征在于，所述第一电压为正电压源，所述第二电压为接地。
  21. 根据权利要求17-20中任意一项所述的方法，其特征在于，所述抵消模块包括抵消电容、第二开关单元以及第三开关单元，所述第二开关单元连接所述抵消电容的一端，所述第三开关单元连接所述抵消电容的另一端。
  22. 根据权利要求21所述的方法，其特征在于，控制抵消模块对所述待测电容进行M次电荷抵消处理包括：
    控制所述第二开关单元和所述第三开关单元处于第一闭合状态，以使所述抵消模块对所述抵消电容进行充电处理；
    控制所述第二开关单元和所述第三开关单元处于第二闭合状态，以使所述抵消电容对所述待测电容进行电荷抵消处理；以及
    控制所述第二开关单元和所述第三开关单元在所述第一闭合状态与所述第二闭合状态来回切换M次，以使所述抵消电容对所述待测电容进行M次电荷抵消处理。
  23. 根据权利要求22所述的方法，其特征在于，所述第二开关单元、所述第三开关单元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第三电压，所述抵消电容的第二端通过第三开关单元电连接第四电压，所述第四电压高于所述第三电压；以及所述第二开关单元和所述第三开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与第五电压电连接，所述第五电压低于所述待测电容的第二端电连接的第二电压。
  24. 根据权利要求22所述的方法，其特征在于，所述第二开关单元、所述第三开关单元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第三电压，所述抵消电容的第二端通过第三开关单元电连接第四电压，所述第四电压高于所述第三电压；以及
    所述第二开关单元和所述第三开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与第六电压电连接，所述第六电压等于所述待测电容的第二端电连接的第二电压。
  25. 根据权利要求17-20中任意一项所述的方法，其特征在于，所述抵消模块包括第二开关单元，控制抵消模块对所述待测电容进行M次电荷抵消处理包括：
    所述抵消模块包括第二开关单元，
    控制所述第二开关单元处于第一闭合状态，以使所述抵消模块对所述抵消电容进行充电处理；
    控制所述第二开关单元处于第二闭合状态，以使所述抵消电容对所述待测电容进行电荷抵消处理；以及
    控制所述第二开关单元在所述第一闭合状态与所述第二闭合状态来回切换M次，以使所述抵消电容对所述待测电容进行M次电荷抵消处理。
  26. 根据权利要求25所述的方法，其特征在于，所述第二开关单元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第七电压，所述抵消电容的第二端电连接第八电压，所述第七电压低于所述第八电压；以及
    所述第二开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与所述第八电压电连接，所述第八电压等于所述待测电容的第二端电连接的第二电压。
  27. 根据权利要求25所述的方法，其特征在于，所述第二开关单元处于所述第一闭合状态时，所述抵消电容的第一端通过所述第二开关单元电连接第九电压，所述抵消电容的第二端接第十电压，所述第九电压等于第十电压；以及
    所述第二开关单元处于第二闭合状态时，所述抵消电容的第一端与所述待测电容的第一端电连接，所述抵消电容的第二端与所述第八电压电连接，所述第八电压等于所述待测电容的第二端电连接的第二电压。
  28. 根据权利要求17-27中任意一项所述的方法，其特征在于，所述抵消电容的电容值和M的值与所述待测电容的大小相关，以使所述抵消电容对所述待测电容进行M次电荷抵消处理。
  29. 根据权利要求28所述的方法，其特征在于，所述抵消电容的电容值和M的值成反比例关系，所述M的值越大，所述抵消电容的电容值越小。
  30. 根据权利要求17-29中任意一项所述的方法，其特征在于，电容检测电路包括第四开关单元，控制所述第四开关单元处于闭 合状态以使所述电荷转移模块与所述待测电容电连接，以对所述M次电荷抵消处理后所述待测电容的电荷进行转化处理生成输出电压。
  31. 根据权利要求30所述的方法，其特征在于，进一步控制所述第四开关单元处于断开状态，以对所述电荷转移模块进行复位。
  32. 根据权利要求17-31中任意一项所述的方法，其特征在于，控制电荷转移模块检测N次，得到N个输出电压，所述处理模块根据所述N个输出电压确定所述待测电容的电容变化量。
  33. 一种触控芯片，包括：权利要求1-16任一项所述的电路。
  34. 一种电子设备，其特征在于，包括权利要求33所述的触控芯片。
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US11206019B2 (en) 2021-12-21
EP3770738A1 (en) 2021-01-27
EP3770738B1 (en) 2022-02-23
CN112313611B (zh) 2024-03-19
CN112313611A (zh) 2021-02-02
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