WO2020232795A1

WO2020232795A1 - Array substrate test key and display panel

Info

Publication number: WO2020232795A1
Application number: PCT/CN2019/092907
Authority: WO
Inventors: 谭刚; 贺超
Original assignee: 武汉华星光电技术有限公司
Priority date: 2019-05-23
Filing date: 2019-06-26
Publication date: 2020-11-26
Also published as: CN110112149A

Abstract

The present invention provides an array substrate test key and a display panel. The array substrate test key sequentially comprises a glass substrate, a multi-buffer layer, a gate insulating layer, a gate layer, a source/drain electrode layer, an indium tin oxide layer, and a flat organic layer from bottom to top, and further comprises a semiconductor layer; the semiconductor layer is provided between the multi-buffer layer and the gate insulating layer and can absorb a part of static electricity which consumes electrical energy to prevent the array substrate test key from being damaged. The display panel comprises the array substrate test key.

Description

Array substrate detection key and display panel

Technical field

The invention relates to the field of display, in particular to an array substrate detection key and a display panel.

Background technique

The existing method for the electrical monitoring of the array substrate is to make the test key (Test Key) in the test element group (TEG) at the same time as the array substrate is manufactured, and the Measure the square resistance at the detection key, divide the voltage value by the resistance value to get the current value, and then detect the current value change curve of the array substrate. Through comparative analysis, the uniformity of the array substrate can be obtained, and then the array substrate can be understood quality.

Please refer to FIG. 1, which is a plan view of an existing array substrate detection key. The array substrate detection key 200 is provided with a test groove 210 in the middle of the array substrate detection key 200 that penetrates the array substrate detection key 200 from top to bottom. A probe is connected in the test slot 210 to measure the resistance value.

Please refer to FIG. 2, which is a partial structural cross-sectional view of the detection key of the array substrate shown in FIG. 1 along the AA direction. The test area 210 includes a glass substrate 211, a multi-buffer layer 212, and a gate insulation layer stacked from bottom to top. Layer 213, gate layer 214, source/drain electrode layer 215, indium tin oxide layer 216, and flat organic layer 217; the test groove 210 penetrates the flat organic layer 217 and exposes the indium tin oxide layer 216 in the test groove In 210, the probe is electrically connected to the indium tin oxide layer 216, and the indium tin oxide layer 216 is electrically connected to the source/drain electrode layer 215 and the gate layer 214, so that circuit conduction can be realized.

However, with the gradual popularity of low-temperature polysilicon (LTPS) panels, the circuit design of array substrates has become more and more refined. The array substrate needs to undergo 9 to 14 manufacturing processes. It is inevitable that slight electrostatic discharge (ESD) will occur under complex manufacturing processes. The phenomenon of explosion damage to the detection key, especially the explosion damage to the gate insulating layer 213 of the detection key of the array substrate is the most prominent, resulting in abnormal measurement values in the electrical monitoring, and the characteristics of the array substrate cannot be correctly fed back.

Summary of the invention

technical problem

The object of the present invention is to provide an array substrate detection key and a display panel, which solves the technical problem that the detection key is weak against static electricity, which causes the array substrate detection key to explode and cannot be used for monitoring, and to ensure that the array substrate detection key Normal test.

The solution to the problem

Technical solutions

In order to solve the above problems, the present invention provides an array substrate detection key, which includes a glass substrate, multiple buffer layers, a gate insulating layer, a gate layer, a source and drain electrode layer, an indium tin oxide layer, and a flat organic layer from bottom to top. Wherein, it also includes a semiconductor layer, the semiconductor layer is provided between the multi-buffer layer and the gate insulating layer, can absorb part of the static electricity on the power consumption to prevent the array substrate detection keys from being blown up; the flat organic layer A groove is opened, the groove penetrates the flat organic layer and exposes the indium tin oxide layer in the groove; the indium tin oxide layer, the source and drain electrode layer, and the gate layer are electrically conductive connection.

Further, the thickness of the semiconductor layer is less than 1,000.

Further, the material of the semiconductor layer includes polysilicon.

Further, the polysilicon is doped by implanting phosphorus ions.

Further, the polysilicon is doped by implanting boron ions.

Further, the polysilicon is doped by implanting chromium ions.

Further, the resistance value of the semiconductor layer ranges from 10 ⁸ Ω to 10 ¹² Ω.

Further, the multi-buffer layer includes a light-shielding layer, a first buffer layer, and a second buffer layer that are stacked. Specifically, the first buffer layer is located on the light shielding layer; the second buffer layer is located on the first buffer layer away from the light shielding layer.

Further, the material of the first buffer layer or the second buffer layer includes SiNx or SiOx.

The present invention also provides a display panel including the array substrate detection key.

The beneficial effect of the present invention is to provide an array substrate detection key and its display panel. The present invention increases the resistance of the array substrate detection key by adding a semiconductor layer between the multi-buffer layer and the gate insulating layer. The semiconductor layer can absorb and consume electrical energy during the manufacturing process of the array substrate, that is, the semiconductor layer acts as a resistor to reduce the potential difference. Therefore, the probability of electrostatic damage is reduced, and the risk of explosion damage to the detection key of the array substrate is reduced.

The beneficial effects of the invention

Beneficial effect

Brief description of the drawings

Description of the drawings

Fig. 1 is a plan view of a detection key of an existing array substrate;

Figure 2 is a cross-sectional view along the A-A direction in Figure 1;

3 is a plan view of an array substrate detection key in an embodiment of the present invention;

Figure 4 is a cross-sectional view along the B-B direction in Figure 3;

FIG. 5 is a schematic diagram of the structure of the multiple buffer layers in an embodiment of the present invention.

The components in the figure are identified as follows:

100. Array substrate detection key, 10. Groove,

11. Glass substrate, 12, multiple buffer layers, 13, semiconductor layer, 14, gate insulating layer,

15. Gate layer, 16, source and drain electrode layer, 17, indium tin oxide layer, 18, flat organic layer,

121, light-shielding layer, 122, first buffer layer, 123, second buffer layer.

Invention embodiment

Embodiments of the invention

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " "Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise" and other directions or The positional relationship is based on the position or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the pointed device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it cannot be understood as a limitation to the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more than two, unless specifically defined otherwise.

Please refer to FIG. 3 and FIG. 4, in an embodiment of the present invention, an array substrate detection key 100 is provided in the present invention for testing the resistance value of the array substrate. The array substrate detection key 100 includes stacks from bottom to top. The glass substrate 11, the multiple buffer layer 12, the semiconductor layer 13, the gate insulating layer 14, the gate layer 15, the source and drain electrode layer 16, the indium tin oxide layer 17, and the flat organic layer 18 are provided. Specifically, the multiple buffer layer 12 is provided on the glass substrate 11; the semiconductor layer 13 is provided on the multiple buffer layer 12; the gate insulating layer 14 is provided on the semiconductor layer 13; the gate The electrode layer 15 is provided on the gate insulating layer 14; the source and drain electrode layer 16 is provided on the gate layer 15; the indium tin oxide layer 17 is provided on the source and drain electrode layer 16; The flat organic layer 18 is provided on the indium tin oxide layer 17. The semiconductor layer 13 can absorb part of the static electricity generated in the manufacturing process of the array substrate, the semiconductor layer 13 has a relatively high resistance value, and the resistance value of the semiconductor layer 13 ranges from 10 ⁸ Ω to 10 ¹² Ω, which can resist The power consumption prevents the array substrate detection key 100 from being blown up. The semiconductor layer 13 can increase the resistance of the detection key 100 of the array substrate to prevent the influence of slight electrostatic discharge (ESD) in time, and the semiconductor layer 13 can prevent slight electrostatic discharge (ESD) during the manufacturing process of the array substrate ( ESD) performs absorption and power consumption, that is, the semiconductor layer 13 acts as a resistor to reduce the potential difference, thereby reducing the probability of electrostatic damage, thereby reducing the risk of the array substrate detection key 100 being injured.

Wherein, the flat organic layer 18 defines a groove 10 which penetrates the flat organic layer 18 and exposes the indium tin oxide layer 17 in the groove 10. The resistance value is measured by connecting a probe in the groove 10, the probe can be electrically connected to the indium tin oxide layer 17, the indium tin oxide layer 17 and the source and drain electrode layer 16 and the gate layer 15 Electrical connection. Specifically, by applying a voltage to the array substrate and measuring the square resistance at the groove of the array substrate detection key 100, the current value can be obtained by dividing the voltage value by the resistance value, and the current value change of the array substrate can be detected Curve, through comparative analysis, the uniformity of the array substrate and other characteristics can be obtained, and then the quality of the array substrate can be understood.

The present invention increases the resistance value of the detection key 100 of the array substrate by adding the semiconductor layer 13 to prevent the influence of slight electrostatic discharge (ESD) in time, and the semiconductor layer 13 can be used in the manufacturing process of the array substrate. Slight electrostatic discharge (ESD) absorbs and consumes power, that is, the semiconductor layer 13 acts as a resistor to reduce the potential difference, thereby reducing the probability of electrostatic damage, thereby reducing the risk of the array substrate detection key 100 being injured.

In this embodiment, the thickness of the semiconductor layer 13 is less than 1,000.

In this embodiment, the material of the semiconductor layer 13 is a semiconductor, the semiconductor layer 13 is made by chemical vapor deposition, and the material of the semiconductor layer 13 includes polysilicon.

Preferably, the polysilicon is doped by implanting phosphorus ions to form P-type polysilicon.

Preferably, the polysilicon is doped by implanting boron ions to form N-type polysilicon.

Preferably, the polysilicon is doped by implanting chromium ions.

Please refer to FIG. 5. In this embodiment, the multi-buffer layer 12 includes a light shielding layer 121, a first buffer layer 122 and a second buffer layer 123 that are stacked. Specifically, the first buffer layer 122 is located on the light shielding layer 121; the second buffer layer 123 is located on the first buffer layer 122 away from the light shielding layer 121.

In this embodiment, the material of the first buffer layer or the second buffer layer includes SiNx or SiOx. Preferably, the material of the first buffer layer is SiNx, and the material of the second buffer layer is SiOx.

In this embodiment, the material of the gate insulating layer 14 includes SiOx.

The present invention also provides a display panel including the array substrate detection key 100.

In use, the resistance value of the array substrate can be measured by applying a voltage U on the display panel where the array substrate detection key 100 is located, and connecting the probes to the exposed indium tin oxide layer 17 in the groove respectively R, by calculating U/R, it can be known that the current I passing through the array substrate detection key 100 is the current I passing through the display panel where the array substrate detection key 100 is located. By counting the curve of the current I change with time, and comparing it with the standard change curve, it can be known whether the current I passing through the display panel changes normally. In particular, by comparing the maximum trend value of the current I, the display can be inferred. Whether the uniformity of the array substrate portion of the panel is good, so that the life span of the display panel can be judged. In addition, the resistance value R is a square resistance, and its measurement method is in the prior art, which will not be repeated here. The thickness range of the panel can also be inferred from the resistance value R, which is also the prior art and will not be repeated here.

The beneficial effect of the present invention is to provide an array substrate detection key and a display panel thereof. By adding the semiconductor layer, the present invention can increase the resistance of the array substrate detection key and prevent slight electrostatic discharge (ESD) in time. In addition, the semiconductor layer can absorb and consume slight electrostatic discharge (ESD) during the manufacturing process of the array substrate. That is, the semiconductor layer acts as a resistor to reduce the potential difference, thereby reducing the probability of electrostatic damage, thereby reducing The array substrate detects the risk of keys being injured.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be considered This is the protection scope of the present invention.

Claims

An array substrate detection key, which includes a glass substrate, multiple buffer layers, a gate insulating layer, a gate layer, a source and drain electrode layer, an indium tin oxide layer, and a flat organic layer from bottom to top;

It also includes a semiconductor layer, which is provided between the multi-buffer layer and the gate insulating layer, and can absorb part of the static electricity to consume power to prevent the detection keys of the array substrate from being damaged;

Wherein, the flat organic layer is provided with a groove, the groove penetrates the flat organic layer and exposes the indium tin oxide layer in the groove; the indium tin oxide layer, the source and drain electrode layers and The gate layer is electrically connected.
The array substrate detection key according to claim 1, wherein the thickness of the semiconductor layer is less than 1000 angstroms.
The array substrate detection key according to claim 1, wherein the material of the semiconductor layer includes polysilicon.
4. The array substrate detection bond according to claim 3, wherein the polysilicon is doped by implanting phosphorus ions.
4. The array substrate detection bond according to claim 3, wherein the polysilicon is doped by implanting boron ions.
4. The array substrate detection bond according to claim 3, wherein the polysilicon is doped by implanting chromium ions.
The array substrate detection key according to claim 1, wherein the resistance value of the semiconductor layer ranges from 10 8 Ω to 10 12 Ω.
The array substrate detection key according to claim 1, wherein:

The multiple buffer layers include:

Shading layer

The first buffer layer is located on the light shielding layer; and

The second buffer layer is located on the first buffer layer away from the light shielding layer.
The array substrate detection key according to claim 7, wherein the material of the first buffer layer or the second buffer layer includes SiNx or SiOx.
A display panel comprising at least one array substrate detection key according to claim 1.