CN110112149A - Array substrate detects key and display panel - Google Patents
Array substrate detects key and display panel Download PDFInfo
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- CN110112149A CN110112149A CN201910432885.5A CN201910432885A CN110112149A CN 110112149 A CN110112149 A CN 110112149A CN 201910432885 A CN201910432885 A CN 201910432885A CN 110112149 A CN110112149 A CN 110112149A
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- array substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
The present invention provides a kind of array substrate detection key and its display panel.It successively includes glass substrate, more buffer layers, gate insulating layer, grid layer, source-drain electrode layer, indium tin oxide layer and flat organic layer that array substrate detects key from the bottom to top；It wherein, further include semiconductor layer, the semiconductor layer is set between more buffer layers and gate insulating layer, and can absorb partial electrostatic prevents the array substrate detection key from wound power consumption.Display panel includes above-mentioned array substrate detection key.The present invention is by increasing the semiconductor layer, the resistance value of the array substrate detection key can be increased, the influence of slight static discharge (ESD) is prevented in time, and the semiconductor layer can carry out absorption and power consumption to slight static discharge (ESD) in the processing procedure of array substrate, the i.e. described semiconductor layer reduces potential difference as resistance, to reduce the probability of damage by static electricity, to reduce the risk that the array substrate detection key be wound.
Description
Technical field
The present invention relates to display field more particularly to a kind of array substrate detection keys and display panel.
Background technique
The existing method electrically monitored for array substrate is on its periphery while to make while array substrate production
Testing element combines the detection key (Test Key) in (Test Element Group, TEG), by applying electricity to array substrate
Pressure, and square resistance is measured at detection key, current value can be obtained divided by resistance value with voltage value, can be detected array substrate
Current value change curve can obtain the characteristics such as the uniformity of array substrate by comparative analysis, and then can be appreciated that array substrate
Quality.
Refering to Figure 1, detecting the plan view of key for existing array substrate, the array substrate detection key 200 is at it
Middle part offers the test trough 210 for from top to bottom penetrating through the array substrate detection key 200, by the test trough 210
Linking probe measures resistance value.
It please refers to shown in Fig. 2, is that array substrate shown in Fig. 1 detects partial structurtes sectional view of the key along the direction A-A, the survey
Examination area 210 includes glass substrate 211, more buffer layers 212, the gate insulating layer 213, grid layer being cascading from the bottom to top
214, source-drain electrode layer 215, indium tin oxide layer 216 and flat organic layer 217；The test trough 210 is through described flat organic
Layer 217 simultaneously keeps the indium tin oxide layer 216 exposed in test trough 210, realizes that probe is electrically connected with the indium tin oxide layer 216
It connects, the indium tin oxide layer 216 is electrically connected with the source-drain electrode layer 215, the grid layer 214, so that circuit can be realized
Conducting.
But with gradually popularizing for low temperature polycrystalline silicon (LTPS) panel, the circuit design of array substrate is also increasingly finer
Change, array substrate needs to carry out 9 to 14 road processing procedures, and inevitably occurring slight static discharge (ESD) under complex process can be to inspection
The phenomenon that key be wound is surveyed, especially the gate insulating layer 213 of array substrate detection key be wound and protruded the most, caused in electrical prison
Generate that measured value is abnormal in control, cannot correct feed array substrate characteristic.
Summary of the invention
The object of the present invention is to provide a kind of array substrate detection key and display panels, solve detection key antistatic
Weak the technical issues of wound so as to cause array substrate detection key and be not used to monitoring, guarantee the array substrate detection
Key proper testing.
To solve the above-mentioned problems, a kind of array substrate detection key is provided in the present invention, from the bottom to top successively includes glass
Substrate, more buffer layers, gate insulating layer, grid layer, source-drain electrode layer, indium tin oxide layer and flat organic layer；Wherein, it also wraps
Semiconductor layer is included, the semiconductor layer is set between more buffer layers and gate insulating layer, can absorb partial electrostatic to electricity
Can consume prevents the array substrate detection key from wound；The flat organic layer offers a groove, and the groove runs through institute
It states flat organic layer and is exposed to the indium tin oxide layer in groove；The indium tin oxide layer, the source-drain electrode layer and institute
State grid layer electric connection.
Further, the thickness of the semiconductor layer is less than
Further, the material of the semiconductor layer includes polysilicon.
Further, the polysilicon is doped processing through injecting phosphonium ion.
Further, the polysilicon is doped processing through injecting boron ion.
Further, the polysilicon is doped processing through injecting chromium ion.
Further, the resistance value range of the semiconductor layer is 108Ω-1012Ω。
Further, more buffer layers include the light shield layer being stacked, first buffer layer and second buffer layer.Specifically
, the first buffer layer is located on the light shield layer；The second buffer layer is located at the first buffer layer away from the screening
On photosphere.
Further, the material of the first buffer layer or the second buffer layer includes SiNx or SiOx.
The present invention also provides a kind of display panels, including the array substrate to detect key.
The beneficial effects of the present invention are: providing a kind of array substrate detection key and its display panel, the present invention pass through in institute
It states and increases semiconductor layer between more buffer layers and gate insulating layer, increase the resistance value of the array substrate detection key, it is anti-in time
The only influence of slight static discharge (ESD), and the semiconductor layer can be in the processing procedure of array substrate to slight electrostatic
Electric discharge (ESD) carries out absorption and power consumption, i.e., the described semiconductor layer reduces potential difference as resistance, to reduce static shock
The probability of wound, to reduce the risk that the array substrate detection key be wound.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described.It should be evident that the drawings in the following description are only some examples of the present application, for
For those skilled in the art, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the plan view that existing array substrate detects key；
Fig. 2 is the sectional view in Fig. 1 along the direction A-A；
Fig. 3 is a kind of plan view of array substrate detection key in the embodiment of the present invention；
Fig. 4 is the sectional view in Fig. 3 along the direction B-B；
Fig. 5 is the structural schematic diagram of more buffer layers described in the embodiment of the present invention.
Component mark is as follows in figure:
100, array substrate detection key, 10, groove,
11, glass substrate, 12, more buffer layers, 13, semiconductor layer, 14, gate insulating layer,
15, grid layer, 16, source-drain electrode layer, 17, indium tin oxide layer, 18, flat organic layer,
121, light shield layer, 122, first buffer layer, 123, second buffer layer.
Specific embodiment
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise " is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of
The description present invention and simplified description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with spy
Fixed orientation construction and operation, therefore be not considered as limiting the invention.In addition, term " first ", " second " are only used for
Purpose is described, relative importance is not understood to indicate or imply or implicitly indicates the quantity of indicated technical characteristic.
" first " is defined as a result, the feature of " second " can explicitly or implicitly include one or more feature.?
In description of the invention, the meaning of " plurality " is two or more, unless otherwise specifically defined.
It please refers to shown in Fig. 3, Fig. 4, in one embodiment of the invention, a kind of array substrate detection key 100 is provided in the present invention
For the resistance value of hot-wire array substrate, the array substrate detection key 100 successively includes the glass being stacked from the bottom to top
Substrate 11, more buffer layers 12, semiconductor layer 13, gate insulating layer 14, grid layer 15, source-drain electrode layer 16, indium tin oxide layer 17
With flat organic layer 18.Specifically, more buffer layers 12 are set on the glass substrate 11；The semiconductor layer 13 is set to institute
It states on more buffer layers 12；The gate insulating layer 14 is set on semiconductor layer 13；The grid layer 15 is set to the gate insulator
On layer 14；The source-drain electrode layer 16 is set on the grid layer 15；The indium tin oxide layer 17 is set to the source-drain electrode layer
On 16；The flat organic layer 18 is set on the indium tin oxide layer 17.The semiconductor layer 13 can absorb array substrate and exist
The partial electrostatic generated in manufacturing process, the semiconductor layer 13 resistance value with higher, the resistance of the semiconductor layer 13
Being worth range is 108Ω-1012Ω can prevent the array substrate detection key 100 from wound to power consumption.The semiconductor layer
13 can increase the resistance value of the array substrate detection key 100, prevent the influence of slight static discharge (ESD), and institute in time
Absorption and power consumption, i.e. institute can be carried out to slight static discharge (ESD) in the processing procedure of array substrate by stating semiconductor layer 13
Semiconductor layer 13 is stated as resistance to reduce potential difference, so that the probability of damage by static electricity is reduced, to reduce the array substrate
The risk that detection key 100 be wound.
Wherein, the flat organic layer 18 offers a groove 10, and the groove is through the flat organic layer 18 and makes
The indium tin oxide layer 17 is exposed in groove 10.By in the groove 10 linking probe measure resistance value, probe can
It is electrically connected the indium tin oxide layer 17, the indium tin oxide layer 17 electrically connects with the source-drain electrode layer 16 and the grid layer 15
It connects.Specifically, by applying voltage to array substrate, and in the groove measurement side of array substrate detection key 100
Current value can be obtained divided by resistance value with voltage value in block resistance, can be detected the current value change curve of array substrate, by right
The characteristics such as uniformity of array substrate can be obtained than analyzing, and then can be appreciated that the quality of array substrate.
The present invention increases the resistance value of the array substrate detection key 100, prevents in time by increasing the semiconductor layer 13
The only influence of slight static discharge (ESD), and the semiconductor layer 13 can be in the processing procedure of array substrate to slight quiet
Discharge of electricity (ESD) carries out absorption and power consumption, i.e., the described semiconductor layer 13 reduces potential difference as resistance, to reduce quiet
The probability of electric injury, to reduce the risk that the array substrate detection key 100 be wound.
In the present embodiment, the thickness of the semiconductor layer 13 is less than
In the present embodiment, the material of the semiconductor layer 13 is semiconductor, and the semiconductor layer 13 passes through chemical gaseous phase
Depositional mode production, the material of the semiconductor layer 13 includes polysilicon.
Preferably, the polysilicon is doped processing through injecting phosphonium ion, forms p-type polysilicon.
Preferably, the polysilicon is doped processing through injecting boron ion, forms N-type polycrystalline silicon.
Preferably, the polysilicon is doped processing through injecting chromium ion.
It please refers to shown in Fig. 5, in the present embodiment, more buffer layers 12 include the light shield layer 121, first being stacked
Buffer layer 122 and second buffer layer 123.Specifically, the first buffer layer 122 is located on the light shield layer 121；Described second
Buffer layer 123 is located at the first buffer layer 122 on the light shield layer 121.
In the present embodiment, the material of the first buffer layer or the second buffer layer includes SiNx or SiOx.It is preferred that
, the material of the first buffer layer is SiNx, and the material of the second buffer layer is SiOx.
In the present embodiment, the material of the gate insulating layer 14 includes SiOx.
The present invention also provides a kind of display panels, including the array substrate to detect key 100.
When in use, can by applying a voltage U on the display panel where detecting key 100 in the array substrate,
The exposed indium tin oxide layer 17 is separately connected probe to measure the resistance value R of array substrate in the groove, passes through meter
The electric current I for detecting key 100 known to U/R by the array substrate is calculated, 100 place of key is as detected by the array substrate
The electric current I of display panel.The curve changed over time by counting the electric current I, and institute is known with standard variation curve comparison
It whether normal states the electric current I variation that display panel passes through, especially by the maximum trend value for comparing the electric current I, can push away
Know whether the uniformity of the array substrate part of the display panel is good, to can determine whether the service life of the display panel
Length.In addition, the resistance value R is square resistance, measurement method is the prior art, and this will not be repeated here.Pass through the electricity
Resistance value R can also calculate the thickness range for learning the panel, also be the prior art, this will not be repeated here.
The beneficial effects of the present invention are: providing a kind of array substrate detection key and its display panel, the present invention pass through increase
The semiconductor layer, it is possible to increase the resistance value of the array substrate detection key prevents the shadow of slight static discharge (ESD) in time
It rings, and the semiconductor layer can absorb to slight static discharge (ESD) in the processing procedure of array substrate and electric energy disappears
Consumption, i.e., the described semiconductor layer reduces potential difference as resistance, so that the probability of damage by static electricity is reduced, to reduce the array
The risk that substrate detection key be wound.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of array substrate detects key, successively include from the bottom to top glass substrate, more buffer layers, gate insulating layer, grid layer,
Source-drain electrode layer, indium tin oxide layer and flat organic layer；
It is characterized in that, further including semiconductor layer, the semiconductor layer is set between more buffer layers and gate insulating layer,
Partial electrostatic, which can be absorbed, prevents the array substrate detection key from wound power consumption；
Wherein, the flat organic layer offers a groove, and the groove is through the flat organic layer and makes the indium oxide
Tin layers are exposed in groove；The indium tin oxide layer, the source-drain electrode layer and the grid layer are electrically connected.
2. array substrate according to claim 1 detects key, which is characterized in that the thickness of the semiconductor layer is less than
3. array substrate according to claim 1 detects key, which is characterized in that the material of the semiconductor layer includes polycrystalline
Silicon.
4. array substrate according to claim 3 detects key, which is characterized in that the polysilicon is carried out through injection phosphonium ion
Doping treatment.
5. array substrate according to claim 3 detects key, which is characterized in that the polysilicon is carried out through injection boron ion
Doping treatment.
6. array substrate according to claim 3 detects key, which is characterized in that the polysilicon is carried out through injection chromium ion
Doping treatment.
7. array substrate according to claim 1 detects key, which is characterized in that the resistance value range of the semiconductor layer is
108Ω-1012Ω。
8. array substrate according to claim 1 detects key, which is characterized in that
More buffer layers include:
Light shield layer；
First buffer layer is located on the light shield layer；And
Second buffer layer is located at the first buffer layer on the light shield layer.
9. array substrate according to claim 7 detects key, which is characterized in that the first buffer layer is described second slow
The material for rushing layer includes SiNx or SiOx.
10. a kind of display panel, including the described in any item array substrates of an at least claim 1-9 detect key.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910432885.5A CN110112149A (en) | 2019-05-23 | 2019-05-23 | Array substrate detects key and display panel |
| PCT/CN2019/092907 WO2020232795A1 (en) | 2019-05-23 | 2019-06-26 | Array substrate test key and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910432885.5A CN110112149A (en) | 2019-05-23 | 2019-05-23 | Array substrate detects key and display panel |
Publications (1)
| Publication Number | Publication Date |
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| CN110112149A true CN110112149A (en) | 2019-08-09 |
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ID=67491723
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910432885.5A Pending CN110112149A (en) | 2019-05-23 | 2019-05-23 | Array substrate detects key and display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110112149A (en) |
| WO (1) | WO2020232795A1 (en) |
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Also Published As
| Publication number | Publication date |
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| WO2020232795A1 (en) | 2020-11-26 |
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