WO2020228190A1 - 像素电路及oled显示面板 - Google Patents

像素电路及oled显示面板 Download PDF

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Publication number
WO2020228190A1
WO2020228190A1 PCT/CN2019/104373 CN2019104373W WO2020228190A1 WO 2020228190 A1 WO2020228190 A1 WO 2020228190A1 CN 2019104373 W CN2019104373 W CN 2019104373W WO 2020228190 A1 WO2020228190 A1 WO 2020228190A1
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WO
WIPO (PCT)
Prior art keywords
circuit
switch
light
electrically connected
transistor
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Application number
PCT/CN2019/104373
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English (en)
French (fr)
Inventor
李艳
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2020228190A1 publication Critical patent/WO2020228190A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • This application relates to the field of display technology, and in particular to a pixel circuit and an OLED display panel.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • LCD Active Matrix Organic Light Emitting Diode
  • the development of large-size AMOLED panels usually adopts the 3T1C pixel circuit architecture shown in Figure 1.
  • Figure 2 in the data signal writing phase of a display frame, first the scan line Gate inputs high voltage, and the switching transistor T1 is turned on. , To complete the charging of the storage capacitor Cst. At this time, the light-emitting switch tube T2 is turned off.
  • the scanning line Gate inputs low voltage, the switching transistor T1 is turned off, the light-emitting switch tube T2 is turned on, and the display panel emits light.
  • the existing OLED panel has a technical problem of insufficient charging of the storage capacitor Cst, which needs to be improved.
  • the present application provides a pixel circuit and an OLED display panel to solve the technical problem of insufficient charging of the storage capacitor Cst existing in the existing OLED panel.
  • the embodiment of the present application provides a pixel circuit, which includes:
  • a light-emitting circuit for emitting light under the driving of the driving circuit
  • the first storage circuit and
  • the first storage circuit is used to charge under the control of the switch circuit during the data signal writing phase of the first display frame, and provide the driving circuit to the driving circuit during the light-emitting phase of the first display frame
  • the operating voltage is used to trigger the driving circuit to drive the light-emitting circuit to emit light
  • the second storage circuit is used for charging under the control of the switch circuit during the light-emitting stage of the first display frame, and in the second display frame
  • the operating voltage is provided to the driving circuit at time to trigger the driving circuit to drive the light-emitting circuit to emit light.
  • the driving circuit includes a driving transistor, the source of the driving transistor is electrically connected to the power supply voltage, the drain of the driving transistor is electrically connected to the light emitting circuit, and the gate of the driving transistor is electrically connected The first storage circuit and the second storage circuit are connected.
  • the light-emitting circuit includes a light-emitting switch tube and a light-emitting device.
  • the first storage circuit includes a first capacitor
  • the second storage circuit includes a second capacitor
  • the capacitance values of the first capacitor and the second capacitor are the same.
  • the first electrode of the first capacitor and the first electrode of the second capacitor are arranged in the same layer; the second electrode of the first capacitor and the second electrode of the second capacitor Same layer settings.
  • the switch circuit includes a first switch transistor, a first switch, and a first switch, and the drain of the first switch transistor is electrically connected to the first pin of the first switch ,
  • the second pin of the first switch is electrically connected to the first storage circuit, the third pin of the first switch is electrically connected to the second storage circuit, and the second storage circuit passes through the The first switch is electrically connected to the driving circuit.
  • the switch circuit includes a second switch transistor, a third switch transistor, a second switch, and a third switch, and the drain of the second switch transistor is electrically connected to the switch through the second switch.
  • the drain of the third switch transistor is electrically connected to the second storage circuit
  • the second storage circuit is electrically connected to the drain of the second switch transistor through the third switch.
  • the switch circuit includes a fourth switch transistor, a fifth switch transistor, and a second switch.
  • the drain of the fourth switch transistor is electrically connected to the first storage circuit
  • the fifth switch transistor The drain of the switching transistor is electrically connected to the first pin of the second switch
  • the second pin of the second switch is electrically connected to the second storage circuit
  • the third pin of the second switch The driving circuit is electrically connected.
  • This application also proposes an OLED display panel, which includes a pixel array, the pixel array includes at least one pixel circuit, and the pixel circuit includes:
  • a light-emitting circuit for emitting light under the driving of the driving circuit
  • the first storage circuit and
  • the first storage circuit is used to charge under the control of the switch circuit during the data signal writing phase of the first display frame, and provide the driving circuit to the driving circuit during the light-emitting phase of the first display frame
  • the operating voltage is used to trigger the driving circuit to drive the light-emitting circuit to emit light
  • the second storage circuit is used for charging under the control of the switch circuit during the light-emitting stage of the first display frame, and in the second display frame
  • the operating voltage is provided to the driving circuit at time to trigger the driving circuit to drive the light-emitting circuit to emit light.
  • the driving circuit includes a driving transistor, the source of the driving transistor is electrically connected to the power supply voltage, the drain of the driving transistor is electrically connected to the light emitting circuit, and the gate of the driving transistor
  • the first storage circuit and the second storage circuit are electrically connected.
  • the light-emitting circuit includes a light-emitting switch tube and a light-emitting device.
  • the first storage circuit includes a first capacitor
  • the second storage circuit includes a second capacitor
  • the capacitance values of the first capacitor and the second capacitor are the same.
  • the first electrode of the first capacitor and the first electrode of the second capacitor are arranged in the same layer; the second electrode of the first capacitor and the second electrode of the second capacitor The electrodes are arranged on the same layer.
  • the switch circuit includes a first switch transistor, a first switch, and a first switch, and the drain of the first switch transistor is electrically connected to the first lead of the first switch.
  • the second pin of the first switch is electrically connected to the first storage circuit
  • the third pin of the first switch is electrically connected to the second storage circuit
  • the second storage circuit passes through all
  • the first switch is electrically connected to the driving circuit.
  • the switch circuit includes a second switch transistor, a third switch transistor, a second switch, and a third switch, and the drain of the second switch transistor is electrically connected through the second switch
  • the drain of the third switching transistor is electrically connected to the second storage circuit
  • the second storage circuit is electrically connected to the drain of the second switching transistor through the third switch.
  • the switch circuit includes a fourth switch transistor, a fifth switch transistor, and a second switch.
  • the drain of the fourth switch transistor is electrically connected to the first storage circuit.
  • the drain of the five-switch transistor is electrically connected to the first pin of the second switch, the second pin of the second switch is electrically connected to the second storage circuit, and the third lead of the second switch is The pin is electrically connected to the driving circuit.
  • At least two storage circuits are provided, one storage circuit is charged during the light-emitting stage of the first display frame, and then the operating voltage is provided to the driving circuit in the second display frame to trigger the driving circuit to drive all the storage circuits.
  • the light-emitting circuit emits light, which realizes that the storage circuit is charged and the panel emits light simultaneously. Based on this, the charging time can be greatly increased, and the technical problem of insufficient charging of the storage capacitor Cst existing in the existing OLED panel is solved.
  • Fig. 1 is a circuit diagram of a conventional pixel circuit
  • Fig. 2 is a working timing diagram of a conventional pixel circuit
  • FIG. 3 is a schematic diagram of a first circuit of a pixel circuit provided by an embodiment of the application.
  • FIG. 4 is a working timing diagram of the pixel circuit shown in FIG. 3;
  • FIG. 5 is a schematic diagram of a second circuit of a pixel circuit provided by an embodiment of the application.
  • FIG. 6 is a working timing diagram of the pixel circuit shown in FIG. 5;
  • FIG. 7 is a schematic diagram of a third circuit of a pixel circuit provided by an embodiment of the application.
  • FIG. 8 is a working timing diagram of the pixel circuit shown in FIG. 7.
  • the scan line Gate first inputs a high voltage, and the switching transistor T1 is turned on to When the storage capacitor Cst is charged, the light-emitting switch tube T2 is turned off.
  • the scanning line Gate inputs low voltage, the switching transistor T1 is turned off, the light-emitting switch tube T2 is turned on, and the display panel emits light.
  • the charging time of the storage capacitor Cst is compressed shorter and shorter, which leads to the problem of insufficient charging of the storage capacitor Cst in the display screen.
  • this application provides a pixel circuit to solve this problem.
  • the pixel circuit provided by the present application includes:
  • the light-emitting circuit 32 is configured to emit light under the driving of the driving circuit
  • the first storage circuit 34 The first storage circuit 34;
  • the first storage circuit 34 is used for charging under the control of the switch circuit during the data signal writing phase of the first display frame, and charging the driving circuit during the light-emitting phase of the first display frame Provides a working voltage to trigger the driving circuit to drive the light-emitting circuit to emit light;
  • the second storage circuit 35 is used for charging under the control of the switch circuit during the light-emitting phase of the first display frame, and in the second When a frame is displayed, an operating voltage is provided to the driving circuit to trigger the driving circuit to drive the light emitting circuit to emit light.
  • This embodiment provides a pixel circuit, which includes: a drive circuit, a light-emitting circuit, a switch circuit, a first storage circuit, and a second storage circuit; wherein, the first storage circuit is used to control the switch circuit Next, charging is performed during the data signal writing phase of the first display frame, and an operating voltage is provided to the driving circuit during the light-emitting phase of the first display frame to trigger the driving circuit to drive the light-emitting circuit to emit light;
  • the second storage circuit is used to charge under the control of the switch circuit during the light-emitting phase of the first display frame, and provide a working voltage to the driving circuit in the second display frame to trigger the driving circuit to drive The light emitting circuit emits light.
  • At least two storage circuits are provided, one storage circuit is charged during the light-emitting stage of the first display frame, and then the operating voltage is provided to the driving circuit in the second display frame to trigger the driving circuit to drive all the storage circuits.
  • the light-emitting circuit emits light, which realizes that the storage circuit is charged and the panel emits light simultaneously. Based on this, the charging time can be greatly increased, and the technical problem of insufficient charging of the storage capacitor Cst existing in the existing OLED panel is solved.
  • the driving circuit 31 includes a driving transistor G, the source of the driving transistor G is electrically connected to the power supply voltage PW, and the driving transistor G The drain of is electrically connected to the light emitting circuit, and the gate of the driving transistor G is electrically connected to the first storage circuit 34 and the second storage circuit 35.
  • the light-emitting circuit 32 includes a light-emitting switch tube EM and a light-emitting device EL.
  • the light-emitting switch tube EM is turned on or off under the control of the control signal EM, thereby controlling the light-emitting device EL to emit light.
  • the light-emitting switch tube EM is arranged on the driving transistor G and the light-emitting device EL, and the other end of the light-emitting device EL is grounded to GND.
  • the light emitting switch tube EM is arranged between the light emitting device EL and the ground GND.
  • the first storage circuit 34 includes a first capacitor C1
  • the second storage circuit 35 includes a second capacitor C1.
  • the first storage circuit 34 includes a first inductor
  • the second storage circuit 35 includes a second inductor
  • the capacitance values of the first capacitor and the second capacitor are the same. This facilitates the use of the same mask to prepare capacitors and facilitates the calculation of subsequent algorithms.
  • the first electrode of the first capacitor and the first electrode of the second capacitor are arranged in the same layer; the second electrode of the first capacitor and the The second electrode of the second capacitor is arranged in the same layer.
  • the switch circuit 33 includes a first switch transistor ST1, a first switch SW1, and a first switch K1.
  • the source of the transistor ST1 is electrically connected to the source driver, and the storage capacitor is charged according to the voltage of Vdata1, the gate of the first switching transistor ST1 is electrically connected to the gate drive circuit, and the on and off control is realized according to the Gate1 signal.
  • the drain of the first switching transistor ST1 is electrically connected to the first pin SW1-1 of the first switch SW1, and the second pin SW1-2 of the first switch SW1 is electrically connected to the first storage circuit.
  • a capacitor C1 the third pin SW1-3 of the first switch SW1 is electrically connected to the capacitor C2 of the second storage circuit, and the second storage circuit C2 is electrically connected to the driving circuit through the first switch K1
  • the gate of the driving transistor G; the first switch SW1 works under the control of the signal SW1.
  • One display frame includes an initial stage t1, a data signal writing stage t2, a light-emitting stage t3, and a switching stage t4.
  • the working principle of the pixel circuit shown in FIG. 3 is:
  • the first switch transistor ST1 In t1 of the first display frame, the first switch transistor ST1, the light-emitting switch tube EM, and the switch K1 are all turned off, and the first pin SW1-1 and the second pin SW1-2 of the first switch SW1 are connected ;
  • Gate1 is at a high potential, the first switch transistor ST1 is turned on, the light-emitting switch tube EM and the switch K1 are both turned off, and the capacitor C1 is charged.
  • the charging voltage is the gray-scale voltage corresponding to the first display frame ;
  • the first pin SW1-1 and the third pin SW1-3 of the first switch SW1 are connected, Gate1 maintains a high potential, and the first switch transistor ST1 is turned on, which is a capacitor C2.
  • the charging time is t5 (it can be equal to t3, or less than t3), and the charging voltage is the gray-scale voltage corresponding to the second display frame.
  • Switch K1 is off Open;
  • Capacitor C1 provides working voltage for the gate of driving transistor G, EM is high potential, light-emitting switch tube EM is turned on, and light-emitting device EL emits light;
  • the first switch transistor ST1 the light-emitting switch tube EM, and the switch K1 are all turned off, and the first pin SW1-1 and the second pin SW1-2 of the first switch SW1 are connected ,
  • the light-emitting device EL stops emitting light;
  • the first switch transistor ST1 is turned off, the light-emitting switch tube EM and the switch K1 are both turned on, and the first pin SW1-1 and the second pin SW1- of the first switch SW1 2 is connected;
  • the capacitor C2 provides the working voltage for the gate of the driving transistor G, EM is a high potential, the light-emitting switch tube EM is turned on, and the light-emitting device EL emits light;
  • the subsequent cycle from t2 to t4 in the second display frame is the same as t2 to t4 in the first display frame, and charging and display can be cycled in parallel, which will not be repeated.
  • the switch circuit 33 includes a second switch transistor ST2, a third switch transistor ST3, a second switch K2, and a third switch K3,
  • the source of the second switching transistor ST2 is electrically connected to the source driver, and the storage capacitor is charged according to the Vdata2 voltage
  • the gate of the second switching transistor ST2 is electrically connected to the gate driving circuit, and is turned on and off according to the Gate2 signal
  • the drain of the second switch transistor ST2 is electrically connected to the capacitor C1 of the first storage circuit through the second switch K2, and the source of the third switch transistor ST3 is electrically connected to the source driver.
  • the voltage charges the storage capacitor, the gate of the third switching transistor ST3 is electrically connected to the gate drive circuit, and the on and off control is realized according to the Gate3 signal, and the drain of the third switching transistor ST3 is electrically connected to the first The capacitor C2 of the second storage circuit, and the capacitor C2 of the second storage circuit is electrically connected to the drain of the second switch transistor ST2 through the third switch K3.
  • the working principle of the pixel circuit shown in FIG. 5 is:
  • the second switch transistor ST2, the third switch transistor ST3, the switch K2, the switch K3, and the light-emitting switch tube EM are all turned off;
  • Gate2 is at a high potential, the second switching transistor ST2 is turned on, the light-emitting switch tube EM is turned off, and the capacitor C1 is charged, and the charging voltage is the gray-scale voltage corresponding to the first display frame;
  • t3 of the first display frame Gate3 is at a high potential, and the third switching transistor ST3 is turned on to charge the capacitor C2 until the capacity of the capacitor C2 is the sum of the capacitor C1 and the capacitor C2 to reach the potential.
  • the charging time is t5 ( It can be equal to t3 or less than t3), the charging voltage is the gray-scale voltage corresponding to the second display frame; Gate2 becomes a low potential, the second switching transistor ST2 is turned off, and the capacitor C1 provides the operating voltage for the gate of the driving transistor G, EM At high potential, the light-emitting switch tube EM is turned on, and the light-emitting device EL emits light;
  • the second switching transistor ST2, the third switching transistor ST3, the switch K2, the switch K3, and the light-emitting switch tube EM are all turned off, and the light-emitting device EL stops emitting light;
  • the second switching transistor ST2 and the third switching transistor ST3 are kept off, the switch K2 is closed, the switch K3 is closed, the light-emitting switch tube EM is turned on, and the capacitor C2 is the gate of the driving transistor G Provide working voltage, EM is high potential, the light-emitting switch tube EM is turned on, and the light-emitting device EL emits light;
  • the subsequent cycle from t2 to t4 in the second display frame is the same as t2 to t4 in the first display frame, and charging and display can be cycled in parallel, which will not be repeated.
  • the capacitor C1 and the capacitor C2 are both charged synchronously, that is, in the first display frame t2, Gate2 is at a high potential, the second switch transistor ST2 is turned on, and the light-emitting switch tube EM is turned off, which is the capacitor C1.
  • the charging voltage is the gray-scale voltage corresponding to the first display frame;
  • Gate3 is at a high potential, and the third switching transistor ST3 is turned on to charge the capacitor C2 until the power of the capacitor C2 is the sum of the capacitor C1 and the capacitor C2 to reach the potential.
  • the charging time is t5 (may be equal to t3, or less than t3), and the charging voltage is the gray-scale voltage corresponding to the second display frame. After the capacitor C2 is charged, Gate3 becomes low and the third switch transistor ST3 is turned off.
  • the switch circuit 33 includes a fourth switch transistor ST4, a fifth switch transistor ST5, a second switch SW2, and the fourth switch
  • the source of the transistor ST4 is electrically connected to the source driver, and the storage capacitor is charged according to the voltage of Vdata4.
  • the gate of the fourth switching transistor ST4 is electrically connected to the gate drive circuit, and the control of on and off is realized according to the Gate4 signal.
  • the drain of the fourth switching transistor ST4 is electrically connected to the capacitor C1 of the first storage circuit, the source of the fifth switching transistor ST5 is electrically connected to the source driver, and the storage capacitor is charged according to the voltage of Vdata5.
  • the fifth switching transistor The gate of ST5 is electrically connected to the gate drive circuit, and the on and off control is realized according to the Gate5 signal.
  • the drain of the fifth switch transistor ST5 is electrically connected to the first pin SW2-1 of the second switch SW2 ,
  • the second pin SW2-2 of the second switch SW2 is electrically connected to the capacitor C2 of the second storage circuit, and the third pin SW2-3 of the second switch SW2 is electrically connected to the drive circuit
  • the gate of the driving transistor G; the second switch SW2 works under the control of the signal SW2.
  • the working principle of the pixel circuit shown in FIG. 7 is:
  • the fourth switch transistor ST4, the fifth switch transistor ST5, and the light-emitting switch EM are all turned off, and the first pin SW2-1 and the second pin SW2 of the second switch SW2 -2 connected;
  • Gate4 is at a high potential, the fourth switch transistor ST4 is turned on, the light-emitting switch tube EM is turned off, and the capacitor C1 is charged, and the charging voltage is the gray-scale voltage corresponding to the first display frame;
  • Gate5 is at a high potential, and the fifth switching transistor ST5 is turned on to charge the capacitor C2 until the power of the capacitor C2 is the sum of the capacitor C1 and the capacitor C2 to reach the potential.
  • the charging time is t5 ( Can be equal to t3 or less than t3), the charging voltage is the gray-scale voltage corresponding to the second display frame;
  • Gate4 becomes a low potential, the fourth switching transistor ST4 is turned off, and the capacitor C1 provides the operating voltage for the gate of the driving transistor G, EM
  • the light-emitting switch tube EM is turned on, and the light-emitting device EL emits light;
  • the fourth switch transistor ST4, the fifth switch transistor ST5, and the light-emitting switch EM are all turned off, and the first pin SW2-1 and the second pin SW2 of the second switch SW2 -2 is connected, the light emitting device EL stops emitting light;
  • the fourth switch transistor ST4 and the fifth switch transistor ST5 are turned off, the third pin SW2-3 and the second pin SW2-2 of the second switch SW2 are connected, and the light-emitting switch
  • the tube EM is turned on, the capacitor C2 provides a working voltage for the gate of the driving transistor G, EM is a high potential, the light-emitting switch tube EM is turned on, and the light-emitting device EL emits light;
  • the subsequent cycle from t2 to t4 in the second display frame is the same as t2 to t4 in the first display frame, and charging and display can be cycled in parallel, which will not be repeated.
  • the capacitor C1 and the capacitor C2 are both charged synchronously, that is, in the first display frame t2, Gate4 is at a high potential, the fourth switch transistor ST4 is turned on, and the light-emitting switch tube EM is turned off, which is the capacitor C1.
  • the charging voltage is the gray-scale voltage corresponding to the first display frame;
  • Gate5 is at a high potential, and the fifth switching transistor ST5 is turned on to charge the capacitor C2 until the power of the capacitor C2 is the sum of the capacitor C1 and the capacitor C2 to reach the potential.
  • the charging time is t5 (may be equal to t3, or less than t3)
  • the charging voltage is the gray-scale voltage corresponding to the second display frame
  • Gate5 becomes a low potential
  • the fifth switch transistor ST5 is turned off.
  • the present application also provides an OLED display panel, which includes a pixel array, and the pixel array includes at least one pixel circuit provided in the present application.
  • the pixel circuit includes:
  • the pixel circuit includes:
  • the light-emitting circuit 32 is configured to emit light under the driving of the driving circuit
  • the first storage circuit 34 The first storage circuit 34;
  • the first storage circuit 34 is used for charging under the control of the switch circuit during the data signal writing phase of the first display frame, and charging the driving circuit during the light-emitting phase of the first display frame Provides a working voltage to trigger the driving circuit to drive the light-emitting circuit to emit light;
  • the second storage circuit 35 is used for charging under the control of the switch circuit during the light-emitting phase of the first display frame, and in the second When a frame is displayed, an operating voltage is provided to the driving circuit to trigger the driving circuit to drive the light emitting circuit to emit light.
  • This embodiment provides an OLED display panel, the pixel circuit of which includes: a driving circuit, a light-emitting circuit, a switch circuit, a first storage circuit, and a second storage circuit; wherein, the first storage circuit is used to switch Under the control of the circuit, charging is performed during the data signal writing phase of the first display frame, and an operating voltage is provided to the driving circuit during the light-emitting phase of the first display frame to trigger the driving circuit to drive the light-emitting circuit Light;
  • the second storage circuit is used to charge during the light-emitting stage of the first display frame under the control of the switch circuit, and to provide an operating voltage to the driving circuit in the second display frame to trigger the
  • the driving circuit drives the light-emitting circuit to emit light.
  • At least two storage circuits are provided, one storage circuit is charged during the light-emitting stage of the first display frame, and then the operating voltage is provided to the driving circuit in the second display frame to trigger the driving circuit to drive all the storage circuits.
  • the light-emitting circuit emits light, which realizes that the storage circuit is charged and the panel emits light simultaneously. Based on this, the charging time can be greatly increased, and the technical problem of insufficient charging of the storage capacitor Cst existing in the existing OLED panel is solved.
  • the driving circuit 31 includes a driving transistor G, the source of the driving transistor G is electrically connected to the power supply voltage PW, and the drain of the driving transistor G is electrically connected to In the light emitting circuit, the gate of the driving transistor G is electrically connected to the first storage circuit 34 and the second storage circuit 35.
  • the light-emitting circuit 32 includes a light-emitting switch tube EM and a light-emitting device EL.
  • the light-emitting switch tube EM is turned on or off under the control of the control signal EM, thereby controlling the light-emitting device EL to emit light.
  • the light-emitting switch tube EM is disposed on the driving transistor G and the light-emitting device EL, and the other end of the light-emitting device EL is grounded to GND.
  • the light emitting switch tube EM is arranged between the light emitting device EL and the ground GND.
  • the first storage circuit 34 includes a first capacitor C1
  • the second storage circuit 35 includes a second capacitor C1.
  • the first storage circuit 34 includes a first inductor
  • the second storage circuit 35 includes a second inductor
  • the capacitance values of the first capacitor and the second capacitor are the same. This facilitates the use of the same mask to prepare capacitors and facilitates the calculation of subsequent algorithms.
  • the first electrode of the first capacitor and the first electrode of the second capacitor are arranged in the same layer; the second electrode of the first capacitor is The second electrodes of the second capacitor are arranged in the same layer.
  • the switch circuit 33 includes a first switch transistor ST1, a first switch SW1, and a first switch K1.
  • the source of the first switch transistor ST1 The source driver is electrically connected, and the storage capacitor is charged according to the Vdata1 voltage.
  • the gate of the first switching transistor ST1 is electrically connected to the gate driving circuit, and the turn-on and turn-off control is implemented according to the Gate1 signal.
  • the first switching transistor ST1 The drain of the first switch SW1 is electrically connected to the first pin SW1-1, the second pin SW1-2 of the first switch SW1 is electrically connected to the capacitor C1 of the first storage circuit, the The third pin SW1-3 of the first switch SW1 is electrically connected to the capacitor C2 of the second storage circuit, and the second storage circuit C2 is electrically connected to the driving transistor G of the driving circuit through the first switch K1. Grid; the first switch SW1 works under the control of the signal SW1.
  • the switch circuit 33 includes a second switch transistor ST2, a third switch transistor ST3, a second switch K2, and a third switch K3.
  • the source of the transistor ST2 is electrically connected to the source driver, and the storage capacitor is charged according to the voltage of Vdata2, the gate of the second switching transistor ST2 is electrically connected to the gate drive circuit, and the on and off control is realized according to the Gate2 signal.
  • the drain of the second switching transistor ST2 is electrically connected to the capacitor C1 of the first storage circuit through the second switch K2, the source of the third switching transistor ST3 is electrically connected to the source driver, and the storage capacitor is charged according to the voltage of Vdata3 ,
  • the gate of the third switching transistor ST3 is electrically connected to the gate driving circuit, and the on and off control is realized according to the Gate3 signal, and the drain of the third switching transistor ST3 is electrically connected to the capacitor of the second storage circuit C2, the capacitor C2 of the second storage circuit is electrically connected to the drain of the second switch transistor ST2 through the third switch K3.
  • the switch circuit 33 includes a fourth switch transistor ST4, a fifth switch transistor ST5, and a second switch SW2.
  • the source of the fourth switch transistor ST4 The source driver is electrically connected, and the storage capacitor is charged according to the Vdata4 voltage.
  • the gate of the fourth switch transistor ST4 is electrically connected to the gate drive circuit, and the turn-on and turn-off control is implemented according to the Gate4 signal.
  • the fourth switch transistor ST4 The drain of the fifth switch transistor ST5 is electrically connected to the capacitor C1 of the first storage circuit, the source of the fifth switch transistor ST5 is electrically connected to the source driver, and the storage capacitor is charged according to the voltage of Vdata5.
  • the gate of the fifth switch transistor ST5 is electrically connected The gate drive circuit is connected to realize the on and off control according to the Gate5 signal.
  • the drain of the fifth switch transistor ST5 is electrically connected to the first pin SW2-1 of the second switch SW2, and the second The second pin SW2-2 of the switch SW2 is electrically connected to the capacitor C2 of the second storage circuit, and the third pin SW2-3 of the second switch SW2 is electrically connected to the gate of the driving transistor G of the driving circuit. Pole;
  • the second switch SW2 works under the control of the signal SW2.
  • the present application provides a pixel circuit and an OLED display panel.
  • the pixel circuit includes a driving circuit, a light emitting circuit, a switch circuit, a first storage circuit, and a second storage circuit; wherein, the first storage circuit is used for Under the control of the switch circuit, charging is performed during the data signal writing phase of the first display frame, and an operating voltage is provided to the driving circuit during the light-emitting phase of the first display frame to trigger the driving circuit to drive the light-emitting
  • the circuit emits light;
  • the second storage circuit is used to charge during the light-emitting phase of the first display frame under the control of the switch circuit, and to provide an operating voltage to the driving circuit during the second display frame to trigger the
  • the driving circuit drives the light emitting circuit to emit light.
  • At least two storage circuits are provided, one storage circuit is charged during the light-emitting stage of the first display frame, and then the operating voltage is provided to the driving circuit in the second display frame to trigger the driving circuit to drive all the storage circuits.
  • the light-emitting circuit emits light, which realizes that the storage circuit is charged and the panel emits light at the same time. Based on this, the charging time can be greatly increased, and the technical problem of insufficient charging of the storage capacitor Cst existing in the existing OLED panel is solved.

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Abstract

一种像素电路及OLED显示面板，其像素电路包括：驱动电路（31），发光电路（32），开关电路（33），第一存储电路（34），以及第二存储电路（35）；其中，第二存储电路（35）用于在开关电路（33）的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向驱动电路（31）提供工作电压，以触发驱动电路（31）驱动发光电路（32）发光。

Description

像素电路及OLED显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素电路及OLED显示面板。
 背景技术
现有AMOLED（Active Matrix Organic Light Emitting Diode，有源矩阵有机发光二极管）显示面板由于相较于液晶显示面板更加轻薄，具有广泛的应用。
目前大尺寸AMOLED面板的开发通常采用如图1所示的3T1C像素电路架构，如图2所示，在一个显示帧的数据信号写入阶段内，首先扫描线路Gate输入高压，开关晶体管T1导通，以完成存储电容Cst的充电，此时发光开关管T2断开，在一个显示帧的发光阶段内，扫描线路Gate输入低压，开关晶体管T1断开，发光开关管T2导通，显示面板发光。
但是，随着分辨率和帧频不断提升的情况下，存储电容Cst的充电时间被压缩的越来越短，导致显示屏出现存储电容Cst充电不足的问题。
即现有OLED面板存在存储电容Cst充电不足的技术问题，有待改进。
 技术问题
本申请提供一种像素电路及OLED显示面板，以解决现有OLED面板存在的存储电容Cst充电不足的技术问题。
 技术解决方案
本申请实施例提供一种像素电路，其包括：
驱动电路；
发光电路，用于在所述驱动电路的驱动下发光；
开关电路；
第一存储电路；以及
第二存储电路；
其中，所述第一存储电路用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。
在本申请的像素电路中，所述驱动电路包括驱动晶体管，所述驱动晶体管的源极电连接电源电压，所述驱动晶体管的漏极电连接所述发光电路，所述驱动晶体管的栅极电连接所述第一存储电路和所述第二存储电路。
在本申请的像素电路中，所述发光电路包括发光开关管以及发光器件。
在本申请的像素电路中，所述第一存储电路包括第一电容，所述第二存储电路包括第二电容。
在本申请的像素电路中，所述第一电容和所述第二电容的电容值相同。
在本申请的像素电路中，所述第一电容的第一电极和所述第二电容的第一电极同层设置；所述第一电容的第二电极和所述第二电容的第二电极同层设置。
在本申请的像素电路中，所述开关电路包括第一开关晶体管、第一切换开关、以及第一开关，所述第一开关晶体管的漏极电连接所述第一切换开关的第一引脚，所述第一切换开关的第二引脚电连接所述第一存储电路，所述第一切换开关的第三引脚电连接所述第二存储电路，所述第二存储电路通过所述第一开关电连接所述驱动电路。
在本申请的像素电路中，所述开关电路包括第二开关晶体管、第三开关晶体管、第二开关、以及第三开关，所述第二开关晶体管的漏极通过所述第二开关电连接所述第一存储电路，所述第三开关晶体管的漏极电连接所述第二存储电路，所述第二存储电路通过所述第三开关电连接所述第二开关晶体管的漏极。
在本申请的像素电路中，所述开关电路包括第四开关晶体管、第五开关晶体管、第二切换开关，所述第四开关晶体管的漏极电连接所述第一存储电路，所述第五开关晶体管的漏极电连接所述第二切换开关的第一引脚，所述第二切换开关的第二引脚电连接所述第二存储电路，所述第二切换开关的第三引脚电连接所述驱动电路。
本申请还提出了一种OLED显示面板，其中，包括像素阵列，所述像素阵列包括至少一像素电路，所述像素电路包括：
驱动电路；
发光电路，用于在所述驱动电路的驱动下发光；
开关电路；
第一存储电路；以及
第二存储电路；
其中，所述第一存储电路用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。
在本申请的OLED显示面板中，所述驱动电路包括驱动晶体管，所述驱动晶体管的源极电连接电源电压，所述驱动晶体管的漏极电连接所述发光电路，所述驱动晶体管的栅极电连接所述第一存储电路和所述第二存储电路。
在本申请的OLED显示面板中，所述发光电路包括发光开关管以及发光器件。
在本申请的OLED显示面板中，所述第一存储电路包括第一电容，所述第二存储电路包括第二电容。
在本申请的OLED显示面板中，所述第一电容和所述第二电容的电容值相同。
在本申请的OLED显示面板中，所述第一电容的第一电极和所述第二电容的第一电极同层设置；所述第一电容的第二电极和所述第二电容的第二电极同层设置。
在本申请的OLED显示面板中，所述开关电路包括第一开关晶体管、第一切换开关、以及第一开关，所述第一开关晶体管的漏极电连接所述第一切换开关的第一引脚，所述第一切换开关的第二引脚电连接所述第一存储电路，所述第一切换开关的第三引脚电连接所述第二存储电路，所述第二存储电路通过所述第一开关电连接所述驱动电路。
在本申请的OLED显示面板中，所述开关电路包括第二开关晶体管、第三开关晶体管、第二开关、以及第三开关，所述第二开关晶体管的漏极通过所述第二开关电连接所述第一存储电路，所述第三开关晶体管的漏极电连接所述第二存储电路，所述第二存储电路通过所述第三开关电连接所述第二开关晶体管的漏极。
在本申请的OLED显示面板中，所述开关电路包括第四开关晶体管、第五开关晶体管、第二切换开关，所述第四开关晶体管的漏极电连接所述第一存储电路，所述第五开关晶体管的漏极电连接所述第二切换开关的第一引脚，所述第二切换开关的第二引脚电连接所述第二存储电路，所述第二切换开关的第三引脚电连接所述驱动电路。
 有益效果
本申请通过设置至少两个存储电路，通过在第一显示帧的发光阶段对一个存储电路进行充电，然后在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光，实现了存储电路充电与面板发光同时进行，基于此可以大大增加充电时间，解决了现有OLED面板存在的存储电容Cst充电不足的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有像素电路的电路示意图；
图2为现有像素电路的工作时序图；
图3为本申请实施例提供的像素电路的第一种电路示意图；
图4为图3所示像素电路的工作时序图；
图5为本申请实施例提供的像素电路的第二种电路示意图；
图6为图5所示像素电路的工作时序图；
图7为本申请实施例提供的像素电路的第三种电路示意图；
图8为图7所示像素电路的工作时序图。
 本发明的实施方式
下面将结合本申请的具体实施方案，对本申请实施方案和/或实施例中的技术方案进行清楚、完整的描述，显而易见的，下面所描述的实施方案和/或实施例仅仅是本申请一部分实施方案和/或实施例，而不是全部的实施方案和/或实施例。基于本申请中的实施方案和/或实施例，本领域普通技术人员在没有做出创造性劳动前下所获得的所有其他实施方案和/或实施例，都属于本申请保护范围。
本申请所提到的方向用语，例如[上]、[下]、[左]、[右]、[前] 、[后] 、[内] 、[外] 、[侧]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明和理解本申请，而非用以限制本申请。术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或是暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。
参照图1和图2，在现有的OLED像素电路中，在一个显示帧周期内，在一个显示帧的数据信号写入阶段t2内，首先扫描线路Gate输入高压，开关晶体管T1导通，以完成存储电容Cst的充电，此时发光开关管T2断开，在一个显示帧的发光阶段t3内，扫描线路Gate输入低压，开关晶体管T1断开，发光开关管T2导通，显示面板发光。但是，随着分辨率和帧频不断提升的情况下，存储电容Cst的充电时间被压缩的越来越短，导致显示屏出现存储电容Cst充电不足的问题。
针对现有OLED面板存在存储电容Cst充电不足的技术问题，本申请提供一种像素电路可以解决这个问题。
在一种实施例中，如图3所示，本申请提供的像素电路包括：
驱动电路31；
发光电路32，用于在所述驱动电路的驱动下发光；
开关电路33；
第一存储电路34；以及
第二存储电路35；
其中，所述第一存储电路34用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路35用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。
本实施例提供了一种像素电路，其包括：驱动电路，发光电路，开关电路，第一存储电路，以及第二存储电路；其中，所述第一存储电路用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。本申请通过设置至少两个存储电路，通过在第一显示帧的发光阶段对一个存储电路进行充电，然后在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光，实现了存储电路充电与面板发光同时进行，基于此可以大大增加充电时间，解决了现有OLED面板存在的存储电容Cst充电不足的技术问题。
在一种实施例中，如图3所示，在本申请的像素电路中，所述驱动电路31包括驱动晶体管G，所述驱动晶体管G的源极电连接电源电压PW，所述驱动晶体管G的漏极电连接所述发光电路，所述驱动晶体管G的栅极电连接所述第一存储电路34和所述第二存储电路35。
在一种实施例中，如图3所示，在本申请的像素电路中，所述发光电路32包括发光开关管EM以及发光器件EL。发光开关管EM在控制信号EM的控制下导通或断开，进而控制发光器件EL发光。
在一种实施例中，如图3所示，发光开关管EM设置在驱动晶体管G和发光器件EL，所述发光器件EL的另一端接地GND。
在一种实施例中，发光开关管EM设置在发光器件EL和地GND之间。
在一种实施例中，如图3所示，在本申请的像素电路中，所述第一存储电路34包括第一电容C1，所述第二存储电路35包括第二电容C1。
在一种实施例中，在本申请的像素电路中，所述第一存储电路34包括第一电感，所述第二存储电路35包括第二电感。
在一种实施例中，在本申请的像素电路中，所述第一电容和所述第二电容的电容值相同。这样便于使用同样的掩模板制备电容，且便于后续算法的计算。
在一种实施例中，在本申请的像素电路中，所述第一电容的第一电极和所述第二电容的第一电极同层设置；所述第一电容的第二电极和所述第二电容的第二电极同层设置。
现结合图3和图4对开关电路33的第一种实现方式进行描述。
在一种实施例中，如图3所示，在本申请的像素电路中，所述开关电路33包括第一开关晶体管ST1、第一切换开关SW1、以及第一开关K1，所述第一开关晶体管ST1的源极电连接源极驱动器，根据Vdata1电压向存储电容充电，所述第一开关晶体管ST1的栅极电连接栅极驱动电路，根据Gate1信号实现导通和断开的控制，所述第一开关晶体管ST1的漏极电连接所述第一切换开关SW1的第一引脚SW1-1，所述第一切换开关SW1的第二引脚SW1-2电连接所述第一存储电路的电容C1，所述第一切换开关SW1的第三引脚SW1-3电连接所述第二存储电路的电容C2，所述第二存储电路C2通过所述第一开关K1电连接所述驱动电路的驱动晶体管G的栅极；所述第一切换开关SW1在信号SW1的控制下工作。
一个显示帧包括起始阶段t1、数据信号写入阶段t2、发光阶段t3和切换阶段t4。
在一种实施例中，如图4所示，图3所示的像素电路的工作原理为：
在第一显示帧的t1内，第一开关晶体管ST1、发光开关管EM和开关K1都断开，所述第一切换开关SW1的第一引脚SW1-1和第二引脚SW1-2连通；
在第一显示帧的t2内，Gate1为高电位，第一开关晶体管ST1导通，发光开关管EM和开关K1都断开，为电容C1充电，充电电压为第一显示帧对应的灰阶电压；
在第一显示帧的t3内，所述第一切换开关SW1的第一引脚SW1-1和第三引脚SW1-3连通，Gate1保持高电位，第一开关晶体管ST1导通，为电容C2充电，直至电容C2的电量为电容C1和电容C2要达到电位需要的总和，充电时长为t5（可以等于t3，或者小于t3），充电电压为第二显示帧对应的灰阶电压，开关K1断开；电容C1为驱动晶体管G的栅极提供工作电压，EM为高电位，发光开关管EM导通，发光器件EL发光；
在第一显示帧的t4内，第一开关晶体管ST1、发光开关管EM和开关K1都断开，所述第一切换开关SW1的第一引脚SW1-1和第二引脚SW1-2连通，发光器件EL结束发光；
在第二显示帧的t1内，第一开关晶体管ST1断开，发光开关管EM和开关K1都导通，所述第一切换开关SW1的第一引脚SW1-1和第二引脚SW1-2连通；电容C2为驱动晶体管G的栅极提供工作电压，EM为高电位，发光开关管EM导通，发光器件EL发光；
第二显示帧内t2至t4的后续循环，和第一显示帧内的t2至t4相同，可以使充电与显示并行循环，不再赘述。
现结合图5和图6对开关电路33的第二种实现方式进行描述。
在一种实施例中，如图5所示，在本申请的像素电路中，所述开关电路33包括第二开关晶体管ST2、第三开关晶体管ST3、第二开关K2、以及第三开关K3，所述第二开关晶体管ST2的源极电连接源极驱动器，根据Vdata2电压向存储电容充电，所述第二开关晶体管ST2的栅极电连接栅极驱动电路，根据Gate2信号实现导通和断开的控制，所述第二开关晶体管ST2的漏极通过所述第二开关K2电连接所述第一存储电路的电容C1，所述第三开关晶体管ST3的源极电连接源极驱动器，根据Vdata3电压向存储电容充电，所述第三开关晶体管ST3的栅极电连接栅极驱动电路，根据Gate3信号实现导通和断开的控制，所述第三开关晶体管ST3的漏极电连接所述第二存储电路的电容C2，所述第二存储电路的电容C2通过所述第三开关K3电连接所述第二开关晶体管ST2的漏极。
在一种实施例中，如图6所示，图5所示的像素电路的工作原理为：
在第一显示帧的t1内，第二开关晶体管ST2、第三开关晶体管ST3、开关K2、开关K3、发光开关管EM都断开；
在第一显示帧的t2内，Gate2为高电位，第二开关晶体管ST2导通，发光开关管EM断开，为电容C1充电，充电电压为第一显示帧对应的灰阶电压；
在第一显示帧的t3内，Gate3为高电位，第三开关晶体管ST3导通，为电容C2充电，直至电容C2的电量为电容C1和电容C2要达到电位需要的总和，充电时长为t5（可以等于t3，或者小于t3），充电电压为第二显示帧对应的灰阶电压；Gate2变为低电位，第二开关晶体管ST2断开，电容C1为驱动晶体管G的栅极提供工作电压，EM为高电位，发光开关管EM导通，发光器件EL发光；
在第一显示帧的t4内，第二开关晶体管ST2、第三开关晶体管ST3、开关K2、开关K3、发光开关管EM都断开，发光器件EL结束发光；
在第二显示帧的t1内，第二开关晶体管ST2、第三开关晶体管ST3保持断开，所述开关K2闭合、开关K3闭合，发光开关管EM导通，电容C2为驱动晶体管G的栅极提供工作电压，EM为高电位，发光开关管EM导通，发光器件EL发光；
第二显示帧内t2至t4的后续循环，和第一显示帧内的t2至t4相同，可以使充电与显示并行循环，不再赘述。
在一种实施例中，电容C1和电容C2都同步进行充电，即在第一显示帧的t2内，Gate2为高电位，第二开关晶体管ST2导通，发光开关管EM断开，为电容C1充电，充电电压为第一显示帧对应的灰阶电压；Gate3为高电位，第三开关晶体管ST3导通，为电容C2充电，直至电容C2的电量为电容C1和电容C2要达到电位需要的总和，充电时长为t5（可以等于t3，或者小于t3），充电电压为第二显示帧对应的灰阶电压，电容C2充电结束后，Gate3变为低电位，第三开关晶体管ST3断开。
现结合图7和图8对开关电路33的第三种实现方式进行描述。
在一种实施例中，如图7所示，在本申请的像素电路中，所述开关电路33包括第四开关晶体管ST4、第五开关晶体管ST5、第二切换开关SW2，所述第四开关晶体管ST4的源极电连接源极驱动器，根据Vdata4电压向存储电容充电，所述第四开关晶体管ST4的栅极电连接栅极驱动电路，根据Gate4信号实现导通和断开的控制，所述第四开关晶体管ST4的漏极电连接所述第一存储电路的电容C1，所述第五开关晶体管ST5的源极电连接源极驱动器，根据Vdata5电压向存储电容充电，所述第五开关晶体管ST5的栅极电连接栅极驱动电路，根据Gate5信号实现导通和断开的控制，所述第五开关晶体管ST5的漏极电连接所述第二切换开关SW2的第一引脚SW2-1，所述第二切换开关SW2的第二引脚SW2-2电连接所述第二存储电路的电容C2，所述第二切换开关SW2的第三引脚SW2-3电连接所述驱动电路的驱动晶体管G的栅极；所述第二切换开关SW2在信号SW2的控制下工作。
在一种实施例中，如图8所示，图7所示的像素电路的工作原理为：
在第一显示帧的t1内，第四开关晶体管ST4、第五开关晶体管ST5、发光开关管EM都断开，所述第二切换开关SW2的第一引脚SW2-1和第二引脚SW2-2连通；
在第一显示帧的t2内，Gate4为高电位，第四开关晶体管ST4导通，发光开关管EM断开，为电容C1充电，充电电压为第一显示帧对应的灰阶电压；
在第一显示帧的t3内，Gate5为高电位，第五开关晶体管ST5导通，为电容C2充电，直至电容C2的电量为电容C1和电容C2要达到电位需要的总和，充电时长为t5（可以等于t3，或者小于t3），充电电压为第二显示帧对应的灰阶电压；Gate4变为低电位，第四开关晶体管ST4断开，电容C1为驱动晶体管G的栅极提供工作电压，EM为高电位，发光开关管EM导通，发光器件EL发光；
在第一显示帧的t4内，第四开关晶体管ST4、第五开关晶体管ST5、发光开关管EM都断开，所述第二切换开关SW2的第一引脚SW2-1和第二引脚SW2-2连通，发光器件EL结束发光；
在第二显示帧的t1内，第四开关晶体管ST4、第五开关晶体管ST5断开，所述第二切换开关SW2的第三引脚SW2-3和第二引脚SW2-2连通，发光开关管EM导通，电容C2为驱动晶体管G的栅极提供工作电压，EM为高电位，发光开关管EM导通，发光器件EL发光；
第二显示帧内t2至t4的后续循环，和第一显示帧内的t2至t4相同，可以使充电与显示并行循环，不再赘述。
在一种实施例中，电容C1和电容C2都同步进行充电，即在第一显示帧的t2内，Gate4为高电位，第四开关晶体管ST4导通，发光开关管EM断开，为电容C1充电，充电电压为第一显示帧对应的灰阶电压；Gate5为高电位，第五开关晶体管ST5导通，为电容C2充电，直至电容C2的电量为电容C1和电容C2要达到电位需要的总和，充电时长为t5（可以等于t3，或者小于t3），充电电压为第二显示帧对应的灰阶电压，电容C2充电结束后，Gate5变为低电位，第五开关晶体管ST5断开。
同时，本申请还提供一种OLED显示面板，其包括像素阵列，所述像素阵列包括至少一个本申请提供的像素电路，如图3所示，所述像素电路包括：
像素电路包括：
驱动电路31；
发光电路32，用于在所述驱动电路的驱动下发光；
开关电路33；
第一存储电路34；以及
第二存储电路35；
其中，所述第一存储电路34用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路35用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。
本实施例提供了一种OLED显示面板，其像素电路包括：驱动电路，发光电路，开关电路，第一存储电路，以及第二存储电路；其中，所述第一存储电路用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。本申请通过设置至少两个存储电路，通过在第一显示帧的发光阶段对一个存储电路进行充电，然后在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光，实现了存储电路充电与面板发光同时进行，基于此可以大大增加充电时间，解决了现有OLED面板存在的存储电容Cst充电不足的技术问题。
在一种实施例中，在本申请的OLED显示面板中，所述驱动电路31包括驱动晶体管G，所述驱动晶体管G的源极电连接电源电压PW，所述驱动晶体管G的漏极电连接所述发光电路，所述驱动晶体管G的栅极电连接所述第一存储电路34和所述第二存储电路35。
在一种实施例中，在本申请的OLED显示面板中，所述发光电路32包括发光开关管EM以及发光器件EL。发光开关管EM在控制信号EM的控制下导通或断开，进而控制发光器件EL发光。
在一种实施例中，在本申请的OLED显示面板中，发光开关管EM设置在驱动晶体管G和发光器件EL，所述发光器件EL的另一端接地GND。
在一种实施例中，在本申请的OLED显示面板中，发光开关管EM设置在发光器件EL和地GND之间。
在一种实施例中，在本申请的OLED显示面板中，所述第一存储电路34包括第一电容C1，所述第二存储电路35包括第二电容C1。
在一种实施例中，在本申请的OLED显示面板中，所述第一存储电路34包括第一电感，所述第二存储电路35包括第二电感。
在一种实施例中，在本申请的OLED显示面板中，所述第一电容和所述第二电容的电容值相同。这样便于使用同样的掩模板制备电容，且便于后续算法的计算。
在一种实施例中，在本申请的OLED显示面板中，所述第一电容的第一电极和所述第二电容的第一电极同层设置；所述第一电容的第二电极和所述第二电容的第二电极同层设置。
在一种实施例中，在本申请的OLED显示面板中，所述开关电路33包括第一开关晶体管ST1、第一切换开关SW1、以及第一开关K1，所述第一开关晶体管ST1的源极电连接源极驱动器，根据Vdata1电压向存储电容充电，所述第一开关晶体管ST1的栅极电连接栅极驱动电路，根据Gate1信号实现导通和断开的控制，所述第一开关晶体管ST1的漏极电连接所述第一切换开关SW1的第一引脚SW1-1，所述第一切换开关SW1的第二引脚SW1-2电连接所述第一存储电路的电容C1，所述第一切换开关SW1的第三引脚SW1-3电连接所述第二存储电路的电容C2，所述第二存储电路C2通过所述第一开关K1电连接所述驱动电路的驱动晶体管G的栅极；所述第一切换开关SW1在信号SW1的控制下工作。
在一种实施例中，在本申请的OLED显示面板中，所述开关电路33包括第二开关晶体管ST2、第三开关晶体管ST3、第二开关K2、以及第三开关K3，所述第二开关晶体管ST2的源极电连接源极驱动器，根据Vdata2电压向存储电容充电，所述第二开关晶体管ST2的栅极电连接栅极驱动电路，根据Gate2信号实现导通和断开的控制，所述第二开关晶体管ST2的漏极通过所述第二开关K2电连接所述第一存储电路的电容C1，所述第三开关晶体管ST3的源极电连接源极驱动器，根据Vdata3电压向存储电容充电，所述第三开关晶体管ST3的栅极电连接栅极驱动电路，根据Gate3信号实现导通和断开的控制，所述第三开关晶体管ST3的漏极电连接所述第二存储电路的电容C2，所述第二存储电路的电容C2通过所述第三开关K3电连接所述第二开关晶体管ST2的漏极。
在一种实施例中，在本申请的OLED显示面板中，所述开关电路33包括第四开关晶体管ST4、第五开关晶体管ST5、第二切换开关SW2，所述第四开关晶体管ST4的源极电连接源极驱动器，根据Vdata4电压向存储电容充电，所述第四开关晶体管ST4的栅极电连接栅极驱动电路，根据Gate4信号实现导通和断开的控制，所述第四开关晶体管ST4的漏极电连接所述第一存储电路的电容C1，所述第五开关晶体管ST5的源极电连接源极驱动器，根据Vdata5电压向存储电容充电，所述第五开关晶体管ST5的栅极电连接栅极驱动电路，根据Gate5信号实现导通和断开的控制，所述第五开关晶体管ST5的漏极电连接所述第二切换开关SW2的第一引脚SW2-1，所述第二切换开关SW2的第二引脚SW2-2电连接所述第二存储电路的电容C2，所述第二切换开关SW2的第三引脚SW2-3电连接所述驱动电路的驱动晶体管G的栅极；所述第二切换开关SW2在信号SW2的控制下工作。
根据上述实施例可知：
本申请提供一种像素电路及OLED显示面板，其像素电路包括：驱动电路，发光电路，开关电路，第一存储电路，以及第二存储电路；其中，所述第一存储电路用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。本申请通过设置至少两个存储电路，通过在第一显示帧的发光阶段对一个存储电路进行充电，然后在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光，实现了存储电路充电与面板发光同时进行，基于此可以大大增加充电时间，解决了现有OLED面板存在的存储电容Cst充电不足的技术问题。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种像素电路，其中，包括：
    驱动电路；
    发光电路，用于在所述驱动电路的驱动下发光；
    开关电路；
    第一存储电路；以及
    第二存储电路；
    其中，所述第一存储电路用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。
  2. 如权利要求1所述的像素电路，其中，所述驱动电路包括驱动晶体管，所述驱动晶体管的源极电连接电源电压，所述驱动晶体管的漏极电连接所述发光电路，所述驱动晶体管的栅极电连接所述第一存储电路和所述第二存储电路。
  3. 如权利要求1所述的像素电路，其中，所述发光电路包括发光开关管以及发光器件。
  4. 如权利要求1所述的像素电路，其中，所述第一存储电路包括第一电容，所述第二存储电路包括第二电容。
  5. 如权利要求4所述的像素电路，其中，所述第一电容和所述第二电容的电容值相同。
  6. 如权利要求4所述的像素电路，其中，所述第一电容的第一电极和所述第二电容的第一电极同层设置；所述第一电容的第二电极和所述第二电容的第二电极同层设置。
  7. 如权利要求1所述的像素电路，其中，所述开关电路包括第一开关晶体管、第一切换开关、以及第一开关，所述第一开关晶体管的漏极电连接所述第一切换开关的第一引脚，所述第一切换开关的第二引脚电连接所述第一存储电路，所述第一切换开关的第三引脚电连接所述第二存储电路，所述第二存储电路通过所述第一开关电连接所述驱动电路。
  8. 如权利要求1所述的像素电路，其中，所述开关电路包括第二开关晶体管、第三开关晶体管、第二开关、以及第三开关，所述第二开关晶体管的漏极通过所述第二开关电连接所述第一存储电路，所述第三开关晶体管的漏极电连接所述第二存储电路，所述第二存储电路通过所述第三开关电连接所述第二开关晶体管的漏极。
  9. 如权利要求1所述的像素电路，其中，所述开关电路包括第四开关晶体管、第五开关晶体管、第二切换开关，所述第四开关晶体管的漏极电连接所述第一存储电路，所述第五开关晶体管的漏极电连接所述第二切换开关的第一引脚，所述第二切换开关的第二引脚电连接所述第二存储电路，所述第二切换开关的第三引脚电连接所述驱动电路。
  10. 一种OLED显示面板，其中，包括像素阵列，所述像素阵列包括至少一像素电路，所述像素电路包括：
    驱动电路；
    发光电路，用于在所述驱动电路的驱动下发光；
    开关电路；
    第一存储电路；以及
    第二存储电路；
    其中，所述第一存储电路用于在所述开关电路的控制下，在第一显示帧的数据信号写入阶段进行充电，并在所述第一显示帧的发光阶段向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光；所述第二存储电路用于在所述开关电路的控制下，在第一显示帧的发光阶段进行充电，并在第二显示帧时向所述驱动电路提供工作电压，以触发所述驱动电路驱动所述发光电路发光。
  11. 如权利要求10所述的OLED显示面板，其中，所述驱动电路包括驱动晶体管，所述驱动晶体管的源极电连接电源电压，所述驱动晶体管的漏极电连接所述发光电路，所述驱动晶体管的栅极电连接所述第一存储电路和所述第二存储电路。
  12. 如权利要求10所述的OLED显示面板，其中，所述发光电路包括发光开关管以及发光器件。
  13. 如权利要求10所述的OLED显示面板，其中，所述第一存储电路包括第一电容，所述第二存储电路包括第二电容。
  14. 如权利要求13所述的OLED显示面板，其中，所述第一电容和所述第二电容的电容值相同。
  15. 如权利要求13所述的OLED显示面板，其中，所述第一电容的第一电极和所述第二电容的第一电极同层设置；所述第一电容的第二电极和所述第二电容的第二电极同层设置。
  16. 如权利要求10所述的OLED显示面板，其中，所述开关电路包括第一开关晶体管、第一切换开关、以及第一开关，所述第一开关晶体管的漏极电连接所述第一切换开关的第一引脚，所述第一切换开关的第二引脚电连接所述第一存储电路，所述第一切换开关的第三引脚电连接所述第二存储电路，所述第二存储电路通过所述第一开关电连接所述驱动电路。
  17. 如权利要求10所述的OLED显示面板，其中，所述开关电路包括第二开关晶体管、第三开关晶体管、第二开关、以及第三开关，所述第二开关晶体管的漏极通过所述第二开关电连接所述第一存储电路，所述第三开关晶体管的漏极电连接所述第二存储电路，所述第二存储电路通过所述第三开关电连接所述第二开关晶体管的漏极。
  18. 如权利要求10所述的OLED显示面板，其中，所述开关电路包括第四开关晶体管、第五开关晶体管、第二切换开关，所述第四开关晶体管的漏极电连接所述第一存储电路，所述第五开关晶体管的漏极电连接所述第二切换开关的第一引脚，所述第二切换开关的第二引脚电连接所述第二存储电路，所述第二切换开关的第三引脚电连接所述驱动电路。
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