WO2020228100A1 - 显示器驱动系统及显示器驱动方法 - Google Patents

显示器驱动系统及显示器驱动方法 Download PDF

Info

Publication number
WO2020228100A1
WO2020228100A1 PCT/CN2019/092663 CN2019092663W WO2020228100A1 WO 2020228100 A1 WO2020228100 A1 WO 2020228100A1 CN 2019092663 W CN2019092663 W CN 2019092663W WO 2020228100 A1 WO2020228100 A1 WO 2020228100A1
Authority
WO
WIPO (PCT)
Prior art keywords
source driver
timing controller
transmission
signal
transmission channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/092663
Other languages
English (en)
French (fr)
Inventor
赵兴海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Publication of WO2020228100A1 publication Critical patent/WO2020228100A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the invention relates to the field of display technology, in particular to a display driving system and a display driving method.
  • liquid crystal display devices such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED) displays have gradually replaced cathode ray tubes (Cathode ray tubes). Ray Tube, CRT) display device.
  • the liquid crystal display device has many advantages such as thin body, power saving, and no radiation, and has been widely used.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • a liquid crystal display panel consists of a color filter (CF) substrate, a thin film transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and sealant Sealant composition.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules between two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates. The liquid crystal molecules are controlled to change direction by powering on or not, and the light of the backlight module Refraction produces a picture.
  • OLED usually includes: a substrate, an anode provided on the substrate, a hole injection layer (HIL) provided on the anode, a hole transport layer (HTL) provided on the hole injection layer, and a hole transport layer (HTL) provided on the hole transport layer.
  • HIL hole injection layer
  • HTL hole transport layer
  • HTL hole transport layer
  • HTL hole transport layer
  • HTL hole transport layer
  • the light-emitting principle of OLED display devices is that semiconductor materials and organic light-emitting materials are driven by an electric field to cause light emission through carrier injection and recombination.
  • a timing controller In the prior art, a timing controller (Tcon) generally receives data signals in the form of low voltage differential signals (LVDS) and converts them to generate data signals in the form of mini low voltage differential signals (Mini-LVDS) and transmits them to the source via multiple pairs of data transmission channels.
  • the source driver In a pole driver, the source driver can generate a corresponding driving voltage to drive the display panel for display.
  • the timing controller generally transmits to the source driver a command signal for setting the source driver, including polarity control signals, output displacement signals, multiple selection signals, color exchange signals, etc. The controller needs to set multiple output pins to output these command signals.
  • the source driver also needs to set multiple input pins to receive these command signals, which greatly increases the number of pins of the timing controller and the source driver. , Which greatly increases the cost of chip and circuit design for driving the display driving system.
  • the purpose of the present invention is to provide a display driving system that can reduce the number of pins of the timing controller and the source driver, and reduce the cost of the chip and the circuit design.
  • Another object of the present invention is to provide a display driving method, which can reduce the number of pins of the timing controller and the source driver, and reduce the chip cost and circuit design cost.
  • the present invention first provides a display driving system, including a timing controller and a source driver; the timing controller is electrically connected to the source driver via multiple sets of transmission channels; the multiple sets of transmission channels include a first One set of transmission channels and a second set of transmission channels;
  • the working sequence of the display driving system includes an initial stage, a command signal transmission stage, a reset stage, and a display data transmission stage in sequence; in the initial stage, the timing controller transmits the command transmission to the source driver via the second set of transmission channels Start signal; in the command signal transmission stage, the timing controller transmits at least one command signal to the source driver via the second group of transmission channels; in the reset stage, the timing controller transmits a reset signal to the source driver via the first group of transmission channels; In the display data transmission stage, the timing controller transmits line display data to the source driver via multiple sets of transmission channels.
  • Each command signal is one of a polarity inversion control signal, an output displacement control signal, a data polarity inversion signal, a selection signal, and a color exchange signal.
  • the timing controller transmits a high-level reset signal to the source driver through the first group of transmission channels and transmits an invalid signal to the source driver through the second group of transmission channels;
  • the timing controller sequentially transmits invalid signals with a duration of a preset period to the source driver via the first group of transmission channels, the duration is the low level of the preset period, and the duration is the preset period
  • the timing controller transmits the invalid signal with a duration of 3 times the preset period to the source driver through the second transmission channel, and then transmits the row display data to the source driver.
  • the duration of the reset phase is greater than or equal to 3 times the preset period.
  • the duration of the reset phase is greater than or equal to 50 ns.
  • the timing controller transmits a high-level start signal to the source driver through the second group of transmission channels and transmits an invalid signal to the source driver through the first group of transmission channels;
  • the timing controller sequentially transmits invalid signals with a duration of the preset period, a duration of the low level of the preset period, and a duration of the preset period to the source driver via the second set of transmission channels. Periodic invalid signals and then sequentially transmit multiple command signals to the source driver. The transmission duration of each command signal is the preset period. The timing controller sequentially transmits the invalid signals and low power to the source driver via the first group of transmission channels. level.
  • the duration of the initial phase is equal to the duration of the reset phase.
  • the timing controller is also electrically connected to the source driver via clock signal wiring; in the initial stage, command signal transmission stage, reset stage and display data transmission stage, the timing controller transmits to the source driver via the clock signal wiring Clock signal; the duty cycle of the clock signal is 0.5, and the period of the clock signal is the preset period.
  • the source driver includes a receiving module, and the timing controller is electrically connected to the receiving module of the source driver via multiple sets of transmission channels.
  • the present invention also provides a display driving method, which is applied to the above-mentioned display driving system, and includes the following steps:
  • Step S1 enter the initial stage
  • the timing controller transmits the command transmission start signal to the source driver via the second group of transmission channels;
  • Step S2 enter the command signal transmission stage
  • the timing controller transmits the command signal to the source driver via the second group of transmission channels
  • Step S3 enter the reset phase
  • the timing controller transmits the reset signal to the source driver via the first group of transmission channels
  • Step S4 enter the display data transmission stage
  • the timing controller transmits line display data to the source driver via multiple transmission channels.
  • the display driving system of the present invention includes a timing controller and a source driver, and the timing controller is electrically connected with the source driver through multiple sets of transmission channels.
  • the timing controller transmits a command to the source driver via the second set of transmission channels.
  • the transmission start signal indicates the start of the transmission of the command signal.
  • the timing controller transmits to the source via the second set of transmission channels.
  • the driver transmits command signals.
  • the timing controller transmits a reset signal to the source driver via the first set of transmission channels to indicate the start of the transmission of line display data.
  • the timing controller transmits to the source via multiple sets of transmission channels.
  • the driver transmits line display data, which can reduce the number of pins of the timing controller and the source driver, and reduce chip cost and circuit design cost.
  • the display driving method of the present invention can reduce the number of pins of the timing controller and the source driver, and reduce the chip cost and circuit design cost.
  • FIG. 1 is a schematic diagram of the structure of the display driving system of the present invention
  • Figure 2 is a timing diagram of the display drive system of the present invention.
  • FIG. 3 is a flowchart of the display driving method of the present invention.
  • the present invention provides a display driving system, including a timing controller 10 and a source driver 20.
  • the timing controller 10 is electrically connected to the source driver 20 via multiple sets of transmission channels 30.
  • the multiple groups of transmission channels 30 include a first group of transmission channels LV0P/N and a second group of transmission channels LV1P/N, and other groups of transmission channels except the first group of transmission channels LV0P/N and the second group of transmission channels LV1P/N. 30.
  • multiple groups of transmission channels 30 generally include 3 to 6 groups of transmission channels 30.
  • the source driver 20 includes a receiving module 21, and the timing controller 10 is electrically connected to the receiving module 21 of the source driver 20 via multiple sets of transmission channels 30.
  • the source driver 20 further includes a shift register module 22 electrically connected to the receiving module 21, a latch module 23 electrically connected to the shift register module 22, and a latch module 23
  • the digital-to-analog conversion module 24 is electrically connected and the output buffer module 25 is electrically connected to the digital-to-analog conversion module 24.
  • the timing controller 10 is also electrically connected to the source driver 20 via a clock signal wiring 40.
  • the working sequence of the display driving system includes an initial phase T1, a command signal transmission phase T2, a reset phase T3, and a display data transmission phase T4, which are sequentially performed.
  • the timing controller 10 transmits a command transmission start signal to the source driver 20 via the second group of transmission channels LV1P/N to indicate that the transmission of the command signal CMD is about to start.
  • the timing controller 10 transmits a high level (indicated by H in FIG. 2) to the source driver 20 via the second group of transmission channels LV1P/N
  • the start signal transmits an invalid signal to the source driver 20 via the first group of transmission channels LV0P/N (indicated by x in FIG. 2).
  • the timing controller 10 before the arrival of the initial stage T1, transmits a low level to the source driver 20 via the second group of transmission channels LV1P/N (indicated by L in the figure) And the invalid signal is transmitted to the source driver 20 through the first group of transmission channels LV0P/N.
  • the timing controller 10 transmits at least one command signal CMD to the source driver 20 via the second group of transmission channels LV1P/N.
  • each command signal CMD is one of a polarity inversion control signal, an output displacement control signal, a data polarity inversion signal, a selection signal, and a color exchange signal.
  • the above-mentioned signals are all timing controllers in the prior art.
  • the command signal directly transmitted to the source driver through the corresponding pin is not described here.
  • the timing controller 10 sequentially transmits invalid signals with a duration of a predetermined period to the source driver 20 via the second group of transmission channels LV1P/N.
  • the duration is the low level of the preset period
  • the duration is the invalid signal of the preset period
  • a plurality of command signals CMD are sequentially transmitted to the source driver 20, and the transmission duration of each command signal CMD is the preset Periodically
  • the timing controller 10 sequentially transmits an invalid signal and a low level to the source driver 20 via the first group of transmission channels LVOP/N.
  • the timing controller 10 transmits a reset signal to the source driver 20 via the first group of transmission channels LV0P/N.
  • the timing controller 10 transmits a high-level reset signal to the source driver 20 via the first group of transmission channels LVOP/N to indicate the transmission of the row data signal. It is about to start, and the invalid signal is transmitted to the source driver 20 via the second group of transmission channels LV1P/N.
  • the duration of the reset phase T3 is greater than or equal to 3 times the preset period, or the duration of the reset phase T3 is greater than or equal to 50 ns.
  • the duration of the initial phase T1 is equal to the duration of the reset phase T3.
  • the timing controller 10 transmits line display data to the source driver 20 via multiple sets of transmission channels 30.
  • the timing controller 10 sequentially transmits invalid signals with a duration of the preset period to the source driver 10 via the first group of transmission channels LVOP/N.
  • the line display data is transmitted to the source driver 20 (indicated by Data in FIG. 2), and the timing controller 10 transmits through the second transmission
  • the channel LV1P/N transmits an invalid signal with a duration of 3 times the preset period to the source driver 20 and then transmits line display data to the source driver 20.
  • the timing controller 10 transmits the clock signal CLKP to the source driver 20 via the clock signal wiring 40.
  • the duty cycle of the clock signal CLKP is 0.5, and the period of the clock signal CLKP is the preset period.
  • the timing controller 10 passes through the multiple transmission channels 30 except for the first group of transmission channels LV0P/N and the second group of transmission channels LV1P/N.
  • the group transmission channel 30 transmits an invalid signal to the source driver 20, and in the display data transmission phase T4, the timing controller 10 except the first group transmission channel LV0P/N and the second group transmission channel LV1P/N through the multiple transmission channels 30
  • the other transmission channels 30 transmit invalid signals with a duration of 3 times the preset period to the source driver 20 and then transmit line display data to the source driver 20.
  • the display driving system of the present invention uses the timing controller 10 to transmit a command transmission start signal to the source driver 20 via the second group of transmission channels LV1P/N in the initial stage T1 to indicate the start of transmission of the command signal CMD.
  • the timing controller 10 is used to transmit the command signal CMD to the source driver 20 via the second group of transmission channels LV1P/N
  • the timing controller 10 is used to transmit the command signal CMD to the source via the first group of transmission channels LV0P/N.
  • the pole driver 20 transmits a reset signal to indicate the start of the transmission of the line display data.
  • the timing controller 10 is used to transmit the line display data to the source driver 20 via multiple sets of transmission channels 30. Compared with the prior art, it needs to be
  • the timing controller is additionally provided with pins for outputting command signals and the source driver is additionally provided with pins only for receiving command signals.
  • the present invention can reduce the number of pins of the timing controller 10 and the source driver 20, Reduce chip cost and circuit design cost.
  • the present invention also provides a display driving method applied to the above-mentioned display driving system.
  • the display driving system will not be described repeatedly here.
  • the display driving method includes the following steps:
  • Step S1 enter the initial phase T1.
  • the timing controller 10 transmits the command transmission start signal to the source driver 20 via the second group of transmission channels LV1P/N.
  • the timing controller 10 transmits a high-level start signal to the source driver 20 via the second group of transmission channels LV1P/N and passes the first group of The transmission channel LV0P/N transmits an invalid signal to the source driver 20.
  • the timing controller 10 before the arrival of the initial stage T1, transmits the low level to the source driver 20 through the second group of transmission channels LV1P/N and then through the first group of transmission channels The LV0P/N transmits an invalid signal to the source driver 20.
  • Step S2 enter the command signal transmission phase T2.
  • the timing controller 10 transmits at least one command signal CMD to the source driver 20 via the second group of transmission channels LV1P/N.
  • each command signal CMD is one of a polarity inversion control signal, an output displacement control signal, a data polarity inversion signal, a selection signal, and a color exchange signal.
  • the above-mentioned signals are all timing controllers in the prior art.
  • the command signal directly transmitted to the source driver through the corresponding pin is not described here.
  • the timing controller 10 sequentially transmits invalid signals with a duration of a predetermined period to the source driver 20 via the second group of transmission channels LV1P/N.
  • the duration is the low level of the preset period
  • the duration is the invalid signal of the preset period
  • a plurality of command signals CMD are sequentially transmitted to the source driver 20, and the transmission duration of each command signal CMD is the preset Periodically
  • the timing controller 10 sequentially transmits an invalid signal and a low level to the source driver 20 via the first group of transmission channels LVOP/N.
  • Step S3 enter the reset phase T3.
  • the timing controller 10 transmits the reset signal to the source driver 20 via the first group of transmission channels LVOP/N.
  • the timing controller 10 transmits a high-level reset signal to the source driver 20 via the first group of transmission channels LVOP/N to indicate the transmission of the row data signal. It is about to start, and the invalid signal is transmitted to the source driver 20 via the second group of transmission channels LV1P/N.
  • the duration of the reset phase T3 is greater than or equal to 3 times the preset period, or the duration of the reset phase T3 is greater than or equal to 50 ns.
  • the duration of the initial phase T1 is equal to the duration of the reset phase T3.
  • Step S4 Enter the display data transmission stage T4.
  • the timing controller 10 transmits line display data to the source driver 20 via multiple sets of transmission channels 30.
  • the timing controller 10 sequentially transmits invalid signals with a duration of the preset period to the source driver 10 via the first group of transmission channels LVOP/N. , After the duration is the low level of the preset period, and the duration is the invalid signal of the preset period, the line display data is transmitted to the source driver 20, and the timing controller 10 transmits the second transmission channel LV1P/N to the source driver After transmitting the invalid signal whose duration is 3 times the preset period, the line display data is transmitted to the source driver 20.
  • the timing controller 10 transmits the clock signal CLKP to the source driver 20 via the clock signal wiring 40.
  • the duty cycle of the clock signal CLKP is 0.5, and the period of the clock signal CLKP is the preset period.
  • the timing controller 10 passes through the multiple transmission channels 30 except for the first group of transmission channels LV0P/N and the second group of transmission channels LV1P/N.
  • the group transmission channel 30 transmits an invalid signal to the source driver 20, and in the display data transmission phase T4, the timing controller 10 except the first group transmission channel LV0P/N and the second group transmission channel LV1P/N through the multiple transmission channels 30
  • the other transmission channels 30 transmit invalid signals with a duration of 3 times the preset period to the source driver 20 and then transmit line display data to the source driver 20.
  • the display driving method of the present invention uses the timing controller 10 to transmit the command transmission start signal to the source driver 20 via the second group of transmission channels LV1P/N in the initial stage T1 to indicate the start of transmission of the command signal CMD.
  • the timing controller 10 is used to transmit the command signal CMD to the source driver 20 via the second group of transmission channels LV1P/N
  • the timing controller 10 is used to transmit the command signal CMD to the source via the first group of transmission channels LV0P/N.
  • the pole driver 20 transmits a reset signal to indicate the start of the transmission of the line display data.
  • the timing controller 10 is used to transmit the line display data to the source driver 20 via multiple sets of transmission channels 30. Compared with the prior art, it needs to be
  • the timing controller is additionally provided with pins for outputting command signals and the source driver is additionally provided with pins only for receiving command signals.
  • the present invention can reduce the number of pins of the timing controller 10 and the source driver 20, Reduce chip cost and circuit design cost.
  • the display driving system of the present invention includes a timing controller and a source driver, and the timing controller is electrically connected to the source driver via multiple sets of transmission channels.
  • the timing controller transmits a command to the source driver via the second set of transmission channels.
  • the transmission start signal indicates the start of the transmission of the command signal.
  • the timing controller transmits through the second set of transmission channels.
  • the command signal is transmitted to the source driver.
  • the timing controller transmits a reset signal to the source driver via the first set of transmission channels to indicate the start of the transmission of line display data.
  • the timing controller uses multiple sets of transmission channels
  • the transmission of line display data to the source driver can reduce the number of pins of the timing controller and the source driver, thereby reducing chip cost and circuit design cost.
  • the display driving method of the present invention can reduce the number of pins of the timing controller and the source driver, and reduce the chip cost and circuit design cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明提供一种显示器驱动系统及显示器驱动方法。本发明的显示器驱动系统包括时序控制器及源极驱动器，时序控制器经多组传输通道与源极驱动器电性连接。工作时，在起始阶段时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号以指示命令信号的传输开始，在命令信号传输阶段时序控制器经第二组传输通道向源极驱动器传输命令信号，在复位阶段时序控制器经第一组传输通道向源极驱动器传输复位信号以指示行显示数据的传输开始，在显示数据传输阶段时序控制器经多组传输通道向源极驱动器传输行显示数据。本发明的显示器驱动系统能够减少时序控制器及源极驱动器的管脚数目，降低芯片成本及电路设计成本。

Description

显示器驱动系统及显示器驱动方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示器驱动系统及显示器驱动方法。
 背景技术
在显示技术领域，液晶显示装置（Liquid Crystal Display，LCD）、有机发光二极管（Organic Light-Emitting Diode，OLED）显示器等平板显示装置已经逐步取代阴极射线管（Cathode Ray Tube，CRT）显示装置。液晶显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组（backlight module）。通常液晶显示面板由彩膜（Color Filter，CF）基板、薄膜晶体管（Thin Film Transistor，TFT）阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶（Liquid Crystal，LC）及密封胶框（Sealant）组成。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
OLED通常包括：基板、设于基板上的阳极、设于阳极上的空穴注入层（HIL）、设于空穴注入层上的空穴传输层（HTL）、设于空穴传输层上的发光层、设于发光层上的电子传输层（ETL）、设于电子传输层上的电子注入层（EIL）及设于电子注入层上的阴极。OLED显示器件的发光原理为半导体材料和有机发光材料在电场驱动下，通过载流子注入和复合导致发光。
现有技术中，一般由时序控制器（Tcon）接收低压差分信号（LVDS）形式的数据信号并进行转换产生迷你低压差分信号（Mini-LVDS）形式的数据信号经由多对数据传输通道传输至源极驱动器中，以便于源极驱动器产生对应的驱动电压驱动显示面板进行显示。与此同时，时序控制器一般还向源极驱动器传输包括极性控制信号、输出位移信号、多个选择信号、颜色交换信号等等在内用于对源极驱动器进行设定的命令信号，时序控制器需要设置多个输出管脚以输出该些命令信号，与此同时源极驱动器也需要设置多个输入管脚来接收该些命令信号，大大增加时序控制器及源极驱动器的管脚数目，使得用于驱动显示器的驱动系统的芯片及电路设计成本大大增加。
 技术问题
本发明的目的在于提供一种显示器驱动系统，能够减少时序控制器及源极驱动器的管脚数目，降低芯片成本及电路设计成本。
本发明的另一目的在于提供一种显示器驱动方法，能够减少时序控制器及源极驱动器的管脚数目，降低芯片成本及电路设计成本。
 技术解决方案
为实现上述目的，本发明首先提供一种显示器驱动系统，包括时序控制器及源极驱动器；所述时序控制器经多组传输通道与源极驱动器电性连接；所述多组传输通道包括第一组传输通道及第二组传输通道；
所述显示器驱动系统的工作时序包括依次进行的起始阶段、命令信号传输阶段、复位阶段及显示数据传输阶段；在起始阶段，时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号；在命令信号传输阶段，时序控制器经第二组传输通道向源极驱动器传输至少一个命令信号；在复位阶段，时序控制器经第一组传输通道向源极驱动器传输复位信号；在显示数据传输阶段，时序控制器经多组传输通道向源极驱动器传输行显示数据。
每一命令信号为极性反转控制信号、输出位移控制信号、数据极性反转信号、选择信号、颜色交换信号中的一种。
在复位阶段，时序控制器经第一组传输通道向源极驱动器传输高电平的复位信号并经第二组传输通道向源极驱动器传输无效信号；
在显示数据传输阶段，时序控制器经第一组传输通道向源极驱动器依次传输时长为一预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号后向源极驱动器传输行显示数据，时序控制器经第二传输通道向源极驱动器传输时长为3倍预设周期的无效信号后向源极驱动器传输行显示数据。
所述复位阶段的时长大于等于3倍的预设周期。
所述复位阶段的时长大于等于50ns。
在起始阶段，时序控制器经第二组传输通道向源极驱动器传输高电平的起始信号并经第一组传输通道向源极驱动器传输无效信号；
在命令信号传输阶段，时序控制器经第二组传输通道向源极驱动器依次传输时长为所述预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号而后向源极驱动器依次传输多个命令信号，每一命令信号的传输时长为所述预设周期，时序控制器经第一组传输通道向源极驱动器依次传输无效信号及低电平。
所述起始阶段的时长等于复位阶段的时长。
所述时序控制器还经时钟信号走线与源极驱动器电性连接；在起始阶段、命令信号传输阶段、复位阶段及显示数据传输阶段，时序控制器经时钟信号走线向源极驱动器传输时钟信号；所述时钟信号的占空比为0.5，所述时钟信号的周期为所述预设周期。
所述源极驱动器包括接收模块，所述时序控制器经多组传输通道与源极驱动器的接收模块电性连接。
本发明还提供一种显示器驱动方法，应用于上述的显示器驱动系统，包括如下步骤：
步骤S1、进入起始阶段；
时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号；
步骤S2、进入命令信号传输阶段；
时序控制器经第二组传输通道向源极驱动器传输命令信号；
步骤S3、进入复位阶段；
时序控制器经第一组传输通道向源极驱动器传输复位信号；
步骤S4、进入显示数据传输阶段；
时序控制器经多组传输通道向源极驱动器传输行显示数据。
 有益效果
本发明的有益效果：本发明的显示器驱动系统包括时序控制器及源极驱动器，时序控制器经多组传输通道与源极驱动器电性连接。工作时，在起始阶段时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号以指示命令信号的传输开始，在命令信号传输阶段时序控制器经第二组传输通道向源极驱动器传输命令信号，在复位阶段时序控制器经第一组传输通道向源极驱动器传输复位信号以指示行显示数据的传输开始，在显示数据传输阶段时序控制器经多组传输通道向源极驱动器传输行显示数据，能够减少时序控制器及源极驱动器的管脚数目，降低芯片成本及电路设计成本。本发明的显示器驱动方法能够减少时序控制器及源极驱动器的管脚数目，降低芯片成本及电路设计成本。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的显示器驱动系统的结构示意图；
图2为本发明的显示器驱动系统的时序图；
图3为本发明的显示器驱动方法的流程图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1及图2，本发明提供一种显示器驱动系统，包括时序控制器10及源极驱动器20。所述时序控制器10经多组传输通道30与源极驱动器20电性连接。所述多组传输通道30包括第一组传输通道LV0P/N及第二组传输通道LV1P/N以及除了第一组传输通道LV0P/N及第二组传输通道LV1P/N以外的其他组传输通道30，一般多组传输通道30一般包括3至6组传输通道30。
具体地，请参阅图1，所述源极驱动器20包括接收模块21，所述时序控制器10经多组传输通道30与源极驱动器20的接收模块21电性连接。
进一步地，请参阅图1，所述源极驱动器20还包括与接收模块21电性连接的移位寄存模块22、与移位寄存器模块22电性连接的锁存模块23、与锁存模块23电性连接的数模转换模块24以及与数模转换模块24电性连接的输出缓冲模块25。
具体地，请参阅图1，所述时序控制器10还经时钟信号走线40与源极驱动器20电性连接。
请结合图2，所述显示器驱动系统的工作时序包括依次进行的起始阶段T1、命令信号传输阶段T2、复位阶段T3及显示数据传输阶段T4。
请结合图2，在起始阶段T1，时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输命令传输起始信号，以指示命令信号CMD的传输即将开始。
具体地，在图2所示的实施例中，在起始阶段T1，时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输高电平（图2中以H表示）的起始信号并经第一组传输通道LV0P/N向源极驱动器20传输无效信号（图2中以x表示）。
进一步地，在图2所示的实施例中，在起始阶段T1到来之前，时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输低电平（图中以L表示）并经第一组传输通道LV0P/N向源极驱动器20传输无效信号。
请结合图2，在命令信号传输阶段T2，时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输至少一个命令信号CMD。
具体地，每一命令信号CMD为极性反转控制信号、输出位移控制信号、数据极性反转信号、选择信号、颜色交换信号中的一种，上述信号均为现有技术中时序控制器通过对应的管脚直接传输至源极驱动器的命令信号，在此不展开描述。
具体地，在图2所示的实施例中，在命令信号传输阶段T2中，时序控制器10经第二组传输通道LV1P/N向源极驱动器20依次传输时长为一预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号而后向源极驱动器20依次传输多个命令信号CMD，每一命令信号CMD的传输时长为所述预设周期，时序控制器10经第一组传输通道LV0P/N向源极驱动器20依次传输无效信号及低电平。
请结合图2，在复位阶段T3，时序控制器10经第一组传输通道LV0P/N向源极驱动器20传输复位信号。
具体地，在图2所示的实施例中，在复位阶段T3，时序控制器10经第一组传输通道LV0P/N向源极驱动器20传输高电平的复位信号以指示行数据信号的传输即将开始，并经第二组传输通道LV1P/N向源极驱动器20传输无效信号。
具体地，所述复位阶段T3的时长大于等于3倍的预设周期，或者，所述复位阶段T3的时长大于等于50ns。
优选地，所述起始阶段T1的时长等于复位阶段T3的时长。
请结合图2，在显示数据传输阶段T4，时序控制器10经多组传输通道30向源极驱动器20传输行显示数据。
具体地，在图2所示的实施例中，在显示数据传输阶段T4，时序控制器10经第一组传输通道LV0P/N向源极驱动器10依次传输时长为所述预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号后向源极驱动器20传输行显示数据（图2中以Data表示），时序控制器10经第二传输通道LV1P/N向源极驱动器20传输时长为3倍预设周期的无效信号后向源极驱动器20传输行显示数据。
具体地，在起始阶段T1、命令信号传输阶段T2、复位阶段T3及显示数据传输阶段T4，时序控制器10经时钟信号走线40向源极驱动器20传输时钟信号CLKP。所述时钟信号CLKP的占空比为0.5，所述时钟信号CLKP的周期为所述预设周期。
具体地，在初始阶段T1、命令信号传输阶段T2、复位阶段T3，时序控制器10经多组传输通道30中除了第一组传输通道LV0P/N及第二组传输通道LV1P/N以外的其他组传输通道30向源极驱动器20传输无效信号，而在显示数据传输阶段T4，时序控制器10经多组传输通道30中除了第一组传输通道LV0P/N及第二组传输通道LV1P/N以外的其他组传输通道30向源极驱动器20传输时长为3倍预设周期的无效信号后向源极驱动器20传输行显示数据。
需要说明的是，本发明的显示器驱动系统在起始阶段T1利用时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输命令传输起始信号以指示命令信号CMD的传输开始，在命令信号传输阶段T2利用时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输命令信号CMD，在复位阶段T3利用时序控制器10经第一组传输通道LV0P/N向源极驱动器20传输复位信号以指示行显示数据的传输开始，在显示数据传输阶段T4利用时序控制器10经多组传输通道30向源极驱动器20传输行显示数据，相比于现有技术需要在时序控制器上额外设置用于输出命令信号的管脚以及在源极驱动器上额外设置仅用于接收命令信号的管脚，本发明能够减少时序控制器10及源极驱动器20的管脚数目，降低芯片成本及电路设计成本。
请参阅图3，并结合图1及图2，基于同一发明构思，本发明还提供一种显示器驱动方法，应用于上述的显示器驱动系统，在此不再对显示器驱动系统进行重复性描述。该显示器驱动方法包括如下步骤：
步骤S1、进入起始阶段T1。
时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输命令传输起始信号。
具体地，在图2所示的实施例中，在起始阶段T1，时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输高电平的起始信号并经第一组传输通道LV0P/N向源极驱动器20传输无效信号。
进一步地，在图2所示的实施例中，在起始阶段T1到来之前，时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输低电平并经第一组传输通道LV0P/N向源极驱动器20传输无效信号。
步骤S2、进入命令信号传输阶段T2。
时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输至少一个命令信号CMD。
具体地，每一命令信号CMD为极性反转控制信号、输出位移控制信号、数据极性反转信号、选择信号、颜色交换信号中的一种，上述信号均为现有技术中时序控制器通过对应的管脚直接传输至源极驱动器的命令信号，在此不展开描述。
具体地，在图2所示的实施例中，在命令信号传输阶段T2中，时序控制器10经第二组传输通道LV1P/N向源极驱动器20依次传输时长为一预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号而后向源极驱动器20依次传输多个命令信号CMD，每一命令信号CMD的传输时长为所述预设周期，时序控制器10经第一组传输通道LV0P/N向源极驱动器20依次传输无效信号及低电平。
步骤S3、进入复位阶段T3。
时序控制器10经第一组传输通道LV0P/N向源极驱动器20传输复位信号。
具体地，在图2所示的实施例中，在复位阶段T3，时序控制器10经第一组传输通道LV0P/N向源极驱动器20传输高电平的复位信号以指示行数据信号的传输即将开始，并经第二组传输通道LV1P/N向源极驱动器20传输无效信号。
具体地，所述复位阶段T3的时长大于等于3倍的预设周期，或者，所述复位阶段T3的时长大于等于50ns。
优选地，所述起始阶段T1的时长等于复位阶段T3的时长。
步骤S4、进入显示数据传输阶段T4。
时序控制器10经多组传输通道30向源极驱动器20传输行显示数据。
具体地，在图2所示的实施例中，在显示数据传输阶段T4，时序控制器10经第一组传输通道LV0P/N向源极驱动器10依次传输时长为所述预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号后向源极驱动器20传输行显示数据，时序控制器10经第二传输通道LV1P/N向源极驱动器20传输时长为3倍预设周期的无效信号后向源极驱动器20传输行显示数据。
具体地，在起始阶段T1、命令信号传输阶段T2、复位阶段T3及显示数据传输阶段T4，时序控制器10经时钟信号走线40向源极驱动器20传输时钟信号CLKP。所述时钟信号CLKP的占空比为0.5，所述时钟信号CLKP的周期为所述预设周期。
具体地，在初始阶段T1、命令信号传输阶段T2、复位阶段T3，时序控制器10经多组传输通道30中除了第一组传输通道LV0P/N及第二组传输通道LV1P/N以外的其他组传输通道30向源极驱动器20传输无效信号，而在显示数据传输阶段T4，时序控制器10经多组传输通道30中除了第一组传输通道LV0P/N及第二组传输通道LV1P/N以外的其他组传输通道30向源极驱动器20传输时长为3倍预设周期的无效信号后向源极驱动器20传输行显示数据。
需要说明的是，本发明的显示器驱动方法在起始阶段T1利用时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输命令传输起始信号以指示命令信号CMD的传输开始，在命令信号传输阶段T2利用时序控制器10经第二组传输通道LV1P/N向源极驱动器20传输命令信号CMD，在复位阶段T3利用时序控制器10经第一组传输通道LV0P/N向源极驱动器20传输复位信号以指示行显示数据的传输开始，在显示数据传输阶段T4利用时序控制器10经多组传输通道30向源极驱动器20传输行显示数据，相比于现有技术需要在时序控制器上额外设置用于输出命令信号的管脚以及在源极驱动器上额外设置仅用于接收命令信号的管脚，本发明能够减少时序控制器10及源极驱动器20的管脚数目，降低芯片成本及电路设计成本。
综上所述，本发明的显示器驱动系统包括时序控制器及源极驱动器，时序控制器经多组传输通道与源极驱动器电性连接。工作时，在起始阶段中时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号以指示命令信号的传输开始，在命令信号传输阶段中时序控制器经第二组传输通道向源极驱动器传输命令信号，在复位阶段中时序控制器经第一组传输通道向源极驱动器传输复位信号以指示行显示数据的传输开始，在显示数据传输阶段时序控制器经多组传输通道向源极驱动器传输行显示数据，能够减少时序控制器及源极驱动器的管脚数目，降低芯片成本及电路设计成本。本发明的显示器驱动方法能够减少时序控制器及源极驱动器的管脚数目，降低芯片成本及电路设计成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (18)

  1. 一种显示器驱动系统，包括时序控制器及源极驱动器；所述时序控制器经多组传输通道与源极驱动器电性连接；所述多组传输通道包括第一组传输通道及第二组传输通道；
    所述显示器驱动系统的工作时序包括依次进行的起始阶段、命令信号传输阶段、复位阶段及显示数据传输阶段；在起始阶段，时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号；在命令信号传输阶段，时序控制器经第二组传输通道向源极驱动器传输至少一个命令信号；在复位阶段，时序控制器经第一组传输通道向源极驱动器传输复位信号；在显示数据传输阶段，时序控制器经多组传输通道向源极驱动器传输行显示数据。
  2. 如权利要求1所述的显示器驱动系统，其中，每一命令信号为极性反转控制信号、输出位移控制信号、数据极性反转信号、选择信号、颜色交换信号中的一种。
  3. 如权利要求1所述的显示器驱动系统，其中，在复位阶段，时序控制器经第一组传输通道向源极驱动器传输高电平的复位信号并经第二组传输通道向源极驱动器传输无效信号；
    在显示数据传输阶段，时序控制器经第一组传输通道向源极驱动器依次传输时长为一预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号后向源极驱动器传输行显示数据，时序控制器经第二传输通道向源极驱动器传输时长为3倍预设周期的无效信号后向源极驱动器传输行显示数据。
  4. 如权利要求3所述的显示器驱动系统，其中，所述复位阶段的时长大于等于3倍的预设周期。
  5. 如权利要求3所述的显示器驱动系统，其中，所述复位阶段的时长大于等于50ns。
  6. 如权利要求3所述的显示器驱动系统，其中，在起始阶段，时序控制器经第二组传输通道向源极驱动器传输高电平的起始信号并经第一组传输通道向源极驱动器传输无效信号；
    在命令信号传输阶段，时序控制器经第二组传输通道向源极驱动器依次传输时长为所述预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号而后向源极驱动器依次传输多个命令信号，每一命令信号的传输时长为所述预设周期，时序控制器经第一组传输通道向源极驱动器依次传输无效信号及低电平。
  7. 如权利要求6所述的显示器驱动系统，其中，所述起始阶段的时长等于复位阶段的时长。
  8. 如权利要求3所述的显示器驱动系统，其中，所述时序控制器还经时钟信号走线与源极驱动器电性连接；在起始阶段、命令信号传输阶段、复位阶段及显示数据传输阶段，时序控制器经时钟信号走线向源极驱动器传输时钟信号；所述时钟信号的占空比为0.5，所述时钟信号的周期为所述预设周期。
  9. 如权利要求1所述的显示器驱动系统，其中，所述源极驱动器包括接收模块，所述时序控制器经多组传输通道与源极驱动器的接收模块电性连接。
  10. 一种显示器驱动方法，应用于显示器驱动系统，所述显示器驱动系统包括时序控制器及源极驱动器；所述时序控制器经多组传输通道与源极驱动器电性连接；所述多组传输通道包括第一组传输通道及第二组传输通道；
    所述显示器驱动系统的工作时序包括依次进行的起始阶段、命令信号传输阶段、复位阶段及显示数据传输阶段；在起始阶段，时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号；在命令信号传输阶段，时序控制器经第二组传输通道向源极驱动器传输至少一个命令信号；在复位阶段，时序控制器经第一组传输通道向源极驱动器传输复位信号；在显示数据传输阶段，时序控制器经多组传输通道向源极驱动器传输行显示数据；所述显示器驱动方法包括如下步骤：
    步骤S1、进入起始阶段；
    时序控制器经第二组传输通道向源极驱动器传输命令传输起始信号；
    步骤S2、进入命令信号传输阶段；
    时序控制器经第二组传输通道向源极驱动器传输至少一个命令信号；
    步骤S3、进入复位阶段；
    时序控制器经第一组传输通道向源极驱动器传输复位信号；
    步骤S4、进入显示数据传输阶段；
    时序控制器经多组传输通道向源极驱动器传输行显示数据。
  11. 如权利要求10所述的显示器驱动方法，其中，每一命令信号为极性反转控制信号、输出位移控制信号、数据极性反转信号、选择信号、颜色交换信号中的一种。
  12. 如权利要求10所述的显示器驱动方法，其中，在复位阶段，时序控制器经第一组传输通道向源极驱动器传输高电平的复位信号并经第二组传输通道向源极驱动器传输无效信号；
    在显示数据传输阶段，时序控制器经第一组传输通道向源极驱动器依次传输时长为一预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号后向源极驱动器传输行显示数据，时序控制器经第二传输通道向源极驱动器传输时长为3倍预设周期的无效信号后向源极驱动器传输行显示数据。
  13. 如权利要求12所述的显示器驱动方法，其中，所述复位阶段的时长大于等于3倍的预设周期。
  14. 如权利要求12所述的显示器驱动方法，其中，所述复位阶段的时长大于等于50ns。
  15. 如权利要求12所述的显示器驱动方法，其中，在起始阶段，时序控制器经第二组传输通道向源极驱动器传输高电平的起始信号并经第一组传输通道向源极驱动器传输无效信号；
    在命令信号传输阶段，时序控制器经第二组传输通道向源极驱动器依次传输时长为所述预设周期的无效信号、时长为所述预设周期的低电平、时长为所述预设周期的无效信号而后向源极驱动器依次传输多个命令信号，每一命令信号的传输时长为所述预设周期，时序控制器经第一组传输通道向源极驱动器依次传输无效信号及低电平。
  16. 如权利要求15所述的显示器驱动方法，其中，所述起始阶段的时长等于复位阶段的时长。
  17. 如权利要求12所述的显示器驱动方法，其中，所述时序控制器还经时钟信号走线与源极驱动器电性连接；在起始阶段、命令信号传输阶段、复位阶段及显示数据传输阶段，时序控制器经时钟信号走线向源极驱动器传输时钟信号；所述时钟信号的占空比为0.5，所述时钟信号的周期为所述预设周期。
  18. 如权利要求10所述的显示器驱动方法，其中，所述源极驱动器包括接收模块，所述时序控制器经多组传输通道与源极驱动器的接收模块电性连接。
PCT/CN2019/092663 2019-05-10 2019-06-25 显示器驱动系统及显示器驱动方法 Ceased WO2020228100A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910390517.9 2019-05-10
CN201910390517.9A CN110060632A (zh) 2019-05-10 2019-05-10 显示器驱动系统及显示器驱动方法

Publications (1)

Publication Number Publication Date
WO2020228100A1 true WO2020228100A1 (zh) 2020-11-19

Family

ID=67323003

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/092663 Ceased WO2020228100A1 (zh) 2019-05-10 2019-06-25 显示器驱动系统及显示器驱动方法

Country Status (2)

Country Link
CN (1) CN110060632A (zh)
WO (1) WO2020228100A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120154356A1 (en) * 2010-12-17 2012-06-21 Chin-Hung Hsu Timing Controller, Source Driving Device, Panel Driving Device, Display Device and Driving Method
CN104715706A (zh) * 2013-12-11 2015-06-17 联咏科技股份有限公司 用于显示设备的传输方法
CN107481682A (zh) * 2017-07-21 2017-12-15 惠科股份有限公司 显示面板的驱动方法及驱动装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4213637B2 (ja) * 2003-09-25 2009-01-21 株式会社日立製作所 表示装置及びその駆動方法
TW200719305A (en) * 2005-11-10 2007-05-16 Novatek Microelectronics Corp Method for transmitted control signal of flat panel display
CN101022630A (zh) * 2007-04-02 2007-08-22 上海闻泰电子科技有限公司 一种双模手机通讯的控制方法
US8421779B2 (en) * 2008-05-29 2013-04-16 Himax Technologies Limited Display and method thereof for signal transmission
CN101609440B (zh) * 2008-06-20 2011-11-16 华为技术有限公司 总线系统和总线从锁定状态中恢复的方法
KR20100077705A (ko) * 2008-12-29 2010-07-08 주식회사 동부하이텍 디스플레이 및 그의 통신 방법
TWI441129B (zh) * 2011-09-15 2014-06-11 Himax Tech Ltd 顯示器及其操作方法
TWI573121B (zh) * 2013-03-11 2017-03-01 奇景光電股份有限公司 源極驅動器
KR102368079B1 (ko) * 2015-09-25 2022-02-25 삼성디스플레이 주식회사 데이터 구동 장치 및 이를 이용한 표시 장치
CN107481674B (zh) * 2017-08-14 2020-04-28 深圳市华星光电半导体显示技术有限公司 显示设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120154356A1 (en) * 2010-12-17 2012-06-21 Chin-Hung Hsu Timing Controller, Source Driving Device, Panel Driving Device, Display Device and Driving Method
CN104715706A (zh) * 2013-12-11 2015-06-17 联咏科技股份有限公司 用于显示设备的传输方法
CN107481682A (zh) * 2017-07-21 2017-12-15 惠科股份有限公司 显示面板的驱动方法及驱动装置

Also Published As

Publication number Publication date
CN110060632A (zh) 2019-07-26

Similar Documents

Publication Publication Date Title
CN113950715B (zh) 像素电路及其驱动方法、显示装置
CN113707090B (zh) 像素驱动电路的驱动方法、显示面板和显示装置
CN1901017B (zh) 有机发光显示装置和产生驱动该装置的扫描信号的方法
US7920109B2 (en) Emission driving device of organic light emitting display device
WO2020220447A1 (zh) 显示面板驱动系统及显示面板驱动方法
US11615752B2 (en) Backlight driver, backlight device including the same, and operating method of the backlight device
CN105304021B (zh) 移位寄存器电路、栅极驱动电路及显示面板
CN110706653A (zh) 驱动电路、显示面板、驱动方法及显示装置
US10672343B2 (en) Signal control apparatus and method, display control apparatus and method, and display apparatus
US9099030B2 (en) Display device
US11749210B2 (en) Signal control apparatus and method, display control apparatus and method, and display apparatus
US12354538B2 (en) Array substrate and driving method therefor, and display apparatus
US11935464B2 (en) Multi-row buffering for active-matrix cluster displays
CN114141204B (zh) 背光驱动电路及显示装置
CN110992876B (zh) 显示装置
US11900865B2 (en) Light emitting diode (LED) driver for backlight improving accuracy of output current and increasing uniformity of brightness between LED channels
WO2023216322A1 (zh) 显示面板及显示装置
WO2023206672A1 (zh) 显示装置
WO2021082756A1 (zh) 电子基板及其驱动方法、显示装置
WO2019041617A1 (zh) 透明双面显示装置及其驱动方法
WO2020124870A1 (zh) 信号传输系统及信号传输方法
WO2026081257A1 (zh) 显示装置及其驱动方法
WO2020228100A1 (zh) 显示器驱动系统及显示器驱动方法
CN104361856B (zh) 有源矩阵有机发光二极管像素电路的驱动电路及驱动方法
TWI918012B (zh) 電子裝置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19928344

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19928344

Country of ref document: EP

Kind code of ref document: A1