WO2020224332A1 - Cloud platform connection port control device and control method - Google Patents

Cloud platform connection port control device and control method Download PDF

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Publication number
WO2020224332A1
WO2020224332A1 PCT/CN2020/079657 CN2020079657W WO2020224332A1 WO 2020224332 A1 WO2020224332 A1 WO 2020224332A1 CN 2020079657 W CN2020079657 W CN 2020079657W WO 2020224332 A1 WO2020224332 A1 WO 2020224332A1
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Prior art keywords
data
pin
diode
resistor
capacitor
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PCT/CN2020/079657
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French (fr)
Chinese (zh)
Inventor
徐磊
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南京瑞贻电子科技有限公司
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Publication of WO2020224332A1 publication Critical patent/WO2020224332A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/01—Protocols
    • H04L67/10—Protocols in which an application is distributed across nodes in the network
    • H04L67/1097—Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0428—Safety, monitoring
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/565—Conversion or adaptation of application format or content
    • H04L67/5651—Reducing the amount or size of exchanged application data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00—Network arrangements or protocols for supporting network services or applications
    • H04L67/50—Network services
    • H04L67/56—Provisioning of proxy services
    • H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
    • H04L67/5682—Policies or rules for updating, deleting or replacing the stored data

Definitions

  • the invention relates to a data parallel transmission technology, in particular to a cloud platform connection port control device.
  • Cloud platforms and multi-port control devices are new research directions that have emerged in recent years.
  • For the original control device by using the cloud platform to improve big data processing and further data sharing, more and better function extensions and functional improvements can be made to the control device.
  • Specific use cases such as satellite positioning and car navigation have all been well received by the market after they were developed.
  • connection port control devices on the market is still in progress. Due to the continuous research and development of new functions, the parallel data that needs to be transmitted is also increasing, and the update of data transmission methods and data processing methods also needs to follow Continuously improve. Especially for the parallel data transmission of multiple connection ports, it is necessary to ensure the data accuracy of the data transmitted in parallel to avoid the transmission phenomenon of data error or data error.
  • a cloud platform connection port control device is provided to solve the above problems.
  • a cloud platform connection port control device includes a port control system, an upper-level detection communication system, a transmission system and a buffer storage system,
  • the port control system is characterized by including a port control circuit, which can be specifically divided into an input current control module, an output protection module and a four-way control module.
  • a port control circuit which can be specifically divided into an input current control module, an output protection module and a four-way control module.
  • the upper-level detection communication system transmits the content of the detection communication according to the self-defined transmission password, reduces the problem of data confusion caused by the error or omission of the transmission protocol, and strengthens the accuracy of data reception;
  • the transmission system carries out the upper and lower data stream transmission of the received data respectively, and the top-down and bottom-up operation modes do not interfere with each other;
  • the buffer storage system buffers and saves the data error patterns that occur during the transmission process, and after troubleshooting the buffered data according to the protocol algorithm, the data is uploaded again, which is a transfer station in the cloud platform connection system;
  • the input current control module includes operational amplifier AR1, motor MO1, ammeter M1, diode D1, diode D2, diode D3, diode D4, diode D5, diode D11, MOS tube Q1, inductor L1, and resistor R1.
  • the diode D11 The anode of the diode D11 is connected to the voltage signal Vref, the cathode of the diode D11 is connected to the second pin of the operational amplifier AR1, and the first pin of the operational amplifier AR1 is connected to the fourth pin of the operational amplifier AR1.
  • the fifth pin of the operational amplifier AR1, the seventh pin of the operational amplifier AR1, and the eighth pin of the operational amplifier AR1 are all disconnected.
  • the sixth pin of the operational amplifier AR1 is connected to the motor MO1.
  • the other end of the motor MO1 is connected to one end of the inductor L1, the cathode of the diode D3, and the cathode of the diode D1.
  • the other end of the inductor L1 is connected to the anode of the diode D5.
  • the D pole of the MOS transistor Q1 is connected, the cathode of the diode D5 is connected to one end of the resistor R1 and the third pin of the operational amplifier AR1, and the other end of the resistor R1 is connected to the MOS
  • the S pole of the tube Q1, the anode of the diode D4, and the anode of the diode D2 are connected, the cathode of the diode D4 is connected to the anode of the diode D3 and one end of the ammeter M1, and the cathode of the diode D2 Respectively connected to the anode of the diode D1 and the other end of the ammeter M1;
  • the output protection module includes a bridge DB1, an operational amplifier AR2, a MOS transistor Q2, a diode D6, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4.
  • the bridge The second pin of RB1 is connected to one end of the resistor R3, one end of the capacitor C3, one end of the capacitor C1, and one end of the capacitor C2.
  • the fourth pin of the bridge RB1 is connected to the One end of the resistor R2 is connected, the other end of the resistor R2 is connected to the anode of the diode D6 and the S electrode of the MOS transistor Q2, and the cathode of the diode D6 is connected to the other end of the capacitor C3.
  • the S pole of the MOS transistor Q2 is grounded, the other end of the resistor R3 is connected to the G pole of the MOS transistor Q2, and the other end of the capacitor C1 is respectively connected to the other end of the capacitor C2 and one end of the resistor R4 ,
  • the other end of the resistor R4 is connected to the second pin of the operational amplifier AR2, the first pin of the operational amplifier AR2 is connected to the fourth pin of the operational amplifier AR2, and the first pin of the operational amplifier AR2
  • the five pins, the seventh pin of the operational amplifier AR2, and the eighth pin of the operational amplifier AR2 are all open circuits.
  • the sixth pin of the operational amplifier AR2 is connected to the voltage signal Vout and the resistor R5. One end is connected, the third pin of the operational amplifier AR2 is respectively connected to the other end of the resistor R5 and one end of the capacitor C4, and the other end of the capacitor C4 is grounded;
  • the four-way control module includes integrated chip U1, oscillator Y1, switch S1, transistor Q3, transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C5 , Capacitor C6, capacitor C7, capacitor C8, capacitor C9, inductor L2, inductor L3, inductor L4, diode D7, diode D8, diode D9, and diode D10.
  • the first pin of the bridge RB1 is connected to the resistor R7.
  • One end of the integrated chip U1, the sixteenth pin of the integrated chip U1, the fourth pin of the integrated chip U1, and the voltage signal Vcc are connected, and the other end of the resistor R7 is connected to the seventh pin of the integrated chip U1 ,
  • the third pin of the bridge RB1 is connected to the ninth pin of the integrated chip U1, and the tenth pin of the integrated chip U1 is connected to the eleventh pin of the integrated chip U1.
  • the twelfth pin of the chip U1, the thirteenth pin of the integrated chip U1, the fourteenth pin of the integrated chip U1, and the fifteenth pin of the integrated chip U1 are all open circuits.
  • the sixth pin of the integrated chip U1 is connected to one end of the oscillator Y1 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the resistor R8, and the other end of the resistor R8 is respectively Connected to the other end of the oscillator Y1 and one end of the switch S1, the other end of the switch S1 is connected to the first pin of the integrated chip U1, and the eighth pin of the integrated chip U1 is grounded,
  • the third pin of the integrated chip U1 is connected to one end of the inductor L4, and the other end of the inductor L4 is respectively connected to the G pole of the MOS transistor Q5 and the G pole of the MOS transistor Q6.
  • the second pin of the chip U1 is connected to one end of the resistor R9 and one end of the capacitor C9, the other end of the capacitor C9 is grounded, and the other end of the resistor R9 is connected to the voltage signal Vref.
  • the integrated chip The fifth pin of U1 is connected to one end of the inductor L2, and the other end of the inductor L2 is respectively connected to the emitter of the transistor Q3, the cathode of the diode D7, one end of the capacitor C5, and the transistor Q4.
  • the emitter of the diode D8, the cathode of the diode D8, and one end of the capacitor cabinet C6 are connected, the base of the transistor Q4 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the transistor Q3.
  • the base, the voltage signal Vin, and the G pole of the MOS transistor Q1 are connected, and the collector of the transistor Q3 is connected to the anode of the diode D7, the other end of the capacitor C5, the D pole of the MOS transistor Q5, The anode of the diode D9 and one end of the capacitor C7 are connected, and the other end of the capacitor C7 is connected to the cathode of the diode D9, the S electrode of the MOS transistor Q5, the D electrode of the MOS transistor Q6, and the The cathode of the diode D10 and one end of the capacitor C8 are connected, and the other end of the capacitor C8 is connected to the anode of the diode D10, the S pole of the MOS transistor Q6, and the capacitor The other end of C6, the anode of the diode D8, and the collector of the transistor Q4 are connected.
  • the ammeter M1 is respectively connected to the connection nodes of the two current branches, and the currents of the two branches can be directly compared.
  • the current measurement value is too large, it indicates the current of the branch If the value is out of the safe range, the input voltage needs to be adjusted.
  • the inside of the transmission system can be directly divided into a top-down data receiving branch and a bottom-up data transmission branch, and the two branches operate independently and interfere with each other.
  • a method of segmented data transmission In the process of data transmission on the cloud platform, due to the need for simultaneous and parallel transmission of data from multiple systems, when long-byte commands are transmitted, segmented transmission is required to avoid The chaos of data reorganization requires the identification of the same data command to ensure the integrity of data reception.
  • the specific steps are as follows:
  • Step 1 Judge the length of the command data, and use the safe transmission limit of each system as the standard.
  • the short byte command is directly transmitted, and then go directly to step 3; the long byte command enters the character identification step, which is the step 2;
  • Step 2 Perform length segmentation on the long byte command and perform data identification
  • Step 21 Except for the first segment, use the data space of one unit storage row less than the maximum safe transmission limit as the standard for data storage, and the remaining segments always use the data space of two unit storage rows less than the maximum safe transmission limit as the standard.
  • the transmission data is divided; the first segment retains the last blank line, and the remaining segments retain the initial blank line and the last blank line until the byte length of the remaining transmitted data is equal to or less than a maximum safe transmission limit;
  • Step 22 Identify the end data of the segmented transmission data, copy the data of the second half of the last line of the first segment as the beginning of the blank line data at the end of the first segment, complete it with zeros, and complete it. Fill in the initial blank line of the second segment, and so on, copy the second half of the last line of the second segment as the beginning of the last blank line of the second segment, complete with zeros, and Fill the completed data into the initial blank row of the third segment...until all the data are identified;
  • Step 23 Go to step 3 to transmit the segmented data
  • data matching can be performed according to the last row of data and the initial row of data of different segments.
  • the identification matching is completed , You can eliminate the same rows and directly reorganize the data.
  • a method for character judgment to cache data which temporarily caches data transmission on the cloud platform.
  • the specific steps are divided into:
  • Step 1 Determine the nature of the cached data.
  • One type is used for data segmentation because of the long command length, and the other type is for protective data storage due to unexpected interruption during system operation.
  • the former data is segmented and then transmitted.
  • Step 2 Perform protective long-term storage for the cached fragments containing judged characters to ensure that no data loss problems will occur due to system operations. After confirming the data content, the judged characters can be retained and re-stored; after confirming the data content, it is judged that it is necessary For the deleted data content, first delete the judging character, and then delete the data content to ensure sufficient cache space.
  • specific cloud platform use systems have different data processing protocols for the cache space.
  • This method can be divided into a default ISO protocol and a custom protocol to ensure that the content of cached data is more intelligently determined.
  • the present invention can solve the problem of too many connection ports in the prior art that it is difficult to unify data management, strengthen the stability and accuracy of parallel data transmission, further solve the problem of data confusion that is easily caused by parallel transmission, and increase the possibility of data transmission. Reliability.
  • Figure 1 is a system control block diagram of the present invention.
  • Figure 2 is a schematic diagram of the port control circuit of the present invention.
  • Fig. 3 is a flowchart of a data segment transmission method of the present invention.
  • a cloud platform connection port control device includes a port control system, an upper-level detection communication system, a transmission system, and a buffer storage system,
  • the port control system is characterized by including a port control circuit, which can be specifically divided into an input current control module, an output protection module and a four-way control module.
  • a port control circuit which can be specifically divided into an input current control module, an output protection module and a four-way control module.
  • the upper-level detection communication system transmits the content of the detection communication according to the self-defined transmission password, reduces the problem of data confusion caused by the error or omission of the transmission protocol, and strengthens the accuracy of data reception;
  • the transmission system carries out the upper and lower data stream transmission of the received data respectively, and the top-down and bottom-up operation modes do not interfere with each other;
  • the buffer storage system buffers and saves the data error patterns that occur during the transmission process, and after troubleshooting the buffered data according to the protocol algorithm, the data is uploaded again, which is a transfer station in the cloud platform connection system;
  • the input current control module includes operational amplifier AR1, motor MO1, ammeter M1, diode D1, diode D2, diode D3, diode D4, diode D5, diode D11, MOS tube Q1, inductor L1, and resistor R1.
  • the diode D11 The anode of the diode D11 is connected to the voltage signal Vref, the cathode of the diode D11 is connected to the second pin of the operational amplifier AR1, and the first pin of the operational amplifier AR1 is connected to the fourth pin of the operational amplifier AR1.
  • the fifth pin of the operational amplifier AR1, the seventh pin of the operational amplifier AR1, and the eighth pin of the operational amplifier AR1 are all disconnected.
  • the sixth pin of the operational amplifier AR1 is connected to the motor MO1.
  • the other end of the motor MO1 is connected to one end of the inductor L1, the cathode of the diode D3, and the cathode of the diode D1.
  • the other end of the inductor L1 is connected to the anode of the diode D5.
  • the D pole of the MOS transistor Q1 is connected, the cathode of the diode D5 is connected to one end of the resistor R1 and the third pin of the operational amplifier AR1, and the other end of the resistor R1 is connected to the MOS
  • the S pole of the tube Q1, the anode of the diode D4, and the anode of the diode D2 are connected, the cathode of the diode D4 is connected to the anode of the diode D3 and one end of the ammeter M1, and the cathode of the diode D2 Respectively connected to the anode of the diode D1 and the other end of the ammeter M1;
  • the output protection module includes a bridge DB1, an operational amplifier AR2, a MOS transistor Q2, a diode D6, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4.
  • the bridge The second pin of RB1 is connected to one end of the resistor R3, one end of the capacitor C3, one end of the capacitor C1, and one end of the capacitor C2.
  • the fourth pin of the bridge RB1 is connected to the One end of the resistor R2 is connected, the other end of the resistor R2 is connected to the anode of the diode D6 and the S electrode of the MOS transistor Q2, and the cathode of the diode D6 is connected to the other end of the capacitor C3.
  • the S pole of the MOS transistor Q2 is grounded, the other end of the resistor R3 is connected to the G pole of the MOS transistor Q2, and the other end of the capacitor C1 is respectively connected to the other end of the capacitor C2 and one end of the resistor R4 ,
  • the other end of the resistor R4 is connected to the second pin of the operational amplifier AR2, the first pin of the operational amplifier AR2 is connected to the fourth pin of the operational amplifier AR2, and the first pin of the operational amplifier AR2
  • the five pins, the seventh pin of the operational amplifier AR2, and the eighth pin of the operational amplifier AR2 are all open circuits.
  • the sixth pin of the operational amplifier AR2 is connected to the voltage signal Vout and the resistor R5. One end is connected, the third pin of the operational amplifier AR2 is respectively connected to the other end of the resistor R5 and one end of the capacitor C4, and the other end of the capacitor C4 is grounded;
  • the four-way control module includes integrated chip U1, oscillator Y1, switch S1, transistor Q3, transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C5 , Capacitor C6, capacitor C7, capacitor C8, capacitor C9, inductor L2, inductor L3, inductor L4, diode D7, diode D8, diode D9, and diode D10.
  • the first pin of the bridge RB1 is connected to the resistor R7.
  • One end of the integrated chip U1, the sixteenth pin of the integrated chip U1, the fourth pin of the integrated chip U1, and the voltage signal Vcc are connected, and the other end of the resistor R7 is connected to the seventh pin of the integrated chip U1 ,
  • the third pin of the bridge RB1 is connected to the ninth pin of the integrated chip U1, and the tenth pin of the integrated chip U1 is connected to the eleventh pin of the integrated chip U1.
  • the twelfth pin of the chip U1, the thirteenth pin of the integrated chip U1, the fourteenth pin of the integrated chip U1, and the fifteenth pin of the integrated chip U1 are all open circuits.
  • the sixth pin of the integrated chip U1 is connected to one end of the oscillator Y1 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the resistor R8, and the other end of the resistor R8 is respectively Connected to the other end of the oscillator Y1 and one end of the switch S1, the other end of the switch S1 is connected to the first pin of the integrated chip U1, and the eighth pin of the integrated chip U1 is grounded,
  • the third pin of the integrated chip U1 is connected to one end of the inductor L4, and the other end of the inductor L4 is respectively connected to the G pole of the MOS transistor Q5 and the G pole of the MOS transistor Q6.
  • the second pin of the chip U1 is connected to one end of the resistor R9 and one end of the capacitor C9, the other end of the capacitor C9 is grounded, and the other end of the resistor R9 is connected to the voltage signal Vref.
  • the integrated chip The fifth pin of U1 is connected to one end of the inductor L2, and the other end of the inductor L2 is respectively connected to the emitter of the transistor Q3, the cathode of the diode D7, one end of the capacitor C5, and the transistor Q4.
  • the emitter of the diode D8, the cathode of the diode D8, and one end of the capacitor cabinet C6 are connected, the base of the transistor Q4 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the transistor Q3.
  • the base, the voltage signal Vin, and the G pole of the MOS transistor Q1 are connected, and the collector of the transistor Q3 is connected to the anode of the diode D7, the other end of the capacitor C5, the D pole of the MOS transistor Q5, The anode of the diode D9 and one end of the capacitor C7 are connected, and the other end of the capacitor C7 is connected to the cathode of the diode D9, the S electrode of the MOS transistor Q5, the D electrode of the MOS transistor Q6, and the The cathode of the diode D10 and one end of the capacitor C8 are connected, and the other end of the capacitor C8 is connected to the anode of the diode D10, the S pole of the MOS transistor Q6, and the capacitor The other end of C6, the anode of the diode D8, and the collector of the transistor Q4 are connected.
  • the ammeter M1 is respectively connected to the connection nodes of the two current branches, and the currents of the two branches can be directly compared. When the current measurement value is too large, it indicates the current of the branch. If the value is out of the safe range, the input voltage needs to be adjusted.
  • the transistor Q3, the transistor Q4, the MOS transistor Q5, and the MOS transistor Q6 each belong to a control branch, which can process four channels of data in parallel; the diodes D7, The diode D8, the diode D9 and the diode D10 respectively control the strength of the current signal of the input branch and perform phase conversion.
  • the inside of the transmission system can be directly divided into a top-down data receiving branch and a bottom-up data transmission branch, and the two branches operate independently, with complementary interference.
  • the oscillator Y1 is connected in parallel with the branch composed of the resistor R8 and the inductor L3, and the feedback input of the oscillating current is performed through external parallel electronic components, thereby ensuring the stability of the oscillating circuit .
  • the resistor R9 and the diode D11 are connected to the voltage signal Vref, and a unified reference voltage setting is performed on the voltage reference terminal and the current detection branch of the integrated chip U1 to ensure parallel data processing During the process, there is no mismatch of current magnitude due to voltage distortion.
  • a method of segmented data transmission In the process of data transmission on the cloud platform, due to the need for simultaneous and parallel transmission of data from multiple systems, when long-byte commands are transmitted, segmented transmission is required to avoid The chaos of data reorganization requires the identification of the same data command to ensure the integrity of data reception.
  • the specific steps are as follows:
  • Step 1 Judge the length of the command data, and use the safe transmission limit of each system as the standard.
  • the short byte command is directly transmitted, and then go directly to step 3; the long byte command enters the character identification step, which is the step 2;
  • Step 2 Perform length segmentation on the long byte command and perform data identification
  • Step 21 Except for the first segment, use the data space of one unit storage row less than the maximum safe transmission limit as the standard for data storage, and the remaining segments always use the data space of two unit storage rows less than the maximum safe transmission limit as the standard.
  • the transmission data is divided; the first segment retains the last blank line, and the remaining segments retain the initial blank line and the last blank line until the byte length of the remaining transmitted data is equal to or less than a maximum safe transmission limit;
  • Step 22 Identify the end data of the segmented transmission data, copy the data of the second half of the last line of the first segment as the beginning of the blank line data at the end of the first segment, complete it with zeros, and complete it. Fill in the initial blank line of the second segment, and so on, copy the second half of the last line of the second segment as the beginning of the last blank line of the second segment, complete with zeros, and Fill the completed data into the initial blank row of the third segment...until all the data are identified;
  • Step 23 Go to step 3 to transmit the segmented data
  • data matching can be performed according to the last row of data and the initial row of data of different segments. When the data overlaps, the identification matching is completed. , You can eliminate the same rows and directly reorganize the data.
  • a method for character judgment to cache data which temporarily caches data transmission on the cloud platform.
  • the specific steps are divided into:
  • Step 1 Determine the nature of the cached data.
  • One type is used for data segmentation because of the long command length, and the other type is for protective data storage due to unexpected interruption during system operation.
  • the former data is segmented and then transmitted.
  • Step 2 Perform protective long-term storage for the cached fragments containing judged characters to ensure that no data loss problems will occur due to system operations. After confirming the data content, the judged characters can be retained and re-stored; after confirming the data content, it is judged that it is necessary For the deleted data content, first delete the judging character, and then delete the data content to ensure sufficient cache space.
  • the specific cloud platform usage system has different data processing protocols for the cache space. This method can be divided into a default ISO protocol and a custom protocol to ensure that the content of the cached data is determined more intelligently.
  • the present invention has the following advantages: by performing circuit control on multiple connection ports, the stability and feasibility of multiple parallel data transmission are enhanced, and the long command data in the parallel data transmission is further identified and segmented and buffered. The accuracy of data transmission is improved. On the whole, the present invention greatly enhances the operation speed of data transmission and the ability of data self-correction, and has a high degree of practicality.

Abstract

Disclosed is a cloud platform connection port control device and control method, the device comprising a port control system, an upper-level detection communication system, a transmission system, and a buffer storage system. The port control device performs grouping and integration for a plurality of connection ports, performs unified management by means of circuits, and increases the parallel processing speed of data upload by the ports. The upper-level detection communication system can mark and perform grouping transmission on long command data. The buffer storage system can temporarily store the data generated due to accidental interruption and segment marks during the transmission process, so that the stability and security of the entire data upload process are ensured. The present invention can perform unified port management on multi-port devices, and improves the stability of data transmission of multiple ports. The method for marking data segments and temporary buffer storage further solves the problem of data garbling due to transmission of multiple data, and strengthens the stability and accuracy of data processing.

Description

一种云平台连接端口控制装置及控制方法Cloud platform connection port control device and control method 技术领域Technical field
本发明涉及一种数据并行传输技术，尤其是一种云平台连接端口控制装置。 The invention relates to a data parallel transmission technology, in particular to a cloud platform connection port control device.
背景技术Background technique
伴随着我国科技水平的不断提高，我国人均计算机使用水平也在随之进行提高。与此同时，生活中和工业生产中使用计算机控制取代人工控制的装置也在不断出现，这现象提升了我国智能化工业生产的水平，同时也对计算机控制装置的性能有了新的要求。With the continuous improvement of my country's scientific and technological level, the per capita use of computers in my country is also improving. At the same time, devices that use computer control instead of manual control in daily life and industrial production are also constantly appearing. This phenomenon has improved the level of intelligent industrial production in my country, and at the same time has new requirements for the performance of computer control devices.
云平台和多连接端口的控制装置是近几年出现的新的研究方向。针对原有的控制装置，通过使用云平台提高大数据处理和进一步的数据分享，可以对控制装置进行更多更好的功能扩展和功能完善。具体的使用实例诸如卫星定位、车载导航，都在研发出来之后受到了市面上的广大好评。Cloud platforms and multi-port control devices are new research directions that have emerged in recent years. For the original control device, by using the cloud platform to improve big data processing and further data sharing, more and better function extensions and functional improvements can be made to the control device. Specific use cases such as satellite positioning and car navigation have all been well received by the market after they were developed.
目前市面上针对云平台连接端口控制装置的研究还在不断进行中，由于新型功能的不断研发，需要传送的并行数据也在不断增加，对数据传输方式和数据处理方式的更新也就需要随着不断进行提升。特别是针对多路连接端口的并行数据传输，需要对并行传递的数据进行数据准确度的保证，避免出现数据错漏、数据错行的传递现象。At present, the research on cloud platform connection port control devices on the market is still in progress. Due to the continuous research and development of new functions, the parallel data that needs to be transmitted is also increasing, and the update of data transmission methods and data processing methods also needs to follow Continuously improve. Especially for the parallel data transmission of multiple connection ports, it is necessary to ensure the data accuracy of the data transmitted in parallel to avoid the transmission phenomenon of data error or data error.
技术问题technical problem
提供一种云平台连接端口控制装置，以解决上述问题。A cloud platform connection port control device is provided to solve the above problems.
技术解决方案Technical solutions
一种云平台连接端口控制装置，包括端口控制系统、上层检测通讯系统、传输系统和缓冲存储系统， A cloud platform connection port control device includes a port control system, an upper-level detection communication system, a transmission system and a buffer storage system,
端口控制系统，其特征在于，包括一种端口控制电路，具体可以分为输入电流控制模块、输出保护模块和四路控制模块，通过对端口数据进行分组，实现多系统数据的同步处理支路，提高数据处理的运行能力和运行速度；The port control system is characterized by including a port control circuit, which can be specifically divided into an input current control module, an output protection module and a four-way control module. By grouping the port data, the synchronization processing branch of multi-system data is realized. Improve the operational capacity and speed of data processing;
上层检测通讯系统，根据自定义的传输口令，对检测通讯的内容进行传输，减少因为传输协议错漏造成的数据错乱问题，加强数据接收的准确性；The upper-level detection communication system transmits the content of the detection communication according to the self-defined transmission password, reduces the problem of data confusion caused by the error or omission of the transmission protocol, and strengthens the accuracy of data reception;
传输系统，对接受到的数据进行分别进行上下层的数据流传输，自上而下和自下而上的两种运行模式互不干扰；The transmission system carries out the upper and lower data stream transmission of the received data respectively, and the top-down and bottom-up operation modes do not interfere with each other;
缓冲存储系统，对传输过程中出现的数据错误模式进行数据缓冲保存，根据协议算法对缓冲的数据进行排错处理之后，完成数据的再次上传，是云平台连接系统中的中转站；The buffer storage system buffers and saves the data error patterns that occur during the transmission process, and after troubleshooting the buffered data according to the protocol algorithm, the data is uploaded again, which is a transfer station in the cloud platform connection system;
所述输入电流控制模块，包括运算放大器AR1、电机MO1、电流表M1、二极管D1、二极管D2、二极管D3、二极管D4、二极管D5、二极管D11、MOS管Q1、电感L1和电阻R1，所述二极管D11的正极与电压信号Vref连接，所述二极管D11的负极与所述运算放大器AR1的第二引脚连接，所述运算放大器AR1的第一引脚与所述运算放大器AR1的第四引脚、所述运算放大器AR1的第五引脚、所述运算放大器AR1的第七引脚、所述运算放大器AR1的第八引脚均为断路，所述运算放大器AR1的第六引脚与所述电机MO1的一端连接，所述电机MO1的另一端分别与所述电感L1的一端、所述二极管D3的负极、所述二极管D1的负极连接，所述电感L1的另一端分别与所述二极管D5的正极、所述MOS管Q1的D极连接，所述二极管D5的负极分别与所述电阻R1的一端、所述运算放大器AR1的第三引脚连接，所述电阻R1的另一端分别与所述MOS管Q1的S极、所述二极管D4的正极、所述二极管D2的正极连接，所述二极管D4的负极分别与所述二极管D3的正极、所述电流表M1的一端连接，所述二极管D2的负极分别与所述二极管D1的正极、所述电流表M1的另一端连接；The input current control module includes operational amplifier AR1, motor MO1, ammeter M1, diode D1, diode D2, diode D3, diode D4, diode D5, diode D11, MOS tube Q1, inductor L1, and resistor R1. The diode D11 The anode of the diode D11 is connected to the voltage signal Vref, the cathode of the diode D11 is connected to the second pin of the operational amplifier AR1, and the first pin of the operational amplifier AR1 is connected to the fourth pin of the operational amplifier AR1. The fifth pin of the operational amplifier AR1, the seventh pin of the operational amplifier AR1, and the eighth pin of the operational amplifier AR1 are all disconnected. The sixth pin of the operational amplifier AR1 is connected to the motor MO1. The other end of the motor MO1 is connected to one end of the inductor L1, the cathode of the diode D3, and the cathode of the diode D1. The other end of the inductor L1 is connected to the anode of the diode D5. The D pole of the MOS transistor Q1 is connected, the cathode of the diode D5 is connected to one end of the resistor R1 and the third pin of the operational amplifier AR1, and the other end of the resistor R1 is connected to the MOS The S pole of the tube Q1, the anode of the diode D4, and the anode of the diode D2 are connected, the cathode of the diode D4 is connected to the anode of the diode D3 and one end of the ammeter M1, and the cathode of the diode D2 Respectively connected to the anode of the diode D1 and the other end of the ammeter M1;
所述输出保护模块，包括电桥DB1、运算放大器AR2、MOS管Q2、二极管D6、电阻R2、电阻R3、电阻R4、电阻R5、电容C1、电容C2、电容C3和电容C4，所述电桥RB1的第二引脚分别与所述电阻R3的一端、所述电容C3的一端、所述电容C1的一端、所述电容C2的一端连接，所述电桥RB1的第四引脚与所述电阻R2的一端连接，所述电阻R2的另一端分别与所述二极管D6的正极、所述MOS管Q2的S极连接，所述二极管D6的负极与所述电容C3的另一端连接，所述MOS管Q2的S极接地，所述电阻R3的另一端与所述MOS管Q2的G极连接，所述电容C1的另一端分别与所述电容C2的另一端、所述电阻R4的一端连接，所述电阻R4的另一端与所述运算放大器AR2的第二引脚连接，所述运算放大器AR2的第一引脚与所述运算放大器AR2的第四引脚、所述运算放大器AR2的第五引脚、所述运算放大器AR2的第七引脚、所述运算放大器AR2的第八引脚均为断路，所述运算放大器AR2的第六引脚分别与电压信号Vout、所述电阻R5的一端连接，所述运算放大器AR2的第三引脚分别与所述电阻R5的另一端、所述电容C4的一端连接，所述电容C4的另一端接地；The output protection module includes a bridge DB1, an operational amplifier AR2, a MOS transistor Q2, a diode D6, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4. The bridge The second pin of RB1 is connected to one end of the resistor R3, one end of the capacitor C3, one end of the capacitor C1, and one end of the capacitor C2. The fourth pin of the bridge RB1 is connected to the One end of the resistor R2 is connected, the other end of the resistor R2 is connected to the anode of the diode D6 and the S electrode of the MOS transistor Q2, and the cathode of the diode D6 is connected to the other end of the capacitor C3. The S pole of the MOS transistor Q2 is grounded, the other end of the resistor R3 is connected to the G pole of the MOS transistor Q2, and the other end of the capacitor C1 is respectively connected to the other end of the capacitor C2 and one end of the resistor R4 , The other end of the resistor R4 is connected to the second pin of the operational amplifier AR2, the first pin of the operational amplifier AR2 is connected to the fourth pin of the operational amplifier AR2, and the first pin of the operational amplifier AR2 The five pins, the seventh pin of the operational amplifier AR2, and the eighth pin of the operational amplifier AR2 are all open circuits. The sixth pin of the operational amplifier AR2 is connected to the voltage signal Vout and the resistor R5. One end is connected, the third pin of the operational amplifier AR2 is respectively connected to the other end of the resistor R5 and one end of the capacitor C4, and the other end of the capacitor C4 is grounded;
所述四路控制模块，包括集成芯片U1、振荡器Y1、开关S1、三极管Q3、三极管Q4、MOS管Q5、MOS管Q6、电阻R6、电阻R7、电阻R8、电阻R9、电阻R10、电容C5、电容C6、电容C7、电容C8、电容C9、电感L2、电感L3、电感L4、二极管D7、二极管D8、二极管D9和二极管D10，所述电桥RB1的第一引脚分别与所述电阻R7的一端、所述集成芯片U1的第十六引脚、所述集成芯片U1的第四引脚、电压信号Vcc连接，所述电阻R7的另一端与所述集成芯片U1的第七引脚连接，所述电桥RB1的第三引脚与所述集成芯片U1的第九引脚连接，所述集成芯片U1的第十引脚与所述集成芯片U1的第十一引脚、所述集成芯片U1的第十二引脚、所述集成芯片U1的第十三引脚、所述集成芯片U1的第十四引脚、所述集成芯片U1的第十五引脚均为断路，所述集成芯片U1的第六引脚分别与所述振荡器Y1的一端、所述电感L3的一端连接，所述电感L3的另一端与所述电阻R8的一端连接，所述电阻R8的另一端分别与所述振荡器Y1的另一端、所述开关S1的一端连接，所述开关S1的另一端与所述集成芯片U1的第一引脚连接，所述集成芯片U1的第八引脚接地，所述集成芯片U1的第三引脚与所述电感L4的一端连接，所述电感L4的另一端分别与所述MOS管Q5的G极、所述MOS管Q6的G极连接，所述集成芯片U1的第二引脚分别与所述电阻R9的一端、所述电容C9的一端连接，所述电容C9的另一端接地，所述电阻R9的另一端与电压信号Vref连接，所述集成芯片U1的第五引脚与所述电感L2的一端连接，所述电感L2的另一端分别与所述三极管Q3的发射极、所述二极管D7的负极、所述电容C5的一端、所述三极管Q4的发射极、所述二极管D8的负极、所述电容柜C6的一端连接，所述三极管Q4的基极与所述电阻R6的一端连接，所述电阻R6的另一端分别与所述三极管Q3的基极、电压信号Vin、所述MOS管Q1的G极连接，所述三极管Q3的集电极分别与所述二极管D7的正极、所述电容C5的另一端、所述MOS管Q5的D极、所述二极管D9的正极、所述电容C7的一端连接，所述电容C7的另一端分别与所述二极管D9的负极、所述MOS管Q5的S极、所述MOS管Q6的D极、所述二极管D10的负极、所述电容C8的一端连接，所述电容C8的另一端分别与所述二极管D10的正极、所述MOS管Q6的S极、所述电容C6的另一端、所述二极管D8的正极、所述三极管Q4的集电极连接。The four-way control module includes integrated chip U1, oscillator Y1, switch S1, transistor Q3, transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C5 , Capacitor C6, capacitor C7, capacitor C8, capacitor C9, inductor L2, inductor L3, inductor L4, diode D7, diode D8, diode D9, and diode D10. The first pin of the bridge RB1 is connected to the resistor R7. One end of the integrated chip U1, the sixteenth pin of the integrated chip U1, the fourth pin of the integrated chip U1, and the voltage signal Vcc are connected, and the other end of the resistor R7 is connected to the seventh pin of the integrated chip U1 , The third pin of the bridge RB1 is connected to the ninth pin of the integrated chip U1, and the tenth pin of the integrated chip U1 is connected to the eleventh pin of the integrated chip U1. The twelfth pin of the chip U1, the thirteenth pin of the integrated chip U1, the fourteenth pin of the integrated chip U1, and the fifteenth pin of the integrated chip U1 are all open circuits. The sixth pin of the integrated chip U1 is connected to one end of the oscillator Y1 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the resistor R8, and the other end of the resistor R8 is respectively Connected to the other end of the oscillator Y1 and one end of the switch S1, the other end of the switch S1 is connected to the first pin of the integrated chip U1, and the eighth pin of the integrated chip U1 is grounded, The third pin of the integrated chip U1 is connected to one end of the inductor L4, and the other end of the inductor L4 is respectively connected to the G pole of the MOS transistor Q5 and the G pole of the MOS transistor Q6. The second pin of the chip U1 is connected to one end of the resistor R9 and one end of the capacitor C9, the other end of the capacitor C9 is grounded, and the other end of the resistor R9 is connected to the voltage signal Vref. The integrated chip The fifth pin of U1 is connected to one end of the inductor L2, and the other end of the inductor L2 is respectively connected to the emitter of the transistor Q3, the cathode of the diode D7, one end of the capacitor C5, and the transistor Q4. The emitter of the diode D8, the cathode of the diode D8, and one end of the capacitor cabinet C6 are connected, the base of the transistor Q4 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the transistor Q3. The base, the voltage signal Vin, and the G pole of the MOS transistor Q1 are connected, and the collector of the transistor Q3 is connected to the anode of the diode D7, the other end of the capacitor C5, the D pole of the MOS transistor Q5, The anode of the diode D9 and one end of the capacitor C7 are connected, and the other end of the capacitor C7 is connected to the cathode of the diode D9, the S electrode of the MOS transistor Q5, the D electrode of the MOS transistor Q6, and the The cathode of the diode D10 and one end of the capacitor C8 are connected, and the other end of the capacitor C8 is connected to the anode of the diode D10, the S pole of the MOS transistor Q6, and the capacitor The other end of C6, the anode of the diode D8, and the collector of the transistor Q4 are connected.
根据本发明的一个方面，所述电流表M1分别与两路电流支路的连接节点进行连接，可以直接对两路支路进行电流比较，当出现电流测量值过大的情况时，表示支路电流值超出安全范围，需要对输入电压进行调整。According to one aspect of the present invention, the ammeter M1 is respectively connected to the connection nodes of the two current branches, and the currents of the two branches can be directly compared. When the current measurement value is too large, it indicates the current of the branch If the value is out of the safe range, the input voltage needs to be adjusted.
根据本发明的一个方面，所述传输系统内部直接可以分成自上而下的数据接收支路和自下而上的数据传送支路，两个支路独立运行，互补干扰。According to one aspect of the present invention, the inside of the transmission system can be directly divided into a top-down data receiving branch and a bottom-up data transmission branch, and the two branches operate independently and interfere with each other.
一种数据分段传输方法，在云平台数据传输的过程当中，由于需要对多种系统的数据进行同时并行传输，在长字节的命令进行传输的时候，需要进行分段传输，为了避免出现数据重组的混乱，需要对同一数据命令进行标识，保证数据接收的完整性，具体步骤为：A method of segmented data transmission. In the process of data transmission on the cloud platform, due to the need for simultaneous and parallel transmission of data from multiple systems, when long-byte commands are transmitted, segmented transmission is required to avoid The chaos of data reorganization requires the identification of the same data command to ensure the integrity of data reception. The specific steps are as follows:
步骤1、对命令数据的长度进行判断，以各系统的安全传输界限为标准，短字节的命令进行直接传输，直接进入步骤3；长字节的命令进入到字符标识步骤中，也就是步骤2；Step 1. Judge the length of the command data, and use the safe transmission limit of each system as the standard. The short byte command is directly transmitted, and then go directly to step 3; the long byte command enters the character identification step, which is the step 2;
步骤2、对长字节的命令进行长度分段并进行数据标识；Step 2. Perform length segmentation on the long byte command and perform data identification;
步骤21、除了第一分段，以比最大安全传输界限少一个单元存储行的数据空间作为标准进行数据存储，其余分段始终以比最大安全传输界限少两个单元存储行的数据空间作为标准，进行传送数据划分；第一分段保留末位空白行，其余分段均保留初始空白行和末位空白行两行，直到剩余传送数据的字节长度刚好等于或者小于一个最大安全传输界限；Step 21. Except for the first segment, use the data space of one unit storage row less than the maximum safe transmission limit as the standard for data storage, and the remaining segments always use the data space of two unit storage rows less than the maximum safe transmission limit as the standard. , The transmission data is divided; the first segment retains the last blank line, and the remaining segments retain the initial blank line and the last blank line until the byte length of the remaining transmitted data is equal to or less than a maximum safe transmission limit;
步骤22、对于分段的传送数据的结尾数据进行标识，复制第一分段的最后一行后半段的数据作为第一分段末位空白行数据的开头，以零补充完整，并将补充完整的数据填充到第二分段的初始空白行中，以此类推，复制第二分段的最后一行的后半段数据作为第二分段末位空白行数据的开头，以零补充完整，并将补充完整的数据填充到第三分段的初始空白行中···直到数据全都标识完成；Step 22: Identify the end data of the segmented transmission data, copy the data of the second half of the last line of the first segment as the beginning of the blank line data at the end of the first segment, complete it with zeros, and complete it. Fill in the initial blank line of the second segment, and so on, copy the second half of the last line of the second segment as the beginning of the last blank line of the second segment, complete with zeros, and Fill the completed data into the initial blank row of the third segment...until all the data are identified;
步骤23、进入到步骤3中，对分段数据进行传输；Step 23: Go to step 3 to transmit the segmented data;
步骤3、传送数据。Step 3. Transfer data.
根据本发明的一个方面，对数据进行分段标识之后，在重新进行数据整合的时候，可以根据不同分段的数据末位行和数据初始行进行数据匹配，当数据重合时，进行标识匹配完成，可以进行消除相同行，直接进行数据重组。According to one aspect of the present invention, after the data is segmented and identified, when re-integrating the data, data matching can be performed according to the last row of data and the initial row of data of different segments. When the data overlaps, the identification matching is completed , You can eliminate the same rows and directly reorganize the data.
一种字符判定缓存数据的方法，对云平台的数据传输进行暂时数据缓存，具体步骤分成：A method for character judgment to cache data, which temporarily caches data transmission on the cloud platform. The specific steps are divided into:
步骤1、对缓存数据进行性质判定，因为命令长度较长进行数据分段的为一种，另一种为系统运行中因为意外中断进行的保护性数据存储，前者数据进行分段后传输，后者进行判定字符的增加；Step 1. Determine the nature of the cached data. One type is used for data segmentation because of the long command length, and the other type is for protective data storage due to unexpected interruption during system operation. The former data is segmented and then transmitted. The person to determine the increase of characters;
步骤2、对含有判定字符的缓存片段，进行保护性长时间存储，保证不因为系统操作产生数据丢失问题，确认数据内容之后可以对判定字符进行保留后重新存贮；确认数据内容后判定是需要删除的数据内容，先进行判定字符的删除后，再进行数据内容的删除，保证缓存空间的充足。Step 2. Perform protective long-term storage for the cached fragments containing judged characters to ensure that no data loss problems will occur due to system operations. After confirming the data content, the judged characters can be retained and re-stored; after confirming the data content, it is judged that it is necessary For the deleted data content, first delete the judging character, and then delete the data content to ensure sufficient cache space.
根据本发明的一个方面，具体的云平台使用系统对缓存空间的数据处理协议不同，本方法中可以分成默认的ISO协议和自定义协议，保证缓存数据的内容判定更加智能化。According to one aspect of the present invention, specific cloud platform use systems have different data processing protocols for the cache space. This method can be divided into a default ISO protocol and a custom protocol to ensure that the content of cached data is more intelligently determined.
有益效果Beneficial effect
本发明能够解决现有的技术中连接端口过多难以统一数据管理的问题，加强了并行数据传递的稳定性和准确性，进一步解决了并行传递容易造成的数据错乱问题，增加了数据传输的可信度。The present invention can solve the problem of too many connection ports in the prior art that it is difficult to unify data management, strengthen the stability and accuracy of parallel data transmission, further solve the problem of data confusion that is easily caused by parallel transmission, and increase the possibility of data transmission. Reliability.
附图说明Description of the drawings
图1是本发明的系统控制框图。Figure 1 is a system control block diagram of the present invention.
图2是本发明的端口控制电路的原理图。Figure 2 is a schematic diagram of the port control circuit of the present invention.
图3是本发明的一种数据分段传输方法的流程框图。Fig. 3 is a flowchart of a data segment transmission method of the present invention.
本发明的实施方式Embodiments of the invention
如图1所示，在该实施例中，一种云平台连接端口控制装置，包括端口控制系统、上层检测通讯系统、传输系统和缓冲存储系统，As shown in Figure 1, in this embodiment, a cloud platform connection port control device includes a port control system, an upper-level detection communication system, a transmission system, and a buffer storage system,
端口控制系统，其特征在于，包括一种端口控制电路，具体可以分为输入电流控制模块、输出保护模块和四路控制模块，通过对端口数据进行分组，实现多系统数据的同步处理支路，提高数据处理的运行能力和运行速度；The port control system is characterized by including a port control circuit, which can be specifically divided into an input current control module, an output protection module and a four-way control module. By grouping the port data, the synchronization processing branch of multi-system data is realized. Improve the operational capacity and speed of data processing;
上层检测通讯系统，根据自定义的传输口令，对检测通讯的内容进行传输，减少因为传输协议错漏造成的数据错乱问题，加强数据接收的准确性；The upper-level detection communication system transmits the content of the detection communication according to the self-defined transmission password, reduces the problem of data confusion caused by the error or omission of the transmission protocol, and strengthens the accuracy of data reception;
传输系统，对接受到的数据进行分别进行上下层的数据流传输，自上而下和自下而上的两种运行模式互不干扰；The transmission system carries out the upper and lower data stream transmission of the received data respectively, and the top-down and bottom-up operation modes do not interfere with each other;
缓冲存储系统，对传输过程中出现的数据错误模式进行数据缓冲保存，根据协议算法对缓冲的数据进行排错处理之后，完成数据的再次上传，是云平台连接系统中的中转站；The buffer storage system buffers and saves the data error patterns that occur during the transmission process, and after troubleshooting the buffered data according to the protocol algorithm, the data is uploaded again, which is a transfer station in the cloud platform connection system;
所述输入电流控制模块，包括运算放大器AR1、电机MO1、电流表M1、二极管D1、二极管D2、二极管D3、二极管D4、二极管D5、二极管D11、MOS管Q1、电感L1和电阻R1，所述二极管D11的正极与电压信号Vref连接，所述二极管D11的负极与所述运算放大器AR1的第二引脚连接，所述运算放大器AR1的第一引脚与所述运算放大器AR1的第四引脚、所述运算放大器AR1的第五引脚、所述运算放大器AR1的第七引脚、所述运算放大器AR1的第八引脚均为断路，所述运算放大器AR1的第六引脚与所述电机MO1的一端连接，所述电机MO1的另一端分别与所述电感L1的一端、所述二极管D3的负极、所述二极管D1的负极连接，所述电感L1的另一端分别与所述二极管D5的正极、所述MOS管Q1的D极连接，所述二极管D5的负极分别与所述电阻R1的一端、所述运算放大器AR1的第三引脚连接，所述电阻R1的另一端分别与所述MOS管Q1的S极、所述二极管D4的正极、所述二极管D2的正极连接，所述二极管D4的负极分别与所述二极管D3的正极、所述电流表M1的一端连接，所述二极管D2的负极分别与所述二极管D1的正极、所述电流表M1的另一端连接；The input current control module includes operational amplifier AR1, motor MO1, ammeter M1, diode D1, diode D2, diode D3, diode D4, diode D5, diode D11, MOS tube Q1, inductor L1, and resistor R1. The diode D11 The anode of the diode D11 is connected to the voltage signal Vref, the cathode of the diode D11 is connected to the second pin of the operational amplifier AR1, and the first pin of the operational amplifier AR1 is connected to the fourth pin of the operational amplifier AR1. The fifth pin of the operational amplifier AR1, the seventh pin of the operational amplifier AR1, and the eighth pin of the operational amplifier AR1 are all disconnected. The sixth pin of the operational amplifier AR1 is connected to the motor MO1. The other end of the motor MO1 is connected to one end of the inductor L1, the cathode of the diode D3, and the cathode of the diode D1. The other end of the inductor L1 is connected to the anode of the diode D5. The D pole of the MOS transistor Q1 is connected, the cathode of the diode D5 is connected to one end of the resistor R1 and the third pin of the operational amplifier AR1, and the other end of the resistor R1 is connected to the MOS The S pole of the tube Q1, the anode of the diode D4, and the anode of the diode D2 are connected, the cathode of the diode D4 is connected to the anode of the diode D3 and one end of the ammeter M1, and the cathode of the diode D2 Respectively connected to the anode of the diode D1 and the other end of the ammeter M1;
所述输出保护模块，包括电桥DB1、运算放大器AR2、MOS管Q2、二极管D6、电阻R2、电阻R3、电阻R4、电阻R5、电容C1、电容C2、电容C3和电容C4，所述电桥RB1的第二引脚分别与所述电阻R3的一端、所述电容C3的一端、所述电容C1的一端、所述电容C2的一端连接，所述电桥RB1的第四引脚与所述电阻R2的一端连接，所述电阻R2的另一端分别与所述二极管D6的正极、所述MOS管Q2的S极连接，所述二极管D6的负极与所述电容C3的另一端连接，所述MOS管Q2的S极接地，所述电阻R3的另一端与所述MOS管Q2的G极连接，所述电容C1的另一端分别与所述电容C2的另一端、所述电阻R4的一端连接，所述电阻R4的另一端与所述运算放大器AR2的第二引脚连接，所述运算放大器AR2的第一引脚与所述运算放大器AR2的第四引脚、所述运算放大器AR2的第五引脚、所述运算放大器AR2的第七引脚、所述运算放大器AR2的第八引脚均为断路，所述运算放大器AR2的第六引脚分别与电压信号Vout、所述电阻R5的一端连接，所述运算放大器AR2的第三引脚分别与所述电阻R5的另一端、所述电容C4的一端连接，所述电容C4的另一端接地；The output protection module includes a bridge DB1, an operational amplifier AR2, a MOS transistor Q2, a diode D6, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4. The bridge The second pin of RB1 is connected to one end of the resistor R3, one end of the capacitor C3, one end of the capacitor C1, and one end of the capacitor C2. The fourth pin of the bridge RB1 is connected to the One end of the resistor R2 is connected, the other end of the resistor R2 is connected to the anode of the diode D6 and the S electrode of the MOS transistor Q2, and the cathode of the diode D6 is connected to the other end of the capacitor C3. The S pole of the MOS transistor Q2 is grounded, the other end of the resistor R3 is connected to the G pole of the MOS transistor Q2, and the other end of the capacitor C1 is respectively connected to the other end of the capacitor C2 and one end of the resistor R4 , The other end of the resistor R4 is connected to the second pin of the operational amplifier AR2, the first pin of the operational amplifier AR2 is connected to the fourth pin of the operational amplifier AR2, and the first pin of the operational amplifier AR2 The five pins, the seventh pin of the operational amplifier AR2, and the eighth pin of the operational amplifier AR2 are all open circuits. The sixth pin of the operational amplifier AR2 is connected to the voltage signal Vout and the resistor R5. One end is connected, the third pin of the operational amplifier AR2 is respectively connected to the other end of the resistor R5 and one end of the capacitor C4, and the other end of the capacitor C4 is grounded;
所述四路控制模块，包括集成芯片U1、振荡器Y1、开关S1、三极管Q3、三极管Q4、MOS管Q5、MOS管Q6、电阻R6、电阻R7、电阻R8、电阻R9、电阻R10、电容C5、电容C6、电容C7、电容C8、电容C9、电感L2、电感L3、电感L4、二极管D7、二极管D8、二极管D9和二极管D10，所述电桥RB1的第一引脚分别与所述电阻R7的一端、所述集成芯片U1的第十六引脚、所述集成芯片U1的第四引脚、电压信号Vcc连接，所述电阻R7的另一端与所述集成芯片U1的第七引脚连接，所述电桥RB1的第三引脚与所述集成芯片U1的第九引脚连接，所述集成芯片U1的第十引脚与所述集成芯片U1的第十一引脚、所述集成芯片U1的第十二引脚、所述集成芯片U1的第十三引脚、所述集成芯片U1的第十四引脚、所述集成芯片U1的第十五引脚均为断路，所述集成芯片U1的第六引脚分别与所述振荡器Y1的一端、所述电感L3的一端连接，所述电感L3的另一端与所述电阻R8的一端连接，所述电阻R8的另一端分别与所述振荡器Y1的另一端、所述开关S1的一端连接，所述开关S1的另一端与所述集成芯片U1的第一引脚连接，所述集成芯片U1的第八引脚接地，所述集成芯片U1的第三引脚与所述电感L4的一端连接，所述电感L4的另一端分别与所述MOS管Q5的G极、所述MOS管Q6的G极连接，所述集成芯片U1的第二引脚分别与所述电阻R9的一端、所述电容C9的一端连接，所述电容C9的另一端接地，所述电阻R9的另一端与电压信号Vref连接，所述集成芯片U1的第五引脚与所述电感L2的一端连接，所述电感L2的另一端分别与所述三极管Q3的发射极、所述二极管D7的负极、所述电容C5的一端、所述三极管Q4的发射极、所述二极管D8的负极、所述电容柜C6的一端连接，所述三极管Q4的基极与所述电阻R6的一端连接，所述电阻R6的另一端分别与所述三极管Q3的基极、电压信号Vin、所述MOS管Q1的G极连接，所述三极管Q3的集电极分别与所述二极管D7的正极、所述电容C5的另一端、所述MOS管Q5的D极、所述二极管D9的正极、所述电容C7的一端连接，所述电容C7的另一端分别与所述二极管D9的负极、所述MOS管Q5的S极、所述MOS管Q6的D极、所述二极管D10的负极、所述电容C8的一端连接，所述电容C8的另一端分别与所述二极管D10的正极、所述MOS管Q6的S极、所述电容C6的另一端、所述二极管D8的正极、所述三极管Q4的集电极连接。The four-way control module includes integrated chip U1, oscillator Y1, switch S1, transistor Q3, transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C5 , Capacitor C6, capacitor C7, capacitor C8, capacitor C9, inductor L2, inductor L3, inductor L4, diode D7, diode D8, diode D9, and diode D10. The first pin of the bridge RB1 is connected to the resistor R7. One end of the integrated chip U1, the sixteenth pin of the integrated chip U1, the fourth pin of the integrated chip U1, and the voltage signal Vcc are connected, and the other end of the resistor R7 is connected to the seventh pin of the integrated chip U1 , The third pin of the bridge RB1 is connected to the ninth pin of the integrated chip U1, and the tenth pin of the integrated chip U1 is connected to the eleventh pin of the integrated chip U1. The twelfth pin of the chip U1, the thirteenth pin of the integrated chip U1, the fourteenth pin of the integrated chip U1, and the fifteenth pin of the integrated chip U1 are all open circuits. The sixth pin of the integrated chip U1 is connected to one end of the oscillator Y1 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the resistor R8, and the other end of the resistor R8 is respectively Connected to the other end of the oscillator Y1 and one end of the switch S1, the other end of the switch S1 is connected to the first pin of the integrated chip U1, and the eighth pin of the integrated chip U1 is grounded, The third pin of the integrated chip U1 is connected to one end of the inductor L4, and the other end of the inductor L4 is respectively connected to the G pole of the MOS transistor Q5 and the G pole of the MOS transistor Q6. The second pin of the chip U1 is connected to one end of the resistor R9 and one end of the capacitor C9, the other end of the capacitor C9 is grounded, and the other end of the resistor R9 is connected to the voltage signal Vref. The integrated chip The fifth pin of U1 is connected to one end of the inductor L2, and the other end of the inductor L2 is respectively connected to the emitter of the transistor Q3, the cathode of the diode D7, one end of the capacitor C5, and the transistor Q4. The emitter of the diode D8, the cathode of the diode D8, and one end of the capacitor cabinet C6 are connected, the base of the transistor Q4 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the transistor Q3. The base, the voltage signal Vin, and the G pole of the MOS transistor Q1 are connected, and the collector of the transistor Q3 is connected to the anode of the diode D7, the other end of the capacitor C5, the D pole of the MOS transistor Q5, The anode of the diode D9 and one end of the capacitor C7 are connected, and the other end of the capacitor C7 is connected to the cathode of the diode D9, the S electrode of the MOS transistor Q5, the D electrode of the MOS transistor Q6, and the The cathode of the diode D10 and one end of the capacitor C8 are connected, and the other end of the capacitor C8 is connected to the anode of the diode D10, the S pole of the MOS transistor Q6, and the capacitor The other end of C6, the anode of the diode D8, and the collector of the transistor Q4 are connected.
在进一步的实施例中，所述电流表M1分别与两路电流支路的连接节点进行连接，可以直接对两路支路进行电流比较，当出现电流测量值过大的情况时，表示支路电流值超出安全范围，需要对输入电压进行调整。In a further embodiment, the ammeter M1 is respectively connected to the connection nodes of the two current branches, and the currents of the two branches can be directly compared. When the current measurement value is too large, it indicates the current of the branch. If the value is out of the safe range, the input voltage needs to be adjusted.
在更进一步的实施例中，所述三极管Q3与所述三极管Q4、所述MOS管Q5、所述MOS管Q6分别属于一个控制支路，可以对四路数据进行并行处理；所述二极管D7、二极管D8、二极管D9和二极管D10分别控制输入支路的电流信号的强弱，进行相位的转换。In a further embodiment, the transistor Q3, the transistor Q4, the MOS transistor Q5, and the MOS transistor Q6 each belong to a control branch, which can process four channels of data in parallel; the diodes D7, The diode D8, the diode D9 and the diode D10 respectively control the strength of the current signal of the input branch and perform phase conversion.
在进一步的实施例中，所述传输系统内部直接可以分成自上而下的数据接收支路和自下而上的数据传送支路，两个支路独立运行，互补干扰。In a further embodiment, the inside of the transmission system can be directly divided into a top-down data receiving branch and a bottom-up data transmission branch, and the two branches operate independently, with complementary interference.
在更进一步的实施例中，所述振荡器Y1与所述电阻R8和所述电感L3组成的支路进行并联，通过外接并联电子元器件进行震荡电流的反馈输入，从而保证震荡电路的稳定性。In a further embodiment, the oscillator Y1 is connected in parallel with the branch composed of the resistor R8 and the inductor L3, and the feedback input of the oscillating current is performed through external parallel electronic components, thereby ensuring the stability of the oscillating circuit .
在更进一步的实施例中，所述电阻R9与所述二极管D11与电压信号Vref进行连接，对所述集成芯片U1的电压参考端和电流检测支路进行统一的参考电压设置，保证并行数据处理的过程中不因为电压畸变产生电流大小的匹配错漏。In a further embodiment, the resistor R9 and the diode D11 are connected to the voltage signal Vref, and a unified reference voltage setting is performed on the voltage reference terminal and the current detection branch of the integrated chip U1 to ensure parallel data processing During the process, there is no mismatch of current magnitude due to voltage distortion.
一种数据分段传输方法，在云平台数据传输的过程当中，由于需要对多种系统的数据进行同时并行传输，在长字节的命令进行传输的时候，需要进行分段传输，为了避免出现数据重组的混乱，需要对同一数据命令进行标识，保证数据接收的完整性，具体步骤为：A method of segmented data transmission. In the process of data transmission on the cloud platform, due to the need for simultaneous and parallel transmission of data from multiple systems, when long-byte commands are transmitted, segmented transmission is required to avoid The chaos of data reorganization requires the identification of the same data command to ensure the integrity of data reception. The specific steps are as follows:
步骤1、对命令数据的长度进行判断，以各系统的安全传输界限为标准，短字节的命令进行直接传输，直接进入步骤3；长字节的命令进入到字符标识步骤中，也就是步骤2；Step 1. Judge the length of the command data, and use the safe transmission limit of each system as the standard. The short byte command is directly transmitted, and then go directly to step 3; the long byte command enters the character identification step, which is the step 2;
步骤2、对长字节的命令进行长度分段并进行数据标识；Step 2. Perform length segmentation on the long byte command and perform data identification;
步骤21、除了第一分段，以比最大安全传输界限少一个单元存储行的数据空间作为标准进行数据存储，其余分段始终以比最大安全传输界限少两个单元存储行的数据空间作为标准，进行传送数据划分；第一分段保留末位空白行，其余分段均保留初始空白行和末位空白行两行，直到剩余传送数据的字节长度刚好等于或者小于一个最大安全传输界限；Step 21. Except for the first segment, use the data space of one unit storage row less than the maximum safe transmission limit as the standard for data storage, and the remaining segments always use the data space of two unit storage rows less than the maximum safe transmission limit as the standard. , The transmission data is divided; the first segment retains the last blank line, and the remaining segments retain the initial blank line and the last blank line until the byte length of the remaining transmitted data is equal to or less than a maximum safe transmission limit;
步骤22、对于分段的传送数据的结尾数据进行标识，复制第一分段的最后一行后半段的数据作为第一分段末位空白行数据的开头，以零补充完整，并将补充完整的数据填充到第二分段的初始空白行中，以此类推，复制第二分段的最后一行的后半段数据作为第二分段末位空白行数据的开头，以零补充完整，并将补充完整的数据填充到第三分段的初始空白行中···直到数据全都标识完成；Step 22: Identify the end data of the segmented transmission data, copy the data of the second half of the last line of the first segment as the beginning of the blank line data at the end of the first segment, complete it with zeros, and complete it. Fill in the initial blank line of the second segment, and so on, copy the second half of the last line of the second segment as the beginning of the last blank line of the second segment, complete with zeros, and Fill the completed data into the initial blank row of the third segment...until all the data are identified;
步骤23、进入到步骤3中，对分段数据进行传输；Step 23: Go to step 3 to transmit the segmented data;
步骤3、传送数据。Step 3. Transfer data.
在进一步的实施例中，对数据进行分段标识之后，在重新进行数据整合的时候，可以根据不同分段的数据末位行和数据初始行进行数据匹配，当数据重合时，进行标识匹配完成，可以进行消除相同行，直接进行数据重组。In a further embodiment, after the data is segmented and identified, when re-integrating the data, data matching can be performed according to the last row of data and the initial row of data of different segments. When the data overlaps, the identification matching is completed. , You can eliminate the same rows and directly reorganize the data.
一种字符判定缓存数据的方法，对云平台的数据传输进行暂时数据缓存，具体步骤分成：A method for character judgment to cache data, which temporarily caches data transmission on the cloud platform. The specific steps are divided into:
步骤1、对缓存数据进行性质判定，因为命令长度较长进行数据分段的为一种，另一种为系统运行中因为意外中断进行的保护性数据存储，前者数据进行分段后传输，后者进行判定字符的增加；Step 1. Determine the nature of the cached data. One type is used for data segmentation because of the long command length, and the other type is for protective data storage due to unexpected interruption during system operation. The former data is segmented and then transmitted. The person to determine the increase of characters;
步骤2、对含有判定字符的缓存片段，进行保护性长时间存储，保证不因为系统操作产生数据丢失问题，确认数据内容之后可以对判定字符进行保留后重新存贮；确认数据内容后判定是需要删除的数据内容，先进行判定字符的删除后，再进行数据内容的删除，保证缓存空间的充足。Step 2. Perform protective long-term storage for the cached fragments containing judged characters to ensure that no data loss problems will occur due to system operations. After confirming the data content, the judged characters can be retained and re-stored; after confirming the data content, it is judged that it is necessary For the deleted data content, first delete the judging character, and then delete the data content to ensure sufficient cache space.
在进一步的实施例中，具体的云平台使用系统对缓存空间的数据处理协议不同，本方法中可以分成默认的ISO协议和自定义协议，保证缓存数据的内容判定更加智能化。In a further embodiment, the specific cloud platform usage system has different data processing protocols for the cache space. This method can be divided into a default ISO protocol and a custom protocol to ensure that the content of the cached data is determined more intelligently.
总之，本发明具有以下优点：通过对多路连接端口进行电路调控，加强了多路并行数据传递的稳定性和可行度，进一步对并行数据传递中的长命令数据进行标识分段和缓冲存储， 提高了数据传输的准确度，整体来说，本发明大大加强数据传输的运行速度和数据自我纠错能力，实用度很高。In summary, the present invention has the following advantages: by performing circuit control on multiple connection ports, the stability and feasibility of multiple parallel data transmission are enhanced, and the long command data in the parallel data transmission is further identified and segmented and buffered. The accuracy of data transmission is improved. On the whole, the present invention greatly enhances the operation speed of data transmission and the ability of data self-correction, and has a high degree of practicality.
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合。为了避免不必要的重复，本发明对各种可能的组合方式不再另行说明。In addition, it should be noted that the various specific technical features described in the foregoing specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, various possible combinations are not described separately in the present invention.

Claims (7)

  1. 一种云平台连接端口控制装置，包括端口控制系统、上层检测通讯系统、传输系统和缓冲存储系统， A cloud platform connection port control device includes a port control system, an upper-level detection communication system, a transmission system and a buffer storage system,
    端口控制系统，其特征在于，包括一种端口控制电路，具体可以分为输入电流控制模块、输出保护模块和四路控制模块，通过对端口数据进行分组，实现多系统数据的同步处理支路，提高数据处理的运行能力和运行速度；The port control system is characterized by including a port control circuit, which can be specifically divided into an input current control module, an output protection module and a four-way control module. By grouping the port data, the synchronization processing branch of multi-system data is realized. Improve the operational capacity and speed of data processing;
    上层检测通讯系统，根据自定义的传输口令，对检测通讯的内容进行传输，减少因为传输协议错漏造成的数据错乱问题，加强数据接收的准确性；The upper-level detection communication system transmits the content of the detection communication according to the self-defined transmission password, reduces the problem of data confusion caused by the error or omission of the transmission protocol, and strengthens the accuracy of data reception;
    传输系统，对接受到的数据进行分别进行上下层的数据流传输，自上而下和自下而上的两种运行模式互不干扰；The transmission system carries out the upper and lower data stream transmission of the received data respectively, and the top-down and bottom-up operation modes do not interfere with each other;
    缓冲存储系统，对传输过程中出现的数据错误模式进行数据缓冲保存，根据协议算法对缓冲的数据进行排错处理之后，完成数据的再次上传，是云平台连接系统中的中转站；The buffer storage system buffers and saves the data error patterns that occur during the transmission process, and after troubleshooting the buffered data according to the protocol algorithm, the data is uploaded again, which is a transfer station in the cloud platform connection system;
    所述输入电流控制模块，包括运算放大器AR1、电机MO1、电流表M1、二极管D1、二极管D2、二极管D3、二极管D4、二极管D5、二极管D11、MOS管Q1、电感L1和电阻R1，所述二极管D11的正极与电压信号Vref连接，所述二极管D11的负极与所述运算放大器AR1的第二引脚连接，所述运算放大器AR1的第一引脚与所述运算放大器AR1的第四引脚、所述运算放大器AR1的第五引脚、所述运算放大器AR1的第七引脚、所述运算放大器AR1的第八引脚均为断路，所述运算放大器AR1的第六引脚与所述电机MO1的一端连接，所述电机MO1的另一端分别与所述电感L1的一端、所述二极管D3的负极、所述二极管D1的负极连接，所述电感L1的另一端分别与所述二极管D5的正极、所述MOS管Q1的D极连接，所述二极管D5的负极分别与所述电阻R1的一端、所述运算放大器AR1的第三引脚连接，所述电阻R1的另一端分别与所述MOS管Q1的S极、所述二极管D4的正极、所述二极管D2的正极连接，所述二极管D4的负极分别与所述二极管D3的正极、所述电流表M1的一端连接，所述二极管D2的负极分别与所述二极管D1的正极、所述电流表M1的另一端连接；The input current control module includes operational amplifier AR1, motor MO1, ammeter M1, diode D1, diode D2, diode D3, diode D4, diode D5, diode D11, MOS tube Q1, inductor L1, and resistor R1. The diode D11 The anode of the diode D11 is connected to the voltage signal Vref, the cathode of the diode D11 is connected to the second pin of the operational amplifier AR1, and the first pin of the operational amplifier AR1 is connected to the fourth pin of the operational amplifier AR1. The fifth pin of the operational amplifier AR1, the seventh pin of the operational amplifier AR1, and the eighth pin of the operational amplifier AR1 are all disconnected. The sixth pin of the operational amplifier AR1 is connected to the motor MO1. The other end of the motor MO1 is connected to one end of the inductor L1, the cathode of the diode D3, and the cathode of the diode D1. The other end of the inductor L1 is connected to the anode of the diode D5. The D pole of the MOS transistor Q1 is connected, the cathode of the diode D5 is connected to one end of the resistor R1 and the third pin of the operational amplifier AR1, and the other end of the resistor R1 is connected to the MOS The S pole of the tube Q1, the anode of the diode D4, and the anode of the diode D2 are connected, the cathode of the diode D4 is connected to the anode of the diode D3 and one end of the ammeter M1, and the cathode of the diode D2 Respectively connected to the anode of the diode D1 and the other end of the ammeter M1;
    所述输出保护模块，包括电桥DB1、运算放大器AR2、MOS管Q2、二极管D6、电阻R2、电阻R3、电阻R4、电阻R5、电容C1、电容C2、电容C3和电容C4，所述电桥RB1的第二引脚分别与所述电阻R3的一端、所述电容C3的一端、所述电容C1的一端、所述电容C2的一端连接，所述电桥RB1的第四引脚与所述电阻R2的一端连接，所述电阻R2的另一端分别与所述二极管D6的正极、所述MOS管Q2的S极连接，所述二极管D6的负极与所述电容C3的另一端连接，所述MOS管Q2的S极接地，所述电阻R3的另一端与所述MOS管Q2的G极连接，所述电容C1的另一端分别与所述电容C2的另一端、所述电阻R4的一端连接，所述电阻R4的另一端与所述运算放大器AR2的第二引脚连接，所述运算放大器AR2的第一引脚与所述运算放大器AR2的第四引脚、所述运算放大器AR2的第五引脚、所述运算放大器AR2的第七引脚、所述运算放大器AR2的第八引脚均为断路，所述运算放大器AR2的第六引脚分别与电压信号Vout、所述电阻R5的一端连接，所述运算放大器AR2的第三引脚分别与所述电阻R5的另一端、所述电容C4的一端连接，所述电容C4的另一端接地；The output protection module includes a bridge DB1, an operational amplifier AR2, a MOS transistor Q2, a diode D6, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4. The bridge The second pin of RB1 is connected to one end of the resistor R3, one end of the capacitor C3, one end of the capacitor C1, and one end of the capacitor C2. The fourth pin of the bridge RB1 is connected to the One end of the resistor R2 is connected, the other end of the resistor R2 is connected to the anode of the diode D6 and the S electrode of the MOS transistor Q2, and the cathode of the diode D6 is connected to the other end of the capacitor C3. The S pole of the MOS transistor Q2 is grounded, the other end of the resistor R3 is connected to the G pole of the MOS transistor Q2, and the other end of the capacitor C1 is respectively connected to the other end of the capacitor C2 and one end of the resistor R4 , The other end of the resistor R4 is connected to the second pin of the operational amplifier AR2, the first pin of the operational amplifier AR2 is connected to the fourth pin of the operational amplifier AR2, and the first pin of the operational amplifier AR2 The five pins, the seventh pin of the operational amplifier AR2, and the eighth pin of the operational amplifier AR2 are all open circuits. The sixth pin of the operational amplifier AR2 is connected to the voltage signal Vout and the resistor R5. One end is connected, the third pin of the operational amplifier AR2 is respectively connected to the other end of the resistor R5 and one end of the capacitor C4, and the other end of the capacitor C4 is grounded;
    所述四路控制模块，包括集成芯片U1、振荡器Y1、开关S1、三极管Q3、三极管Q4、MOS管Q5、MOS管Q6、电阻R6、电阻R7、电阻R8、电阻R9、电阻R10、电容C5、电容C6、电容C7、电容C8、电容C9、电感L2、电感L3、电感L4、二极管D7、二极管D8、二极管D9和二极管D10，所述电桥RB1的第一引脚分别与所述电阻R7的一端、所述集成芯片U1的第十六引脚、所述集成芯片U1的第四引脚、电压信号Vcc连接，所述电阻R7的另一端与所述集成芯片U1的第七引脚连接，所述电桥RB1的第三引脚与所述集成芯片U1的第九引脚连接，所述集成芯片U1的第十引脚与所述集成芯片U1的第十一引脚、所述集成芯片U1的第十二引脚、所述集成芯片U1的第十三引脚、所述集成芯片U1的第十四引脚、所述集成芯片U1的第十五引脚均为断路，所述集成芯片U1的第六引脚分别与所述振荡器Y1的一端、所述电感L3的一端连接，所述电感L3的另一端与所述电阻R8的一端连接，所述电阻R8的另一端分别与所述振荡器Y1的另一端、所述开关S1的一端连接，所述开关S1的另一端与所述集成芯片U1的第一引脚连接，所述集成芯片U1的第八引脚接地，所述集成芯片U1的第三引脚与所述电感L4的一端连接，所述电感L4的另一端分别与所述MOS管Q5的G极、所述MOS管Q6的G极连接，所述集成芯片U1的第二引脚分别与所述电阻R9的一端、所述电容C9的一端连接，所述电容C9的另一端接地，所述电阻R9的另一端与电压信号Vref连接，所述集成芯片U1的第五引脚与所述电感L2的一端连接，所述电感L2的另一端分别与所述三极管Q3的发射极、所述二极管D7的负极、所述电容C5的一端、所述三极管Q4的发射极、所述二极管D8的负极、所述电容柜C6的一端连接，所述三极管Q4的基极与所述电阻R6的一端连接，所述电阻R6的另一端分别与所述三极管Q3的基极、电压信号Vin、所述MOS管Q1的G极连接，所述三极管Q3的集电极分别与所述二极管D7的正极、所述电容C5的另一端、所述MOS管Q5的D极、所述二极管D9的正极、所述电容C7的一端连接，所述电容C7的另一端分别与所述二极管D9的负极、所述MOS管Q5的S极、所述MOS管Q6的D极、所述二极管D10的负极、所述电容C8的一端连接，所述电容C8的另一端分别与所述二极管D10的正极、所述MOS管Q6的S极、所述电容C6的另一端、所述二极管D8的正极、所述三极管Q4的集电极连接。The four-way control module includes integrated chip U1, oscillator Y1, switch S1, transistor Q3, transistor Q4, MOS transistor Q5, MOS transistor Q6, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, capacitor C5 , Capacitor C6, capacitor C7, capacitor C8, capacitor C9, inductor L2, inductor L3, inductor L4, diode D7, diode D8, diode D9, and diode D10. The first pin of the bridge RB1 is connected to the resistor R7. One end of the integrated chip U1, the sixteenth pin of the integrated chip U1, the fourth pin of the integrated chip U1, and the voltage signal Vcc are connected, and the other end of the resistor R7 is connected to the seventh pin of the integrated chip U1 , The third pin of the bridge RB1 is connected to the ninth pin of the integrated chip U1, and the tenth pin of the integrated chip U1 is connected to the eleventh pin of the integrated chip U1. The twelfth pin of the chip U1, the thirteenth pin of the integrated chip U1, the fourteenth pin of the integrated chip U1, and the fifteenth pin of the integrated chip U1 are all open circuits. The sixth pin of the integrated chip U1 is connected to one end of the oscillator Y1 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the resistor R8, and the other end of the resistor R8 is respectively Connected to the other end of the oscillator Y1 and one end of the switch S1, the other end of the switch S1 is connected to the first pin of the integrated chip U1, and the eighth pin of the integrated chip U1 is grounded, The third pin of the integrated chip U1 is connected to one end of the inductor L4, and the other end of the inductor L4 is respectively connected to the G pole of the MOS transistor Q5 and the G pole of the MOS transistor Q6. The second pin of the chip U1 is connected to one end of the resistor R9 and one end of the capacitor C9, the other end of the capacitor C9 is grounded, and the other end of the resistor R9 is connected to the voltage signal Vref. The integrated chip The fifth pin of U1 is connected to one end of the inductor L2, and the other end of the inductor L2 is respectively connected to the emitter of the transistor Q3, the cathode of the diode D7, one end of the capacitor C5, and the transistor Q4. The emitter of the diode D8, the cathode of the diode D8, and one end of the capacitor cabinet C6 are connected, the base of the transistor Q4 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the transistor Q3. The base, the voltage signal Vin, and the G pole of the MOS transistor Q1 are connected, and the collector of the transistor Q3 is connected to the anode of the diode D7, the other end of the capacitor C5, the D pole of the MOS transistor Q5, The anode of the diode D9 and one end of the capacitor C7 are connected, and the other end of the capacitor C7 is connected to the cathode of the diode D9, the S electrode of the MOS transistor Q5, the D electrode of the MOS transistor Q6, and the The cathode of the diode D10 and one end of the capacitor C8 are connected, and the other end of the capacitor C8 is connected to the anode of the diode D10, the S pole of the MOS transistor Q6, and the capacitor The other end of C6, the anode of the diode D8, and the collector of the transistor Q4 are connected.
  2. 根据权利要求1所述的一种云平台连接端口控制装置，其特征在于，所述电流表M1分别与两路电流支路的连接节点进行连接，可以直接对两路支路进行电流比较，当出现电流测量值过大的情况时，表示支路电流值超出安全范围，需要对输入电压进行调整。 The cloud platform connection port control device according to claim 1, wherein the ammeter M1 is respectively connected to the connection nodes of the two current branches, and the currents of the two branches can be directly compared. When the current measurement value is too large, it means that the branch current value is out of the safe range and the input voltage needs to be adjusted.
  3. 根据权利要求1所述的一种云平台连接端口控制装置，其特征在于，所述传输系统内部直接可以分成自上而下的数据接收支路和自下而上的数据传送支路，两个支路独立运行，互补干扰。 The cloud platform connection port control device according to claim 1, wherein the transmission system can be directly divided into a top-down data receiving branch and a bottom-up data transmission branch. Branch circuits operate independently and interfere with each other.
  4. 基于权利要求1至3任一项云平台连接端口控制装置的控制方法，其特征在于，所述传输系统采用如下数据分段传输方法，在云平台数据传输的过程当中，由于需要对多种系统的数据进行同时并行传输，在长字节的命令进行传输的时候，需要进行分段传输，为了避免出现数据重组的混乱，需要对同一数据命令进行标识，保证数据接收的完整性，具体步骤为： A control method based on a cloud platform connection port control device according to any one of claims 1 to 3, characterized in that the transmission system adopts the following data segment transmission method. In the process of cloud platform data transmission, due to the need for multiple systems The data is transmitted in parallel at the same time. When the long-byte command is transmitted, it needs to be transmitted in segments. In order to avoid the confusion of data reorganization, the same data command needs to be identified to ensure the integrity of data reception. The specific steps are :
    步骤1、对命令数据的长度进行判断，以各系统的安全传输界限为标准，短字节的命令进行直接传输，直接进入步骤3；长字节的命令进入到字符标识步骤中，也就是步骤2；Step 1. Judge the length of the command data, and use the safe transmission limit of each system as the standard. The short byte command is directly transmitted, and then go directly to step 3; the long byte command enters the character identification step, which is the step 2;
    步骤2、对长字节的命令进行长度分段并进行数据标识；Step 2. Perform length segmentation on the long byte command and perform data identification;
    步骤21、除了第一分段，以比最大安全传输界限少一个单元存储行的数据空间作为标准进行数据存储，其余分段始终以比最大安全传输界限少两个单元存储行的数据空间作为标准，进行传送数据划分；第一分段保留末位空白行，其余分段均保留初始空白行和末位空白行两行，直到剩余传送数据的字节长度刚好等于或者小于一个最大安全传输界限；Step 21. Except for the first segment, use the data space of one unit storage row less than the maximum safe transmission limit as the standard for data storage, and the remaining segments always use the data space of two unit storage rows less than the maximum safe transmission limit as the standard. , The transmission data is divided; the first segment retains the last blank line, and the remaining segments retain the initial blank line and the last blank line until the byte length of the remaining transmitted data is equal to or less than a maximum safe transmission limit;
    步骤22、对于分段的传送数据的结尾数据进行标识，复制第一分段的最后一行后半段的数据作为第一分段末位空白行数据的开头，以零补充完整，并将补充完整的数据填充到第二分段的初始空白行中，以此类推，复制第二分段的最后一行的后半段数据作为第二分段末位空白行数据的开头，以零补充完整，并将补充完整的数据填充到第三分段的初始空白行中···直到数据全都标识完成；Step 22: Identify the end data of the segmented transmission data, copy the data of the second half of the last line of the first segment as the beginning of the blank line data at the end of the first segment, complete it with zeros, and complete it. Fill in the initial blank line of the second segment, and so on, copy the second half of the last line of the second segment as the beginning of the last blank line of the second segment, complete with zeros, and Fill the completed data into the initial blank row of the third segment...until all the data are identified;
    步骤23、进入到步骤3中，对分段数据进行传输；Step 23: Go to step 3 to transmit the segmented data;
    步骤3、传送数据。Step 3. Transfer data.
  5. 根据权利要求4所述的基于云平台连接端口控制装置的控制方法，其特征在于，对数据进行分段标识之后，在重新进行数据整合的时候，可以根据不同分段的数据末位行和数据初始行进行数据匹配，当数据重合时，进行标识匹配完成，可以进行消除相同行，直接进行数据重组。 The control method based on the cloud platform connection port control device according to claim 4, characterized in that after the data is segmented and identified, when the data is reintegrated, the data can be based on the last row and data of different segments. The initial row performs data matching. When the data overlaps, the identification matching is completed, the same row can be eliminated, and the data reorganization can be performed directly.
  6. 根据权利要求4所述的基于云平台连接端口控制装置的控制方法，其特征在于，所述缓冲存储系统对云平台的数据传输进行暂时数据缓存的具体步骤分成： The control method based on the cloud platform connection port control device according to claim 4, wherein the specific steps of the buffer storage system for temporarily data buffering the data transmission of the cloud platform are divided into:
    步骤1、对缓存数据进行性质判定，因为命令长度较长进行数据分段的为一种，另一种为系统运行中因为意外中断进行的保护性数据存储，前者数据进行分段后传输，后者进行判定字符的增加；Step 1. Determine the nature of the cached data. One type is used for data segmentation because of the long command length, and the other type is for protective data storage due to unexpected interruption during system operation. The former data is segmented and then transmitted. The person to determine the increase of characters;
    步骤2、对含有判定字符的缓存片段，进行保护性长时间存储，保证不因为系统操作产生数据丢失问题，确认数据内容之后可以对判定字符进行保留后重新存贮；确认数据内容后判定是需要删除的数据内容，先进行判定字符的删除后，再进行数据内容的删除，保证缓存空间的充足。Step 2. Perform protective long-term storage for the cached fragments containing judged characters to ensure that no data loss problems will occur due to system operations. After confirming the data content, the judged characters can be retained and re-stored; after confirming the data content, it is judged that it is necessary For the deleted data content, first delete the judging character, and then delete the data content to ensure sufficient cache space.
  7. 根据权利要求6所述的基于云平台连接端口控制装置的控制方法，其特征在于，具体的云平台使用系统对缓存空间的数据处理协议不同，本方法中可以分成默认的ISO协议和自定义协议，保证缓存数据的内容判定更加智能化。 The control method based on the cloud platform connection port control device according to claim 6, wherein the specific cloud platform using system has different data processing protocols for the cache space, and this method can be divided into a default ISO protocol and a custom protocol , To ensure that the content judgment of cached data is more intelligent.
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