CN104091192B - CLF chip interface circuit in a kind of SWP agreement - Google Patents
CLF chip interface circuit in a kind of SWP agreement Download PDFInfo
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- CN104091192B CN104091192B CN201410266766.4A CN201410266766A CN104091192B CN 104091192 B CN104091192 B CN 104091192B CN 201410266766 A CN201410266766 A CN 201410266766A CN 104091192 B CN104091192 B CN 104091192B
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Abstract
The invention discloses CLF chip interface circuit in a kind of SWP agreement, including input shaper module, output loading modulation module, current sample module and output Shaping module；The input of described input shaper module is for connecting the voltage modulation signal of CLF chip output, the input of described output loading modulation module is connected with the output of described input shaper module, and the output of described output loading modulation module is for being connected with the C6 pin of UICC chip；The input of described current sample module is connected with the C6 pin of UICC chip；The input of described output Shaping module is connected to the output of described current sample module, and the output of described output Shaping module is used for exporting current modulated to CLF chip.The present invention can be realized the function of CLF chip interface circuit in SWP agreement by current sampling technique, and correct is sent to UICC chip voltage signal S1 in SWP agreement, also can be properly received UICC chip current signal S2 simultaneously, thus realize full-duplex communication.
Description
Technical field
The invention belongs to CLF chip field, more particularly, to a kind of NFC system realizes based on
The interface circuit communicating between the CLF chip of SWP agreement with NFC SIM chip.
Background technology
NFC (Near Field Communication) is a kind of logical for electric room near radio
The emerging technology of letter, needs to be attached CLF chip with SIM chip.8 of SIM are drawn
In pin, 5 are had to be daily and mobile communication conventional pin, in remaining three pins, C4 and C8
Expanded to the high-speed interface of a new generation's SIM by International Standards Organization.Thus C6 pin is used to even
Connect CLF chip and SIM chip, realized by SWP (Single Wire Protocol) agreement
Connect between them.
SWP agreement be Gemalto company propose the patent based on SIM C6 pin, CLF with
Connected by three lines between UICC chip: Vcc (C1 port), SWIO (C6 port), Gnd
(C5 port), wherein SWIO holding wire use voltage and current transmission realize CLF module and
The full-duplex communication of SIM chip, as shown in Figure 1.
Be illustrated in figure 2 the schematic diagram of signal transmission defined in SWP agreement, there is defined S1 and
The signal of S2 both direction, the principle of SWP single-wire-protocol is that S1 is fixed based on full-duplex communication transmission
Justice is voltage modulation signal, and S2 is current modulated.
When the S1 signal of CLF is L, S2 signal is invalid；Only when the S1 signal of CLF
During for H, S2 signal is just effective, and at this moment SIM leads to excessive current (H) or low current (L)
The low and high level of the S2 signal of status representative transmission is as shown in Figure 3.
The technology that in SWP agreement, CLF chip interface circuit has used has difference channel amplifying technique and base
Quasi-comparison techniques, but owing to difference channel amplifying technique needs the complicated amplifier of design, benchmark compares
Technology needs design basis circuit and comparison circuit, adds complex circuit designs degree and power consumption.
Content of the invention
For the defect of prior art, it is an object of the invention to realize SWP based on current sampling technique
CLF chip interface circuit in agreement, reduces circuit complexity, decreases area and power consumption simultaneously.
The invention provides CLF chip interface circuit in a kind of SWP agreement, including input shaper module,
Output loading modulation module, current sample module and output Shaping module；Described input shaper module
Input is used for connecting the voltage modulation signal of CLF chip output, described output loading modulation module
Input is connected with the output of described input shaper module, the output of described output loading modulation module
End is for being connected with the C6 pin of UICC chip；The input of described current sample module and UICC
The C6 pin of chip is connected；The input of described output Shaping module is connected to described current sample module
Output, the output of described output Shaping module is used for exporting current modulated to CLF chip.
Wherein, described load modulation module includes phase inverter I3, PMOS MP1 and NMOS tube
MN1；The source electrode of described MP1 connects power supply VCC, and the grid of described MP1 is with described MN1's
Grid is connected with the output of described phase inverter I3 after connecting；The source ground of described MN1, described
The drain electrode of MN1 be connected with the drain electrode of described MP1 after as described load modulation module output；Institute
State the input as described load modulation module for the input of phase inverter I3.
Wherein, current sample module includes switching tube, scale tube, amplifier and sampling output circuit；
First end of described switching tube connects the C6 pin of UICC chip, and the second end of described switching tube connects
Y point, the control end of described switching tube connectsPoint；Described scale tube connects the X point of described amplifier
With Y point；Described sampling output circuit connects X point and the Y point of described amplifier；Wherein X point is for putting
The first input end of big device, Y point be amplifier the second input,Point is anti-in load modulation module
The output of phase device I3.
Wherein, described switching tube is PMOS MP2, and the source electrode of described MP2 is as described switching tube
The first end, the drain electrode of described MP2 is made as the second end of described switching tube, the grid of described MP2
Control end for described switching tube.
Wherein, described scale tube includes PMOS MP3 and PMOS MP4；Described MP3's
Source electrode is all connected with power supply VCC with the source electrode of described MP4, and the grid of described MP3 is connected to Q point,
The drain electrode of described MP3 connects Y point, the grounded-grid of described MP4, and the drain electrode of described MP4 connects
X point；The output that wherein Q point is described input shaper module.
Wherein, the breadth length ratio of described MP1, MP3 and MP4 is M:1:1；
Wherein (W/L)1、(W/L)3、(W/L)4Being respectively MP1, MP3, MP4 breadth length ratio, M value is
Integer more than 1.
Wherein, described amplifier includes PMOS MP5, PMOS MP6, NMOS tube MN2
With NMOS tube MN3；The source electrode of described MP5 is connected to Y point, the drain electrode of described MP5 with described
The drain electrode of MN2 connects, the source ground of described MN2；The source electrode of described MP6 is connected to X point,
The drain electrode of described MP6 is connected to the drain electrode of described MN3, and the drain electrode of described MP6 is also with its grid even
Connect；The source ground of described MN3；The grid of described MP6 is connected with the grid of described MP5, institute
The grid stating MN2 is connected with the grid of described MN3.
Wherein, described sampling output circuit includes PMOS MP7, PMOS MP8 and resistance R；
The source electrode of described MP7 is connected to X point, the grid of described MP7 be connected to described MP5 with described
The connection end of MN2；The drain electrode of described MP7 is grounded by described resistance R；The grid of described MP8
Being connected to the drain electrode of described MP6, the source electrode of described MP8 is connected to Y point, the drain electrode of described MP8
As the output of output circuit of sampling after being connected to the drain electrode of MP7.
The present invention can be realized the work(of CLF chip interface circuit in SWP agreement by current sampling technique
Can, correct is sent to UICC chip voltage signal S1 in SWP agreement, also can be properly received simultaneously
UICC chip current signal S2, thus realize full-duplex communication；Circuit structure is simple, low in energy consumption.
Brief description
Fig. 1 is the CLF-UICC connection scheme schematic diagram in SWP agreement based on C6 pin；
Fig. 2 is the schematic diagram of signal transmission defined in SWP agreement；
Fig. 3 is the sequential chart of S1, S2 signal in SWP agreement；
Fig. 4 is the circuit module connection diagram based on current sample structure of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing
And embodiment, the present invention is further elaborated.It should be appreciated that described herein specifically
Embodiment only in order to explain the present invention, is not intended to limit the present invention.
The problem that the present invention solves is to devise CLF chip interface circuit in a kind of SWP agreement, correctly
Be sent to UICC chip voltage signal S1 in SWP agreement, also can be properly received UICC core simultaneously
Piece current signal S2, thus realize full-duplex communication.
For solving above-mentioned technical problem, CLF chip interface circuit in the SWP agreement of the present invention, such as figure
Shown in 4, comprising: input shaper module 1 is connected with CLF chip output, by phase inverter I1 and anti-
Phase device I2 cascades composition；Output loading modulation module 2 is connected to input shaper module 1 and UICC core
Between piece C6, be made up of phase inverter I3, PMOS MP1 and NMOS tube MN1, wherein MP1,
MP2 grid withPoint is connected, and MP1 source electrode is connected with power supply VCC and C6 respectively with drain electrode, MP2
Source electrode is connected with ground and C6 respectively with drain electrode；Current sample module 3 is connected with UICC chip C6；
Output Shaping module 4 is connected between current sample module 3 and CLF chip input, by phase inverter
I4 and phase inverter I5 cascade composition.
In current sample module, by current mirror proportional sampling MP1 leakage current, PMOS
MP1, MP3, MP4 dimension scale is M:1:1, decreases the use of transistor and resistance, reduces
Power consumption.Wherein MP3 grid is connected with Q point, MP3 source electrode and drain electrode respectively with power supply VCC and
Y point is connected；MP4 grid is connected to the ground, MP4 source electrode and drain electrode respectively with power supply VCC and X point
It is connected；PMOS MP2 uses as switching tube, MP2 grid withPoint be connected, MP2 source electrode and
Drain electrode is connected with C6 mouth and Y point respectively；PMOS MP5, MP6 and NMOS tube MN2,
MN3 forms amplifier, and MP5 grid is connected with MP6 grid, MP5 source electrode and drain electrode respectively with Y
Point is connected with MN2 drain electrode, and MP6 source electrode is connected with X point, MP6 drain electrode and MP6 grid, MN3
Drain electrode is connected with MN8 grid；MN2 grid is connected with MN3 grid, MN2 source electrode and drain electrode point
Not draining with ground and MP5 and being connected, MN3 source electrode drains with ground and MP6 respectively with drain electrode and is connected；Adopt
Sample output circuit is made up of PMOS MP7 and resistance R, and MP7 grid is connected with MP5 drain electrode,
MP7 source electrode is connected with X point and R resistance respectively with drain electrode；Resistance R one end is connected with MP7 drain electrode,
The other end is connected to the ground.
PMOS MP8 has been additionally provided a compensation branch road, thus improves whole current sample
Precision, MP8 grid is connected with the drain electrode of PMOS MP6, and the source electrode of MP8 and drain electrode are respectively at Y
Point is connected with resistance R.
As shown in Figure 4,1 is input shaper module, is cascaded by phase inverter I1 and phase inverter I2 and forms.
CLF chip output voltage signal S1 is through 1 input shaper, output voltage signal Q, Q level state
With S1 signal homophase.2 is load modulation module, by phase inverter I3, PMOS MP1 and NMOS
Pipe MN1 forms.I3 output voltage signalLevel state is anti-phase with Q.When Q is high level,For low level, MP1 turns on, and current signal S2 is circulated to UICC chip, wherein S2 height electric current
State is defined as 600 μ A～1000 μ A, and low current condition is defined as 0～20 μ A；When Q is low level,For high level, MP1 is not turned on, S2 invalidating signal.
Current sampling technique is a kind of method of conventional sensed current signal, at numerous current samples
In technology, current mirror techniques is a kind of current sample method of low power consumption high-precision.3 is current sample
Module, is core circuit of the present invention, by switching tube the 31st, scale tube the 32nd, amplifier 33 with sample defeated
Go out circuit 34 to form.Switching tube 31 can be made up of PMOS MP2.Scale tube 32 can be by
PMOS MP3, MP4 composition, for proportional sampling MP1 leakage current, MP1, MP3 and
The breadth length ratio of MP4 is set to M:1:1.Amplifier 33 can be by PMOS MP5, MP6 and NMOS
Pipe MN2, MN3 form, and input Y point and the X point drain terminal with MP3 and MP4 respectively
It is connected.Sampling output circuit 34 can be made up of PMOS MP7, MP8 and resistance R.
Above-mentioned module breaker in middle pipe 31 can be realized by the NMOS tube with control conducting function；Put
Big device 33 can be realized by other amplifier architectures with double-width grinding.
The course of work of circuit is: when S1 (Q) is high level, MP3 is not turned on, and MP2 turns on,
MP1 and MP4 forms current mirroring circuit, and amplifier 33 ensures that X point is equal with Y point voltage, thus
Make MP1 and MP4 drain terminal voltage equal, it is achieved two pipes match, then current ratio can be accuratelyWherein IMP1、IMP4It is respectively MP1, MP4 leakage current, (W/L)1、(W/L)4
It is respectively MP1, MP4 breadth length ratio.At this moment circuit is in sample states, owing to amplifier is lost one
Divide quiescent current Ib, MP8 has been additionally provided a current compensation branch road, can have been obtained by current relationship
IsenseAs shown in formula (1)；If not compensating branch road, IsenseAs shown in formula (2), therefore MP8
Collocation structure further increases the precision of current sample.
Wherein IsenseFor actual samples electric current, ILFor being sampled electric current, IbFor amplifier quiescent current.
MP7, MP8 and resistance R composition sampling output circuit, wherein Vsense=IsenseR, VsenseDefeated for sampling
Go out voltage.When S1 (Q) is low level, MP3 turns on, and MP2 is not turned on, MP3 and MP4
Composition current mirroring circuit, forces Y point and X point also can keep high level, prevents next cycle S1
Re-establish for Y point during high level, improve the sample rate of whole circuit.4 is output Shaping electricity
Road, is cascaded by phase inverter I4 and phase inverter I5 and forms, by the V of samplingsenseIt is quantified as digital level S'2Defeated
Enter to CLF input port.
As it will be easily appreciated by one skilled in the art that and the foregoing is only presently preferred embodiments of the present invention,
Not in order to limit the present invention, all made within the spirit and principles in the present invention any modification, etc.
With replacement and improvement etc., should be included within the scope of the present invention.
Claims (8)
1. CLF chip interface circuit in a SWP agreement, it is characterised in that include input shaper
Module (1), output loading modulation module (2), current sample module (3) and output Shaping module
(4)；
The input of described input shaper module (1) is for connecting the voltage modulated letter of CLF chip output
Number, the input of described output loading modulation module (2) is defeated with described input shaper module (1)
Going out end to connect, the output of described output loading modulation module (2) is for the C6 with UICC chip
Pin connects；
The described input of current sample module (3) is connected with the C6 pin of UICC chip；Described
The input of output Shaping module (4) is connected to the output of described current sample module (3), institute
The output stating output Shaping module (4) is used for exporting current modulated to CLF chip.
2. interface circuit as claimed in claim 1, it is characterised in that mould is modulated in described output loading
Block (2) includes phase inverter I3, PMOS MP1 and NMOS tube MN1；
The source electrode of described MP1 connects power supply VCC, the grid of the grid of described MP1 and described MN1
It is connected with the output of described phase inverter I3 after connection；The source ground of described MN1, described MN1
Drain electrode be connected with the drain electrode of described MP1 after as the output of described output loading modulation module (2)
End；The input of described phase inverter I3 is as the input of described output loading modulation module (2).
3. interface circuit as claimed in claim 1, it is characterised in that described current sample module (3)
Including switching tube (31), scale tube (32), amplifier (33) and sampling output circuit (34)；
First end of described switching tube (31) connects the C6 pin of UICC chip, described switching tube (31)
The second end connect Y point, the control end of described switching tube (31) connectsPoint；Described scale tube (32)
Connect X point and the Y point of described amplifier (33)；Described sampling output circuit (34) connects described
The X point of amplifier (33) and Y point；
First input end, Y point that wherein X point is amplifier (33) are the second of amplifier (33)
Input,Point is the output of phase inverter I3 in output loading modulation module (2).
4. interface circuit as claimed in claim 3, it is characterised in that described switching tube (31) is
PMOS MP2, the source electrode of described MP2 is as the first end of described switching tube (31), described
The drain electrode of MP2 is opened as described as the second end of described switching tube (31), the grid of described MP2
Close the control end of pipe (31).
5. the interface circuit as described in claim 3 or 4, it is characterised in that described scale tube (32)
Including PMOS MP3 and PMOS MP4；The source electrode of described MP3 and the source of described MP4
Pole is all connected with power supply VCC, and the grid of described MP3 is connected to Q point, and the drain electrode of described MP3 connects
Y point, the grounded-grid of described MP4, the drain electrode of described MP4 connects X point；Wherein Q point is institute
State the output of input shaper module (1).
6. interface circuit as claimed in claim 5, it is characterised in that described MP1, MP3 and
The breadth length ratio of MP4 is set to M:1:1；Wherein (W/L)1、(W/L)3、(W/L)4
Being respectively MP1, MP3, MP4 breadth length ratio, M value is the integer more than 1.
7. interface circuit as claimed in claim 4, it is characterised in that described amplifier (33) wraps
Include PMOS MP5, PMOS MP6, NMOS tube MN2 and NMOS tube MN3；
The source electrode of described MP5 is connected to Y point, and the drain electrode of described MP5 is with the drain electrode of described MN2 even
Connect, the source ground of described MN2；
The source electrode of described MP6 is connected to X point, and the drain electrode of described MP6 is connected to the leakage of described MN3
Pole, the drain electrode of described MP6 is also connected with its grid；The source ground of described MN3；Described MP6
Grid be connected with the grid of described MP5, the grid of described MN2 is connected with the grid of described MN3.
8. interface circuit as claimed in claim 7, it is characterised in that described sampling output circuit (34)
Including PMOS MP7, PMOS MP8 and resistance R；
The source electrode of described MP7 is connected to X point, and the grid of described MP7 is connected to described MP5 and institute
State the connection end of MN2；The drain electrode of described MP7 is grounded by described resistance R；The grid of described MP8
Pole is connected to the drain electrode of described MP6, and the source electrode of described MP8 is connected to Y point, the leakage of described MP8
Pole is connected to the output after the drain electrode of MP7 as sampling output circuit (34).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410266766.4A CN104091192B (en) | 2014-06-16 | 2014-06-16 | CLF chip interface circuit in a kind of SWP agreement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410266766.4A CN104091192B (en) | 2014-06-16 | 2014-06-16 | CLF chip interface circuit in a kind of SWP agreement |
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| Publication Number | Publication Date |
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| CN104091192A CN104091192A (en) | 2014-10-08 |
| CN104091192B true CN104091192B (en) | 2016-10-05 |
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| CN201410266766.4A Expired - Fee Related CN104091192B (en) | 2014-06-16 | 2014-06-16 | CLF chip interface circuit in a kind of SWP agreement |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111835373B (en) * | 2019-11-18 | 2023-11-14 | 紫光同芯微电子有限公司 | Novel SWP interface circuit |
| CN112149439B (en) * | 2020-11-17 | 2021-04-09 | 四川科道芯国智能技术股份有限公司 | Decoding self-alignment method, device and equipment for SWP physical layer S2 |
| CN112118004B (en) * | 2020-11-19 | 2021-04-09 | 四川科道芯国智能技术股份有限公司 | SWP interface circuit and terminal |
| CN112448709B (en) * | 2021-02-01 | 2021-05-18 | 北京紫光青藤微系统有限公司 | SWP main interface circuit and terminal |
| CN112511153B (en) * | 2021-02-02 | 2021-05-18 | 北京紫光青藤微系统有限公司 | SWP main interface circuit and terminal |
| CN115174431B (en) * | 2022-06-30 | 2023-09-05 | 无锡融卡科技有限公司 | Simple SWP full duplex logic signal acquisition device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236453A (en) * | 2008-01-30 | 2008-08-06 | 上海华虹集成电路有限责任公司 | Connection structure and communicating method between NFC control chip and SIM card chip |
| JP2011191999A (en) * | 2010-03-15 | 2011-09-29 | Renesas Electronics Corp | Ic card |
| CN203941540U (en) * | 2014-06-16 | 2014-11-12 | 华中科技大学 | A kind of CLF chip interface circuit |
-
2014
- 2014-06-16 CN CN201410266766.4A patent/CN104091192B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236453A (en) * | 2008-01-30 | 2008-08-06 | 上海华虹集成电路有限责任公司 | Connection structure and communicating method between NFC control chip and SIM card chip |
| JP2011191999A (en) * | 2010-03-15 | 2011-09-29 | Renesas Electronics Corp | Ic card |
| CN203941540U (en) * | 2014-06-16 | 2014-11-12 | 华中科技大学 | A kind of CLF chip interface circuit |
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