Cloud platform connection port control device and control method
Technical Field
The invention relates to a data parallel transmission technology, in particular to a cloud platform connection port control device.
Background
Along with the continuous improvement of the scientific and technological level of China, the use level of computers by everyone in China is also improved. Meanwhile, devices which replace manual control with computer control in life and industrial production are continuously generated, the phenomenon improves the level of intelligent industrial production in China, and meanwhile, new requirements on the performance of computer control devices are met.
Cloud platforms and multi-port controllers are new research directions that have emerged in recent years. Aiming at the original control device, the cloud platform is used for improving the big data processing and further data sharing, and more and better function expansion and function improvement can be carried out on the control device. Specific use examples such as satellite positioning and vehicle navigation are well appreciated in the market after being developed.
At present, research on the cloud platform connection port control device in the market is continuously carried out, and due to continuous research and development of novel functions, parallel data needing to be transmitted are also continuously increased, and updating of a data transmission mode and a data processing mode is also required to be continuously promoted. Particularly, for parallel data transmission of multiple connection ports, data accuracy of data transmitted in parallel needs to be guaranteed, and transmission phenomena of data missing and data missing are avoided.
Disclosure of Invention
The purpose of the invention is as follows: a cloud platform connection port control device is provided to solve the above problems.
The technical scheme is as follows: a cloud platform connection port control device comprises a port control system, an upper layer detection communication system, a transmission system and a buffer storage system,
the port control system is characterized by comprising a port control circuit which can be specifically divided into an input current control module, an output protection module and a four-way control module, and the port data are grouped, so that synchronous processing branches of the multi-system data are realized, and the operation capacity and the operation speed of data processing are improved;
the upper detection communication system transmits the content of detection communication according to the self-defined transmission password, reduces the problem of data disorder caused by transmission protocol error and leakage and enhances the accuracy of data reception;
the transmission system is used for respectively carrying out data stream transmission of an upper layer and a lower layer on received data, and the two operation modes from top to bottom and from bottom to top are not interfered with each other;
the buffer storage system is used for buffering and storing data of a data error mode occurring in the transmission process, and finishing the re-uploading of the data after the buffered data is subjected to debugging processing according to a protocol algorithm, and is a transfer station in the cloud platform connection system;
the input current control module comprises an operational amplifier AR1, a motor MO1, an ammeter M1, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D11, a MOS transistor Q1, an inductor L1 and a resistor R1, wherein the anode of the diode D11 is connected with a voltage signal Vref, the cathode of the diode D11 is connected with the second pin of the operational amplifier AR1, the first pin of the operational amplifier AR1 is connected with the fourth pin of the operational amplifier AR1, the fifth pin of the operational amplifier AR1, the seventh pin of the operational amplifier AR1 and the eighth pin of the operational amplifier AR1 are all open circuits, the sixth pin of the operational amplifier AR1 is connected with one end of the motor MO1, and the other end of the motor MO1 is respectively connected with one end of the inductor L1, the cathode of the diode D3 and the cathode of the diode D1, the other end of the inductor L1 is connected to the anode of the diode D5 and the D-pole of the MOS transistor Q1, the cathode of the diode D5 is connected to one end of the resistor R1 and the third pin of the operational amplifier AR1, the other end of the resistor R1 is connected to the S-pole of the MOS transistor Q1, the anode of the diode D4 and the anode of the diode D2, the cathode of the diode D4 is connected to the anode of the diode D3 and one end of the ammeter M1, and the cathode of the diode D2 is connected to the anode of the diode D1 and the other end of the ammeter M1;
the output protection module comprises a bridge DB1, an operational amplifier AR2, a MOS transistor Q2, a diode D6, a resistor R6, a capacitor C6, and a capacitor C6, wherein a second pin of the bridge DB 6 is connected to one end of the resistor R6, one end of the capacitor C6, and one end of the capacitor C6, a fourth pin of the bridge DB 6 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to an anode of the diode D6 and an S-pole of the MOS transistor Q6, a cathode of the diode D6 is connected to the other end of the capacitor C6, the S-pole of the MOS transistor Q6 is grounded, the other end of the resistor R6 is connected to a G-pole of the MOS transistor Q6, the other end of the capacitor C6 is connected to the second pin of the resistor R6, and the other end of the capacitor R6 are connected to the second pin of the resistor R6, a first pin of the operational amplifier AR2, a fourth pin of the operational amplifier AR2, a fifth pin of the operational amplifier AR2, a seventh pin of the operational amplifier AR2, and an eighth pin of the operational amplifier AR2 are all open circuits, a sixth pin of the operational amplifier AR2 is respectively connected to a voltage signal Vout and one end of the resistor R5, a third pin of the operational amplifier AR2 is respectively connected to the other end of the resistor R5 and one end of the capacitor C4, and the other end of the capacitor C4 is grounded;
the four-way control module comprises an integrated chip U1, an oscillator Y1, a switch S1, a triode Q3, a triode Q4, a MOS tube Q5, a MOS tube Q6, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, an inductor L2, an inductor L3, an inductor L4, a diode D7, a diode D8, a diode D9 and a diode D10, wherein a first pin of the bridge DB1 is connected with one end of the resistor R7, a sixteenth pin of the integrated chip U1, a fourth pin of the integrated chip U1 and a voltage signal Vcc, the other end of the resistor R7 is connected with a seventh pin of the integrated chip U1, a third pin of the DB1 is connected with a ninth pin of the integrated chip U1, and a twelfth pin of the integrated chip U1 are connected with the eleventh pin of the integrated chip U1 and the twelfth pin of the integrated chip 1, A thirteenth pin of the integrated chip U1, a fourteenth pin of the integrated chip U1, and a fifteenth pin of the integrated chip U1 are all open circuits, a sixth pin of the integrated chip U1 is connected to one end of the oscillator Y1 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the other end of the oscillator Y1 and one end of the switch S1, the other end of the switch S1 is connected to the first pin of the integrated chip U1, the eighth pin of the integrated chip U1 is grounded, a third pin of the integrated chip U1 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to the G-pole of the MOS transistor Q5 and the G-pole of the MOS transistor Q6, and a second pin of the integrated chip U1 is connected to one end of the resistor R9, One end of the capacitor C9 is connected, the other end of the capacitor C9 is grounded, the other end of the resistor R9 is connected to a voltage signal Vref, the fifth pin of the integrated chip U1 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to the emitter of the transistor Q3, the cathode of the diode D7, one end of the capacitor C5, the emitter of the transistor Q4, the cathode of the diode D8, and one end of the capacitor C6, the base of the transistor Q4 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the base of the transistor Q3, the voltage signal Vin, and the G of the MOS transistor Q1, the collector of the transistor Q3 is connected to the anode of the diode D7, the other end of the capacitor C5, the D of the MOS transistor Q5, the anode of the diode D9, and one end of the capacitor C7, the other end of the capacitor C7 is connected to the cathode of the diode D9, the S-pole of the MOS transistor Q5, the D-pole of the MOS transistor Q6, the cathode of the diode D10, and one end of the capacitor C8, and the other end of the capacitor C8 is connected to the anode of the diode D10, the S-pole of the MOS transistor Q6, the other end of the capacitor C6, the anode of the diode D8, and the collector of the transistor Q4.
According to one aspect of the invention, the ammeter M1 is respectively connected to the connection nodes of the two current branches, so that the current comparison between the two current branches can be directly performed, and when the measured current value is too large, it indicates that the current value of the branch exceeds the safety range, and the input voltage needs to be adjusted.
According to one aspect of the invention, the transmission system can be directly internally divided into a top-down data receiving branch and a bottom-up data transmitting branch, and the two branches operate independently and are in complementary interference.
A data segmentation transmission method, in the course of cloud platform data transmission, because need carry on the concurrent parallel transmission to the data of multiple systems, while the order of the long byte is transmitted, need carry on the segmentation transmission, in order to avoid appearing the confusion of the data recombination, need label the same data order, guarantee the integrality of data reception, the concrete step is:
step 1, judging the length of command data, directly transmitting the command of short bytes by taking the safe transmission limit of each system as a standard, and directly entering step 3; the command of long byte enters into the character identification step, namely step 2;
step 2, carrying out length segmentation on the long byte command and carrying out data identification;
step 21, except for the first segment, performing data storage by using a data space of one unit storage line less than the maximum safe transmission limit as a standard, and performing transmission data division by using a data space of two unit storage lines less than the maximum safe transmission limit as a standard in the rest segments; the first segment reserves a last blank line, and the other segments reserve two lines of an initial blank line and a last blank line until the byte length of the residual transmission data is just equal to or less than a maximum safe transmission limit;
step 22, identifying the end data of the segmented transmission data, copying the data of the second half segment of the last line of the first segment as the start of the first segment end blank line data, completing with zero padding, filling the data with complete padding into the initial blank line of the second segment, and so on, copying the data of the second half segment of the last line as the start of the second segment end blank line data, completing with zero padding, and filling the data with complete padding into the initial blank line of the third segment until all the data are identified;
step 23, entering step 3, and transmitting the segmented data;
and 3, transmitting data.
According to one aspect of the invention, after the data are segmented and identified, when the data are integrated again, the data can be matched according to the last data line and the first data line of different segments, when the data are overlapped, the identification matching is completed, the same line can be eliminated, and the data recombination can be directly carried out.
A method for judging cache data by characters is used for temporarily caching data in data transmission of a cloud platform, and comprises the following specific steps:
step 1, judging the properties of cache data, wherein one is used for segmenting data due to longer command length, the other is used for storing protective data due to unexpected interruption in system operation, the former data is transmitted after segmentation, and the latter is used for judging the increase of characters;
step 2, performing protective long-time storage on the cache segment containing the judgment character to ensure that the problem of data loss caused by system operation is avoided, and reserving the judgment character and then storing the judgment character again after confirming the data content; after the data content is confirmed, the data content to be deleted is judged, the data content is deleted after the judgment character is deleted, and the sufficient buffer space is ensured.
According to one aspect of the invention, the data processing protocols of the cache space of the specific cloud platform using system are different, and the method can be divided into a default ISO protocol and a self-defined protocol, so that the content judgment of the cache data is more intelligent.
Has the advantages that: the invention can solve the problem that the data management is difficult to unify due to too many connecting ports in the prior art, enhances the stability and the accuracy of parallel data transmission, further solves the problem of data confusion easily caused by parallel transmission, and increases the reliability of data transmission.
Drawings
FIG. 1 is a system control block diagram of the present invention.
Fig. 2 is a schematic diagram of the port control circuit of the present invention.
Fig. 3 is a flow chart of a data segment transmission method of the present invention.
Detailed Description
In this embodiment, as shown in fig. 1, a cloud platform is connected to a port control device, which includes a port control system, an upper layer detection communication system, a transmission system and a buffer storage system,
the port control system is characterized by comprising a port control circuit which can be specifically divided into an input current control module, an output protection module and a four-way control module, and the port data are grouped, so that synchronous processing branches of the multi-system data are realized, and the operation capacity and the operation speed of data processing are improved;
the upper detection communication system transmits the content of detection communication according to the self-defined transmission password, reduces the problem of data disorder caused by transmission protocol error and leakage and enhances the accuracy of data reception;
the transmission system is used for respectively carrying out data stream transmission of an upper layer and a lower layer on received data, and the two operation modes from top to bottom and from bottom to top are not interfered with each other;
the buffer storage system is used for buffering and storing data of a data error mode occurring in the transmission process, and finishing the re-uploading of the data after the buffered data is subjected to debugging processing according to a protocol algorithm, and is a transfer station in the cloud platform connection system;
the input current control module comprises an operational amplifier AR1, a motor MO1, an ammeter M1, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D11, a MOS transistor Q1, an inductor L1 and a resistor R1, wherein the anode of the diode D11 is connected with a voltage signal Vref, the cathode of the diode D11 is connected with the second pin of the operational amplifier AR1, the first pin of the operational amplifier AR1 is connected with the fourth pin of the operational amplifier AR1, the fifth pin of the operational amplifier AR1, the seventh pin of the operational amplifier AR1 and the eighth pin of the operational amplifier AR1 are all open circuits, the sixth pin of the operational amplifier AR1 is connected with one end of the motor MO1, and the other end of the motor MO1 is respectively connected with one end of the inductor L1, the cathode of the diode D3 and the cathode of the diode D1, the other end of the inductor L1 is connected to the anode of the diode D5 and the D-pole of the MOS transistor Q1, the cathode of the diode D5 is connected to one end of the resistor R1 and the third pin of the operational amplifier AR1, the other end of the resistor R1 is connected to the S-pole of the MOS transistor Q1, the anode of the diode D4 and the anode of the diode D2, the cathode of the diode D4 is connected to the anode of the diode D3 and one end of the ammeter M1, and the cathode of the diode D2 is connected to the anode of the diode D1 and the other end of the ammeter M1;
the output protection module comprises a bridge DB1, an operational amplifier AR2, a MOS transistor Q2, a diode D6, a resistor R6, a capacitor C6, and a capacitor C6, wherein a second pin of the bridge DB 6 is connected to one end of the resistor R6, one end of the capacitor C6, and one end of the capacitor C6, a fourth pin of the bridge DB 6 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to an anode of the diode D6 and an S-pole of the MOS transistor Q6, a cathode of the diode D6 is connected to the other end of the capacitor C6, the S-pole of the MOS transistor Q6 is grounded, the other end of the resistor R6 is connected to a G-pole of the MOS transistor Q6, the other end of the capacitor C6 is connected to the second pin of the resistor R6, and the other end of the capacitor R6 are connected to the second pin of the resistor R6, a first pin of the operational amplifier AR2, a fourth pin of the operational amplifier AR2, a fifth pin of the operational amplifier AR2, a seventh pin of the operational amplifier AR2, and an eighth pin of the operational amplifier AR2 are all open circuits, a sixth pin of the operational amplifier AR2 is respectively connected to a voltage signal Vout and one end of the resistor R5, a third pin of the operational amplifier AR2 is respectively connected to the other end of the resistor R5 and one end of the capacitor C4, and the other end of the capacitor C4 is grounded;
the four-way control module comprises an integrated chip U1, an oscillator Y1, a switch S1, a triode Q3, a triode Q4, a MOS tube Q5, a MOS tube Q6, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, an inductor L2, an inductor L3, an inductor L4, a diode D7, a diode D8, a diode D9 and a diode D10, wherein a first pin of the bridge DB1 is connected with one end of the resistor R7, a sixteenth pin of the integrated chip U1, a fourth pin of the integrated chip U1 and a voltage signal Vcc, the other end of the resistor R7 is connected with a seventh pin of the integrated chip U1, a third pin of the DB1 is connected with a ninth pin of the integrated chip U1, and a twelfth pin of the integrated chip U1 are connected with the eleventh pin of the integrated chip U1 and the twelfth pin of the integrated chip 1, A thirteenth pin of the integrated chip U1, a fourteenth pin of the integrated chip U1, and a fifteenth pin of the integrated chip U1 are all open circuits, a sixth pin of the integrated chip U1 is connected to one end of the oscillator Y1 and one end of the inductor L3, the other end of the inductor L3 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the other end of the oscillator Y1 and one end of the switch S1, the other end of the switch S1 is connected to the first pin of the integrated chip U1, the eighth pin of the integrated chip U1 is grounded, a third pin of the integrated chip U1 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to the G-pole of the MOS transistor Q5 and the G-pole of the MOS transistor Q6, and a second pin of the integrated chip U1 is connected to one end of the resistor R9, One end of the capacitor C9 is connected, the other end of the capacitor C9 is grounded, the other end of the resistor R9 is connected to a voltage signal Vref, the fifth pin of the integrated chip U1 is connected to one end of the inductor L2, the other end of the inductor L2 is connected to the emitter of the transistor Q3, the cathode of the diode D7, one end of the capacitor C5, the emitter of the transistor Q4, the cathode of the diode D8, and one end of the capacitor C6, the base of the transistor Q4 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the base of the transistor Q3, the voltage signal Vin, and the G of the MOS transistor Q1, the collector of the transistor Q3 is connected to the anode of the diode D7, the other end of the capacitor C5, the D of the MOS transistor Q5, the anode of the diode D9, and one end of the capacitor C7, the other end of the capacitor C7 is connected to the cathode of the diode D9, the S-pole of the MOS transistor Q5, the D-pole of the MOS transistor Q6, the cathode of the diode D10, and one end of the capacitor C8, and the other end of the capacitor C8 is connected to the anode of the diode D10, the S-pole of the MOS transistor Q6, the other end of the capacitor C6, the anode of the diode D8, and the collector of the transistor Q4.
In a further embodiment, the ammeter M1 is respectively connected to the connection nodes of the two current branches, so that the current comparison between the two current branches can be directly performed, and when the measured current value is too large, it indicates that the current value of the branch exceeds the safety range, and the input voltage needs to be adjusted.
In a further embodiment, the transistor Q3, the transistor Q4, the MOS transistor Q5, and the MOS transistor Q6 belong to a control branch, respectively, and can perform parallel processing on four paths of data; the diode D7, the diode D8, the diode D9 and the diode D10 respectively control the strength of the current signal of the input branch circuit to perform phase conversion.
In a further embodiment, the transmission system can be directly internally divided into a top-down data receiving branch and a bottom-up data transmitting branch, and the two branches operate independently and are in complementary interference.
In a further embodiment, the oscillator Y1 is connected in parallel with the branch circuit formed by the resistor R8 and the inductor L3, and the oscillation current is fed back and input through an external parallel electronic component, so as to ensure the stability of the oscillation circuit.
In a further embodiment, the resistor R9 and the diode D11 are connected to a voltage signal Vref, and a uniform reference voltage setting is performed on the voltage reference terminal and the current detection branch of the integrated chip U1, so that no matching error or leakage of current magnitude is generated due to voltage distortion in the process of parallel data processing.
A data segmentation transmission method, in the course of cloud platform data transmission, because need carry on the concurrent parallel transmission to the data of multiple systems, while the order of the long byte is transmitted, need carry on the segmentation transmission, in order to avoid appearing the confusion of the data recombination, need label the same data order, guarantee the integrality of data reception, the concrete step is:
step 1, judging the length of command data, directly transmitting the command of short bytes by taking the safe transmission limit of each system as a standard, and directly entering step 3; the command of long byte enters into the character identification step, namely step 2;
step 2, carrying out length segmentation on the long byte command and carrying out data identification;
step 21, except for the first segment, performing data storage by using a data space of one unit storage line less than the maximum safe transmission limit as a standard, and performing transmission data division by using a data space of two unit storage lines less than the maximum safe transmission limit as a standard in the rest segments; the first segment reserves a last blank line, and the other segments reserve two lines of an initial blank line and a last blank line until the byte length of the residual transmission data is just equal to or less than a maximum safe transmission limit;
step 22, identifying the end data of the segmented transmission data, copying the data of the second half segment of the last line of the first segment as the start of the first segment end blank line data, completing with zero padding, filling the data with complete padding into the initial blank line of the second segment, and so on, copying the data of the second half segment of the last line as the start of the second segment end blank line data, completing with zero padding, and filling the data with complete padding into the initial blank line of the third segment until all the data are identified;
step 23, entering step 3, and transmitting the segmented data;
and 3, transmitting data.
In a further embodiment, after the data are segmented and identified, when the data are integrated again, data matching can be performed according to the last data line and the first data line of different segments, when the data are overlapped, the identification matching is completed, the same line can be eliminated, and the data recombination can be directly performed.
A method for judging cache data by characters is used for temporarily caching data in data transmission of a cloud platform, and comprises the following specific steps:
step 1, judging the properties of cache data, wherein one is used for segmenting data due to longer command length, the other is used for storing protective data due to unexpected interruption in system operation, the former data is transmitted after segmentation, and the latter is used for judging the increase of characters;
step 2, performing protective long-time storage on the cache segment containing the judgment character to ensure that the problem of data loss caused by system operation is avoided, and reserving the judgment character and then storing the judgment character again after confirming the data content; after the data content is confirmed, the data content to be deleted is judged, the data content is deleted after the judgment character is deleted, and the sufficient buffer space is ensured.
In a further embodiment, the specific cloud platform usage system has different data processing protocols for the cache space, and the method can be divided into a default ISO protocol and a custom protocol, so that the content judgment of the cache data is more intelligent.
In summary, the present invention has the following advantages: the circuit regulation and control are carried out on the multi-path connecting port, the stability and the feasibility of multi-path parallel data transmission are enhanced, the identification segmentation and the buffer storage are further carried out on the long command data in the parallel data transmission, the accuracy of data transmission is improved, overall speaking, the running speed and the data self-error correction capability of the data transmission are greatly enhanced, and the practicability is high.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.