WO2020220673A1 - 一种稳压电路、控制方法及显示装置 - Google Patents

一种稳压电路、控制方法及显示装置 Download PDF

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Publication number
WO2020220673A1
WO2020220673A1 PCT/CN2019/122526 CN2019122526W WO2020220673A1 WO 2020220673 A1 WO2020220673 A1 WO 2020220673A1 CN 2019122526 W CN2019122526 W CN 2019122526W WO 2020220673 A1 WO2020220673 A1 WO 2020220673A1
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Prior art keywords
transistor
electrically connected
terminal
power management
integrated circuit
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PCT/CN2019/122526
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English (en)
French (fr)
Inventor
王添鸿
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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Priority to US16/623,768 priority Critical patent/US11138948B2/en
Publication of WO2020220673A1 publication Critical patent/WO2020220673A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the invention relates to the technical field of voltage stabilization of display circuits, and more specifically, to a voltage stabilizing circuit, a control method and a display device.
  • LCD Liquid Crystal Display
  • other flat display devices are widely used in mobile phones, televisions, personal digital assistants, digital cameras, and notebooks due to their advantages of high image quality, power saving, thin body and wide application range.
  • Various consumer electronic products such as computers and desktop computers have become the mainstream of display devices.
  • each sub-pixel has a thin film transistor (TFT), the gate of which is connected to the horizontal scan line, the drain is connected to the vertical data line, and the source is connected to Pixel electrode.
  • TFT thin film transistor
  • Applying enough voltage on the horizontal scan line will turn on all the TFTs on the horizontal scan line.
  • the pixel electrode on the horizontal scan line will be connected to the data line in the vertical direction, thereby connecting the data line
  • the display signal voltage is written into the pixels to control the transmittance of different liquid crystals to achieve the effect of color control.
  • the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly completed by the external chip (IC) of the panel, and the external IC can control the charging and discharging of the horizontal scanning lines at all levels.
  • GOA Array substrate line drive
  • FIG. 1 is a GOA circuit diagram of the prior art, in which the Gn output node is connected to the transistor T21 and the transistor T31.
  • the GOA circuit For the GOA circuit to work normally, it needs to have an STV signal that controls the opening of the GOA and a clock signal (CLOCK, abbreviated as CK) that controls the output of the GOA.
  • CLOCK clock signal
  • the Gate output needs to be pulled down to the VSSG potential.
  • another low potential VGL potential is introduced.
  • FIG. 2 is a schematic diagram of a node waveform during normal operation in the prior art.
  • Figure 2 shows the operating waveform of a specific embodiment G3 of the node Gn, when the duty cycle of the clock signal is 40% or 60%.
  • Q3 is still high, and Gn is pulled down to CKL (VGL) through T21.
  • CK1 is high
  • G5 is high.
  • T31 is turned on, because the node Gn that GOA outputs the Gate signal is pulling down to
  • the potential is low, one path is pulled down to VSSG through T31, and the other path is pulled down to VGL through T21.
  • FIG. 3 is a circuit diagram of a prior art VSSG generating circuit.
  • PMIC Power Management IC, power management integrated circuit
  • PMIC Power Management IC, power management integrated circuit
  • R90 and C1 voltage stabilizing RC circuits are usually added to the conventional system board.
  • R90 is a fixed resistor. You can change the resistance after connecting to the LCD to stabilize the VSSG at the set value.
  • FIG 4 is a schematic diagram of current-voltage changes during transistor aging.
  • IV drifts in the positive direction, and its output current I off will decrease, causing the resistance value of R on to increase and I on to decrease , And the V ds voltage does not change, so the resistance of the TFT becomes larger, making the resistance value of the equivalent resistance R equal larger.
  • VSSG is controlled by the PMIC to divide the VGL output A potential, so Requal changes, its partial pressure also changes, resulting in a change in VSSG potential.
  • the voltage stabilizing circuit in the prior art VSSG generating circuit has defects, and a voltage stabilizing circuit that can solve the problem of VSSG potential drift caused by the aging of the transistor is needed.
  • the invention provides a voltage stabilizing circuit, a control method and a display device, which solves the problem of VSSG potential drift caused by transistor aging in the prior art.
  • the present invention provides a voltage stabilizing circuit including a first transistor, a second transistor, and a third transistor;
  • the source of the first transistor is electrically connected to the drain of the second transistor and the gate of the third transistor, and the drain of the first transistor is electrically connected to the first control of the power management integrated circuit Output terminal, the gate of the first transistor is electrically connected to the second control output terminal of the power management integrated circuit, and the gate of the second transistor is electrically connected to the second control output terminal of the power management integrated circuit
  • the output terminal, the drain of the third transistor is electrically connected to the first level terminal for connecting to the display panel.
  • the first level terminal is also electrically connected to one end of the voltage stabilizing capacitor.
  • the first level terminal is electrically connected to the third control output terminal of the power management integrated circuit through a triode.
  • the base of the triode is electrically connected to the third control output terminal of the power management integrated circuit, and the collector of the triode is electrically connected to the first level terminal , The emitter of the triode is electrically connected to the second level terminal.
  • the second level terminal is electrically connected to the display panel, and an equivalent resistance is formed in the display panel between the first level terminal and the second level terminal .
  • the first level terminal is also electrically connected to the feedback terminal of the power management integrated circuit, and when the voltage of the gate of the first transistor changes, the The first level terminal feeds back the change signal to the feedback terminal of the power management integrated circuit.
  • the first level terminal is electrically connected to the display panel through a level conversion circuit.
  • the third transistor works in a linear region.
  • a method for controlling a voltage stabilizing circuit is provided, which is implemented by using the voltage stabilizing circuit described above, including:
  • the power management integrated circuit respectively outputs a first voltage signal through a first control output terminal and a second voltage signal through a second control output terminal, where the first voltage signal is different from the second voltage signal;
  • a change signal is fed back to the feedback end of the power management integrated circuit through the first level terminal, and the power management integrated circuit randomly adjusts according to the change signal.
  • the first voltage signal and the second voltage signal are fed back to the feedback end of the power management integrated circuit through the first level terminal, and the power management integrated circuit randomly adjusts according to the change signal.
  • a display device including the voltage stabilizing circuit described above.
  • Figure 1 is a GOA circuit diagram of the prior art
  • Fig. 2 is a schematic diagram of a node waveform during normal operation in the prior art
  • Figure 3 is a circuit diagram of a prior art VSSG generating circuit
  • Figure 4 is a schematic diagram of current-voltage changes during transistor aging
  • Figure 5 is a voltage stabilizing circuit diagram provided by an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a VSSG generating circuit provided by an embodiment of the present invention.
  • the voltage stabilizing circuit provided by the present invention can be applied to GOA (Gate Driver On Array, line scanning technology integrated on the array substrate), and is especially suitable for a-siGOA (non-standard) in active LCD (Liquid Crystal Display).
  • GOA Gate Driver On Array, line scanning technology integrated on the array substrate
  • a-siGOA non-standard
  • active LCD Liquid Crystal Display
  • FIG. 5 is a diagram of a voltage stabilizing circuit provided by an embodiment of the present invention.
  • the voltage stabilizing circuit includes a first transistor 1, a second transistor 2 and a third transistor 3.
  • the source of the first transistor 1 is electrically connected to the drain of the second transistor 2 and the gate of the third transistor 3, and the drain of the first transistor 1 is electrically connected to the power management
  • the first control output terminal 51 of the integrated circuit 5 PMIC, Power Management IC
  • the gate of the first transistor 1 is electrically connected to the second control output terminal 52 of the power management integrated circuit 5
  • the second The gate of the transistor 2 is electrically connected to the second control output terminal 52 of the power management integrated circuit 5
  • the drain of the third transistor 3 is electrically connected to the first level terminal 4 for connecting to the display panel 10.
  • the first transistor 1, the second transistor 2 and the third transistor 3 are field effect transistors
  • the display panel 10 is an LCD panel.
  • FIG. 6 is a diagram of the VSSG generating circuit provided by an embodiment of the present invention.
  • the first level terminal 4 is also electrically connected to one end of the voltage stabilizing capacitor 8.
  • the first level terminal 4 is electrically connected to the third control output terminal 53 of the power management integrated circuit 5 through a transistor 6, wherein the base of the transistor 6 is electrically connected to the power management integrated circuit 5
  • the third control output terminal 53, the collector of the triode 6 is electrically connected to the first level terminal 4, and the emitter of the triode 6 is electrically connected to the second level terminal 7.
  • the second level terminal 7 is electrically connected to the display panel 10, and an equivalent resistance is formed between the first level terminal 4 and the second level terminal 7 in the display panel 10.
  • the first level terminal 4 is also electrically connected to the feedback terminal 54 of the power management integrated circuit 5.
  • the first voltage The flat terminal 4 feeds back a change signal to the feedback terminal 54 of the power management integrated circuit 5.
  • the first level terminal 4 is electrically connected to the display panel 10 through a level conversion circuit 9.
  • the gate voltage of the third transistor 3 is ensured to be in a certain range, so that the third transistor 3 works in the linear region.
  • the present invention also provides a control method of a voltage stabilizing circuit, which is realized by adopting the voltage stabilizing circuit as described above, and is realized by implanting a program in the power management integrated circuit 5.
  • the control method includes steps S1-S2:
  • the power management integrated circuit 5 outputs a first voltage signal through the first control output terminal 51 and a second voltage signal through the second control output terminal 52, the first voltage signal is different from the second voltage signal;
  • the R90 shown in Figure 3 is replaced with a voltage stabilizing circuit composed of 3 transistors (T1, T2, T3); among them, Vdd1 and Vdd2 are two different high potentials controlled by the PMIC.
  • the change signal is fed back to the feedback terminal 54 of the power management integrated circuit 5 through the first level terminal 4, and the power management integrated circuit 5 is based on The change signal randomly adjusts the first voltage signal and the second voltage signal respectively. That is, when the gate voltage of the first transistor 1 changes, the PMIC receives the feedback signal and randomly adjusts the voltages of Vdd1 and Vdd2 to change the voltage division state of the first transistor 1 and the second transistor 2, so that the third transistor When the gate voltage of 3 changes, the equivalent resistance between the drain and source of the third transistor 3 changes accordingly, and the purpose of adjusting the VSSG voltage can be achieved.
  • the present invention also provides a display device, which includes the voltage stabilizing circuit described above.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种稳压电路、控制方法及显示装置，电路包括第一晶体管（1）、第二晶体管（2）及第三晶体管（3）；第一晶体管（1）的源极电性连接于第二晶体管（2）的漏极及第三晶体管（3）的栅极，第一晶体管（1）的漏极电性连接于电源管理集成电路（5）的第一控制输出端（51），第一晶体管（1）的栅极电性连接于电源管理集成电路（5）的第二控制输出端（52），第二晶体管（2）的栅极电性连接于电源管理集成电路（5）的第二控制输出端（52），第三晶体管（3）的漏极电性连接于用于连接显示面板（10）的第一电平端（4）。解决了晶体管老化带来VSSG电位飘移的问题，进一步保证显示面板（10）正常工作。

Description

一种稳压电路、控制方法及显示装置 技术领域
本发明涉及显示器电路稳压技术领域，更具体地说，涉及一种稳压电路、控制方法及显示装置。
 背景技术
液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
主动式液晶显示器中，每个子像素具有一个薄膜晶体管(TFT)，其栅极(Gate)连接至水平扫描线，漏极(Drain)连接至垂直方向的数据线，源极(Source)则连接至像素电极。在水平扫描线上施加足够的电压，会使得该条水平扫描线上的所有TFT打开，此时该条水平扫描线上的像素电极会与垂直方向上的数据线连通，从而将数据线上的显示信号电压写入像素，控制不同液晶的透光度进而达到控制色彩的效果。目前主动式液晶显示面板水平扫描线的驱动主要由面板外接的芯片（IC）来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。阵列基板行驱动（Gate Driver On Array，简称GOA）技术，也就是利用现有薄膜晶体管液晶显示器阵列（Array）制程将栅极（Gate）行扫描驱动信号电路制作在Array基板上，实现对Gate逐行扫描的驱动方式。
参见图1，图1为现有技术的GOA电路图，其中Gn输出节点连接晶体管T21及晶体管T31。GOA电路若要正常工作，需要有控制GOA开启的STV讯号以及控制GOA输出的时钟讯号（CLOCK，后续简写为CK）。同时，GOA不进行工作时，需要把Gate输出拉低至VSSG电位。为了能够更好的保证好GOA电路内部TFT的开关状态，因此引入了另一个低电位VGL电位。
参见图2，图2为现有技术的正常工作时的节点波形示意图，图2示出了节点Gn的一个具体实施例G3的工作波形，在时钟信号的占空比为40%或者60%的情况下，在G3下拉阶段，Q3依旧为高，Gn通过T21下拉至CKL（即VGL），当CK1为高时，G5为高，此时T31打开，因GOA输出Gate讯号的节点Gn在下拉至低电位时，一个路径是通过T31下拉至VSSG，另一个路径是通过T21下拉至VGL。因此，VGL以及VSSG之间存在一个等效电阻（T21以及T31两颗TFT在开启状态下的形成的开态电阻R21、R31），其阻值大小R equal=R31+R21。待Q3为低时，T21关闭，因TFT的关闭电阻较大，所以CKL以及VSSG之间相当于开路；此为单级情况下的情况，因为GOA逐级打开，所以从LCD外部看，CKL以及VSSG之间一直存在着一个等效电阻。
参见图3，图3为现有技术的VSSG发生电路图，PMIC（Power Management IC，电源管理集成电路）产生一个I B电流通过一个BJT管，使得该BJT管变成一个电阻，其阻值为R BJT。系统板设计初期，无法将其连接LCD来调整I B电流，通常是系统端自行设定一个理论的I B值，将输出一个VSSG的理想值。一旦后续连接至LCD面板，存在一个R equal后，放大系数Av=[-β*（R c‖R equal）]/I B*R be。此时I B不变，导致放大系数Av变大，使得VSSG发生变化，可能导致LCD出现异常。因此，通常会在常规系统板上加上R90以及C1的稳压RC电路，此时R90是个固定电阻，可以在连接LCD后去更换该阻值，来使VSSG稳定在设定值。
参见图4，图4为晶体管老化过程中的电流-电压变化示意图，在晶体管老化（aging）后，I-V正向漂移，其输出电流I off会下降，导致R on阻值变大，I on降低，而V ds电压不变，因此TFT的电阻变大，使得等效电阻的阻值R equal变大，在系统板上（C-Board），VSSG是通过PMIC控制，将VGL进行分压输出的一个电位，因此Requal变化，其分压也随之发生变化，导致VSSG电位发生变化。
因此，现有技术的VSSG发生电路中的稳压电路存在缺陷，需要一种可解决晶体管老化带来VSSG电位飘移问题的稳压电路。
 技术问题
本发明提供了一种稳压电路、控制方法及显示装置，解决现有技术中晶体管老化带来VSSG电位飘移的问题。
 技术解决方案
一方面，本发明提供了一种稳压电路，包括第一晶体管、第二晶体管及第三晶体管；
所述第一晶体管的源极电性连接于所述第二晶体管的漏极及所述第三晶体管的栅极，所述第一晶体管的漏极电性连接于电源管理集成电路的第一控制输出端，所述第一晶体管的栅极电性连接于所述电源管理集成电路的第二控制输出端，所述第二晶体管的栅极电性连接于所述电源管理集成电路的第二控制输出端，所述第三晶体管的漏极电性连接于用于连接显示面板的第一电平端。
在本发明所述的稳压电路中，所述第一电平端还电性连接于稳压电容的一端。
在本发明所述的稳压电路中，所述第一电平端通过三极管电性连接于所述电源管理集成电路的第三控制输出端。
在本发明所述的稳压电路中，所述三极管的基极电性连接于所述电源管理集成电路的第三控制输出端，所述三极管的集电极电性连接于所述第一电平端，所述三极管的发射极电性连接于第二电平端。
在本发明所述的稳压电路中，所述第二电平端电性连接于所述显示面板，所述第一电平端及所述第二电平端之间于显示面板中形成一等效电阻。
在本发明所述的稳压电路中，所述第一电平端还电性连接于所述电源管理集成电路的反馈端，当所述第一晶体管的栅极的电压发生变化时，通过所述第一电平端向所述电源管理集成电路的反馈端反馈变化信号。
在本发明所述的稳压电路中，所述第一电平端通过电平转换电路电性连接于所述显示面板。
在本发明所述的稳压电路中，所述第三晶体管工作在线性区。
一方面，提供一种稳压电路的控制方法，采用如上所述的稳压电路实现，包括：
电源管理集成电路分别通过第一控制输出端输出第一电压信号及通过第二控制输出端输出第二电压信号，所述第一电压信号异于所述第二电压信号；
当所述第一晶体管的栅极的电压发生变化时，通过所述第一电平端向所述电源管理集成电路的反馈端反馈变化信号，所述电源管理集成电路依据所述变化信号分别随机调整所述第一电压信号及所述第二电压信号。
一方面，提供一种显示装置，包括如上所述的稳压电路。
 有益效果
解决晶体管老化带来VSSG电位飘移的问题，进一步保证显示面板正常工作。
 附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1为现有技术的GOA电路图；
图2为现有技术的正常工作时的节点波形示意图；
图3为现有技术的VSSG发生电路图；
图4为晶体管老化过程中的电流-电压变化示意图；
图5为本发明实施例提供的稳压电路图；
图6为本发明实施例提供的VSSG发生电路图。
 本发明的实施方式
为了对本发明的技术特征、目的和效果有更加清楚的理解，现对照附图详细说明本发明的具体实施方式。
本发明提供的一种稳压电路，可以应用在GOA（Gate Driver On Array，集成在阵列基板上的行扫描技术）中，尤其适用于主动型LCD（Liquid Crystal Display）中的a-siGOA（非晶硅薄膜晶体管的GOA）产品。
参见图5，图5为本发明实施例提供的稳压电路图，该稳压电路包括第一晶体管1、第二晶体管2及第三晶体管3。其中，所述第一晶体管1的源极电性连接于所述第二晶体管2的漏极及所述第三晶体管3的栅极，所述第一晶体管1的漏极电性连接于电源管理集成电路5（PMIC，Power Management IC）的第一控制输出端51，所述第一晶体管1的栅极电性连接于所述电源管理集成电路5的第二控制输出端52，所述第二晶体管2的栅极电性连接于所述电源管理集成电路5的第二控制输出端52，所述第三晶体管3的漏极电性连接于用于连接显示面板10的第一电平端4。优选的，第一晶体管1、第二晶体管2及第三晶体管3为场效应管，显示面板10是LCD面板。
本发明的稳压电路应用于VSSG发生电路如图6所示，图6为本发明实施例提供的VSSG发生电路图，所述第一电平端4还电性连接于稳压电容8的一端。所述第一电平端4通过三极管6电性连接于所述电源管理集成电路5的第三控制输出端53，其中，所述三极管6的基极电性连接于所述电源管理集成电路5的第三控制输出端53，所述三极管6的集电极电性连接于所述第一电平端4，所述三极管6的发射极电性连接于第二电平端7。
所述第二电平端7电性连接于所述显示面板10，所述第一电平端4及所述第二电平端7之间于显示面板10中形成一等效电阻。该等效电阻即为背景技术中的等效电阻，其阻值大小R equal=R31+R21。
图6中，所述第一电平端4还电性连接于所述电源管理集成电路5的反馈端54，当所述第一晶体管1的栅极的电压发生变化时，通过所述第一电平端4向所述电源管理集成电路5的反馈端54反馈变化信号。所述第一电平端4通过电平转换电路9电性连接于所述显示面板10。
通过调整第一晶体管1及第二晶体管2的器件大小与沟道长度，以及其比例关系，来保证第三晶体管3的栅极电压处于一定范围，使得第三晶体管3工作在线性区。
本发明还提供一种稳压电路的控制方法，采用如上所述的稳压电路实现，同时通过在电源管理集成电路5中植入程序实现，该控制方法包括步骤S1-S2：
S1、电源管理集成电路5分别通过第一控制输出端51输出第一电压信号及通过第二控制输出端52输出第二电压信号，所述第一电压信号异于所述第二电压信号；即将图3所示的R90替换成一个由3颗晶体管（T1,T2,T3）组成的稳压电路；其中，Vdd1与Vdd2是受PMIC控制输出的两个不同高电位。
S2、当所述第一晶体管1的栅极的电压发生变化时，通过所述第一电平端4向所述电源管理集成电路5的反馈端54反馈变化信号，所述电源管理集成电路5依据所述变化信号分别随机调整所述第一电压信号及所述第二电压信号。即当第一晶体管1的栅极电压发生变化时，PMIC收到反馈讯号，随机调整Vdd1以及Vdd2的电压大小，即可改变第一晶体管1以及第二晶体管2的分压状态，使得第三晶体管3的栅极电压发生改变，第三晶体管3的漏极与源极之间的等效电阻随之发生变化，即可达到调节VSSG电压的目的。
此外，本发明还提供一种显示装置，该显示装置包括如上所述的稳压电路。
上面结合附图对本发明的实施例进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。

Claims (11)

  1. 一种稳压电路，其中，包括第一晶体管、第二晶体管及第三晶体管；
    所述第一晶体管的源极电性连接于所述第二晶体管的漏极及所述第三晶体管的栅极，所述第一晶体管的漏极电性连接于电源管理集成电路的第一控制输出端，所述第一晶体管的栅极电性连接于所述电源管理集成电路的第二控制输出端，所述第二晶体管的栅极电性连接于所述电源管理集成电路的第二控制输出端，所述第三晶体管的漏极电性连接于用于连接显示面板的第一电平端；所述第一电平端通过三极管电性连接于所述电源管理集成电路的第三控制输出端。
  2. 根据权利要求1所述的稳压电路，其中，所述第一电平端还电性连接于稳压电容的一端。
  3. 根据权利要求1所述的稳压电路，其中，所述第一电平端还电性连接于所述电源管理集成电路的反馈端，当所述第一晶体管的栅极的电压发生变化时，通过所述第一电平端向所述电源管理集成电路的反馈端反馈变化信号。
  4. 根据权利要求1所述的稳压电路，其中，所述三极管的基极电性连接于所述电源管理集成电路的第三控制输出端，所述三极管的集电极电性连接于所述第一电平端，所述三极管的发射极电性连接于第二电平端。
  5. 根据权利要求4所述的稳压电路，其中，所述第一电平端还电性连接于所述电源管理集成电路的反馈端，当所述第一晶体管的栅极的电压发生变化时，通过所述第一电平端向所述电源管理集成电路的反馈端反馈变化信号。
  6. 根据权利要求4所述的稳压电路，其中，所述第二电平端电性连接于所述显示面板，所述第一电平端及所述第二电平端之间于显示面板中形成一等效电阻。
  7. 根据权利要求6所述的稳压电路，其中，所述第一电平端还电性连接于所述电源管理集成电路的反馈端，当所述第一晶体管的栅极的电压发生变化时，通过所述第一电平端向所述电源管理集成电路的反馈端反馈变化信号。
  8. 根据权利要求1所述的稳压电路，其中，所述第一电平端通过电平转换电路电性连接于所述显示面板。
  9. 根据权利要求1所述的稳压电路，其中，所述第三晶体管工作在线性区。
  10. 一种稳压电路的控制方法，采用如权利要求1所述的稳压电路实现，其中，包括：
    电源管理集成电路分别通过第一控制输出端输出第一电压信号及通过第二控制输出端输出第二电压信号，所述第一电压信号异于所述第二电压信号；
    当所述第一晶体管的栅极的电压发生变化时，通过所述第一电平端向所述电源管理集成电路的反馈端反馈变化信号，所述电源管理集成电路依据所述变化信号分别随机调整所述第一电压信号及所述第二电压信号。
  11. 一种显示装置，其中，包括如权利要求1所述的稳压电路。
PCT/CN2019/122526 2019-04-29 2019-12-03 一种稳压电路、控制方法及显示装置 Ceased WO2020220673A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100020057A1 (en) * 2008-07-28 2010-01-28 Samsung Electronics Co., Ltd. Power circuit and liquid crystal display having the same
CN105304047A (zh) * 2015-11-19 2016-02-03 深圳市华星光电技术有限公司 保护电路及具有该保护电路的液晶显示器
CN107424577A (zh) * 2017-08-15 2017-12-01 京东方科技集团股份有限公司 一种显示驱动电路、显示装置及其驱动方法
CN107731186A (zh) * 2017-10-31 2018-02-23 京东方科技集团股份有限公司 一种控制电路、控制方法及显示装置
CN110010099A (zh) * 2019-04-29 2019-07-12 深圳市华星光电技术有限公司 一种稳压电路、控制方法及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482496B2 (en) * 2006-01-06 2013-07-09 Pixtronix, Inc. Circuits for controlling MEMS display apparatus on a transparent substrate
TWI408542B (zh) * 2005-05-12 2013-09-11 Lg Display Co Ltd 用於供應電源的設備
KR100669205B1 (ko) * 2005-06-17 2007-01-16 엘지전자 주식회사 듀얼 평판 표시장치의 구동장치
US7471148B2 (en) * 2007-05-21 2008-12-30 Sekio Epson Corporation Differential low noise amplifier (LNA) with common mode feedback and gain control
CN106488607B (zh) * 2016-09-09 2018-04-10 深圳创维－Rgb电子有限公司 开关电源及电视机
CN106710566B (zh) * 2017-03-31 2018-09-28 京东方科技集团股份有限公司 放电电路及其驱动方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100020057A1 (en) * 2008-07-28 2010-01-28 Samsung Electronics Co., Ltd. Power circuit and liquid crystal display having the same
CN105304047A (zh) * 2015-11-19 2016-02-03 深圳市华星光电技术有限公司 保护电路及具有该保护电路的液晶显示器
CN107424577A (zh) * 2017-08-15 2017-12-01 京东方科技集团股份有限公司 一种显示驱动电路、显示装置及其驱动方法
CN107731186A (zh) * 2017-10-31 2018-02-23 京东方科技集团股份有限公司 一种控制电路、控制方法及显示装置
CN110010099A (zh) * 2019-04-29 2019-07-12 深圳市华星光电技术有限公司 一种稳压电路、控制方法及显示装置

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