WO2020220538A1 - Inverter driving system with ultra-low switching power consumption and ultra-low output end electromagnetic interference - Google Patents

Abstract

The invention discloses an inverter driving system with ultra-low switching power consumption and ultra-low output end electromagnetic interference, comprising a three-phase driving system. Each phase driving system is an independent system and comprises a feedback control unit, a comparative control unit and a power switch circuit. Each feedback control unit calculates output setting current i set(t) required for the phase by inputting a sinusoidal input signal u sin(t), and an output end voltage feedback signal u out(t) and an output current feedback signal i out(t) fed back by the power switch circuit, and outputs the output setting current i set(t) required for the phase to the comparative control unit. Each comparison control unit calculates an inductance peak current I peak(t) required for switching of a switching state by outputting setting current i set(t) and the structural characteristics of the power switch circuit, compares with the inductance current i L(t) measured in real time to determine the switching state corresponding to a switching device in the power switch circuit, and outputs a switch state signal to the power switch circuit. According to the invention, low switching loss and low output end high frequency electromagnetic interference are achieved.

Description

An inverter drive system with ultra-low switching power consumption and ultra-low output end electromagnetic interference Technical field

The present invention relates to the technical field of frequency converters, in particular to an inverter drive system with ultra-low switching power consumption and ultra-low output end electromagnetic interference.

Background technique

In the conventional inverter drive system, since the inverter modulates the output through high-frequency switching, the switching process produces extremely high du/dt at the output, which will generate a large common mode through the parasitic capacitance of the cable and the motor winding to the ground. interference. Therefore, it is necessary to use a π-filter or a power cable with a shield in a long distance and sensitive application environment to electromagnetic interference. In the case of the same output power, when a lower switching frequency is used, the filter size will be greatly increased, and when a higher switching frequency is used, the switching loss generated by the power switching device will also increase at the same time. At the same time, it not only increases the weight and cost of the system, but also causes problems such as additional reactive power and grounding resistance of the wire shielding layer.

In the present invention, through the combination of the power switch device and the inductor-capacitor output circuit, the power switch device is operated in the boundary transmission mode BCM (Boundary Reduction Mode), and the low-frequency sinusoidal voltage and current output is maintained at the output end, and the inductor current is During the high-frequency switching cycle, the reverse switching current increases to the peak current and then decreases to the reverse switching current. In principle, it provides the output of a sinusoidal voltage circuit with low and higher harmonic components. At the same time, since the current of the inductor is negative at the beginning and end of each switching cycle, the zero voltage switching of the power switching device can be realized through this current. , Abbreviated ZVS), so as to achieve extremely low switching loss, thereby reducing the heat of the power switching device during high-frequency switching.

Summary of the invention

In order to solve the above-mentioned background art problems, the purpose of the present invention is to provide an inverter drive system with ultra-low switching power consumption and ultra-low electromagnetic interference at the output end.

In order to achieve the above objectives, the technical solutions adopted by the present invention are:

The invention provides an inverter drive system with ultra-low switching power consumption and ultra-low output end electromagnetic interference, including a three-phase drive system, each phase drive system is an independent system, and the output end of each phase drive system is sinusoidal AC, each The phase drive system includes the following parts: feedback control unit, comparison control unit and power switch circuit;

Each feedback control unit calculates the required value of the phase through input signals: sinusoidal input signal u _sin (t), output terminal voltage feedback signal u _out (t), output terminal current feedback signal i _out (t) Output the set current i _set (t), and output the output set current i _set (t) required by the phase to the comparison control unit of the drive system of the phase;

Each of the comparison control units uses the required output output set current i _set (t) and the real-time measured inductor current value i _L (t) from the feedback control unit of the phase drive system as input signals; The output setting current i _set (t) output by the control unit and the structural characteristics of the power switch circuit calculate the inductance peak current I _peak (t) and the intermediate comparison current I _comp (t) required when the switching state is switched, and measure them in real time. Compare the inductance current i _L (t) with the logic calculation to determine the corresponding switching state of the switching device in the power switching circuit, and output the switching state signal to the power switching circuit of the phase drive system;

For each of the power switch circuits, the input signal is the switching state signal output by the comparison control unit of the phase drive system; the output signal is the output terminal voltage feedback signal u _out (t), the output terminal current feedback signal i _out (t ) And the inductor current real-time measurement output signal i _L (t); the inductor current real-time measurement output signal i _L (t) is fed back to the comparison control unit of the phase drive system, and the output terminal voltage feedback signal u _out (t) And the output current feedback signal i _out (t) is fed back to the feedback control unit of the phase drive system;

The power input terminal of the power switch circuit is: the positive and negative poles (+U _in and -U _in ) of the input DC power supply, and the power output terminal of each power switch circuit is: a sinusoidal voltage output U _out (t), That is, the output terminal voltage of each phase drive system;

Among them, ω is the angular velocity, t is the actual time, and the reference point of U _A is the intermediate point potential of the input DC power supply, that is, half of the input DC power supply voltage.

In the above technical solution, the feedback control unit establishes a feedback control network through a sinusoidal input signal u _sin (t), an output voltage feedback signal u _out (t), and an output current feedback signal i _out (t), thereby calculating the The required output setting current i _set (t) of the phase, namely:

i _set (t)=G(u _sin (t), u _out (t), i _out (t))

Among them, the output voltage and current can be expressed as:

Where C _out is the capacity of the output capacitor;

The feedback control unit includes a PID controller; its specific workflow for establishing a feedback control network is:

(1) The voltage difference signal is obtained by comparing the sinusoidal voltage input signal u _sin (t) with the output voltage feedback signal u _out (t), and input to the PID controller;

(2) The charge and discharge current of the output capacitor C _{out is} obtained by calculating the derivative of the sinusoidal voltage input u _sin (t) with respect to time and multiplying it with the output capacitor capacity;

(3) The voltage difference feedback incremental current output by the PID controller in (1) is added to the output capacitor charging and discharging current obtained in (2) and the current output current i _out (t), and the result is the output setting current i _set (t), and input to the comparison control unit.

In the above technical solution, according to application requirements, the power switch circuit is divided into a half-bridge power switch circuit and a full-bridge power switch circuit, respectively corresponding to a low-power application environment and a high-power application environment.

In the above technical solution, each of the half-bridge power switch circuits includes a high-side switching device SW1, a low-side switching device SW2, and auxiliary switching capacitors C1 and C2 connected in parallel with the high-side switching device SW1 and the low-side switching device SW2, respectively. Coil L1 and output capacitors C3 and C4; the input end of the half-bridge power switch circuit is connected to the input end of the DC power supply, the inductor coil L1 is connected between the output end of the half-bridge power switch circuit and the output capacitors C3 and C4, and the output capacitors C3 and C4 Connected in series between the positive and negative terminals of the DC power supply input terminal;

Both the high-side switching device SW1 and the low-side switching device SW2 are controlled by a zero voltage switching (ZVS) gate driver.

In the above technical solution, the comparison control unit has a built-in comparator and a logic calculation unit, and sets a switching current I _const for zero voltage switching; the logic calculation unit sets the current i _set (t) according to the output output by the feedback control unit Calculate the inductor peak current I _peak (t) required for switching state switching with the structural characteristics of the half-bridge power switch circuit, and compare it with the inductor current i _L (t) measured in real time through a comparator. According to the half-bridge power The structure of the switch circuit determines the corresponding switch state to the power switch circuit, specifically:

In the half-bridge power switch circuit, the calculated relationship between the inductor peak current I _peak and the output set current i _set (t) is:

The corresponding switch state is:

When i _set (t)>0A,

When i _set (t)＜0A,

Among them, state 0 is off and 1 is on.

In the above technical solution, each of the full-bridge power switch circuits includes switching devices SW1, SW2, SW3, SW4, SW5, and auxiliary switching capacitors C1, C2, C3 connected in parallel with the switching devices SW1, SW2, SW3, SW4, SW5, respectively , C4, C5, the inductor L1, and the output capacitors C6, C7; the switching devices SW1 and SW2 are connected in series between the positive and negative terminals of the DC power supply input terminal, and the switching devices SW3 and SW4 are connected in series between the positive and negative terminals of the DC power supply input terminal The left and right half bridges in the full-bridge switching circuit are formed respectively; the input end of the full-bridge power switch circuit is connected to the input end of the DC power supply, and the inductor L1 is connected to one of the half-bridge output ends on both sides of the full-bridge switching circuit. The output switching device SW5 is connected between the output capacitors C6 and C7 and the right half-bridge output of the full-bridge switching circuit; the output capacitors C6 and C7 are connected in series between the positive and negative terminals of the DC power supply input.

The switching devices SW1, SW2, SW3, SW4, and SW5 are all controlled by a zero voltage switching (ZVS) gate driver. The combination of switches can achieve a high inductance average current during the switching cycle to support high-power output applications.

In the above technical solution, when the full-bridge power switch circuit does not need to support boost output, the switching device SW5 is a bidirectional cut-off power switch device, and the switching devices SW1, SW2, SW3, and SW4 are all unidirectional cut-off power Switching device; when the full-bridge power switch circuit supports boost output, the switching devices SW3, SW4, and SW5 are all bidirectional cut-off power switching devices, and the switching devices SW1 and SW2 are all unidirectional cut-off power switching devices.

In the above technical solution, the comparison control unit has a built-in comparator and a logic calculation unit, and sets a switching current I _const for zero voltage switching; the logic calculation unit sets the current i _set (t) according to the output output by the feedback control unit Calculate the inductor peak current I _peak (t) and the intermediate comparison current I _comp (t) required for switching state switching with the structural characteristics of the full-bridge power switch circuit, and pass it with the inductor current i _L (t) obtained by real-time measurement The comparator compares and determines the corresponding switch state to the power switch circuit according to the structure of the full-bridge power switch circuit, which is specifically:

In this circuit, by applying a DC input voltage U _in to the inductor, the inductor current i _L (t) increases from the switching current I _const opposite to the output current direction to the positive intermediate comparison current I _comp in a short time. In this way, a higher average inductor current can be achieved in the switching period through a lower inductor peak current I _peak ; the intermediate comparison current I _comp is between the switching current I _const and the inductor peak current I _peak , and the direction is the same as the inductor peak current I the direction of _{peak is} the same;

Since the inductor current increases from the reverse switching current -I _const to the positive intermediate comparison current I _{comp for} a very short time, the effect of this process on the average inductor current in the entire switching cycle can be ignored, and the inductor peak current I _peak The calculation relationship with the output setting current i _set (t) is:

(1) When the full-bridge power switch circuit does not need to support boost output, the corresponding switch state is:

When i _set (t)>0A, then I _comp >0A and I _peak >0A,

When i _set (t)＜0A, then I _comp ＜0A and I _peak ＜0A,

Among them, state 0 is off, 1 is on;

(2) When the full-bridge power switch circuit supports boost output, the corresponding switch state is:

When i _set (t)>0, U _out (t)>U _in /2, then I _comp >0A and I _peak >0A;

When i _set (t)>0, U _out (t)<-U _in /2, I _comp >0A and I _peak >0A at this time;

When i _set (t)<0, U _out (t)>U _in /2, then I _comp <0A and I _peak <0A;

When i _set (t)<0, U _out (t)<-U _in /2, then I _comp <0A and I _peak <0A;

Among them, state 0 is off and 1 is on.

The working principle of the present invention is:

The present invention makes the power switch device work in the boundary transmission mode BCM (Boundary Reduction Mode) through the combination of the switch device, the inductor coil and the capacitor output circuit, and maintains the low-frequency sinusoidal voltage and current output at the output end, and the inductor current is Within one high-frequency switching cycle, the reverse switching current increases to the peak current and then decreases to the reverse switching current. In principle, it provides the output of a sinusoidal voltage circuit with low and higher harmonic components. At the same time, since the current of the inductor is negative at the beginning and end of each switching cycle, the zero voltage switching of the power switching device can be realized through this current. , Abbreviated ZVS), so as to achieve extremely low switching loss, thereby reducing the heat of the power switching device during high frequency switching.

The ZVS switching method can achieve ultra-low switching loss. The inductance and capacitance at the output end are similar to a low-pass filter, filtering out the high-frequency switching components generated by the power switching circuit, and outputting low-frequency components. At the same time, because the capacitor can provide energy for the inductor, the switching device can work in the ZVS switching state during the entire switching process.

Compared with the prior art, the beneficial effects of the present invention are:

In the present invention, the power switching devices (SW1 and SW2, or SW1, SW2, SW3, SW4, and SW5) are connected to the output terminal through an inductor L and an output capacitor C _out , and their function is similar to a low-pass filter by filtering out high frequency Switching components to obtain the required low-frequency output voltage; making the output end only have very low high-frequency components, achieving ultra-low electromagnetic interference at the output end; reducing the electromagnetic shielding requirements for connecting cables and motors.

Since the inductor and the output terminal have an output terminal capacitance C _out directly, there is no direct relationship between the inductor current i _L (t) and the output current i _out (t) in each switching cycle; in principle, the output terminal capacitance C _out During the switching period, the voltage of φ provides the energy to realize the reverse inductance current to the inductor, so that the zero voltage switching (ZVS) is realized by the auxiliary switching capacitor connected in parallel to the power switching device. So as to realize the ultra-low switching loss of the power switching device and the characteristics of low-frequency electromagnetic interference at the output end.

Description of the drawings

Figure 1 is a block diagram of the circuit principle of the present invention;

Figure 2 is a circuit schematic diagram of the feedback control unit in the present invention;

Figure 3 is a circuit schematic diagram of a half-bridge power switch circuit;

Figure 4a shows the inductor current, switching state and switching voltage in the half-bridge circuit, where i _set (t) is greater than 0;

Figure 4b shows the inductor current, switching state and switching voltage in the half-bridge circuit, where i _set (t) is less than 0;

Figure 5 is a schematic circuit diagram of a full-bridge power switch circuit;

Figure 5a is a circuit diagram of a full-bridge power switch circuit that does not need to support boost output;

Figure 5b is a circuit diagram of a full-bridge power switch circuit supporting boost output;

Figure 6a shows the inductor current and switching state in a full-bridge circuit that does not need to support boost output, where i _set (t)>0;

Figure 6b shows the inductor current and switching state in a full-bridge circuit that does not need to support boost output, where i _set (t) <0;

Figure 7 is the output voltage curve of each phase drive system output terminal in the full bridge circuit supporting boost output;

Figure 8 shows the full-bridge inductor current;

Figure 9a shows the inductor current and switching state in a full-bridge circuit supporting boost output, where i _set (t)>0, U _out (t)>U _in /2;

Figure 9b shows the inductor current and switching state in a full-bridge circuit supporting boost output, where i _set (t)>0, U _out (t)<-U _in /2;

Figure 9c shows the inductor current and switching state in a full-bridge circuit supporting boost output, where i _set (t)<0, U _out (t)>U _in /2;

Figure 9d shows the inductor current and switching state in a full-bridge circuit supporting boost output, where i _set (t)<0 and U _our (t)<-U _in /2.

Detailed ways

In order to make the technical means, creative features, objectives and effects of the present invention easy to understand, the following describes how the present invention is implemented with reference to the accompanying drawings and specific embodiments.

As shown in Figure 1, the present invention provides an inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference, including a three-phase drive system, each phase drive system is an independent system, and the output of each phase drive system The end is sinusoidal AC, and each phase drive system includes the following parts: feedback control unit, comparison control unit and power switch circuit;

Each of the feedback control units calculates the phase required by input signals: sinusoidal voltage input signal u _sin (t), output voltage feedback signal u _out (t) and output current feedback signal i _our (t) The output setting current i _set (t) of the phase, and the output setting current i _set (t) required by the phase is output to the comparison control unit of the drive system of the phase;

Each of the comparison control units uses the instantaneous value i _set (t) of the phase current required to be output by the feedback control unit of the phase drive system and the real-time measured inductor current value i _L (t) as input signals; The output setting current i _set (t) output by the feedback control unit and the structural characteristics of the power switch circuit are used to calculate the inductor peak current I _peak (t) and the intermediate comparison current I _comp (t) required for switching state switching, and compare them with The real-time measured inductor current i _L (t) is compared, the switch state of the power switch device is determined through logic calculation, and the switch state signal is output to the power switch circuit of the phase drive system;

For each of the power switch circuits, the input signal is the switching state signal output by the comparison control unit of the phase drive system; the output signal is the output voltage feedback signal u _out (t), the output current feedback signal i _out (t ) And the inductor current to measure the output signal i _L (t) in real time. When working, the inductor current measuring circuit in the power switch circuit will feed back the real-time measured inductor current real-time measurement output signal i _L (t) to the comparison control unit of the phase drive system, and the output terminal voltage and current measuring circuit in the power switch circuit will be The measured output terminal voltage feedback signal u _out (t) and current signal feedback signal i _out (t) are fed back to the feedback control unit of the phase drive system.

The power input end of the power switch circuit is: the positive and negative poles (+U _in , -U _in ) of the input DC power supply, and the power output end of each power switch circuit is: sinusoidal voltage output U _out (t), It is the output terminal voltage of each phase drive system. which is:

Among them, ω is the angular velocity, t is the actual time, and the reference point of U _A is the midpoint potential of the input DC power supply, that is, half of the input DC power supply voltage; for example, the output of each phase drive system in a full bridge circuit that supports boost output The output voltage curve at the end (see Figure 7) is the time change of the output voltage at the output end of the drive system of each phase and the DC input voltage.

In the present invention, the output terminal voltage feedback signal u _out (t) is a digital quantization processing on a sensor acquisition of the output terminal voltage U _out (t), and they all substantially represent the output terminal voltage in the construction of the system.

In the present invention, the power switching circuit includes switching devices, auxiliary switching capacitors, inductance coils and output capacitors. The capacity of the auxiliary switching capacitors is much smaller than that of the output capacitors; wherein the gate drive module of the switching devices obtains the switching state signals and switches The real-time voltage across the device realizes zero voltage switching (ZVS) of the switching device.

As shown in Figure 2, the feedback control unit has a built-in feedback control system that establishes feedback through sinusoidal input signal u _sin (t), output voltage feedback signal u _out (t), and output current feedback signal i _out (t). Control the network to calculate the required output set current i _set (t) for this phase, namely:

i _set (t)=G(u _sin (t), u _out (t), i _out (t))

Among them, the output voltage and current can be expressed as:

Where C _out is the capacity of the output capacitor;

The feedback control system includes a PID controller; its specific workflow is:

(1) The voltage difference signal is obtained by comparing the sinusoidal voltage input signal u _sin (t) with the output voltage feedback signal u _out (t), and input to the PID controller;

(2) The charge and discharge current of the output capacitor C _{out is} obtained by calculating the derivative of the sinusoidal voltage input u _sin (t) with respect to time and multiplying it with the output capacitor capacity;

(3) The voltage difference feedback incremental current output by the PID controller in (1) is added to the output capacitor charging and discharging current obtained in (2) and the current output current i _out (t), and the result is the output setting current i _set (t), and input to the comparison control unit.

In this description, the structure of the feedback control unit is a basic structure, and its PID controller is a standard feedback controller, and its parameters are matched and set according to the parameters of the specific circuit design; with the development of control system technology and advanced control systems and adaptive For the application of control system, this feedback control unit can be upgraded and optimized accordingly. But its function in the whole system is still the same as the function of the feedback control unit mentioned above in the whole system, namely:

Through the input signal-sinusoidal voltage input signal u _sjn (t), output voltage feedback signal u _out (t), output current feedback signal i _out (t); calculate the output signal-output set current i _set (t ); and input it to the comparison control unit. Thus, the entire system can work stably and output the output terminal voltage U _out (t) corresponding to the sinusoidal input voltage signal u _sin (t).

In the present invention, according to application requirements, the power switch circuit is divided into a half-bridge power switch circuit and a full-bridge power switch circuit, respectively corresponding to a low-power application environment and a high-power application environment. For example, Figure 8 shows the inductor current i _L (t) curve obtained by real-time measurement in a full-bridge power switch circuit.

(1) Half-bridge power switch circuit

Each of the comparison control units has a built-in comparator and a logic calculation unit, and sets a switching current I _const for zero voltage switching; the output of the feedback control unit sets the current i _set (t) and the power switch circuit The structural characteristics calculate the inductor peak current I _peak (t) required for switching state switching and compare it with the inductor current i _L (t) measured in real time. According to the structure of the half-bridge power switch circuit, determine the corresponding switching state to Power switch circuit;

In each half-bridge power switch circuit, the calculation relationship between the inductor peak current I _peak and the output set current i _set (t) is shown in Table 1:

Table 1 Relationship between inductor peak current I _peak and output set current i _set (t)

To	Peak inductor current	Inductor reverse current
i set (t)＞0A	I peak ＝2·i set (t)+I const	-I const
i set (t) = 0A	I peak ＝I const	-I consy
i set (t)＜0A	I peak ＝2·i set (t)-I const	I const

The corresponding switch states are shown in Figure 4a and Figure 4b, and the specific statistics are shown in Table 2: [State 0 is off, 1 is on]

Table 2 The corresponding switch state is determined by the structure of the half-bridge power switch circuit

(2) Full-bridge power switch circuit

Each comparison control unit has a built-in comparator, a logic calculation unit, and sets a switching current I _const for zero voltage switching; the logic calculation unit sets the current i _set (t) and the full bridge according to the output output by the feedback control unit The structural characteristics of the power switch circuit calculate the inductance peak current I _peak (t) and the intermediate comparison current I _comp (t) required when the switching state is switched, and compare the real-time measured inductor current i _L (t) with the comparator. To compare, determine the corresponding switch state to the power switch circuit according to the structure of the full-bridge power switch circuit, specifically:

In each full-bridge power switching circuit, by applying a DC input voltage U _in to the inductor, the inductor current i _L (t) increases from the switching current I _const opposite to the output current direction to the middle of the positive direction in a short time Compare the current I _comp to achieve a higher average inductor current in the switching cycle through a lower inductor peak current I _peak ; among them, the intermediate comparison current I _comp is between the switching currents I _const and I _peak , and the direction is the same as the inductance peak The direction of the current I _{peak is} the same.

Since the inductor current increases from the reverse switching current -I _const to the positive intermediate comparison current I _{comp for} a very short time, the effect of this process on the average inductor current in the entire switching cycle can be ignored, and the inductor peak current I _peak The calculation relationship with the output setting current i _set (t) is shown in Table 3:

Table 3 Relationship between inductor peak current I _peak and output set current i _set (t)

To	Peak inductor current	Inductor reverse current
i set (t)＞0A	I peak ≈2·i set (t)-I comp	-I const
i set (t) = 0A	I peak ＝I const	-I consy
i set (t)＜0A	I peak ≈2·i set (t)-I comp	I const

(2.1) The corresponding switching state of the structure of the full-bridge power switch circuit that does not need to support boost output is shown in Figure 6a and Figure 6b, and the specific statistics are shown in Table 4: [State 0 is off, 1 is on]

Table 4 The corresponding switch state of the structure of the full-bridge power switch circuit that does not need to support boost output

(2.2) The corresponding switching states of the structure of the full-bridge power switch circuit supporting boost output are shown in Figure 9a, Figure 9b, Figure 9c and Figure 9d, and the specific statistics are shown in Table 5 and Table 6: [State 0 is Turn off, 1 is on]

Table 5 Switching states corresponding to the structure of the full-bridge power switch circuit supporting boost output (1)

Table 6 The corresponding switch state of the structure of the full-bridge power switch circuit supporting boost output (2)

As shown in FIG. 3, each half-bridge power switch circuit includes a high-side switching device SW1, a low-side switching device SW2, and auxiliary switching capacitors C1 and C2 connected in parallel with the high-side switching device SW1 and the low-side switching device SW2, respectively. Inductance coil L1 and output capacitors C3 and C4; the input end of the half-bridge power switch circuit is connected to the input end of the DC power supply, the inductance coil L1 is connected between the output end of the half-bridge power switch circuit and the output capacitors C3 and C4, and the output capacitor C3 is connected to C4 is connected in series between the positive and negative terminals of the DC power input terminal; both the high-side switching device SW1 and the low-side switching device SW2 are controlled by a zero voltage switching (ZVS) gate driver.

Taking the output setting current i _set (t) as a positive current (i _set (t)>0A) as an example (as shown in Figure 4a), since the capacity of the auxiliary switching capacitor is very small, the zero voltage switching (ZVS) time and The change in the inductor current during the process is negligible. The entire switching process can be simplified into the following two parts:

Its working sequence in a switching cycle is shown in Table 7: [State 0 is off, 1 is on]

Table 7 Working sequence in one switching cycle in half-bridge power switch circuit

As shown in FIG. 5, each of the full-bridge power switch circuits includes switching devices SW1, SW2, SW3, SW4, SW5, and auxiliary switching capacitors C1, C2, which are connected in parallel with the switching devices SW1, SW2, SW3, SW4, and SW5, respectively. C3, C4, C5, the inductance coil L1, and the output capacitors C6, C7; the switching devices SW1 and SW2 are connected in series between the positive and negative terminals of the DC power input terminal, and the switching devices SW3 and SW4 are connected in series with the positive and negative terminals of the DC power input terminal The left and right half bridges of the full-bridge switching circuit are formed respectively between them; the input end of the full-bridge power switch circuit is connected to the input end of the DC power supply, and the inductor coil L1 is connected to the output ends of the half-bridges on both sides of the full-bridge switching circuit The switching device SW5 at the output terminal is connected between the output terminal capacitors C6 and C7 and the right half-bridge output terminal of the full-bridge switching circuit; the output terminal capacitors C6 and C7 are connected in series between the positive and negative terminals of the DC power supply input terminal.

When the full-bridge power switch circuit does not need to support boost output, the switching device SW5 is a bidirectional cut-off power switch device, and the switching devices SW1, SW2, SW3, and SW4 are all unidirectional cut-off power switch devices, as shown in the figure As shown in 5a, the switching devices SW1, SW2, SW3, and SW4 are all ordinary MOSFETs or IGBTs (Q1, Q5, Q2, Q6) and freewheeling diodes. The switching devices SW5 are two MOSFETs or IGBTs (Q3, Q3, Q4) Cooperate with freewheeling diodes, and each ordinary MOSFET or IGBT (Q1, Q5, Q2, Q6, Q3, Q4) is connected in parallel with an auxiliary switching capacitor (C1, C4, C2, C5, C7, C8):

When the full-bridge power switch circuit supports boost output, as shown in Figure 5b, the switching devices SW3, SW4, and SW5 are all bidirectional cut-off power switches, and the switching devices SW1 and SW2 are all unidirectional cut-off power switches. The device, as shown in Figure 5b, the switching devices SW1 and SW2 are ordinary MOSFETs or IGBTs (Q1, Q2) with freewheeling diodes, and the switching devices SW3, SW4 and SW5 are two MOSFETs or IGBTs connected in series in opposite directions. Q7 and Q8, phase-to-phase series Q9 and Q10, phase-to-phase series Q19 and Q22) are respectively matched with freewheeling diodes, and each ordinary MOSFET or IGBT (Q1, Q2, Q7, Q8, Q9, Q10, Q19, Q22) is connected in parallel with an auxiliary Switched capacitors (C1, C2, C7, C8, C9, C10, C19, C22).

In the present invention, the two-way cut-off power switch device is usually two MOSFETs or IGBTs connected in series in opposite directions with a freewheeling diode; the unidirectional cut-off power switch device is an ordinary MOSFET or IGBT with a freewheeling diode; and a two-way cut-off power switch device In principle, the on-resistance is larger than that of ordinary one-way cut-off power switching devices, so if there is no boost output requirement, one-way cut-off power switching devices should be used first.

The switching devices SW1, SW2, SW3, SW4, and SW5 are all controlled by a zero voltage switching (ZVS) gate driver. The combination of switches can achieve a high inductance average current during the switching cycle to support high-power output applications.

Taking the output setting current i _set (t) as positive current (i _set (t)>0A) as an example (as shown in Figure 6a), since the capacity of the auxiliary switching capacitor is very small, the zero voltage switching (ZVS) time is The change in the inductor current during the process is negligible. The entire switching process can be simplified into the following four parts:

Its working sequence in a switching cycle is shown in Table 8: [State 0 is off, 1 is on]

Table 8 Working sequence in one switching cycle in a full-bridge power switch circuit that does not require boost to support output

Time zone	Switching condition	SW1	SW2	SW3	SW4	SW5
	i L (t)≤-I const	0	0	0	0	0
(0, t 0 ]	U sw1 = 0V, U sw4 = 0V	1	0	0	1	0
To	i L (t)≥I comp	1	0	0	0	0
(t 0 , t 1 ]	U sw5 = 0V	1	0	0	0	1
To	i L (t)≥I peak	0	0	0	0	1
(t 1 , t 2 ]	U sw2 = 0V	0	1	0	0	1
To	i L (t)≤I comp	0	1	0	0	0
(t 2 , T]	U sw3 = 0V	0	1	1	0	0

The full-bridge power switch circuit can normally open SW3 and SW4 (off) at the same time normally closed SW5 (on) under the working state of small output power to achieve the same working effect as the half-bridge power switch circuit, and its state control method is the same as that of the half-bridge power switch circuit. The bridge power switch circuit is the same.

The present invention regards the combination of the power switching device and the inductor as a controllable current source, and provides the required current to the output capacitor and the output load in the manner of high-frequency switching. The output voltage is provided by the current supplied by the inductor and the current flowing from the load. The current difference is obtained by integrating the time.

Through the restraint of the rate of change of the output voltage by the capacitor and the decoupling of the instantaneous current of the inductor and the output current, the power switching circuit works in the BCM (Boundary Reduction Mode) mode, which in principle achieves both low switching loss and low switching loss. The characteristics of high-frequency electromagnetic interference at the output. It has good compatibility for power switching devices with large parasitic capacitances (such as Superjunction-MOSFET), and plays an auxiliary role in the wide application of faster power switching devices (such as SiC-MOSEFT and GaN-Transistor) in the future.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be implemented Modifications or equivalent replacements, without departing from the purpose and scope of the technical solution of the present invention, shall be covered by the scope of the claims of the present invention.

Claims (8)

1. An inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference, which is characterized in that it includes a three-phase drive system, each phase drive system is an independent system, and the output end of each phase drive system is sinusoidal AC. The phase drive system includes the following parts: feedback control unit, comparison control unit and power switch circuit;

   Each feedback control unit calculates the required value of the phase through input signals: sinusoidal input signal u _sin (t), output terminal voltage feedback signal u _out (t), output terminal current feedback signal i _out (t) Output the set current i _set (t), and output the output set current i _set (t) required by the phase to the comparison control unit of the drive system of the phase;

   Each of the comparison control units uses the required output output set current i _set (t) and the real-time measured inductor current value i _L (t) from the feedback control unit of the phase drive system as input signals; The output setting current i _set (t) output by the control unit and the structural characteristics of the power switch circuit calculate the inductance peak current I _peak (t) and the intermediate comparison current I _comp (t) required when the switching state is switched, and measure them in real time. Compare the inductance current i _L (t) with the logic calculation to determine the corresponding switching state of the switching device in the power switching circuit, and output the switching state signal to the power switching circuit of the phase drive system;

   For each of the power switch circuits, the input signal is the switching state signal output by the comparison control unit of the phase drive system; the output signal is the output terminal voltage feedback signal u _out (t), the output terminal current feedback signal i _out (t ) And the inductor current real-time measurement output signal i _L (t); the inductor current real-time measurement output signal i _L (t) is fed back to the comparison control unit of the phase drive system, and the output terminal voltage feedback signal u _out (t) And the output current feedback signal i _out (t) is fed back to the feedback control unit of the phase drive system;

   The power input terminal of each power switch circuit is: the positive and negative poles (+U _in and -U _in ) of the input DC power supply, and the power output terminal of each power switch circuit is: sinusoidal voltage output U _out (t ), that is, the output voltage of each phase drive system;

   

   Among them, the reference point of U _A is the midpoint potential of the input DC power, that is, half of the input DC power voltage.
2. The inverter drive system with ultra-low switching power consumption and ultra-low output end electromagnetic interference according to claim 1, wherein each of the feedback control units uses a sinusoidal input signal u _sin (t) and an output end The voltage feedback signal u _out (t) and the output current feedback signal i _out (t) establish a feedback control network to calculate the required output set current i _set (t) for this phase, namely:

   i _set (t)=G(u _sin (t), u _out t), i _out (t))

   Among them, the output voltage and current can be expressed as:

   

   

   Where C _out is the capacity of the output capacitor;

   The feedback control unit includes a PID controller; its specific workflow for establishing a feedback control network is:

   (1) The voltage difference signal is obtained by comparing the sinusoidal voltage input signal u _sin (t) with the output voltage feedback signal u _out (t), and input to the PID controller;

   (2) The charge and discharge current of the output capacitor C _{out is} obtained by calculating the derivative of the sinusoidal voltage input u _sin (t) with respect to time and multiplying it with the output capacitor capacity;

   (3) The voltage difference feedback incremental current output by the PID controller in (1) is added to the output capacitor charging and discharging current obtained in (2) and the current output current i _out (t), and the result is the output setting current i _set (t), and input to the comparison control unit.
3. The inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference according to claim 1, wherein the power switch circuit is divided into a half-bridge power switch circuit and a full-bridge according to application requirements. The power switch circuit corresponds to the low-power application environment and the high-power application environment respectively.
4. An inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference according to claim 3, wherein each half-bridge power switching circuit includes a high-side switching device SW1 and a low-side switch Device SW2, auxiliary switching capacitors C1 and C2, inductance coil L1 and output capacitors C3 and C4 connected in parallel with high-side switching device SW1 and low-side switching device SW2 respectively; the input end of the half-bridge power switch circuit is connected to the input end of the DC power supply, The inductor coil L1 is connected between the output terminal of the half-bridge power switch circuit and the output capacitors C3 and C4, and the output capacitors C3 and C4 are connected in series between the positive and negative terminals of the input terminal of the DC power supply;

   Both the high-side switching device SW1 and the low-side switching device SW2 are controlled by a zero voltage switching (ZVS) gate driver.
5. An inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference according to claim 4, wherein the comparison control unit has a built-in comparator and a logic calculation unit, and a ZVS switching current I _const; logic calculation unit calculates the structural characteristic of the half-bridge power switch circuits when the required state of the switch inductor peak current I _peak current according to the output setting i _set (t) output from the feedback control unit ( t), and compare with the inductor current i _L (t) obtained by real-time measurement through a comparator, and determine the corresponding switch state to the power switch circuit according to the structure of the half-bridge power switch circuit, which is specifically:

   In each half-bridge power switch circuit, the calculated relationship between the inductor peak current I _peak and the output set current i _set (t) is:

   

   The corresponding switch state is:

   When i _set (t)>0A,

   

   When i _set (t)＜0A,

   

   Among them, state 0 is off and 1 is on.
6. The inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference according to claim 3, wherein each of the full-bridge power switching circuits includes switching devices SW1, SW2, SW3, SW4 , SW5, auxiliary switching capacitors C1, C2, C3, C4, C5 connected in parallel with the switching devices SW1, SW2, SW3, SW4, SW5, the inductor L1, and the output capacitors C6, C7; the switching devices SW1, SW2 are connected in series Between the positive and negative poles of the DC power supply input terminal and the switching devices SW3 and SW4 in series between the positive and negative poles of the DC power supply input terminal to form the left and right half bridges of the full-bridge switching circuit respectively; the input of the full-bridge power switching circuit The inductance coil L1 is connected between the output ends of the half-bridge on both sides of the full-bridge switching circuit; the switching device SW5 at the output end is connected to the output capacitors C6, C7 and the right half of the full-bridge switching circuit Between the output terminals of the bridge; output terminal capacitors C6 and C7 are connected in series between the positive and negative terminals of the DC power input terminal;

   The switching devices SW1, SW2, SW3, SW4, SW5 are all controlled by a zero voltage switching (ZVS) gate driver.
7. An inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference according to claim 6, wherein when the full-bridge power switching circuit does not need to support boost output, the switching device SW5 is Two-way cut-off power switching devices, the switching devices SW1, SW2, SW3, and SW4 are all unidirectional cut-off power switching devices; when the full-bridge power switch circuit supports boost output, the switching devices SW3, SW4, and SW5 Both are two-way cut-off power switch devices, and the switch devices SW1 and SW2 are both unidirectional cut-off power switch devices.
8. An inverter drive system with ultra-low switching power consumption and ultra-low output electromagnetic interference according to claim 7, wherein each of the comparison control units has a built-in comparator and a logic calculation unit, and one The switching current I _const for zero-voltage switching; the logic calculation unit calculates the inductor peak current I required for switching the switching state according to the output set current i _set (t) output by the feedback control unit and the structural characteristics of the full-bridge power switching circuit _{The peak} (t) and the intermediate comparison current I _comp (t) are compared with the inductor current i _L (t) measured in real time through a comparator, and the corresponding switching state is determined to the power switching circuit according to the structure of the full-bridge power switching circuit ,Specifically:

   In each full-bridge power switching circuit, by applying a DC input voltage U _in to the inductor, the inductor current i _L (t) increases from the switching current I _const opposite to the output current direction to the middle of the positive direction in a short time Compare the current I _comp , so as to achieve a higher average inductor current in the switching cycle through a lower inductor peak current I _peak ; among them, the intermediate comparison current I _comp is between the switching current I _const and the inductor peak current I _peak . Same direction as the inductor peak current I _peak ;

   The time for the inductor current to increase from the reverse switching current -I _const to the positive intermediate comparison current I _comp is very short. During this process, the influence of the inductor average current in the entire switching cycle is ignored. The inductor peak current I _peak and the output setting The calculation relation of current i _set (t) is:

   

   (1) When the full-bridge power switch circuit does not need to support boost output, the corresponding switch state is:

   When i _set (t)>0A, then I _comp >0A and I _peak >0A,

   

   When i _set (t)＜0A, then I _comp ＜0A and I _peak ＜0A,

   

   Among them, state 0 is off, 1 is on;

   (2) When the full-bridge power switch circuit supports boost output, the corresponding switch state is: when i _set (t)> 0, U _out (t)> U _in /2, at this time I _comp > 0A and I _peak ＞0A;

   

   When i _set (t)>0, U _out (t)<-U _in /2, I _comp >0A and I _peak >0A at this time;

   

   When i _set (t)<0, U _out (t)>U _in /2, then I _comp <0A and I _peak <0A;

   

   When i _set (t)<0, U _out (t)<-U _in /2, then I _comp <0A and I _peak <0A;

   

   Among them, state 0 is off and 1 is on.

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