CN111555605B - Control method for reducing critical mode three-level converter switching frequency range - Google Patents

Control method for reducing critical mode three-level converter switching frequency range Download PDF

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CN111555605B
CN111555605B CN202010442793.8A CN202010442793A CN111555605B CN 111555605 B CN111555605 B CN 111555605B CN 202010442793 A CN202010442793 A CN 202010442793A CN 111555605 B CN111555605 B CN 111555605B
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converter
time
level
power device
vector
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CN111555605A (en
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李宁
曹裕捷
张岩
聂程
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Xian University of Technology
Xian Jiaotong University
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Xian University of Technology
Xian Jiaotong University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a control method for reducing the switching frequency range of a critical mode three-level converter, which comprises the steps of sampling the input voltage, the output voltage and the inductive current of the converter, sending the inductive current to a zero current detection module, calculating the average value of the input current in a digital controller, calculating the turn-on time and the turn-off time of a power device according to the average value of the input current, sending the turn-on time and the turn-off time to an SVPWM (space vector pulse width modulation) module, synthesizing a space vector through a voltage vector of the three-level converter, adjusting the sequence of the synthesized space vector according to the input voltage to obtain a three-level switching state and corresponding PWM (pulse width modulation) pulses, and sending the PWM pulses to each power device through a driving circuit, namely completing the control of reducing the switching frequency range of the critical mode three-level converter.

Description

Control method for reducing critical mode three-level converter switching frequency range
Technical Field
The invention belongs to the technical field of electronic power, and relates to a control method for reducing the switching frequency range of a critical mode three-level converter.
Background
The Power Factor Correction (PFC) technology is an important component in Power electronics technology, and PFC converters are often used in battery chargers for electric vehicles, chargers for mobile phones and computers, adapters, and the like. In a low-power application occasion, in order to save cost and improve power density, a PFC converter usually adopts a topological structure such as Buck, boost, flyback and the like; in medium and high power applications, the PFC converter usually employs a topology of a Totem-Pole, single-phase full bridge, or even multi-level. Therefore, different control strategies need to be selected for different topologies.
According to the waveform of the inductor current at the ac side of the PFC converter, the operation modes of the PFC converter can be classified into a Continuous Conduction Mode (CCM), a Discontinuous Conduction Mode (DCM), and a Critical Conduction Mode (CRM). The PFC converter in the CRM mode has the advantages of high power factor and simple control strategy design. The Constant On-Time (COT) control strategy commonly used in the CRM mode enables the converter to obtain unity power factor. In consideration of topological characteristics and control strategy performance, in general, in medium and high power applications, the Totem-Pole converter in CRM mode is usually controlled by COT. However, a disadvantage of this control scheme is that the switching frequency varies greatly, which increases the design difficulty of the EMI filter.
In order to overcome the defect of large variation range of the switching frequency of the PFC converter in the CRM mode, the topological structure and the control strategy can be improved. Three-level Neutral Point ClamPed (NPC) type three levels are a most common three-level topology structure, and the THD on the alternating current side and the average switching frequency of a system can be effectively reduced through the combination of three switching states of N, O and P. However, the conventional three-level converter usually operates in CCM mode, in which although a high power factor can be obtained and the switching frequency is constant, each power device cannot naturally achieve zero current turn-on, which increases the system loss. Meanwhile, the control strategy and the modulation strategy of the traditional three-level converter are complex and are not easy to realize. Therefore, a control strategy capable of reducing the variation range of the switching frequency of the three-level PFC converter operating in the CRM mode needs to be researched to integrate the advantages of the topology and the control strategy.
Disclosure of Invention
The invention aims to provide a control method for reducing the switching frequency range of a critical mode three-level converter, and solves the problem that the switching frequency of the three-level converter in the conventional critical mode is too wide in change.
The invention adopts the technical scheme that the control method for reducing the switching frequency range of the critical mode three-level converter comprises the following steps:
step 1, calculating the conduction time of a power device of a three-level PFC converter;
step 2, calculating the turn-off time of a power device of the three-level PFC converter;
step 3, inputting the calculated on-time and off-time into an SVPWM (space vector pulse width modulation) module, and synthesizing a space vector through a voltage vector of a three-level converter;
and 4, adjusting the sequence of the synthesized space vector according to the input voltage of the converter, correspondingly adjusting the switching state sequence to obtain corresponding PWM pulses, converting the PWM pulses into driving signals and then sending the driving signals to each power device, namely, completing the control of reducing the switching frequency variation range of the three-level PFC converter.
The present invention is also technically characterized in that,
wherein, the specific process of the step 1 is as follows:
step 1.1, sampling input voltage V of three-level PFC converter in An output voltage V o And the inductive current is sent to the zero current detection module, and the average value i of the input current in the CRM mode is calculated in_av ：
Figure BDA0002504758640000031
Wherein θ = ω t, v in_rms For the effective value of the input voltage to be,
Figure BDA0002504758640000032
l is a main inductance value of the converter;
step 1.2, calculating the conduction time T of the power device of the three-level PFC converter on
Figure BDA0002504758640000033
Wherein, P o Outputting power for the converter; η is the converter efficiency and can be approximated as 1.
The specific process of step 2 is as follows:
step 2.1, when 0<V in <V o When the inductor discharges, a direct current side capacitor is connected into an equivalent circuit, and the discharge time of the inductor at the moment, namely the turn-off time of the power device, is calculated as follows:
Figure BDA0002504758640000034
step 2.2, when V o /2<V in <V o And then, when the inductor discharges, two direct current side capacitors are connected to the equivalent circuit, and the inductor discharging time at the moment, namely the turn-off time of the power device, is calculated:
Figure BDA0002504758640000041
the specific process of step 3 is as follows:
step 3.1, inputting the calculated on-time and off-time into an SVPWM modulation module, establishing a single-phase three-level space two-phase static coordinate system, namely an alpha and beta coordinate system, and taking the projection of a reference voltage vector on an alpha axis as a vector to be synthesized:
V α ＝|V ref |cosθ (5)
wherein, V ref Is a reference vector, V α Is the projection of the reference vector on the alpha axis;
step 3.2, synthesizing V according to the volt-second balance principle α And further synthesize a space vector V 1 And V 2 ：
Figure BDA0002504758640000042
/>
Wherein, T s For a switching period, space vector V 1 Namely voltage vectors corresponding to three switch states when the inductor is charged; space vector V 2 Namely, voltage vectors corresponding to six switch states when the inductor discharges.
The specific process of step 4 is as follows:
step 4.1, when 0<V in <V o When/2, adjust the resultant space vector V 1 And V 2 And further adjusting the switching state sequence as follows: OO-PO-PP-PO-OO-ON-NN-ON-OO to obtain corresponding PWM pulses;
step 4.2, when V o /2<V in <V o Adjusting the composite space vector V 1 And V 2 And further adjusting the switching state sequence as follows: OO-PN-PP-PN-NN-PN-OO to obtain corresponding PWM pulse;
and 4.3, sending the obtained PWM pulse into a driving circuit to form a driving signal, and driving each power device by using the driving signal, namely finishing the control of reducing the change range of the switching frequency of the three-level PFC converter.
The invention has the advantages that two control degrees of freedom of a switching frequency discharge strategy and a switching state sequence are increased on the basis of the traditional COT control, the switching frequency and the frequency variation range can be obviously reduced by adjusting the discharge strategy and the switching state sequence, the average switching action times of a power device can be reduced, and the practical value is higher.
Drawings
FIG. 1 is a block flow diagram of a control method of the present invention for reducing the switching frequency range of a critical mode three level converter;
FIG. 2 is a schematic diagram of inductor current and input current when a COT control strategy is employed in an embodiment of the present invention;
fig. 3 is a graph of the switching frequency variation of a conventional PFC converter in critical mode;
FIG. 4 is a graph illustrating the switching frequency of a three-level PFC converter in accordance with the present invention in comparison to the range of the switching frequency of a conventional PFC converter;
FIG. 5 is a space vector coordinate system of a single-phase three-level topology in an embodiment of the present invention;
fig. 6 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the NN state in a half power frequency cycle in the embodiment of the present invention;
fig. 7 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in a half power frequency period in the ON state according to the embodiment of the present invention;
fig. 8 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in a half power frequency period in the PP state according to the embodiment of the present invention;
fig. 9 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in a PO state in a half power frequency cycle according to an embodiment of the present invention;
fig. 10 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the OO state in a half power frequency cycle according to the embodiment of the present invention;
fig. 11 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the PN state in a half power frequency period according to the embodiment of the present invention;
FIG. 12 shows example 0 of the present invention<V in <V o The converter optimized switching sequence and PWM pulse in 2;
FIG. 13 shows a view of V in an embodiment of the present invention o /2<V in <V o The optimized switching sequence and PWM pulse of the time converter;
FIG. 14 is an experimental waveform of input voltage and input current in an embodiment of the present invention;
fig. 15 is an experimental plot of the switching frequency variation of two converters in an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The control method for reducing the switching frequency range of the critical mode three-level converter optimizes the charge-discharge strategy and the switching sequence of the inductor, reduces the switching frequency variation range and is beneficial to the design of an EMI filter based on the constant conduction time control of the traditional three-level PFC converter in the critical mode (also called CRM mode) and the characteristic of three-level topology.
FIG. 1 is a block diagram of a control method for reducing the variation range of the switching frequency of a three-level PFC converter in a CRM mode according to the invention, wherein in a single-phase NPC three-level topology, each phase of bridge arm has four power devices, namely S 11 ，S 12 ，S 13 ，S 14 The whole topology has eight power devices.
In one phase bridge arm, when S 11 ，S 12 When the switch is conducted, the switch state is defined as P; when S is 12 ，S 13 When the switch is conducted, the switch state is defined as O; when S is 13 ，S 14 When conducting, the switch state is defined as N. Therefore, the two-phase bridge arms are combined to have nine switch states, namely PP, PO, PN, OP, ON, OO, NP, NO and NN.
In the control process, firstly, signal sampling is carried out on the input voltage of the network side, the inductive current and the voltage of the two capacitors of the direct current side, and then the signals are input into the DSP through the A/D conversion module.
And secondly, calculating the on-time of the power device in the DSP according to the relationship between the input current and the inductive current, the switching period and the like and a volt-second balance principle.
And thirdly, dividing the operation of the converter into two working conditions according to the change condition of the input voltage, changing the discharge time of the inductor by controlling the quantity of the direct current capacitor under each working condition, and calculating to obtain the turn-off time of the power device.
And finally, sending the on-off time to an SVPWM modulation module, optimizing the switching sequence to obtain PWM pulses, and sending the PWM pulses to a power device through a driving circuit.
The topological structure adopted by the invention is NPC three-level topology, the sampling circuit comprises a voltage sensor and a current sensor, an A/D conversion module is used for sending sampling signals into a digital controller, the digital controller sends PWM pulses through control and modulation, and finally, a driving circuit generates driving signals of power devices, and the driving signals are input into each power device, namely, the switching frequency variation range of the three-level converter in a CRM mode is reduced.
Examples
The invention discloses a control method for reducing the switching frequency range of a critical mode three-level converter, which specifically comprises the following steps:
step 1, calculating the conduction time of a three-level PFC converter power device
The input voltage, the output voltage and the inductive current of the converter are sampled and input into a digital controller to calculate the conduction time of a power device of the PFC converter.
Step 1.1, sampling input voltage V of three-level PFC converter in An output voltage V o And the inductive current is sent to the zero current detection module and is calculated in the digital controller to obtain the average value i of the input current in_αv (θ)。
For the main inductance L of the three-level PFC converter, it can be obtained according to the volt-second balance principle in one switching period:
Figure BDA0002504758640000081
wherein θ = ω t, v in_rms For the effective value of the input voltage to be,
Figure BDA0002504758640000082
T on is the constant on-time, t, of the switching device off (θ) is an off time of the switching device, which varies according to a variation of the input-output voltage.
According to the formula (1), the peak value of the inductor current in one switching period can be obtained as:
Figure BDA0002504758640000083
wherein i L_pk (θ) is the inductor current peak.
In CRM mode, the average value of the input current i in_αv (θ) is half the inductor current peak, i.e.:
Figure BDA0002504758640000084
the relationship between the input voltage, the input current instantaneous value, the input current average value and the switching pulse of the PFC converter in the CRM mode is shown in fig. 2. Equation (3) is an expression of the average value of the input current. As can be seen from fig. 2, when the on-time is constant, the average value of the input current is a linear function of the input voltage, so that the input voltage and the input current are in the same phase, and the input current is also in a perfect sine shape, according to the principle of fourier decomposition, the input current is free of distortion, the THD is zero, and the system can obtain the unit power factor.
Step 1.2, calculating the conduction time T of the power device of the three-level PFC converter on
And calculating the conduction time of the power device under the working condition through parameters such as output power, inductance value and the like according to the obtained average value of the input current.
According to the formula (3), the system input power P in May be:
Figure BDA0002504758640000085
assuming that the system efficiency is η, the input and output power has the following relationship with the efficiency:
P in η＝P o (5)
the constant conduction time T can be obtained by bringing (4) and (5) into (3) on The expression of (c) is:
Figure BDA0002504758640000091
wherein, P o Outputting power for the converter; η is the converter efficiency and can be approximated as 1.
The conventional COT control is applied in the PFC converter, and if not improved, the ripple frequency of the inductor current may be:
Figure BDA0002504758640000092
and the switching frequency is half of the ripple frequency of the inductor current. Meanwhile, due to the fact that in practical application, L and P o Is constant, only the voltage gain will occurThe switching frequency can therefore be normalized, first simplifying it:
Figure BDA0002504758640000093
wherein G is the gain of the direct-current voltage,
Figure BDA0002504758640000094
the constant amount in the formula (8) is taken as a reference value:
Figure BDA0002504758640000095
combining (8) and (9), obtaining a normalized value of the switching frequency of the PFC converter for improvement as follows:
Figure BDA0002504758640000101
according to (10), the change range of the switching frequency of the traditional theoretical three-level PFC converter can be obtained as shown in FIG. 3, and the change range of the switching frequency can be obtained at the moment, so that the conversion range is wide.
Step 2, calculating the turn-off time of the power device of the three-level PFC converter
Step 2.1, judging the input voltage V in When 0 is present<V in <V o And/2, when the inductor discharges, a direct current side capacitor is connected into the equivalent circuit, the discharge time of the inductor is calculated, and the discharge time is prolonged, namely the turn-off time of each switching device is prolonged, so that the equivalent switching frequency is reduced.
Discharge time of inductor, i.e. power device turn-off time:
Figure BDA0002504758640000102
then the ripple frequency of the inductor current at this time may be:
Figure BDA0002504758640000103
at this time, the power device only performs 0.5 switching operations on average in one switching period, and the average switching frequency of the power device is 1/4 of the ripple frequency of the inductive current:
the average switching frequency of each power device in this case is:
Figure BDA0002504758640000104
/>
step 2.2, judging the input voltage V in When V is o /2<V in <V o And then, when the inductor discharges, two direct current side capacitors are connected to the equivalent circuit, and the inductor discharging time at the moment, namely the turn-off time of the power device, is calculated:
Figure BDA0002504758640000111
the ripple frequency of the inductor current at this time is the same as in equation (7).
At the moment, the power device averagely performs 1 switching action in one switching period, and the average switching frequency of the power device is 1/2 of the ripple frequency of the inductive current;
the average switching frequency of each power device in this case is:
Figure BDA0002504758640000112
combining (13) and (15), the switching frequency of the three-level PFC converter of the present invention can be obtained as follows:
Figure BDA0002504758640000113
where alpha is the electrical angle at which the amount of capacitance is switched,
the control method is at V in ＝V o A time of 2 is switched, therefore
Figure BDA0002504758640000114
Similar to step 1, equation (16) is normalized:
Figure BDA0002504758640000115
according to (17), taking G =1.5 as an example, a pair of a switching frequency variation range of a three-level PFC converter in the theoretical present invention and a PFC converter employing conventional control can be obtained as shown in fig. 4.
Step 3, inputting the calculated on-time and off-time into an SVPWM (space vector pulse width modulation) module, and synthesizing a space vector by nine voltage vectors of a three-level converter;
the specific process is as follows:
step 3.1, as shown in fig. 5, a single-phase three-level space two-phase stationary coordinate system, i.e., an α, β coordinate system is established, the whole vector space can be divided into four regions, and the projection of the reference voltage vector on the α axis is taken as a vector to be synthesized:
Vα＝|V ref |cosθ (18)
wherein, V ref As reference vector, V α Is the projection of the reference vector on the alpha axis;
step 3.2, synthesizing V according to the volt-second balance principle α And further synthesize a space vector V 1 And V 2 ：
Figure BDA0002504758640000121
Wherein, T on For the power device conduction time, t, calculated in step 1 off The turn-off time of the power device calculated in the step 2 is also vectorQuantitative duration of action, T s For a switching period of a three-level PFC converter, space vector V 1 Namely voltage vectors corresponding to three switch states during inductor charging; space vector V 2 Namely, voltage vectors corresponding to six switch states when the inductor discharges.
Fig. 6-11 show the current flow direction and the switching state of the three-level PFC converter in a half power frequency period, which include six switching states, that is, PP, OO, NN, PN, PO, and ON, fig. 6 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the half power frequency period in the NN state, fig. 7 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the half power frequency period in the ON state, fig. 8 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the half power frequency period in the PP state, fig. 9 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the half power frequency period in the PO state, fig. 10 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the half power frequency period in the OO state, and fig. 11 is a schematic diagram of the current flow direction and the switching state of the three-level PFC converter in the half power frequency period in the PN state.
Combining FIG. 4 with equations (18), (19), we find V when the reference vector is in each region 1 ，V 2 ，T 1 ，T 2 The values of (a) are shown in table 1, respectively.
TABLE 1 Single-phase three-level space vector and vector action time
Figure BDA0002504758640000131
As can be seen from Table 1, the space vector V 1 Respectively PP, OO and NN; space vector V 2 PN, PO, ON, NO, OP or NP respectively.
Step 4, according to the input voltage V of the converter in And adjusting the sequence of the synthesized voltage space vector, determining the switching state sequence and the corresponding PWM pulse, converting the PWM pulse into a driving signal and sending the driving signal to each power device.
The specific process of step 4 is as follows:
step 4.1, judging the input voltage V in When 0 is present<V in <V o At/2, the switching state sequence is as follows: OO-PO-PP-PO-OO-ON-NN-ON-OO to obtain corresponding PWM pulses, as shown in FIG. 12;
step 4.2, judging the input voltage V in When V is o /2<V in <V o The switching state sequence is as follows: OO-PN-PP-PN-NN-PN-OO, obtaining a corresponding PWM pulse, as shown in FIG. 13;
and 4.3, sending the obtained PWM pulse into a driving circuit to form a driving signal, sending the driving signal into each power device, and driving each power device, namely finishing the control of reducing the switching frequency variation range of the three-level PFC converter.
Aiming at the control method for reducing the switching frequency variation range of the three-level converter in the CRM mode, a hardware platform of 2kW is established and is verified experimentally. The experimental parameters are shown in table 2.
TABLE 2 experiment parameters of 2kW three-level PFC converter
Figure BDA0002504758640000141
From the experimental parameters in table 2, the voltage gain G =1.29 can be derived.
Fig. 14 shows waveforms of input voltage and input current of the three-level PFC converter, and as can be seen from fig. 14, after filtering, the input current is sinusoidal, and as can be seen from analysis, the input current THD =1.6%, and meets the harmonic standard of IEC 61000-3-2Class D.
Fig. 15 is a switching frequency curve of the conventional PFC converter and the three-level PFC converter according to the present invention, which is obtained through experimental tests. Through calculation, compared with the traditional PFC converter, the switching frequency variation range of the three-level PFC converter is reduced by 36.48%.

Claims (1)

1. A control method for reducing the switching frequency range of a critical mode three level converter, comprising the steps of:
step 1, calculating the conduction time of a power device of a three-level PFC converter;
the specific process of the step 1 is as follows:
step 1.1, sampling input voltage V of three-level PFC converter in An output voltage V o And the inductive current is sent to the zero current detection module, and the average value i of the input current in the CRM mode is calculated in_av ：
Figure FDA0004072003920000011
Wherein θ = ω t, v in_rms For the effective value of the input voltage to be,
Figure FDA0004072003920000012
l is a main inductance value of the converter;
step 1.2, calculating the conduction time T of the power device of the three-level PFC converter on
Figure FDA0004072003920000013
Wherein, P o Outputting power for the converter; η is the converter efficiency, approximately 1;
step 2, calculating the turn-off time of a power device of the three-level PFC converter;
the specific process of the step 2 is as follows:
step 2.1, when 0<V in <V o When the inductor discharges, a direct current side capacitor is connected into an equivalent circuit, and the discharge time of the inductor at the moment, namely the turn-off time of the power device, is calculated as follows:
Figure FDA0004072003920000014
step 2.2, when V o /2<V in <V o And then, when the inductor discharges, two direct current side capacitors are connected to the equivalent circuit, and the inductor discharging time at the moment, namely the turn-off time of the power device, is calculated:
Figure FDA0004072003920000021
step 3, inputting the calculated on-time and off-time into an SVPWM (space vector pulse width modulation) module, and synthesizing a space vector through a voltage vector of a three-level converter;
the specific process of the step 3 is as follows:
step 3.1, inputting the calculated on-time and off-time into an SVPWM modulation module, establishing a single-phase three-level space two-phase static coordinate system, namely an alpha and beta coordinate system, and taking the projection of a reference voltage vector on an alpha axis as a vector to be synthesized:
V α ＝|V ref |cosθ (5)
wherein, V ref Is a reference vector, V α Is the projection of the reference vector on the alpha axis;
step 3.2, synthesizing V according to the volt-second balance principle α And further synthesize a space vector V 1 And V 2 ：
Figure FDA0004072003920000022
Wherein, T s For a switching period, space vector V 1 Namely voltage vectors corresponding to three switch states during inductor charging; space vector V 2 Namely voltage vectors corresponding to six switch states when the inductor discharges;
step 4, adjusting the sequence of the synthesized space vector according to the input voltage of the converter, correspondingly adjusting the switching state sequence to obtain corresponding PWM pulses, converting the PWM pulses into driving signals and then sending the driving signals into each power device, namely completing the control of reducing the switching frequency variation range of the three-level PFC converter;
the specific process of the step 4 is as follows:
step 4.1, when 0<V in <V o When/2, adjusting the resultant space vector V 1 And V 2 And further adjusting the switching state sequence as follows: OO-PO-PP-PO-OO-ON-NN-ON-OO to obtain corresponding PWM pulses;
step 4.2, when V o /2<V in <V o Adjusting the composite space vector V 1 And V 2 And further adjusting the switching state sequence as follows: OO-PN-PP-PN-NN-PN-OO to obtain corresponding PWM pulse;
and 4.3, sending the obtained PWM pulse into a driving circuit to form a driving signal, and driving each power device by using the driving signal, namely finishing the control of reducing the switching frequency variation range of the three-level PFC converter.
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