WO2020220481A1 - Esd防护薄膜晶体管及esd防护结构 - Google Patents

Esd防护薄膜晶体管及esd防护结构 Download PDF

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Publication number
WO2020220481A1
WO2020220481A1 PCT/CN2019/097121 CN2019097121W WO2020220481A1 WO 2020220481 A1 WO2020220481 A1 WO 2020220481A1 CN 2019097121 W CN2019097121 W CN 2019097121W WO 2020220481 A1 WO2020220481 A1 WO 2020220481A1
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Prior art keywords
insulating layer
gate
drain
esd protection
electrostatic discharge
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PCT/CN2019/097121
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English (en)
French (fr)
Inventor
肖翔
韩佰祥
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/615,836 priority Critical patent/US20220045180A1/en
Priority to JP2020511770A priority patent/JP7038197B2/ja
Publication of WO2020220481A1 publication Critical patent/WO2020220481A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements

Definitions

  • the invention relates to the field of display technology, in particular to an ESD protection thin film transistor and an ESD protection structure.
  • flat panel display devices are widely used in mobile phones, TVs, personal digital assistants, digital cameras, notebook computers, desktops due to their advantages of high image quality, power saving, thin body and wide application range.
  • Various consumer electronic products such as computers have become the mainstream of display devices.
  • Existing flat panel display devices mainly include liquid crystal display devices (Liquid Crystal Display, LCD) and Organic Light Emitting Display (OLED).
  • an Electro-Static Discharge (ESD) protection structure is generally provided on the substrate.
  • the existing ESD protection structure adopts an ESD protection thin film transistor (Thin Film Transistor) with a floating gate structure (Gate Floating) to release excess charges.
  • the existing ESD protection structure is shown in Figs.
  • An ESD protection thin film transistor 30 is connected between the voltage lines 20 (Common).
  • the ESD protection thin film transistor 30 includes a gate 301, a source 302, a drain 303, and an active layer 304.
  • the gate 301 and the source 302 partially overlap
  • the first coupling capacitor C10 is formed and the gate 301 and the drain 303 partially overlap to form a second coupling capacitor C20.
  • the source 302 is electrically connected to the signal line 10, and the drain 303 is electrically connected to the common voltage line 20.
  • the signal line 10 or the common When the signal line 10 or the common When the static electricity accumulated on the voltage line 20 is too high, it will charge the first coupling capacitor C10 or the second coupling capacitor C20, causing the voltage of the gate 301 of the ESD protection thin film transistor 30 to rise, and then turn on the ESD protection thin film transistor 30 to complete electrostatic discharge .
  • the leakage current of the ESD protection thin film transistor 30 is related to its channel width W and channel length L.
  • the channel width to length ratio (W/L) of the ESD protection thin film transistor 30 is usually designed to be small ( For example, 6:200), when static electricity is generated in the circuit and released through the ESD protective thin film transistor 30, a too low aspect ratio will cause the release not to be rapid enough, which will damage the circuit and reduce the product yield.
  • the purpose of the present invention is to provide an ESD protective thin film transistor, which can improve the efficiency of electrostatic discharge, prevent line explosions, and ensure product yield.
  • the object of the present invention is also to provide an ESD protection structure, which can improve the efficiency of electrostatic discharge, prevent line explosions, and ensure product yield.
  • the present invention provides an ESD protection thin film transistor, including: a substrate, an active layer provided on the substrate, a gate insulating layer provided on the active layer and the substrate, and A gate on the gate insulating layer and opposite to the active layer, an interlayer insulating layer provided on the gate and the gate insulating layer, and spaced sources arranged on the interlayer insulating layer Pole and drain;
  • the source electrode has a plurality of first electrostatic discharge tips
  • the drain has a plurality of second electrostatic discharge tips facing the plurality of first electrostatic discharge tips, respectively.
  • the source and drain are both U-shaped;
  • the source electrode has two first electrostatic discharge tips respectively located at two ends of the source electrode, and the drain electrode has two second electrostatic discharge tips respectively located at two ends of the drain electrode.
  • the material of the active layer is amorphous silicon, polysilicon or oxide semiconductor.
  • a first via hole and a second via hole are provided through the interlayer insulating layer and the gate insulating layer, and the source electrode and the drain electrode respectively pass through the first via hole and the second via hole and the active layer Contact at both ends.
  • the source and the gate at least partially overlap to form a first coupling capacitor, and the drain and the gate at least partially overlap to form a second coupling capacitor to pass the first coupling capacitor or the second coupling
  • the function of the capacitor transmits a voltage to the gate, and the ESD protection thin film transistor is turned on for electrostatic discharge.
  • the present invention also provides an ESD protection structure, including signal lines, common voltage lines and ESD protection thin film transistors;
  • the ESD protection thin film transistor includes: a substrate, an active layer provided on the substrate, a gate insulating layer provided on the active layer and the substrate, and a gate insulating layer provided on the gate insulating layer.
  • the source electrode has a plurality of first electrostatic discharge tips, and the drain has a plurality of second electrostatic discharge tips facing the plurality of first electrostatic discharge tips;
  • the source and drain are respectively electrically connected to the signal line and the common voltage line.
  • the source and drain are both U-shaped;
  • the source electrode has two first electrostatic discharge tips respectively located at two ends of the source electrode, and the drain electrode has two second electrostatic discharge tips respectively located at two ends of the drain electrode.
  • the material of the active layer is amorphous silicon, polysilicon or oxide semiconductor.
  • a first via hole and a second via hole are provided through the interlayer insulating layer and the gate insulating layer, and the source electrode and the drain electrode respectively pass through the first via hole and the second via hole and the active layer Contact at both ends.
  • the source and the gate at least partially overlap to form a first coupling capacitor, and the drain and the gate at least partially overlap to form a second coupling capacitor to pass the first coupling capacitor or the second coupling
  • the function of the capacitor transmits a voltage to the gate, and the ESD protection thin film transistor is turned on for electrostatic discharge.
  • the present invention provides an ESD protection thin film transistor, including: a substrate, an active layer provided on the substrate, a gate insulating layer provided on the active layer and the substrate, and A gate on the gate insulating layer and opposite to the active layer, an interlayer insulating layer provided on the gate and the gate insulating layer, and spaced sources arranged on the interlayer insulating layer Electrode and drain; the source has a plurality of first electrostatic discharge tips, the drain has a plurality of second electrostatic discharge tips facing the first electrostatic discharge tips, through the source and drain A positive electrostatic discharge tip is set on the pole, so that the ESD protective thin film transistor has two electrostatic discharge paths of thin film transistor release and tip discharge at the same time, which can improve the efficiency of electrostatic discharge, prevent line explosions, and ensure product yield.
  • the invention also provides an ESD protection structure, which can improve the efficiency of electrostatic discharge, prevent line explosions and ensure product yield.
  • Figure 1 is a circuit diagram of a conventional ESD protection structure
  • FIG. 2 is a top view of an ESD protection thin film transistor in a conventional ESD protection structure
  • FIG. 3 is a top view of the ESD protection thin film transistor of the present invention.
  • FIG. 5 is a schematic structural diagram of the ESD protection structure of the present invention.
  • Fig. 6 is an equivalent circuit diagram of the ESD protection structure of the present invention.
  • the present invention provides an ESD protection thin film transistor, including: a substrate 1, an active layer provided on the substrate 1, and a gate provided on the active layer 2 and the substrate 1.
  • the source electrode 6 has a plurality of first electrostatic discharge tips 60
  • the drain 7 has a plurality of second electrostatic discharge tips 70 facing the plurality of first electrostatic discharge tips 60 respectively.
  • the source electrode 6 and the drain electrode 7 are both U-shaped; the source electrode 6 has two first electrostatic discharges respectively located at both ends of the source electrode 6
  • the tip 60, the drain 7 has two second electrostatic discharge tips 70 located at both ends of the drain 7 respectively.
  • the material of the active layer 2 is amorphous silicon, polysilicon or oxide semiconductor, wherein the oxide semiconductor may be indium gallium zinc oxide (Indium Gallium Zinc Oxide). gallium zinc oxide, IGZO).
  • the oxide semiconductor may be indium gallium zinc oxide (Indium Gallium Zinc Oxide). gallium zinc oxide, IGZO).
  • a first via 81 and a second via 82 are formed through the interlayer insulating layer 5 and the gate insulating layer 3, and the source 6 and the drain 7 respectively pass through the first via 81 And the second via hole 82 is in contact with both ends of the active layer 2.
  • the source 6 and the gate 4 at least partially overlap to form a first coupling capacitor C1, and the drain 7 and the gate 4 at least partially overlap to form a second coupling capacitor C2.
  • the source 6 and the gate 4 at least partially overlap to form a first coupling capacitor C1
  • the drain 7 and the gate 4 at least partially overlap to form a second coupling capacitor C2.
  • the source 6 and the drain 7 of the ESD protection thin film transistor of the present invention have a first electrostatic discharge tip 60 and a second electrostatic discharge tip 70, respectively, and the first electrostatic discharge tip 60 is facing the first electrostatic discharge tip 60.
  • the second electrostatic discharge tip 70 is set, and when the static electricity accumulated on the line is too high, the first coupling capacitor C1 or the second coupling capacitor C2 will be charged, so that the voltage of the gate 4 of the ESD protection thin film transistor will rise, thereby turning on the ESD protection film Transistor realizes electrostatic discharge.
  • the first electrostatic discharge tip 60 and the second electrostatic discharge tip 70 realize electrostatic discharge through the tip discharge effect, so that the ESD protection thin film transistor of the present invention has both thin film transistor discharge and tip discharge.
  • the path can improve the efficiency of electrostatic discharge, prevent the line from blasting, and ensure the product yield.
  • the present invention also provides an ESD protection structure, including a signal line 100, a common voltage line 200 and an ESD protection thin film transistor T;
  • the ESD protection thin film transistor T includes: a substrate 1, an active layer 2 provided on the substrate 1, a gate insulating layer 3 provided on the active layer 2 and the substrate 1, and a gate insulating layer 3 provided on the gate
  • the source electrode 6 has a plurality of first electrostatic discharge tips 60
  • the drain 7 has a plurality of second electrostatic discharge tips 70 facing the plurality of first electrostatic discharge tips 60 respectively;
  • the source 6 and the drain 7 are electrically connected to the signal line 100 and the common voltage line 200 respectively.
  • the source 6 and the drain 7 are both U-shaped; the source 6 has two first electrostatic discharges respectively located at both ends of the source 6
  • the tip 60, the drain 7 has two second electrostatic discharge tips 70 located at both ends of the drain 7 respectively.
  • the material of the active layer 2 is amorphous silicon, polysilicon or oxide semiconductor, wherein the oxide semiconductor may be indium gallium zinc oxide.
  • a first via 81 and a second via 82 are formed through the interlayer insulating layer 5 and the gate insulating layer 3, and the source 6 and the drain 7 respectively pass through the first via 81 And the second via hole 82 is in contact with both ends of the active layer 2.
  • the source 6 and the gate 4 at least partially overlap to form a first coupling capacitor C1
  • the drain 7 and the gate 4 at least partially overlap to form a second coupling capacitor C2 to pass the
  • the function of the first coupling capacitor C1 or the second coupling capacitor C2 transmits a voltage to the gate 4 and turns on the ESD protection thin film transistor for electrostatic discharge.
  • the signal line 100 is a scan line (Gate) or a data line (Data) in a display panel
  • the common voltage line 200 is a common electrode line (Com) in the display panel.
  • the source 6 and the drain 7 of the ESD protection thin film transistor respectively have a first electrostatic discharge tip 60 and a second electrostatic discharge tip 70, and the first electrostatic discharge tip 60 is facing the second electrostatic discharge tip 60.
  • the electrostatic discharge tip 70 is arranged to charge the first coupling capacitor C1 or the second coupling capacitor C2 when the static electricity accumulated on the signal line 100 or the common voltage line 200 is too high, so that the voltage of the gate 4 of the ESD protection thin film transistor increases, In turn, the ESD protection thin film transistor is turned on.
  • the signal line 100 and the common voltage line 200 are connected together to realize electrostatic discharge.
  • the ESD protection thin film transistor of the present invention has both the thin film transistor release and the tip release static discharge path, which can improve the static discharge efficiency, prevent the circuit from being damaged, and ensure the product yield.
  • the present invention provides an ESD protection thin film transistor, including: a substrate, an active layer provided on the substrate, a gate insulating layer provided on the active layer and the substrate, and A gate electrode on the gate insulating layer and opposite to the active layer, an interlayer insulating layer provided on the gate electrode and the gate insulating layer, and spaced source electrodes provided on the interlayer insulating layer And a drain; the source has a plurality of first electrostatic discharge tips, and the drain has a plurality of second electrostatic discharge tips facing the first electrostatic discharge tips, respectively, through the source and drain
  • the ESD protection thin film transistor is provided with a positive electrostatic discharge tip, so that the ESD protection thin film transistor has both thin film transistor discharge and tip discharge static discharge paths, which can improve the electrostatic discharge efficiency, prevent line explosions, and ensure product yield.
  • the invention also provides an ESD protection structure, which can improve the efficiency of electrostatic discharge, prevent line explosions and ensure product yield.

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  • Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明提供一种ESD防护薄膜晶体管及ESD防护结构。所述ESD防护薄膜晶体管包括：基板、设于所述基板上的有源层、设于所述有源层及基板上的栅极绝缘层、设于所述栅极绝缘层上并与所述有源层相对的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层以及设于所述层间绝缘层上的间隔分布的源极及漏极；所述源极具有数个第一静电释放尖端，所述漏极具有分别正对所述数个第一静电释放尖端的数个第二静电释放尖端，通过在源极和漏极上设置正对的静电释放尖端，使得ESD防护薄膜晶体管同时具有薄膜晶体管释放和尖端释放两种静电释放路径，能够提升静电释放效率，防止线路炸伤，保证产品良率。

Description

ESD防护薄膜晶体管及ESD防护结构 技术领域
本发明涉及显示技术领域，尤其涉及一种ESD防护薄膜晶体管及ESD防护结构。
 背景技术
随着显示技术的发展，平板显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。现有的平板显示装置主要包括液晶显示装置（Liquid Crystal Display，LCD）及有机发光二极管显示装置（Organic Light Emitting Display，OLED）。
现有平板显示装置为了达到防静电的目的，一般在基板上设有静电放电( Electro-Static Discharge，ESD )防护结构。现有的ESD防护结构采用具有浮栅结构(Gate Floating)的ESD防护薄膜晶体管（Thin Film Transistor）释放多余电荷，现有的ESD防护结构如图1及图2所示，在信号线10和公共电压线20（Common）之间连接有ESD防护薄膜晶体管30，ESD防护薄膜晶体管30包括栅极301、源极302、漏极303及有源层304，所述栅极301及源极302部分重叠形成第一耦合电容C10和栅极301和漏极303部分重叠形成第二耦合电容C20，源极302电性连接信号线10，漏极303电性连接公共电压线20，当信号线10或公共电压线20上累积的静电过高时会对第一耦合电容C10或第二耦合电容C20充电，使得ESD防护薄膜晶体管30的栅极301电压上升，进而导通ESD防护薄膜晶体管30，完成静电释放。
为了保证静电释放效果，需要尽可能的减少ESD防护薄膜晶体管30的漏电流，所述ESD防护薄膜晶体管30的漏电流与其沟道宽度W及沟道长度L有关，沟道宽度W越小，漏电越小，沟道长度L越大，漏电流越小，为了减小漏电流，现有技术中，通常会将ESD防护薄膜晶体管30的沟道宽长比（W/L）设计的很小（如6：200），当线路中产生静电并通过ESD防护薄膜晶体管30的释放时，过低的宽长比又会导致释放不够迅速，而炸伤线路，降低产品良率。
 技术问题
本发明的目的在于提供一种ESD防护薄膜晶体管，能够提升静电释放效率，防止线路炸伤，保证产品良率。
本发明的目的还在于提供一种ESD防护结构，能够提升静电释放效率，防止线路炸伤，保证产品良率。
 技术解决方案
为实现上述目的，本发明提供了一种ESD防护薄膜晶体管，包括：基板、设于所述基板上的有源层、设于所述有源层及基板上的栅极绝缘层、设于所述栅极绝缘层上并与所述有源层相对的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层以及设于所述层间绝缘层上的间隔分布的源极及漏极；
所述源极具有数个第一静电释放尖端，所述漏极具有分别正对所述数个第一静电释放尖端的数个第二静电释放尖端。
所述源极和漏极均为U形；
所述源极具有2个分别位于所述源极的两端部的第一静电释放尖端，所述漏极具有2个分别位于所述漏极的两端部的第二静电释放尖端。
所述有源层的材料为非晶硅、多晶硅或氧化物半导体。
贯穿所述述层间绝缘层及栅极绝缘层设有第一过孔及第二过孔，所述源极及漏极分别通过所述第一过孔及第二过孔与有源层的两端接触。
所述源极与所述栅极至少部分交叠形成第一耦合电容，所述漏极与所述栅极至少部分交叠形成第二耦合电容，以通过所述第一耦合电容或第二耦合电容的作用向所述栅极传递电压，导通所述ESD防护薄膜晶体管进行静电释放。
本发明还提供一种ESD防护结构，包括信号线、公共电压线及ESD防护薄膜晶体管；
所述ESD防护薄膜晶体管包括：基板、设于所述基板上的有源层、设于所述有源层及基板上的栅极绝缘层、设于所述栅极绝缘层上并与所述有源层相对的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层以及设于所述层间绝缘层上的间隔分布的源极及漏极；
所述源极具有数个第一静电释放尖端，所述漏极具有分别正对所述数个第一静电释放尖端的数个第二静电释放尖端；
所述源极及漏极分别电性连接所述信号线和所述公共电压线。
所述源极和漏极均为U形；
所述源极具有2个分别位于所述源极的两端部的第一静电释放尖端，所述漏极具有2个分别位于所述漏极的两端部的第二静电释放尖端。
所述有源层的材料为非晶硅、多晶硅或氧化物半导体。
贯穿所述述层间绝缘层及栅极绝缘层设有第一过孔及第二过孔，所述源极及漏极分别通过所述第一过孔及第二过孔与有源层的两端接触。
所述源极与所述栅极至少部分交叠形成第一耦合电容，所述漏极与所述栅极至少部分交叠形成第二耦合电容，以通过所述第一耦合电容或第二耦合电容的作用向所述栅极传递电压，导通所述ESD防护薄膜晶体管进行静电释放。
 有益效果
本发明的有益效果：本发明提供一种ESD防护薄膜晶体管，包括：基板、设于所述基板上的有源层、设于所述有源层及基板上的栅极绝缘层、设于所述栅极绝缘层上并与所述有源层相对的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层以及设于所述层间绝缘层上的间隔分布的源极及漏极；所述源极具有数个第一静电释放尖端，所述漏极具有分别正对所述数个第一静电释放尖端的数个第二静电释放尖端，通过在源极和漏极上设置正对的静电释放尖端，使得ESD防护薄膜晶体管同时具有薄膜晶体管释放和尖端释放两种静电释放路径，能够提升静电释放效率，防止线路炸伤，保证产品良率。本发明还提供一种ESD防护结构，能够提升静电释放效率，防止线路炸伤，保证产品良率。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的ESD防护结构的电路图
图2为现有的ESD防护结构中ESD防护薄膜晶体管的俯视图；
图3为本发明的ESD防护薄膜晶体管的俯视图；
图4为本发明的ESD防护薄膜晶体管的剖面图；
图5为本发明的ESD防护结构的结构示意图；
图6为本发明的ESD防护结构的等效电路图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3和图4，本发明提供一种ESD防护薄膜晶体管，包括：基板1、设于所述基板1上的有源层2、设于所述有源层2及基板1上的栅极绝缘层3、设于所述栅极绝缘层3上并与所述有源层2相对的栅极4、设于所述栅极4及栅极绝缘层3上的层间绝缘层5以及设于所述层间绝缘层5上的间隔分布的源极6及漏极7；
所述源极6具有数个第一静电释放尖端60，所述漏极7具有分别正对所述数个第一静电释放尖端60的数个第二静电释放尖端70。
具体地，在本发明的优选实施例中，所述源极6和漏极7均为U形；所述源极6具有2个分别位于所述源极6的两端部的第一静电释放尖端60，所述漏极7具有2个分别位于所述漏极7的两端部的第二静电释放尖端70。
具体地，所述有源层2的材料为非晶硅、多晶硅或氧化物半导体，其中所述氧化物半导体可以为铟镓锌氧化物（Indium gallium zinc oxide，IGZO）。
具体地，贯穿所述述层间绝缘层5及栅极绝缘层3设有第一过孔81及第二过孔82，所述源极6及漏极7分别通过所述第一过孔81及第二过孔82与有源层2的两端接触。
具体地，结合图6，所述源极6与所述栅极4至少部分交叠形成第一耦合电容C1，所述漏极7与所述栅极4至少部分交叠形成第二耦合电容C2，以通过所述第一耦合电容C1或第二耦合电容C2的作用向所述栅极4传递电压，导通所述ESD防护薄膜晶体管进行静电释放。
需要说明的是，本发明的ESD防护薄膜晶体管的源极6及漏极7分别具有第一静电释放尖端60和第二静电释放尖端70，且所述第一静电释放尖端60正对所述第二静电释放尖端70设置，当线路上累积的静电过高时会对第一耦合电容C1或第二耦合电容C2充电，使得ESD防护薄膜晶体管的栅极4的电压上升，进而导通ESD防护薄膜晶体管，实现静电释放，同时，第一静电释放尖端60和第二静电释放尖端70通过尖端放电效应实现静电释放，从而使得本发明的ESD防护薄膜晶体管同时具有薄膜晶体管释放和尖端释放两种静电释放路径，能够提升静电释放效率，防止线路炸伤，保证产品良率。
请参阅图3至图6，本发明还提供一种ESD防护结构，包括信号线100、公共电压线200及ESD防护薄膜晶体管T；
所述ESD防护薄膜晶体管T包括：基板1、设于所述基板1上的有源层2、设于所述有源层2及基板1上的栅极绝缘层3、设于所述栅极绝缘层3上并与所述有源层2相对的栅极4、设于所述栅极4及栅极绝缘层3上的层间绝缘层5以及设于所述层间绝缘层5上的间隔分布的源极6及漏极7；
所述源极6具有数个第一静电释放尖端60，所述漏极7具有分别正对所述数个第一静电释放尖端60的数个第二静电释放尖端70；
所述源极6及漏极7分别电性连接所述信号线100和所述公共电压线200。
具体地，在本发明的一些实施例中，所述源极6和漏极7均为U形；所述源极6具有2个分别位于所述源极6的两端部的第一静电释放尖端60，所述漏极7具有2个分别位于所述漏极7的两端部的第二静电释放尖端70。
具体地，所述有源层2的材料为非晶硅、多晶硅或氧化物半导体，其中所述氧化物半导体可以为铟镓锌氧化物。
具体地，贯穿所述述层间绝缘层5及栅极绝缘层3设有第一过孔81及第二过孔82，所述源极6及漏极7分别通过所述第一过孔81及第二过孔82与有源层2的两端接触。
具体地，所述源极6与所述栅极4至少部分交叠形成第一耦合电容C1，所述漏极7与所述栅极4至少部分交叠形成第二耦合电容C2，以通过所述第一耦合电容C1或第二耦合电容C2的作用向所述栅极4传递电压，导通所述ESD防护薄膜晶体管进行静电释放。
优选地，所述信号线100为显示面板中的扫描线（Gate）或数据线（Data），所述公共电压线200为显示面板中的公共电极线（Com）。
需要说明的是，所述ESD防护薄膜晶体管的源极6及漏极7分别具有第一静电释放尖端60和第二静电释放尖端70，且所述第一静电释放尖端60正对所述第二静电释放尖端70设置，当信号线100或公共电压线200上累积的静电过高时会对第一耦合电容C1或第二耦合电容C2充电，使得ESD防护薄膜晶体管的栅极4的电压上升，进而导通ESD防护薄膜晶体管，所述信号线100与公共电压线200连通到一起，实现静电释放，同时，第一静电释放尖端60和第二静电释放尖端70通过尖端放电效应实现静电释放，从而使得本发明的ESD防护薄膜晶体管同时具有薄膜晶体管释放和尖端释放两种静电释放路径，能够提升静电释放效率，防止线路炸伤，保证产品良率。
综上所述，本发明提供一种ESD防护薄膜晶体管，包括：基板、设于所述基板上的有源层、设于所述有源层及基板上的栅极绝缘层、设于所述栅极绝缘层上并与所述有源层相对的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层以及设于所述层间绝缘层上的间隔分布的源极及漏极；所述源极具有数个第一静电释放尖端，所述漏极具有分别正对所述数个第一静电释放尖端的数个第二静电释放尖端，通过在源极和漏极上设置正对的静电释放尖端，使得ESD防护薄膜晶体管同时具有薄膜晶体管释放和尖端释放两种静电释放路径，能够提升静电释放效率，防止线路炸伤，保证产品良率。本发明还提供一种ESD防护结构，能够提升静电释放效率，防止线路炸伤，保证产品良率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种ESD防护薄膜晶体管，包括：基板、设于所述基板上的有源层、设于所述有源层及基板上的栅极绝缘层、设于所述栅极绝缘层上并与所述有源层相对的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层以及设于所述层间绝缘层上的间隔分布的源极及漏极；
    所述源极具有数个第一静电释放尖端，所述漏极具有分别正对所述数个第一静电释放尖端的数个第二静电释放尖端。
  2. 如权利要求1所述的ESD防护薄膜晶体管，其中，所述源极和漏极均为U形；
    所述源极具有2个分别位于所述源极的两端部的第一静电释放尖端，所述漏极具有2个分别位于所述漏极的两端部的第二静电释放尖端。
  3. 如权利要求1所述的ESD防护薄膜晶体管，其中，所述有源层的材料为非晶硅、多晶硅或氧化物半导体。
  4. 如权利要求1所述的ESD防护薄膜晶体管，其中，贯穿所述述层间绝缘层及栅极绝缘层设有第一过孔及第二过孔，所述源极及漏极分别通过所述第一过孔及第二过孔与有源层的两端接触。
  5. 如权利要求1所述的ESD防护薄膜晶体管，其中，所述源极与所述栅极至少部分交叠形成第一耦合电容，所述漏极与所述栅极至少部分交叠形成第二耦合电容，以通过所述第一耦合电容或第二耦合电容的作用向所述栅极传递电压，导通所述ESD防护薄膜晶体管进行静电释放。
  6. 一种ESD防护结构，包括信号线、公共电压线及ESD防护薄膜晶体管；
    所述ESD防护薄膜晶体管包括：基板、设于所述基板上的有源层、设于所述有源层及基板上的栅极绝缘层、设于所述栅极绝缘层上并与所述有源层相对的栅极、设于所述栅极及栅极绝缘层上的层间绝缘层以及设于所述层间绝缘层上的间隔分布的源极及漏极；
    所述源极具有数个第一静电释放尖端，所述漏极具有分别正对所述数个第一静电释放尖端的数个第二静电释放尖端；
    所述源极及漏极分别电性连接所述信号线和所述公共电压线。
  7. 如权利要求6所述的ESD防护结构，其中，所述源极和漏极均为U形；
    所述源极具有2个分别位于所述源极的两端部的第一静电释放尖端，所述漏极具有2个分别位于所述漏极的两端部的第二静电释放尖端。
  8. 如权利要求6所述的ESD防护结构，其中，所述有源层的材料为非晶硅、多晶硅或氧化物半导体。
  9. 如权利要求6所述的ESD防护结构，其中，贯穿所述述层间绝缘层及栅极绝缘层设有第一过孔及第二过孔，所述源极及漏极分别通过所述第一过孔及第二过孔与有源层的两端接触。
  10. 如权利要求6所述的ESD防护结构，其中，所述源极与所述栅极至少部分交叠形成第一耦合电容，所述漏极与所述栅极至少部分交叠形成第二耦合电容，以通过所述第一耦合电容或第二耦合电容的作用向所述栅极传递电压，导通所述ESD防护薄膜晶体管进行静电释放。
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