WO2020220326A1 - 开关电路、混频器及电子设备 - Google Patents

开关电路、混频器及电子设备 Download PDF

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Publication number
WO2020220326A1
WO2020220326A1 PCT/CN2019/085335 CN2019085335W WO2020220326A1 WO 2020220326 A1 WO2020220326 A1 WO 2020220326A1 CN 2019085335 W CN2019085335 W CN 2019085335W WO 2020220326 A1 WO2020220326 A1 WO 2020220326A1
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Prior art keywords
lead
gate
symmetry
axis
mos transistor
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PCT/CN2019/085335
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English (en)
French (fr)
Inventor
周永丽
金香菊
赖砚
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP19927224.6A priority Critical patent/EP3955457A4/en
Priority to PCT/CN2019/085335 priority patent/WO2020220326A1/zh
Priority to CN201980093496.2A priority patent/CN113508523A/zh
Publication of WO2020220326A1 publication Critical patent/WO2020220326A1/zh
Priority to US17/514,564 priority patent/US12113481B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1466—Passive mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1491—Arrangements to linearise a transconductance stage of a mixer arrangement
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0088—Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products

Definitions

  • This application relates to the field of electronic technology, in particular to a switch circuit, a mixer and an electronic device.
  • the mixer (namely Mixer) is the core circuit responsible for the spectrum shift function in the transceiver, and it has a wide range of applications in microwave wireless communication systems, radar systems and measurement systems.
  • the technical indicators of the mixer mainly include: IF/RF band, conversion gain, noise figure, linearity, isolation between ports, port standing wave ratio, power consumption, etc.
  • IIP2 input second-order intermodulation point
  • the embodiments of the present application provide a switch circuit, a mixer, and an electronic device to help improve the linearity of the device.
  • an embodiment of the present application provides a switch circuit including a first metal oxide semiconductor MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube.
  • the gate of the first MOS tube The electrode and the gate of the fourth MOS transistor are both connected to the first port, the gate of the second MOS transistor and the gate of the third MOS transistor are both connected to the second port; the gate of the first MOS transistor is connected to the second port.
  • the length of the lead between a port, the length of the lead between the gate of the second MOS transistor and the second port, the length of the lead between the gate of the third MOS transistor and the second port, the The lengths of the leads between the gate of the fourth MOS transistor and the first port are equal.
  • the length of the gate wiring of each MOS transistor in the switch circuit is the same, so that the gate parasitic capacitance of each MOS transistor is the same, and the linearity is higher.
  • the first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through the first position, and the gate of the second MOS transistor and the third MOS transistor
  • the second lead between the gates of the transistor passes through a second position, and the first position and the second position are the same position on different layers in the switching circuit; the lead from the gate of the first MOS transistor to the first position
  • the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, the length of the lead from the gate of the fourth MOS transistor to the second position The lengths of the leads at one location are equal.
  • the lead lengths from the gate of each MOS transistor in the switch circuit to the same position on different layers in the switch circuit are equal, so that the gate parasitic capacitance of each MOS transistor is the same and the linearity is higher.
  • the first MOS tube and the third MOS tube are aligned left and right and symmetrical along a first axis of symmetry
  • the second MOS tube and the fourth MOS tube are aligned left and right and along the first axis of symmetry.
  • Symmetrical the first MOS tube and the second MOS tube are aligned back and forth and symmetrical along the second axis of symmetry
  • the third MOS tube and the fourth MOS tube are aligned front and back and symmetrical along the second axis of symmetry
  • the second axis of symmetry are perpendicular to each other.
  • the symmetrical arrangement of the MOS transistors in the switch circuit can make the parasitic capacitances of the MOS transistors compatible, thereby improving the linearity of the mixer.
  • one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to The second port; the third position and the fourth position are symmetrical along the first axis of symmetry; the switch circuit is symmetrical along the first axis of symmetry.
  • the third lead and the fourth lead are symmetrical along the first symmetry axis, which can make the wiring of the gate of each MOS transistor symmetrical.
  • the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, and the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected.
  • the poles are directly connected to form the second lead, and both the first lead and the second lead are straight lines.
  • the gate of the first MOS tube is directly connected to the gate of the fourth MOS tube, and the gate of the second MOS tube is directly connected to the gate of the third MOS tube, which can effectively reduce the length and cost of the lead. Lower.
  • a part of the third lead is located on one side of the first axis of symmetry, another part of the third lead is located on the other side of the first axis of symmetry; a part of the fourth lead is located One side of the first axis of symmetry, the other part of the fourth lead is located on the other side of the first axis of symmetry; the third lead passes through the fifth position, the fourth lead passes through the sixth position, the fifth position and The sixth position is the same position on different layers in the switch circuit.
  • the gate wiring of each MOS transistor is strictly symmetrical, so that the parasitic capacitance of the gate of each MOS transistor is consistent.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the switch circuit, and the second part of the third lead is parallel to the first axis of symmetry,
  • the third part of the third lead is located on both sides of the first axis of symmetry, and the fourth part of the third lead is parallel to the first axis of symmetry;
  • the first part of the fourth lead and a part of the first lead are located at the At the same position of different layers in the switching circuit, the second part of the fourth lead is parallel to the first axis of symmetry,
  • the third part of the fourth lead is located on both sides of the first axis of symmetry, and the fourth lead of the fourth lead Part is parallel to the first axis of symmetry;
  • the third part of the third lead passes through the fifth position, and the third part of the fourth lead passes through the sixth position.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the switch circuit, and the first part of the fourth lead and part of the first lead are located on the same location on different layers of the switch circuit. Position, can effectively reduce the mutual influence between leads.
  • the third lead is located on one side of the first axis of symmetry, and the fourth lead is located on the other side of the first axis of symmetry; the first part of the third lead and the second lead A part of the switch circuit is located at the same position in different layers, the second part of the third lead is parallel to the first axis of symmetry; the first part of the fourth lead and a part of the first lead are located in different layers of the switch circuit At the same position, the second part of the fourth lead is parallel to the first axis of symmetry.
  • the third lead and the fourth lead are directly connected to the first port and the second port without crossing, and the wiring is simple.
  • the third position and the first position are the same position, and the fourth position and the second position are the same position.
  • the embodiments of the present application provide another switch circuit.
  • the switch circuit includes a first metal oxide semiconductor MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube.
  • the gate and the gate of the fourth MOS tube are both connected to the first port, the gate of the second MOS tube and the gate of the third MOS tube are both connected to the second port; the gate of the first MOS tube is connected to the The leads between the gates of the fourth MOS transistor and the leads between the gates of the second MOS transistor and the gate of the third MOS transistor all pass through the same position on different layers in the switch circuit.
  • the lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor, and the lead between the gate of the second MOS transistor and the gate of the third MOS transistor all pass through the switching circuit In the same position on different layers; can improve the linearity of the switching circuit.
  • the length of the lead between the gate of the first MOS transistor and the first port, the length of the lead between the gate of the second MOS transistor and the second port, the The length of the lead between the gate of the third MOS transistor and the second port, and the length of the lead between the gate of the fourth MOS transistor and the first port are equal.
  • the length of the gate wiring of each MOS transistor in the switch circuit is the same, so that the gate parasitic capacitance of each MOS transistor is the same, and the linearity is higher.
  • the first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through the first position, and the gate of the second MOS transistor and the third MOS transistor
  • the second lead between the gates of the transistor passes through a second position, and the first position and the second position are the same position on different layers in the switching circuit; the lead from the gate of the first MOS transistor to the first position
  • the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, the length of the lead from the gate of the fourth MOS transistor to the second position The lengths of the leads at one location are equal.
  • the lead lengths from the gate of each MOS transistor in the switch circuit to the same position on different layers in the switch circuit are equal, so that the gate parasitic capacitance of each MOS transistor is the same and the linearity is higher.
  • the first MOS tube and the third MOS tube are aligned left and right and symmetrical along a first axis of symmetry
  • the second MOS tube and the fourth MOS tube are aligned left and right and along the first axis of symmetry.
  • Symmetrical the first MOS tube and the second MOS tube are aligned back and forth and symmetrical along the second axis of symmetry
  • the third MOS tube and the fourth MOS tube are aligned front and back and symmetrical along the second axis of symmetry
  • the second axis of symmetry are perpendicular to each other.
  • the symmetrical arrangement of the MOS transistors in the switch circuit can make the parasitic capacitances of the MOS transistors compatible, thereby improving the linearity of the mixer.
  • one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to The second port; the third position and the fourth position are symmetrical along the first axis of symmetry; the switch circuit is symmetrical along the first axis of symmetry.
  • the third lead and the fourth lead are symmetrical along the first symmetry axis, which can make the wiring of the gate of each MOS transistor symmetrical.
  • the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, and the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected.
  • the poles are directly connected to form the second lead, and both the first lead and the second lead are straight lines.
  • the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.
  • a part of the third lead is located on one side of the first axis of symmetry, another part of the third lead is located on the other side of the first axis of symmetry; a part of the fourth lead is located One side of the first axis of symmetry, the other part of the fourth lead is located on the other side of the first axis of symmetry; the third lead passes through the fifth position, the fourth lead passes through the sixth position, the fifth position and The sixth position is the same position on different layers in the switch circuit.
  • the gate wiring of each MOS transistor is strictly symmetrical, so that the parasitic capacitance of the gate of each MOS transistor is consistent.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the switch circuit, and the second part of the third lead is parallel to the first axis of symmetry,
  • the third part of the third lead is located on both sides of the first axis of symmetry, and the fourth part of the third lead is parallel to the first axis of symmetry;
  • the first part of the fourth lead and a part of the first lead are located at the At the same position of different layers in the switching circuit, the second part of the fourth lead is parallel to the first axis of symmetry,
  • the third part of the fourth lead is located on both sides of the first axis of symmetry, and the fourth lead of the fourth lead Part is parallel to the first axis of symmetry;
  • the third part of the third lead passes through the fifth position, and the third part of the fourth lead passes through the sixth position.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the switch circuit, and the first part of the fourth lead and part of the first lead are located on the same location on different layers of the switch circuit. Position, can effectively reduce the mutual influence between leads.
  • the third lead is located on one side of the first axis of symmetry, and the fourth lead is located on the other side of the first axis of symmetry; the first part of the third lead and the second lead A part of the switch circuit is located at the same position in different layers, the second part of the third lead is parallel to the first axis of symmetry; the first part of the fourth lead and a part of the first lead are located in different layers of the switch circuit At the same position, the second part of the fourth lead is parallel to the first axis of symmetry.
  • the third lead and the fourth lead are directly connected to the first port and the second port without crossing, and the wiring is simple.
  • the third position and the first position are the same position, and the fourth position and the second position are the same position.
  • an embodiment of the present application provides a mixer.
  • the mixer includes a first metal oxide semiconductor MOS transistor group; the first MOS transistor group includes a first MOS transistor, a second MOS transistor, and a third MOS transistor.
  • the gate of the first MOS transistor and the gate of the fourth MOS transistor are both connected to the first local oscillator port, and the gate of the second MOS transistor and the gate of the third MOS transistor Are connected to the second local oscillator port; the length of the lead between the gate of the first MOS tube and the first local oscillator port, the length of the lead between the gate of the second MOS tube and the second local oscillator port.
  • the length, the length of the lead between the gate of the third MOS transistor and the second local oscillator port, and the length of the lead between the gate of the fourth MOS transistor and the first local oscillator port are equal.
  • the length of the gate wiring of each MOS transistor in the mixer is the same, so that the gate parasitic capacitance of each MOS transistor is the same, and the linearity is higher.
  • the first local oscillator port and the second local oscillator port are both local oscillator ports that receive a driving voltage; the source of the first MOS transistor and the source of the second MOS transistor are both Connected to the first input port, the source of the third MOS transistor and the source of the fourth MOS transistor are both connected to the second input port; the drain of the first MOS transistor and the drain of the third MOS transistor are both connected to the An output port. The drain of the second MOS transistor and the drain of the fourth MOS transistor are both connected to the second output port.
  • the first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through the first position, and the gate of the second MOS transistor and the third MOS transistor
  • the second lead between the gates of the transistor passes through a second position, and the first position and the second position are the same positions on different layers in the mixer; the gate of the first MOS transistor passes through the first position.
  • the length of the lead, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, the gate of the fourth MOS transistor to the The lengths of the leads in the first position are equal.
  • the lead lengths from the gate of each MOS tube in the mixer to the same position in different layers of the mixer are equal, so that the gate parasitic capacitance of each MOS tube is the same and the linearity is higher.
  • the first MOS tube and the third MOS tube are aligned left and right and symmetrical along a first axis of symmetry
  • the second MOS tube and the fourth MOS tube are aligned left and right and along the first axis of symmetry.
  • Symmetrical the first MOS tube and the second MOS tube are aligned back and forth and symmetrical along the second axis of symmetry
  • the third MOS tube and the fourth MOS tube are aligned front and back and symmetrical along the second axis of symmetry
  • the second axis of symmetry are perpendicular to each other.
  • the symmetrical arrangement of the MOS tubes in the mixer can make the parasitic capacitances of the MOS tubes compatible, thereby improving the linearity of the mixer.
  • one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first local oscillator port;
  • one end of the fourth lead is connected to the fourth position of the second lead, and the other One end is connected to the second local oscillator port;
  • the third position and the fourth position are symmetrical along the first symmetry axis;
  • the mixer is symmetrical along the first symmetry axis.
  • the third lead and the fourth lead are symmetrical along the first symmetry axis, which can make the wiring of the gate of each MOS transistor symmetrical.
  • the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, and the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected.
  • the poles are directly connected to form the second lead, and both the first lead and the second lead are straight lines.
  • the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.
  • a part of the third lead is located on one side of the first axis of symmetry, another part of the third lead is located on the other side of the first axis of symmetry; a part of the fourth lead is located One side of the first axis of symmetry, the other part of the fourth lead is located on the other side of the first axis of symmetry; the third lead passes through the fifth position, the fourth lead passes through the sixth position, the fifth position and The sixth position is the same position on different layers in the mixer.
  • the gate wiring of each MOS transistor is strictly symmetrical, so that the resistance and parasitic capacitance of the gate of each MOS transistor are consistent.
  • the first part of the third lead and a part of the second lead are located at the same position in different layers of the mixer, and the second part of the third lead is parallel to the first axis of symmetry ,
  • the third part of the third lead is located on both sides of the first axis of symmetry,
  • the fourth part of the third lead is parallel to the first axis of symmetry;
  • the first part of the fourth lead and part of the first lead are located At the same position of different layers in the mixer
  • the second part of the fourth lead is parallel to the first axis of symmetry, and the third part of the fourth lead is located on both sides of the first axis of symmetry.
  • the fourth part is parallel to the first symmetry axis;
  • the third part of the third lead passes through the fifth position, and the third part of the fourth lead passes through the sixth position.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the mixer, and the first part of the fourth lead and part of the first lead are located on different layers in the mixer. The same position can effectively reduce the mutual influence between leads.
  • the third lead is located on one side of the first axis of symmetry, and the fourth lead is located on the other side of the first axis of symmetry; the first part of the third lead and the second lead A part of is located in the same position on different layers in the mixer, the second part of the third lead is parallel to the first axis of symmetry; the first part of the fourth lead and a part of the first lead are located in the mixer At the same position of different layers, the second part of the fourth lead is parallel to the first axis of symmetry.
  • the third lead and the fourth lead are directly connected to the first local oscillator port and the second local oscillator port without crossing, and the wiring is simple.
  • the third position and the first position are the same position, and the fourth position and the second position are the same position.
  • the first input port and the second input port are both connected to a low noise amplifier, and the first output port and the second output port are both connected to a transimpedance amplifier.
  • an embodiment of the present application provides another mixer.
  • the mixer includes a first metal oxide semiconductor MOS tube group and a second MOS tube group;
  • the first MOS tube group includes a first MOS tube,
  • the second MOS tube, the third MOS tube and the fourth MOS tube, the gate of the first MOS tube and the gate of the fourth MOS tube are both connected to the first local oscillator port, and the gate of the second MOS tube is connected to the
  • the length of the gate wiring of each MOS transistor in the mixer is the same, so that the gate parasitic capacitance of each MOS transistor is the same, and the linearity is higher.
  • the first MOS transistor group and the second MOS transistor group are aligned left and right and are symmetrical along the reference symmetry axis.
  • symmetrical placement of the first MOS transistor group and the second MOS transistor group can make the parasitic capacitances of the two MOS transistor groups consistent, and improve the linearity of the mixer.
  • the first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through the first position, and the gate of the second MOS transistor and the third MOS transistor
  • the second lead between the gates of the transistor passes through a second position, and the first position and the second position are the same positions on different layers in the mixer; the gate of the first MOS transistor passes through the first position.
  • the length of the lead, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, the gate of the fourth MOS transistor to the The lengths of the leads in the first position are equal.
  • the lead lengths from the gate of each MOS tube in the mixer to the same position in different layers of the mixer are equal, so that the gate parasitic capacitance of each MOS tube is the same and the linearity is higher.
  • the first MOS tube and the third MOS tube are aligned left and right and symmetrical along a first axis of symmetry
  • the second MOS tube and the fourth MOS tube are aligned left and right and along the first axis of symmetry.
  • Symmetrical the first MOS tube and the second MOS tube are aligned back and forth and symmetrical along the second axis of symmetry
  • the third MOS tube and the fourth MOS tube are aligned front and back and symmetrical along the second axis of symmetry
  • the second axis of symmetry are perpendicular to each other.
  • the symmetrical arrangement of the MOS tubes in the mixer can make the parasitic capacitances of the MOS tubes compatible, thereby improving the linearity of the mixer.
  • one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to The second port; the third position and the fourth position are symmetrical along the first axis of symmetry; the mixer is symmetrical along the first axis of symmetry.
  • the third lead and the fourth lead are symmetrical along the first symmetry axis, which can make the wiring of the gate of each MOS transistor symmetrical.
  • the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, and the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected.
  • the poles are directly connected to form the second lead, and both the first lead and the second lead are straight lines.
  • the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.
  • a part of the third lead is located on one side of the first axis of symmetry, another part of the third lead is located on the other side of the first axis of symmetry; a part of the fourth lead is located One side of the first axis of symmetry, the other part of the fourth lead is located on the other side of the first axis of symmetry; the third lead passes through the fifth position, the fourth lead passes through the sixth position, the fifth position and The sixth position is the same position on different layers in the mixer.
  • the gate wiring of each MOS transistor is strictly symmetrical, so that the resistance and parasitic capacitance of the gate of each MOS transistor are consistent.
  • the first part of the third lead and a part of the second lead are located at the same position in different layers of the mixer, and the second part of the third lead is parallel to the first axis of symmetry ,
  • the third part of the third lead is located on both sides of the first axis of symmetry,
  • the fourth part of the third lead is parallel to the first axis of symmetry;
  • the first part of the fourth lead and part of the first lead are located At the same position of different layers in the mixer
  • the second part of the fourth lead is parallel to the first axis of symmetry, and the third part of the fourth lead is located on both sides of the first axis of symmetry.
  • the fourth part is parallel to the first symmetry axis;
  • the third part of the third lead passes through the fifth position, and the third part of the fourth lead passes through the sixth position.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the mixer, and the first part of the fourth lead and part of the first lead are located on different layers in the mixer. The same position can effectively reduce the mutual influence between leads.
  • the third lead is located on one side of the first axis of symmetry, and the fourth lead is located on the other side of the first axis of symmetry; the first part of the third lead and the second lead A part of is located in the same position on different layers in the mixer, the second part of the third lead is parallel to the first axis of symmetry; the first part of the fourth lead and a part of the first lead are located in the mixer At the same position of different layers, the second part of the fourth lead is parallel to the first axis of symmetry.
  • the third lead and the fourth lead are directly connected to the first local oscillator port and the second local oscillator port without crossing, and the wiring is simple.
  • the third position and the first position are the same position, and the fourth position and the second position are the same position.
  • the first MOS transistor group and the second MOS transistor group are placed on different deep N wells.
  • the isolation between the first MOS transistor group and the second MOS transistor group is relatively high.
  • the first input port and the second input port are both connected to a low noise amplifier, and the first output port and the second output port are both connected to a transimpedance amplifier.
  • the embodiments of the present application provide yet another mixer.
  • the mixer includes a first metal oxide semiconductor MOS tube group and a second MOS tube group, the first MOS tube group and the second MOS tube group The groups are placed on different deep N wells.
  • the circuit structure of the second MOS transistor group is the same as the circuit structure of the first MOS transistor group.
  • two MOS transistor groups are placed on different deep N-wells, which can improve the isolation between the two MOS transistor groups.
  • the first MOS tube group includes a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube, the gate of the first MOS tube and the fourth MOS tube
  • the gates of the first MOS transistor are connected to the first port, the gate of the second MOS transistor and the gate of the third MOS transistor are both connected to the second port; the lead wire between the gate of the first MOS transistor and the first port Length, the length of the lead between the gate of the second MOS tube and the second port, the length of the lead between the gate of the third MOS tube and the second port, the gate of the fourth MOS tube
  • the lengths of the leads between the first port and the first port are equal.
  • the length of the gate wiring of each MOS tube in the mixer is the same, so that the gate parasitic capacitance of each MOS tube is the same, and the linearity is higher.
  • the first MOS transistor group and the second MOS transistor group are aligned left and right and are symmetrical along the reference symmetry axis.
  • symmetrical placement of the first MOS transistor group and the second MOS transistor group can make the parasitic capacitances of the two MOS transistor groups consistent, and improve the linearity of the mixer.
  • the first lead between the gate of the first MOS transistor and the gate of the fourth MOS transistor passes through the first position, and the gate of the second MOS transistor and the third MOS transistor
  • the second lead between the gates of the transistor passes through a second position, and the first position and the second position are the same positions on different layers in the mixer; the gate of the first MOS transistor passes through the first position.
  • the length of the lead, the length of the lead from the gate of the second MOS transistor to the second position, the length of the lead from the gate of the third MOS transistor to the second position, the gate of the fourth MOS transistor to the The lengths of the leads in the first position are equal.
  • the lead lengths from the gate of each MOS tube in the mixer to the same position in different layers of the mixer are equal, so that the gate parasitic capacitance of each MOS tube is the same and the linearity is higher.
  • the first MOS tube and the third MOS tube are aligned left and right and symmetrical along a first axis of symmetry
  • the second MOS tube and the fourth MOS tube are aligned left and right and along the first axis of symmetry.
  • Symmetrical the first MOS tube and the second MOS tube are aligned back and forth and symmetrical along the second axis of symmetry
  • the third MOS tube and the fourth MOS tube are aligned front and back and symmetrical along the second axis of symmetry
  • the second axis of symmetry are perpendicular to each other.
  • the symmetrical arrangement of the MOS tubes in the mixer can make the parasitic capacitances of the MOS tubes compatible, thereby improving the linearity of the mixer.
  • one end of the third lead is connected to the third position of the first lead, and the other end is connected to the first port; one end of the fourth lead is connected to the fourth position of the second lead, and the other end is connected to The second port; the third position and the fourth position are symmetrical along the first axis of symmetry; the mixer is symmetrical along the first axis of symmetry.
  • the third lead and the fourth lead are symmetrical along the first symmetry axis, which can make the wiring of the gate of each MOS transistor symmetrical.
  • the gate of the first MOS transistor and the gate of the fourth MOS transistor are directly connected to form the first lead, and the gate of the second MOS transistor and the gate of the third MOS transistor are directly connected.
  • the poles are directly connected to form the second lead, and both the first lead and the second lead are straight lines.
  • the gate of the first MOS transistor is directly connected to the gate of the fourth MOS transistor, and the gate of the second MOS transistor is directly connected to the gate of the third MOS transistor, which can effectively reduce the length of the lead.
  • a part of the third lead is located on one side of the first axis of symmetry, another part of the third lead is located on the other side of the first axis of symmetry; a part of the fourth lead is located One side of the first axis of symmetry, the other part of the fourth lead is located on the other side of the first axis of symmetry; the third lead passes through the fifth position, the fourth lead passes through the sixth position, the fifth position and The sixth position is the same position on different layers in the mixer.
  • the gate wiring of each MOS transistor is strictly symmetrical, so that the resistance and parasitic capacitance of the gate of each MOS transistor are consistent.
  • the first part of the third lead and a part of the second lead are located at the same position in different layers of the mixer, and the second part of the third lead is parallel to the first axis of symmetry ,
  • the third part of the third lead is located on both sides of the first axis of symmetry,
  • the fourth part of the third lead is parallel to the first axis of symmetry;
  • the first part of the fourth lead and part of the first lead are located At the same position of different layers in the mixer
  • the second part of the fourth lead is parallel to the first axis of symmetry, and the third part of the fourth lead is located on both sides of the first axis of symmetry.
  • the fourth part is parallel to the first symmetry axis;
  • the third part of the third lead passes through the fifth position, and the third part of the fourth lead passes through the sixth position.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the mixer, and the first part of the fourth lead and part of the first lead are located on different layers in the mixer. The same position can effectively reduce the mutual influence between leads.
  • the third lead is located on one side of the first axis of symmetry, and the fourth lead is located on the other side of the first axis of symmetry; the first part of the third lead and the second lead A part of is located in the same position on different layers in the mixer, the second part of the third lead is parallel to the first axis of symmetry; the first part of the fourth lead and a part of the first lead are located in the mixer At the same position of different layers, the second part of the fourth lead is parallel to the first axis of symmetry.
  • the third lead and the fourth lead are directly connected to the first port and the second port without crossing, and the wiring is simple.
  • the third position and the first position are the same position, and the fourth position and the second position are the same position.
  • the first input port and the second input port are both connected to a low noise amplifier, and the first output port and the second output port are both connected to a transimpedance amplifier.
  • an embodiment of the present application provides an electronic device, which includes the mixer in any one of the foregoing third aspect to the foregoing fifth aspect and any optional implementation manner.
  • the electronic device may be a receiver, a transceiver, or a radio frequency chip in a terminal (such as a mobile phone, a base station, etc.), a terminal, or other devices.
  • Figure 1 is a schematic diagram of the structure of the front and rear stages of a mixer in a receiver
  • Figure 2 is a circuit schematic diagram of a mixer
  • Figure 3 is a layout structure of a traditional mixer
  • Figure 4 is a layout structure of a set of switching circuits in a mixer
  • Figure 5 is a schematic circuit diagram of a switch circuit
  • FIG. 6 is a layout structure of a mixer provided by an embodiment of the application.
  • FIG. 7 provides a layout structure of a switch circuit according to an embodiment of the application.
  • FIG. 8 is a layout structure of another switch circuit provided by an embodiment of the application.
  • FIG. 9A is a layout structure of a traditional mixer
  • FIG. 9B is a layout structure of a mixer provided by an embodiment of the application.
  • the mixer (namely Mixer) is the core circuit responsible for the spectrum shift function in the transceiver, and it has a wide range of applications in microwave wireless communication systems, radar systems and measurement systems.
  • the receiver basically includes components such as amplifiers, filters, mixers, etc., which are used to amplify, filter, and perform several frequency shifts or conversions of analog input signals, and then pass the analog-to-digital converter (Analog-to-Digital Converter, ADC ) Sampling and sending the digital signal to a computer or digital signal processor for further processing.
  • ADC Analog-to-Digital Converter
  • the mixer is in a position where the RF signal amplitude is high in the receiver and many interference signals are not effectively suppressed.
  • Fig. 1 is a structural diagram of the front and back stages of a mixer in a receiver.
  • 101 is a low-noise amplifier
  • 102 is a mixer
  • 103 is a transimpedance amplifier
  • the mixer 102 is at the rear stage of the low-noise amplifier 101
  • the transimpedance amplifier 103 is at the rear stage of the mixer 102 ;
  • the low-noise amplifier 101 processes the received weak signals through low-noise amplification, and inputs quadrature radio frequency signals to the two input ends of the mixer 102;
  • the mixer 102 mixes the radio frequency signals at its input ends with the local oscillator signal Frequency (ie, frequency shift) to obtain an intermediate frequency signal;
  • the transimpedance amplifier 103 converts the received intermediate frequency signal into a voltage signal.
  • Fig. 1 is only an example provided in this application.
  • the mixer can be used in a variety of circuits, and this application does not limit the
  • Figure 2 is a circuit diagram of a mixer.
  • the dashed frame on the left is the first switch circuit, and the dashed frame on the right is the second switch circuit;
  • the first switch circuit is composed of M1 to M4, and M1 to M4 are all metal oxide semiconductors (Metal Oxide Semiconductor, MOS) tube, the gate of M1 and the gate of M4 are both connected to the input port LOP1, the gate of M2 and the gate of M3 are both connected to the input port LON1, the source of M1 and the source of M2 are both connected to the input port RFIP, the source of M3 and the source of M4 are all connected to the input port RFIN, the output ports of the first switch circuit are IFIP and IFIN;
  • the second switch circuit is composed of M5 ⁇ M8, M5 ⁇ M8 are all MOS transistors, M5 The gate of M8 and the gate of M8 are both connected to the input port LOP2, the gate of M6 and the gate of M7 are both connected to the input port
  • FIG. 2 is only an example of a circuit principle diagram of a mixer provided in this application.
  • the circuit principle diagrams of different types of mixers are different, and this application does not limit the circuit principle diagram of the mixer.
  • the mixer includes two sets of switching circuits with the same structure.
  • the gates of M1 and M4 are both connected to the input port LOP1, and the gates of M2 and M3 are both connected to the input port.
  • the gates of LON1, M5 and M8 are all connected to the input port LOP2, and the gates of M6 and M7 are both connected to the input port LON2.
  • the two sets of switching circuits are driven by orthogonal quadrature local oscillator signals.
  • One group outputs I-channel IF signals, and the other group outputs Q-channel IF signals.
  • the layout structure of the mixer includes two sets of symmetrically arranged switching circuits.
  • the gates of the four MOS transistors in each set of switching circuits are connected to a lead; among them, two gate leads are connected to an output port of the LO, and the other two The gate lead is connected to the other output port of the LO.
  • Figure 3 shows the layout structure of a traditional mixer. As shown in Figure 3, M1 ⁇ M8 correspond to M1 ⁇ M8 in Figure 2 in turn.
  • the layout structure on the left half of Figure 3 corresponds to the switch circuit in the dashed box on the left in Figure 2, and the layout structure on the right half of Figure 3 corresponds to Figure 2.
  • the poles are all connected to the output port LOP2 of LO, the gate of M6 and the gate of M7 are both connected to the output port LON2 of LO;
  • the drain of M1 and the drain of M3 are connected to the output port IFIP, the drain of M2 and the drain of M4 Both are connected to the output port IFIN, the drain of M5 and M7 are connected to the output port IFQP, the drain of M6 and the drain of M8 are both connected to the output port IFQN;
  • the source of M1 and the source of M2 are both connected to the input port RFIP ,
  • the source of M3 and the source of M4 are both connected to the input port RFIN; the source of M
  • Figure 4 shows the layout structure of a group of switching circuits in the mixer.
  • M1 ⁇ M4 correspond to M1 ⁇ M4 in Figure 2
  • the gate of M1 and the gate of M4 are both connected to the input port LOP1 of LO
  • the gate of M2 and M3 are both connected to the output of LO Port LON1
  • the drain stage of M1 and the drain stage of M3 are connected to the output port IFIP
  • the drain stage of M2 and the drain stage of M4 are both connected to the output port IFIN
  • the source of M1 and the source of M2 are connected to the same input port RFIP
  • the source of M4 and the source of M4 are connected to another input port RFIN.
  • Fig. 5 is a schematic diagram of the circuit corresponding to the layout structure in Fig. 4.
  • M1 to M4 in Figure 5 correspond to M1 to M4 in Figure 4, the gate of M1 and the gate of M4 are both connected to the input port LOP1, the gate of M2 and the gate of M3 are both connected to the input port LON1, the source of M1 The source of M2 and M2 are both connected to the input port RFIP, the source of M3 and the source of M4 are both connected to the input port RFIN, and the output ports of the first switch circuit are IFIP and IFIN.
  • the gate trace lengths of the four MOS transistors are inconsistent, which makes the parasitics of the gates of the four MOS transistors inconsistent, which directly destroys the symmetry of the MOS transistors. It affects the linearity of the mixer. Therefore, it is necessary to solve the problem of asymmetry of the wiring of the MOS transistors in the layout structure of the traditional mixer, so that the parasitics of the gates of the four MOS transistors are consistent, thereby improving the linearity of the mixer.
  • the circuit principle diagram corresponding to the layout structure of the mixer provided in this application is a mixer circuit including two sets of switch circuits.
  • FIG. 1 is an example of a circuit principle diagram corresponding to the layout structure.
  • Fig. 6 is a layout structure of a mixer provided by this application. As shown in Figure 6, M1 to M8 correspond to M1 to M8 in Figure 2, and the layout structure in the left half of Figure 6 corresponds to the first switch circuit (corresponding to the first MOS tube group) in the dashed box on the left in Figure 2.
  • the layout structure in the right half of 6 corresponds to the second switch circuit (corresponding to the second MOS tube group) in the dotted line on the right in Figure 2; the gate of M1 and the gate of M4 are directly connected through the first lead (601 in the figure) and The first lead is connected to one end of the third lead (603 in the figure), and the other end of the third lead is connected to the output port LOP1 of LO.
  • the gate of M2 and the gate of M3 directly pass through the second lead (602 in the figure).
  • the first lead and the third lead are located on the same layer, and the second lead and the fourth lead are located on the same layer.
  • the left half of the diagram in FIG. 6 corresponds to the first layout area of the first switching circuit (corresponding to the first MOS tube group), and the right half of the diagram in FIG. 6 corresponds to the second switching circuit (corresponding to the second MOS tube group).
  • the second layout area of the tube group), the first layout area and the second layout area are aligned left and right and symmetrical along the reference symmetry axis. Comparing FIG. 6 and FIG. 3, it can be seen that the layout structure of the mixer provided by the embodiment of the present application is compared with the layout structure of the traditional mixer.
  • the main difference is that the gates of the four MOS transistors in each group of switching circuits
  • the wiring length is the same, which makes the parasitic of the gate of the MOS tube the same.
  • the first lead between the gate of M1 and the gate of M4 and the second lead between the gate of M2 and the gate of M3 are located in different layers of the layout structure. That is, the first lead and the second lead will not intersect.
  • the layout structure of the mixer provided by the embodiment of the application, the layout structure of the two groups of switching tubes is symmetrical. In order to more conveniently describe the layout structure of each group of switching circuits in the layout structure of the mixer, the following specifically describes one group The layout structure of the switch circuit.
  • FIG. 7 is a layout structure of a switch circuit provided by an embodiment of the application, and a circuit diagram corresponding to the layout structure is shown in FIG. 5.
  • the layout structure of the switch circuit in FIG. 7 is an example of the layout structure of the first MOS transistor group.
  • the layout structure of the switch circuit includes a first MOS tube (ie M1 in Figure 7), a second MOS tube (ie M2 in Figure 7), and a third MOS tube (ie M3 in Figure 7)
  • the fourth MOS tube (ie M4 in Figure 7) the gate of M1 and the gate of M4 are directly connected through the first lead (701 in the figure) and the first lead is connected to the third lead (703 in the figure)
  • the gate of M2 and the gate of M3 are directly connected through the second lead (702 in the figure) and the second lead is connected to the One end of the four lead (704 in the figure), the other end of the fourth lead is connected to the output port LON1 of the LO (corresponding to the second port)
  • M1 and M3 are aligned left and right and symmetrical along the first symmetry axis
  • M2 and M4 are aligned left and right and Symmetrical along the
  • the first position is the midpoint of the first lead
  • the second position is the midpoint of the second lead
  • the intersection of the axes is at the same position on different layers in the layout structure.
  • the third position is the midpoint of the first lead
  • the fourth position is the midpoint of the second lead
  • the intersection of the axes is at the same position on different layers in the layout structure.
  • the third position and the fourth position are not the same position on different layers in the layout structure.
  • the third position and the first position are the same position
  • the fourth position and the second position are the same position.
  • the gate of M1 and the gate of M4 are directly connected to form the first lead, and the gate of M2 and M3 are directly connected to form the second lead. Both the first lead and the second lead are straight lines.
  • the gate of M1 and the gate of M4 are directly connected, and the gate of M2 and the gate of M3 are directly connected, which can effectively reduce the length of the lead and lower the cost.
  • a part of the third lead (703 in the figure) is located on one side of the first symmetry axis, and another part of the third lead is located on the first symmetry axis.
  • part of the fourth lead (704 in the figure) is located on one side of the first axis of symmetry, and another part of the fourth lead is located on the other side of the first axis of symmetry;
  • the third lead passes through the At five positions, the fourth lead passes through the sixth position, and the fifth position and the sixth position are the same positions on different layers in the layout structure.
  • the gate traces of M1 ⁇ M4 are crossed twice to the LO port (that is, the input ports LOP1 and LON1 in the figure), so that the gate traces of M1 ⁇ M4 are strictly symmetrical, which can further improve the switch The linearity of the circuit.
  • the first part of the third lead (7031 in the figure) and a part of the second lead (702 in the figure) are located on the same layer in different layers of the layout structure. Position, the second part of the third lead (7032 in the figure) is parallel to the first symmetry axis, and the third part of the third lead (7033 in the figure) is located on both sides of the first symmetry axis.
  • the fourth part of the lead (7034 in the figure) is parallel to the first axis of symmetry; the first part of the fourth lead (which is symmetrical to 7031 about the first axis of symmetry) and a part of the first lead are located in different layers in the above layout structure At the same position, the second part of the fourth lead (symmetric with 7032 about the first axis of symmetry) is parallel to the first axis of symmetry, and the third part of the fourth lead (symmetric with 7033 about the first axis of symmetry) is located here On both sides of the first axis of symmetry, the fourth part of the fourth lead (which is symmetric with 7034 about the first axis of symmetry) is parallel to the first axis of symmetry; the third part of the third lead passes through the fifth position, and the first The third part of the four-lead passes through the sixth position described above.
  • the third lead and the first lead are on the same layer of the layout structure, and the second lead and the fourth lead are on the same layer of the layout structure.
  • the first part of the third lead and a part of the second lead are located at the same position on different layers in the above-mentioned layout structure, and the first part of the fourth lead and a part of the first lead are located at the same position on different layers in the layout structure. Position, can effectively reduce the mutual influence between leads.
  • the gate traces of M1 to M4 pass through two cross leads to the LO port (that is, the input ports LOP1 and LON1 in the figure).
  • the gate traces of M1 to M4 can pass through at least one crossover lead to the LO port.
  • the gate traces of M1 to M4 in the layout structure of the mixer can be crossed to the LO port through an even number of times, so that the layout structure has better linearity performance.
  • the gate traces of M1 to M4 can pass through a crossover lead to the LO port.
  • FIG. 8 is a layout structure of another switch circuit provided by an embodiment of the application, and the circuit diagram corresponding to the layout structure is shown in FIG. 5.
  • 801 is the first lead
  • 802 is the second lead
  • 8031 is the first part of the third lead
  • 8032 is the second part of the first lead
  • 804 is the fourth lead.
  • the first part (8031) of the third lead and a part of the second lead are at the same position on different layers of the layout structure, and the second part (8032) of the third lead is parallel to the first axis of symmetry;
  • the first part of the fourth lead (symmetrical with 8031 along the first symmetry axis) and a part of the first lead are at the same position in different layers of the layout structure, and the second part of the fourth lead (symmetrical with 8032 along the first symmetry axis) ) Is parallel to the first axis of symmetry.
  • the third lead and the first lead are on the same layer of the layout structure, and the second lead and the fourth lead are on the same layer of the layout structure.
  • one end of the third lead is connected to the midpoint of the first lead, and one end of the fourth lead is connected to the midpoint of the second lead. Comparing FIG. 7 and FIG. 8, it can be seen that the layout structure in FIG. 8 is different from the layout structure in FIG. 7 in that the gate traces of M1 to M4 can pass through a cross lead to the LO port.
  • the third lead and the fourth lead are directly connected to the LO port without crossing, and the wiring is simple.
  • the first switch circuit and the second switch circuit are placed on different deep N-wells (also called deep n-wel, abbreviated as DNW).
  • DNW deep n-wel
  • two sets of switching circuits are placed on the same deep N-well, one set of switching circuits corresponds to the I channel, and the other set of switching circuits corresponds to the Q channel, and the isolation of the I and Q channels is poor.
  • Figure 9A is a layout structure of a conventional mixer. As shown in FIG. 9A, the first switching circuit and the second switching circuit are placed on the same deep N-well, which makes the isolation of the IQ two paths poor.
  • FIG. 9B is a layout structure of a mixer provided by an embodiment of the application.
  • the first switch circuit is placed on DNW1, and the second switch circuit is placed on DNW2.
  • the first switch circuit and the second switch circuit are placed on different deep N-wells in order to enhance the isolation of the IQ two paths.
  • the first switch circuit and the second switch circuit in Fig. 9B are arranged on different deep N-wells.
  • the first switch circuit corresponds to the I channel
  • the second switch circuit corresponds to the Q channel. This can enhance both I and Q. Road isolation.
  • the layout structure of the switching circuit provided in this application is a layout structure with better linearity performance, and is not limited to being applied to the layout structure of a mixer, but can also be applied to other circuits. In this application, equality is not limited to complete equality, but a certain deviation is allowed.
  • One purpose of the solution of the present application is to make the lengths of the traces of the gates of the MOSs as equal as possible, and does not limit the length of the traces of the gates of the MOSs to be completely consistent.
  • the above are only specific implementations of this application, but the protection scope of this application is not limited to this.
  • anyone familiar with the technical field can easily think of various equivalents within the technical scope disclosed in this application. Modifications or replacements, these modifications or replacements shall be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

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Abstract

本申请实施例公开了一种开关电路、混频器及电子设备，该开关电路包括第一金属氧化物半导体MOS管、第二MOS管、第三MOS管以及第四MOS管，该第一MOS管的栅极和该第四MOS管的栅极均连接第一端口，该第二MOS管的栅极和该第三MOS管的栅极均连接第二端口；该第一MOS管的栅极与该第一端口之间的引线的长度、该第二MOS管的栅极与该第二端口之间的引线的长度、该第三MOS管的栅极与该第二端口之间的引线的长度、该第四MOS管的栅极与该第一端口之间的引线的长度均相等；线性度较高。

Description

开关电路、混频器及电子设备 技术领域
本申请涉及电子技术领域，尤其涉及一种开关电路、混频器及电子设备。
背景技术
在电子通讯系统中，混频器(即Mixer)是收发机中负责频谱搬移功能的核心电路，在微波无线通信系统、雷达系统和测量系统中有着广泛的应用。混频器的技术指标主要有：中频/射频频带、变频增益、噪声系数、线性度、端口间隔离度、端口驻波比、功耗等。
由于混频器在接收机中处于射频信号幅度较高的位置且许多干扰信号未得到有效抑制，因此，线性度是一个非常重要(甚至是最重要的)的指标。其中，输入二阶交调点(IIP2)是衡量混频器的线性度的重要指标之一。IIP2是量化由电路(诸如放大器和混频器)的非线性而产生的二阶失真的线性度的度量。当前，混频器的线性度较差，需要研究线性度更优的混频器。
发明内容
本申请实施例提供了开关电路、混频器及电子设备，以利于改善器件的线性度。
第一方面，本申请实施例提供了一种开关电路，该开关电路包括第一金属氧化物半导体MOS管、第二MOS管、第三MOS管以及第四MOS管，该第一MOS管的栅极和该第四MOS管的栅极均连接第一端口，该第二MOS管的栅极和该第三MOS管的栅极均连接第二端口；该第一MOS管的栅极与该第一端口之间的引线的长度、该第二MOS管的栅极与该第二端口之间的引线的长度、该第三MOS管的栅极与该第二端口之间的引线的长度、该第四MOS管的栅极与该第一端口之间的引线的长度均相等。
本申请实施例中，开关电路中各MOS管的栅极走线的长度相同，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极之间的第一引线经过第一位置，该第二MOS管的栅极和该第三MOS管的栅极之间的第二引线经过第二位置，该第一位置和该第二位置为该开关电路中不同层的同一位置；该第一MOS管的栅极至该第一位置的引线的长度、该第二MOS管的栅极至该第二位置的引线的长度、该第三MOS管的栅极至该第二位置的引线的长度、该第四MOS管的栅极至该第一位置的引线的长度相等。
在该实现方式中，开关电路中各MOS管的栅极至开关电路中不同层的同一位置的引线长度相等，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一MOS管和该第三MOS管左右对齐且沿第一对称轴对称，该第二MOS管和该第四MOS管左右对齐且沿该第一对称轴对称，该第一MOS管和该第二MOS管前后对齐且沿第二对称轴对称，该第三MOS管和该第四MOS管前后对 齐且沿该第二对称轴对称，该第一对称轴和该第二对称轴相互垂直。
在该实现方式中，开关电路中各MOS管对称布置，可以使得各MOS管的寄生电容相容，进而改善该混频器的线性度。
在一个可选的实现方式中，第三引线的一端连接该第一引线的第三位置，另一端连接该第一端口；第四引线的一端连接该第二引线的第四位置，另一端连接该第二端口；该第三位置和该第四位置沿该第一对称轴对称；该开关电路沿该第一对称轴对称。
在该实现方式中，第三引线和第四引线沿第一对称轴对称，可以使得各MOS管的栅极的走线对称。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极直接连接形成该第一引线，该第二MOS管的栅极和该第三MOS管的栅极直接连接形成该第二引线，该第一引线和该第二引线均为直线。
在这种实现方式中，第一MOS管的栅极和第四MOS管的栅极直接连接，第二MOS管的栅极和第三MOS管的栅极直接，可以有效减少引线的长度，成本较低。
在一个可选的实现方式中，该第三引线的一部分位于该第一对称轴的一侧，该第三引线的另一部分位于该第一对称轴的另一侧；该第四引线的一部分位于该第一对称轴的一侧，该第四引线的另一部分位于该第一对称轴的另一侧；该第三引线经过第五位置，该第四引线经过第六位置，该第五位置和该第六位置为该开关电路中不同层的同一位置。
在该实现方式中，各MOS管的栅极走线严格对称，使得各MOS管的栅极的寄生电容一致。
在一个可选的实现方式中，该第三引线的第一部分和该第二引线的一部分位于该开关电路中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴，该第三引线的第三部分位于该第一对称轴的两侧，该第三引线的第四部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该开关电路中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴，该第四引线的第三部分位于该第一对称轴的两侧，该第四引线的第四部分平行于该第一对称轴；该第三引线的第三部分经过该第五位置，该第四引线的第三部分经过该第六位置。
在该实现方式中，第三引线的第一部分和第二引线的一部分位于该开关电路中不同层的同一位置,第四引线的第一部分和第一引线的一部分位于该开关电路中不同层的同一位置，可以有效减少引线之间的相互影响。
在一个可选的实现方式中，该第三引线位于该第一对称轴的一侧，该第四引线位于该第一对称轴的另一侧；该第三引线的第一部分和该第二引线的一部分位于该开关电路中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该开关电路中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴。
在该实现方式中，第三引线和第四引线不经过交叉而是直接连接第一端口和第二端口，走线简单。
在一个可选的实现方式中，该第三位置和该第一位置为同一位置，该第四位置和该第二位置为同一位置。
第二方面，本申请实施例提供了另一种开关电路，该开关电路包括第一金属氧化物半导体MOS管、第二MOS管、第三MOS管以及第四MOS管，该第一MOS管的栅极和该第四MOS管的栅极均连接第一端口，该第二MOS管的栅极和该第三MOS管的栅极均连接第二端口；该第一MOS管的栅极和该第四MOS管的栅极之间的引线，与该第二MOS管的栅极和该第三MOS管的栅极之间的引线均经过该开关电路中不同层的同一位置。
本申请实施例中，第一MOS管的栅极和第四MOS管的栅极之间的引线，与第二MOS管的栅极和第三MOS管的栅极之间的引线均经过开关电路中不同层的同一位置；可以改善该开关电路的线性度。
在一个可选的实现方式中，该第一MOS管的栅极与该第一端口之间的引线的长度、该第二MOS管的栅极与该第二端口之间的引线的长度、该第三MOS管的栅极与该第二端口之间的引线的长度、该第四MOS管的栅极与该第一端口之间的引线的长度均相等。
在该实现方式中，开关电路中各MOS管的栅极走线的长度相同，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极之间的第一引线经过第一位置，该第二MOS管的栅极和该第三MOS管的栅极之间的第二引线经过第二位置，该第一位置和该第二位置为该开关电路中不同层的同一位置；该第一MOS管的栅极至该第一位置的引线的长度、该第二MOS管的栅极至该第二位置的引线的长度、该第三MOS管的栅极至该第二位置的引线的长度、该第四MOS管的栅极至该第一位置的引线的长度相等。
在该实现方式中，开关电路中各MOS管的栅极至开关电路中不同层的同一位置的引线长度相等，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一MOS管和该第三MOS管左右对齐且沿第一对称轴对称，该第二MOS管和该第四MOS管左右对齐且沿该第一对称轴对称，该第一MOS管和该第二MOS管前后对齐且沿第二对称轴对称，该第三MOS管和该第四MOS管前后对齐且沿该第二对称轴对称，该第一对称轴和该第二对称轴相互垂直。
在该实现方式中，开关电路中各MOS管对称布置，可以使得各MOS管的寄生电容相容，进而改善该混频器的线性度。
在一个可选的实现方式中，第三引线的一端连接该第一引线的第三位置，另一端连接该第一端口；第四引线的一端连接该第二引线的第四位置，另一端连接该第二端口；该第三位置和该第四位置沿该第一对称轴对称；该开关电路沿该第一对称轴对称。
在该实现方式中，第三引线和第四引线沿第一对称轴对称，可以使得各MOS管的栅极的走线对称。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极直接连接形成该第一引线，该第二MOS管的栅极和该第三MOS管的栅极直接连接形成该第二引线，该第一引线和该第二引线均为直线。
在这种实现方式中，第一MOS管的栅极和第四MOS管的栅极直接连接，第二MOS管的栅极和第三MOS管的栅极直接，可以有效减少引线的长度。
在一个可选的实现方式中，该第三引线的一部分位于该第一对称轴的一侧，该第三引 线的另一部分位于该第一对称轴的另一侧；该第四引线的一部分位于该第一对称轴的一侧，该第四引线的另一部分位于该第一对称轴的另一侧；该第三引线经过第五位置，该第四引线经过第六位置，该第五位置和该第六位置为该开关电路中不同层的同一位置。
在该实现方式中，各MOS管的栅极走线严格对称，使得各MOS管的栅极的寄生电容一致。
在一个可选的实现方式中，该第三引线的第一部分和该第二引线的一部分位于该开关电路中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴，该第三引线的第三部分位于该第一对称轴的两侧，该第三引线的第四部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该开关电路中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴，该第四引线的第三部分位于该第一对称轴的两侧，该第四引线的第四部分平行于该第一对称轴；该第三引线的第三部分经过该第五位置，该第四引线的第三部分经过该第六位置。
在该实现方式中，第三引线的第一部分和第二引线的一部分位于该开关电路中不同层的同一位置,第四引线的第一部分和第一引线的一部分位于该开关电路中不同层的同一位置，可以有效减少引线之间的相互影响。
在一个可选的实现方式中，该第三引线位于该第一对称轴的一侧，该第四引线位于该第一对称轴的另一侧；该第三引线的第一部分和该第二引线的一部分位于该开关电路中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该开关电路中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴。
在该实现方式中，第三引线和第四引线不经过交叉而是直接连接第一端口和第二端口，走线简单。
在一个可选的实现方式中，该第三位置和该第一位置为同一位置，该第四位置和该第二位置为同一位置。
第三方面，本申请实施例提供了一种混频器，该混频器包括第一金属氧化物半导体MOS管组；该第一MOS管组包括第一MOS管、第二MOS管、第三MOS管以及第四MOS管，该第一MOS管的栅极和该第四MOS管的栅极均连接第一本振端口，该第二MOS管的栅极和该第三MOS管的栅极均连接第二本振端口；该第一MOS管的栅极与该第一本振端口之间的引线的长度、该第二MOS管的栅极与该第二本振端口之间的引线的长度、该第三MOS管的栅极与该第二本振端口之间的引线的长度、该第四MOS管的栅极与该第一本振端口之间的引线的长度均相等。
本申请实施例中，混频器中各MOS管的栅极走线的长度相同，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一本振端口和该第二本振端口均为接收驱动电压的本振端口；该第一MOS管的源极和该第二MOS管的源极均连接第一输入端口，该第三MOS管的源极和该第四MOS管的源极均连接第二输入端口；该第一MOS管的漏极和该第三MOS管的漏极均连接第一输出端口，该第二MOS管的漏极和该第四MOS管的漏极均连接第二输出端口。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极之间的第一引线经过第一位置，该第二MOS管的栅极和该第三MOS管的栅极之间的第二引线经过第二位置，该第一位置和该第二位置为该混频器中不同层的同一位置；该第一MOS管的栅极至该第一位置的引线的长度、该第二MOS管的栅极至该第二位置的引线的长度、该第三MOS管的栅极至该第二位置的引线的长度、该第四MOS管的栅极至该第一位置的引线的长度相等。
在该实现方式中，混频器中各MOS管的栅极至混频器中不同层的同一位置的引线长度相等，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一MOS管和该第三MOS管左右对齐且沿第一对称轴对称，该第二MOS管和该第四MOS管左右对齐且沿该第一对称轴对称，该第一MOS管和该第二MOS管前后对齐且沿第二对称轴对称，该第三MOS管和该第四MOS管前后对齐且沿该第二对称轴对称，该第一对称轴和该第二对称轴相互垂直。
在该实现方式中，混频器中各MOS管对称布置，可以使得各MOS管的寄生电容相容，进而改善该混频器的线性度。
在一个可选的实现方式中，第三引线的一端连接该第一引线的第三位置，另一端连接该第一本振端口；第四引线的一端连接该第二引线的第四位置，另一端连接该第二本振端口；该第三位置和该第四位置沿该第一对称轴对称；该混频器沿该第一对称轴对称。
在该实现方式中，第三引线和第四引线沿第一对称轴对称，可以使得各MOS管的栅极的走线对称。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极直接连接形成该第一引线，该第二MOS管的栅极和该第三MOS管的栅极直接连接形成该第二引线，该第一引线和该第二引线均为直线。
在这种实现方式中，第一MOS管的栅极和第四MOS管的栅极直接连接，第二MOS管的栅极和第三MOS管的栅极直接，可以有效减少引线的长度。
在一个可选的实现方式中，该第三引线的一部分位于该第一对称轴的一侧，该第三引线的另一部分位于该第一对称轴的另一侧；该第四引线的一部分位于该第一对称轴的一侧，该第四引线的另一部分位于该第一对称轴的另一侧；该第三引线经过第五位置，该第四引线经过第六位置，该第五位置和该第六位置为该混频器中不同层的同一位置。
在该实现方式中，各MOS管的栅极走线严格对称，使得各MOS管的栅极的电阻和寄生电容均一致。
在一个可选的实现方式中，该第三引线的第一部分和该第二引线的一部分位于该混频器中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴，该第三引线的第三部分位于该第一对称轴的两侧，该第三引线的第四部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该混频器中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴，该第四引线的第三部分位于该第一对称轴的两侧，该第四引线的第四部分平行于该第一对称轴；该第三引线的第三部分经过该第五位置，该第四引线的第三部分经过该第六位置。
在该实现方式中，第三引线的第一部分和第二引线的一部分位于该混频器中不同层的 同一位置,第四引线的第一部分和第一引线的一部分位于该混频器中不同层的同一位置，可以有效减少引线之间的相互影响。
在一个可选的实现方式中，该第三引线位于该第一对称轴的一侧，该第四引线位于该第一对称轴的另一侧；该第三引线的第一部分和该第二引线的一部分位于该混频器中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该混频器中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴。
在该实现方式中，第三引线和第四引线不经过交叉而是直接连接第一本振端口和第二本振端口，走线简单。
在一个可选的实现方式中，该第三位置和该第一位置为同一位置，该第四位置和该第二位置为同一位置。
在该实现方式中，可以保证各MOS管的栅极走线严格对称。
在一个可选的实现方式中，该第一输入端口和该第二输入端口均连接低噪声放大器，该第一输出端口和该第二输出端口均连接跨阻放大器。
第四方面，本申请实施例提供了另一种混频器，该混频器包括第一金属氧化物半导体MOS管组和第二MOS管组；该第一MOS管组包括第一MOS管、第二MOS管、第三MOS管以及第四MOS管，该第一MOS管的栅极和该第四MOS管的栅极均连接第一本振端口，该第二MOS管的栅极和该第三MOS管的栅极均连接第二本振端口；该第一MOS管的栅极与该第一本振端口之间的引线的长度、该第二MOS管的栅极与该第二本振端口之间的引线的长度、该第三MOS管的栅极与该第二本振端口之间的引线的长度、该第四MOS管的栅极与该第一本振端口之间的引线的长度均相等。
本申请实施例中，混频器中各MOS管的栅极走线的长度相同，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，第一MOS管组和第二MOS管组左右对齐且沿参考对称轴对称。
在该实现方式中，对称放置第一MOS管组和第二MOS管组，可以使得这两个MOS管组的寄生电容一致，改善混频器的线性度。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极之间的第一引线经过第一位置，该第二MOS管的栅极和该第三MOS管的栅极之间的第二引线经过第二位置，该第一位置和该第二位置为该混频器中不同层的同一位置；该第一MOS管的栅极至该第一位置的引线的长度、该第二MOS管的栅极至该第二位置的引线的长度、该第三MOS管的栅极至该第二位置的引线的长度、该第四MOS管的栅极至该第一位置的引线的长度相等。
在该实现方式中，混频器中各MOS管的栅极至混频器中不同层的同一位置的引线长度相等，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一MOS管和该第三MOS管左右对齐且沿第一对称轴对称，该第二MOS管和该第四MOS管左右对齐且沿该第一对称轴对称，该第一MOS管和该第二MOS管前后对齐且沿第二对称轴对称，该第三MOS管和该第四MOS管前后对 齐且沿该第二对称轴对称，该第一对称轴和该第二对称轴相互垂直。
在该实现方式中，混频器中各MOS管对称布置，可以使得各MOS管的寄生电容相容，进而改善该混频器的线性度。
在一个可选的实现方式中，第三引线的一端连接该第一引线的第三位置，另一端连接该第一端口；第四引线的一端连接该第二引线的第四位置，另一端连接该第二端口；该第三位置和该第四位置沿该第一对称轴对称；该混频器沿该第一对称轴对称。
在该实现方式中，第三引线和第四引线沿第一对称轴对称，可以使得各MOS管的栅极的走线对称。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极直接连接形成该第一引线，该第二MOS管的栅极和该第三MOS管的栅极直接连接形成该第二引线，该第一引线和该第二引线均为直线。
在这种实现方式中，第一MOS管的栅极和第四MOS管的栅极直接连接，第二MOS管的栅极和第三MOS管的栅极直接，可以有效减少引线的长度。
在一个可选的实现方式中，该第三引线的一部分位于该第一对称轴的一侧，该第三引线的另一部分位于该第一对称轴的另一侧；该第四引线的一部分位于该第一对称轴的一侧，该第四引线的另一部分位于该第一对称轴的另一侧；该第三引线经过第五位置，该第四引线经过第六位置，该第五位置和该第六位置为该混频器中不同层的同一位置。
在该实现方式中，各MOS管的栅极走线严格对称，使得各MOS管的栅极的电阻和寄生电容均一致。
在一个可选的实现方式中，该第三引线的第一部分和该第二引线的一部分位于该混频器中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴，该第三引线的第三部分位于该第一对称轴的两侧，该第三引线的第四部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该混频器中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴，该第四引线的第三部分位于该第一对称轴的两侧，该第四引线的第四部分平行于该第一对称轴；该第三引线的第三部分经过该第五位置，该第四引线的第三部分经过该第六位置。
在该实现方式中，第三引线的第一部分和第二引线的一部分位于该混频器中不同层的同一位置,第四引线的第一部分和第一引线的一部分位于该混频器中不同层的同一位置，可以有效减少引线之间的相互影响。
在一个可选的实现方式中，该第三引线位于该第一对称轴的一侧，该第四引线位于该第一对称轴的另一侧；该第三引线的第一部分和该第二引线的一部分位于该混频器中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该混频器中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴。
在该实现方式中，第三引线和第四引线不经过交叉而是直接连接第一本振端口和第二本振端口，走线简单。
在一个可选的实现方式中，该第三位置和该第一位置为同一位置，该第四位置和该第二位置为同一位置。
在该实现方式中，可以保证各MOS管的栅极走线严格对称。
在一个可选的实现方式中，该第一MOS管组和该第二MOS管组放置在不同的深N阱上。
在该实现方式中，第一MOS管组和第二MOS管组之间的隔离度较高。
在一个可选的实现方式中，该第一输入端口和该第二输入端口均连接低噪声放大器，该第一输出端口和该第二输出端口均连接跨阻放大器。
第五方面，本申请实施例提供了又一种混频器，该混频器包括第一金属氧化物半导体MOS管组和第二MOS管组，该第一MOS管组和该第二MOS管组放置在不同的深N阱上。
可选的，该第二MOS管组的电路结构和该第一MOS管组的电路结构相同。
本申请实施例中，两个MOS管组放置在不同的深N阱上，可以提高这两个MOS管组之间的隔离度。
在一个可选的实现方式中，该第一MOS管组包括第一MOS管、第二MOS管、第三MOS管以及第四MOS管，该第一MOS管的栅极和该第四MOS管的栅极均连接第一端口，该第二MOS管的栅极和该第三MOS管的栅极均连接第二端口；该第一MOS管的栅极与该第一端口之间的引线的长度、该第二MOS管的栅极与该第二端口之间的引线的长度、该第三MOS管的栅极与该第二端口之间的引线的长度、该第四MOS管的栅极与该第一端口之间的引线的长度均相等。
在该实现方式中，混频器中各MOS管的栅极走线的长度相同，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，第一MOS管组和第二MOS管组左右对齐且沿参考对称轴对称。
在该实现方式中，对称放置第一MOS管组和第二MOS管组，可以使得这两个MOS管组的寄生电容一致，改善混频器的线性度。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极之间的第一引线经过第一位置，该第二MOS管的栅极和该第三MOS管的栅极之间的第二引线经过第二位置，该第一位置和该第二位置为该混频器中不同层的同一位置；该第一MOS管的栅极至该第一位置的引线的长度、该第二MOS管的栅极至该第二位置的引线的长度、该第三MOS管的栅极至该第二位置的引线的长度、该第四MOS管的栅极至该第一位置的引线的长度相等。
在该实现方式中，混频器中各MOS管的栅极至混频器中不同层的同一位置的引线长度相等，使得各MOS管的栅极寄生电容相同，线性度较高。
在一个可选的实现方式中，该第一MOS管和该第三MOS管左右对齐且沿第一对称轴对称，该第二MOS管和该第四MOS管左右对齐且沿该第一对称轴对称，该第一MOS管和该第二MOS管前后对齐且沿第二对称轴对称，该第三MOS管和该第四MOS管前后对齐且沿该第二对称轴对称，该第一对称轴和该第二对称轴相互垂直。
在该实现方式中，混频器中各MOS管对称布置，可以使得各MOS管的寄生电容相容，进而改善该混频器的线性度。
在一个可选的实现方式中，第三引线的一端连接该第一引线的第三位置，另一端连接 该第一端口；第四引线的一端连接该第二引线的第四位置，另一端连接该第二端口；该第三位置和该第四位置沿该第一对称轴对称；该混频器沿该第一对称轴对称。
在该实现方式中，第三引线和第四引线沿第一对称轴对称，可以使得各MOS管的栅极的走线对称。
在一个可选的实现方式中，该第一MOS管的栅极和该第四MOS管的栅极直接连接形成该第一引线，该第二MOS管的栅极和该第三MOS管的栅极直接连接形成该第二引线，该第一引线和该第二引线均为直线。
在这种实现方式中，第一MOS管的栅极和第四MOS管的栅极直接连接，第二MOS管的栅极和第三MOS管的栅极直接，可以有效减少引线的长度。
在一个可选的实现方式中，该第三引线的一部分位于该第一对称轴的一侧，该第三引线的另一部分位于该第一对称轴的另一侧；该第四引线的一部分位于该第一对称轴的一侧，该第四引线的另一部分位于该第一对称轴的另一侧；该第三引线经过第五位置，该第四引线经过第六位置，该第五位置和该第六位置为该混频器中不同层的同一位置。
在该实现方式中，各MOS管的栅极走线严格对称，使得各MOS管的栅极的电阻和寄生电容均一致。
在一个可选的实现方式中，该第三引线的第一部分和该第二引线的一部分位于该混频器中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴，该第三引线的第三部分位于该第一对称轴的两侧，该第三引线的第四部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该混频器中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴，该第四引线的第三部分位于该第一对称轴的两侧，该第四引线的第四部分平行于该第一对称轴；该第三引线的第三部分经过该第五位置，该第四引线的第三部分经过该第六位置。
在该实现方式中，第三引线的第一部分和第二引线的一部分位于该混频器中不同层的同一位置,第四引线的第一部分和第一引线的一部分位于该混频器中不同层的同一位置，可以有效减少引线之间的相互影响。
在一个可选的实现方式中，该第三引线位于该第一对称轴的一侧，该第四引线位于该第一对称轴的另一侧；该第三引线的第一部分和该第二引线的一部分位于该混频器中不同层的同一位置，该第三引线的第二部分平行于该第一对称轴；该第四引线的第一部分和该第一引线的一部分位于该混频器中不同层的同一位置，该第四引线的第二部分平行于该第一对称轴。
在该实现方式中，第三引线和第四引线不经过交叉而是直接连接第一端口和第二端口，走线简单。
在一个可选的实现方式中，该第三位置和该第一位置为同一位置，该第四位置和该第二位置为同一位置。
在该实现方式中，可以保证各MOS管的栅极走线严格对称。
在一个可选的实现方式中，该第一输入端口和该第二输入端口均连接低噪声放大器，该第一输出端口和该第二输出端口均连接跨阻放大器。
第六方面，本申请实施例提供了一种电子设备，该电子设备包括上述第三方面至上述 第五方面以及任一项可选的实现方式中的混频器。
该电子设备可以是终端(例如手机、基站等)中的接收机，收发机，或射频芯片，也可以是终端，还可以是其他设备。
附图说明
图1为一种接收机中混频器的前后级的结构示意图；
图2为一种混频器的电路原理图；
图3为一种传统的混频器的版图结构；
图4为一种混频器中一组开关电路的版图结构；
图5为一种开关电路的电路原理图；
图6为本申请实施例提供的一种混频器的版图结构；
图7为本申请实施例提供一种开关电路的版图结构；
图8为本申请实施例提供的另一种开关电路的版图结构；
图9A为一种传统的混频器的版图结构；
图9B为本申请实施例提供的一种混频器的版图结构。
具体实施方式
为了使本技术领域的人员更好地理解本申请实施例方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。
本申请的说明书实施例和权利要求书及上述附图中的术语“第一”、“第二”、和“第三”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
在电子通讯系统中，混频器(即Mixer)是收发机中负责频谱搬移功能的核心电路，在微波无线通信系统、雷达系统和测量系统中有着广泛的应用。接收机基本上包括放大器、滤波器、混频器等部件，用于将模拟输入信号放大、滤波并进行若干次频率搬移或变换，再通过模/数转换器(Analog-to-Digital Converter，ADC)采样，将数字信号发送至计算机或数字信号处理器作进一步处理。混频器在接收机中处于射频信号幅度较高的位置且许多干扰信号未得到有效抑制。因此，线性度是混频器的一个非常重要(甚至是最重要的)的指标。图1为一种接收机中混频器的前后级的结构示意图。如图1所示，101为低噪声放大器，102为混频器，103为跨阻放大器；混频器102处在低噪声放大器101的后级，跨阻放大器103处于混频器102的后级；低噪声放大器101将接收到的微弱信号经过低噪声放大处理，向混频器102的两个输入端输入正交的射频信号；混频器102将其输入端的射频信号和本振信号进行混频(即频率搬移)以得到中频信号；跨阻放大器103将接收到的中频信号转换为电压信号。图1仅是本申请提供的一种示例，混频器可以应用在多种电路中， 本申请不对混频器的前后级作限定。
图2为一种混频器的电路原理图。如图2所示，左边的虚线框中为第一开关电路，右边的虚线框中为第二开关电路；该第一开关电路由M1～M4构成，M1～M4均为金属氧化物半导体(Metal Oxide Semiconductor，MOS)管，M1的栅极和M4的栅极均连接输入端口LOP1，M2的栅极和M3的栅极均连接输入端口LON1，M1的源极和M2的源极均连接输入端口RFIP，M3的源极和M4的源极均连接输入端口RFIN，该第一开关电路的输出端口为IFIP和IFIN；该第二开关电路由M5～M8构成，M5～M8均为MOS管，M5的栅极和M8的栅极均连接输入端口LOP2，M6的栅极和M7的栅极均连接输入端口LON2，M5的源极和M6的源极均连接输入端口RFIP，M7的源极和M8的源极均连接输入端口RFIN，该第二开关电路的输出端口为IFQP和IFQN；该第一开关电路和该第二开关电路并联且均由正交本振信号驱动，输出I、Q两路中频信号，构成正交Gilbert混频器；其中，输入端口LOP1输入的信号和输入端口LON1输入的信号为正交的信号，输入端口LOP2输入的信号和输入端口LON2输入的信号为正交的信号。图2仅是本申请提供的一种混频器的电路原理图的示例，不同类型的混频器的电路原理图不同，本申请不对混频器的电路原理图作限定。从图2可以看出，混频器中包括两组结构相同的开关电路，M1的栅极和M4的栅极均接入输入端口LOP1，M2的栅极和M3的栅极均接入输入端口LON1，M5的栅极和M8的栅极均接入输入端口LOP2，M6的栅极和M7的栅极均接入输入端口LON2，两组开关电路均由正交的正交本振信号驱动，一组输出I路中频信号，另一组输出Q路中频信号。
混频器的版图结构中包括两组对称布置的开关电路，每组开关电路中四个MOS管的栅极各自连接一条引线；其中，两条栅极引线连接LO的一个输出端口，另外两条栅极引线连接LO的另一个输出端口。图3为一种传统的混频器的版图结构。如图3所示，M1～M8依次对应图2中的M1～M8，图3中左半边的版图结构对应图2中左边虚线框中的开关电路，图3中右半边的版图结构对应图2中右边虚线中的开关电路；M1的栅极和M4的栅极均连接LO的输入端口LOP1，M2的栅极和M3的栅极均连接LO的输出端口LON1，M5的栅极和M8的栅极均连接LO的输出端口LOP2，M6的栅极和M7的栅极均连接LO的输出端口LON2；M1的漏级和M3的漏级均连接输出端口IFIP，M2的漏级和M4的漏级均连接输出端口IFIN，M5的漏级和M7的漏级均连接输出端口IFQP，M6的漏级和M8的漏级均连接输出端口IFQN；M1的源极和M2的源极均连接输入端口RFIP，M3的源极和M4的源极均连接输入端口RFIN；M5的源极和M6的源极均连接输入端口RFIP，M7的源极和M8的源极均连接输入端口RFIN。如图3所示，由于两组开关电路的版图结构是对称布置的，为更方便的描述混频器的版图结构中每组开关电路的版图结构，下面仅描述一组开关电路的版图结构。图4为混频器中一组开关电路的版图结构。如图4所示，M1～M4依次对应图2中的M1～M4，M1的栅极和M4的栅极均连接LO的输入端口LOP1，M2的栅极和M3的栅极均连接LO的输出端口LON1，M1的漏级和M3的漏级均连接输出端口IFIP，M2的漏级和M4的漏级均连接输出端口IFIN，M1的源极和M2的源极连接同一个输入端口RFIP，M3的源极和M4的源极连接另一个输入端口RFIN。图5为图4中的版图结构对应的电路原理图。图5中的M1～M4依次对应图4中的M1～M4，M1的栅极和M4的栅极均连接输入端口LOP1，M2的栅极和M3的栅极均连接输入端口LON1，M1 的源极和M2的源极均连接输入端口RFIP，M3的源极和M4的源极均连接输入端口RFIN，该第一开关电路的输出端口为IFIP和IFIN。从图4可以看出，采用这种版图结构，四个MOS管的栅极走线长度不一致，这就使得四个MOS管的栅极的寄生并不一致，这样直接破坏了MOS管的走线对称性，影响混频器的线性度。因此，需要解决传统的混频器的版图结构中MOS管的走线不对称的问题，以使得四个MOS管的栅极的寄生一致，从而改善混频器的线性度。
下面介绍本申请实施例提供的一种混频器的版图结构，在该版图结构中MOS管的栅极的寄生一致。本申请提供的混频器的版图结构对应的电路原理图为包括两组开关电路的混频器电路，图1为该版图结构对应的一种电路原理图的示例。图6为本申请提供的一种混频器的版图结构。如图6所示，M1～M8依次对应图2中的M1～M8，图6中左半边的版图结构对应图2中左边虚线框中的第一开关电路(对应第一MOS管组)，图6中右半边的版图结构对应图2中右边虚线中的第二开关电路(对应第二MOS管组)；M1的栅极和M4的栅极直接通过第一引线(图中的601)连接且该第一引线连接第三引线(图中的603)的一端，该第三引线的另一端连接LO的输出端口LOP1，M2的栅极和M3的栅极直接通过第二引线(图中的602)连接且该第二引线连接第四引线(图中的604)的一端，该第四引线的另一端连接LO的输出端口LON1；M5的栅极和M8的栅极直接通过引线连接且该引线通过另一条引线连接LO的输出端口LOP2，M6的栅极和M7的栅极直接通过引线连接且该引线通过另一条引线连接LO的输出端口LON2；M1的漏级和M3的漏级均连接输出端口IFIP，M2的漏级和M4的漏级均连接输出端口IFIN，M5的漏级和M7的漏级均连接输出端口IFQP，M6的漏级和M8的漏级均连接输出端口IFQN。可选的，第一引线和第三引线位于同一层，第二引线和第四引线位于同一层。可以理解，图6中的左半图对应于第一开关电路(对应于第一MOS管组)的第一版图区，图6中的右半图对应于第二开关电路(对应于第二MOS管组)的第二版图区，该第一版图区和该第二版图区左右对齐且沿参考对称轴对称。对比图6和图3可以看出，本申请实施例提供的混频器的版图结构与传统的混频器的版图结构相比，主要区别在于，每组开关电路中四个MOS管的栅极走线长度一致，这就使得MOS管的栅极的寄生相同。图6的混频器的版图结构中，M1的栅极和M4的栅极之间的第一引线与M2的栅极和M3的栅极之间的第二引线位于该版图结构的不同层。也就是说，第一引线和第二引线不会相交。本申请实施例提供的混频器的版图结构中，两组开关管的版图结构是对称的，为更方便的描述混频器的版图结构中每组开关电路的版图结构，下面具体描述一组开关电路的版图结构。
图7为本申请实施例提供的一种开关电路的版图结构，该版图结构对应的电路图如图5所示。图7中的开关电路的版图结构为第一MOS管组的版图结构的一种举例。如图7所示，开关电路的版图结构包括第一MOS管(即图7中的M1)、第二MOS管(即图7中的M2)、第三MOS管(即图7中的M3)以及第四MOS管(即图7中的M4)，M1的栅极和M4的栅极直接通过第一引线(图中的701)连接且该第一引线连接第三引线(图中的703)的一端，该第三引线的另一端LO的输入端口LOP1(对应第一端口)；M2的栅极和M3的栅极直接通过第二引线(图中的702)连接且该第二引线连接第四引线(图中的704)的一端，该第四引线的另一端连接LO的输出端口LON1(对应第二端口)；M1和M3左右对齐 且沿第一对称轴对称，M2和M4左右对齐且沿该第一对称轴对称，M1和M2前后对齐且沿第二对称轴对称，M3和M4前后对齐且沿该第二对称轴对称，该第一对称轴和该第二对称轴相互垂直；M1的栅极和M4的栅极之间的第一引线(图中的701)经过第一位置，M2的栅极和M3的栅极之间的第二引线(图中的702)经过第二位置，该第一位置和该第二位置为该版图结构中不同层的同一位置；M1的栅极至该第一位置的引线的长度、M2的栅极至该第二位置的引线的长度、M3的栅极至该第二位置的引线的长度、M4的栅极至该第一位置的引线的长度相等；第三引线(图中的703)的一端连接该第一引线的第三位置，另一端连接第一端口(即图中的输入端口LOP1)；第四引线(即图中的704)的一端连接该第二引线的第四位置，另一端连接第二端口(即图中的输入端口LON1)；该第三位置和该第四位置沿该第一对称轴对称；该版图结构沿该第一对称轴对称；该第一引线和该第二引线位于版图结构的不同层，该第三引线和该第四引线位于该版图结构的不同层。可选的，上述第一位置为上述第一引线的中点，上述第二位置为上述第二引线的中点，该第一位置、该第二位置以及该第一对称轴和该第二对称轴的交点位于该版图结构中不同层的同一位置。可选的，上述第三位置为上述第一引线的中点，上述第四位置为上述第二引线的中点，该第三位置、该第四位置以及该第一对称轴和该第二对称轴的交点位于该版图结构中不同层的同一位置。可选的，上述第三位置和上述第四位置不是该版图结构中不同层的同一位置。可选的，上述第三位置和上述第一位置为同一位置，上述第四位置和上述第二位置为同一位置。从图7可以看出，M1～M4的栅极走线的长度相同，而且第三引线和第四引线沿第一对称轴对称，这样M1～M4的栅极寄生电容相同，开关电路的线性度较高。
在一个可选的实现方式中，如图7所示，M1的栅极和M4的栅极直接连接形成上述第一引线，M2的栅极和M3的栅极直接连接形成上述第二引线，该第一引线和该第二引线均为直线。在这种实现方式中，M1的栅极和M4的栅极直接连接，以及M2的栅极和M3的栅极直接连接，可以有效减少引线的长度，成本较低。
在一个可选的实现方式中，如图7所示，上述第三引线(图中的703)的一部分位于第一对称轴的一侧，上述第三引线的另一部分位于该第一对称轴的另一侧；上述第四引线(图中的704)的一部分位于该第一对称轴的一侧，上述第四引线的另一部分位于该第一对称轴的另一侧；上述第三引线经过第五位置，上述第四引线经过第六位置，上述第五位置和上述第六位置为上述版图结构中不同层的同一位置。在该实现方式中，M1～M4的栅极走线经过两次交叉引线到LO端口(即图中的输入端口LOP1和LON1)，使得M1～M4的栅端走线严格对称，可以进一步改善开关电路的线性度。
在一个可选的实现方式中，如图7所示，上述第三引线的第一部分(图中的7031)和上述第二引线(图中的702)的一部分位于上述版图结构中不同层的同一位置，上述第三引线的第二部分(图中的7032)平行于第一对称轴，上述第三引线的第三部分(图中的7033)位于该第一对称轴的两侧，上述第三引线的第四部分(图中的7034)平行于该第一对称轴；上述第四引线的第一部分(与7031关于第一对称轴对称)和上述第一引线的一部分位于上述版图结构中不同层的同一位置，上述第四引线的第二部分(与7032关于第一对称轴对称)平行于该第一对称轴，上述第四引线的第三部分(与7033关于第一对称轴对称)位于该第一对称轴的两侧，上述第四引线的第四部分(与7034关于第一对称轴对称)平行于上述第 一对称轴；上述第三引线的第三部分经过上述第五位置，上述第四引线的第三部分经过上述第六位置。可选的，第三引线和第一引线处于版图结构的同一层，第二引线和第四引线处于版图结构的同一层。在该实现方式中，第三引线的第一部分和第二引线的一部分位于上述版图结构中不同层的同一位置，第四引线的第一部分和第一引线的一部分位于该版图结构中不同层的同一位置，可以有效减少引线之间的相互影响。
图7的版图结构中，M1～M4的栅极走线经过两次交叉引线到LO端口(即图中的输入端口LOP1和LON1)。混频器的版图结构中M1～M4的栅极走线可以经过至少一次交叉引线到LO端口。可选的，混频器的版图结构中M1～M4的栅极走线可以经过偶数次交叉引线到LO端口，这样的版图结构线性度性能更好。在开关电路的版图结构中，M1～M4的栅极走线可以经过一次交叉引线到LO端口。图8为本申请实施例提供的另一种开关电路的版图结构，该版图结构对应的电路图如图5所示。图8中，801为第一引线，802为第二引线，8031为第三引线的第一部分，8032为该第一引线的第二部分，804为第四引线。如图8所示，第三引线的第一部分(8031)与该第二引线的一部分处于版图结构的不同层的同一位置，该第三引线的第二部分(8032)平行于第一对称轴；第四引线的第一部分(与8031沿第一对称轴对称)与该第一引线的一部分处于版图结构的不同层的同一位置，该第四引线的第二部分(与8032沿第一对称轴对称)平行于第一对称轴。可选的，第三引线和第一引线处于版图结构的同一层，第二引线和第四引线处于版图结构的同一层。可选的，第三引线的一端连接第一引线的中点，第四引线的一端连接第二引线的中点。对比图7和图8可以看出，图8中的版图结构与图7中的版图结构的区别在于，M1～M4的栅极走线可以经过一次交叉引线到LO端口。在该实现方式中，第三引线和第四引线不经过交叉而是直接连接LO端口，走线简单。
在一个可选的实现方式中，混频器的版图结构中，第一开关电路和第二开关电路放置在不同的深N阱(也称deep n-wel，简写为DNW)上。在传统的混频器的版图结构中，两组开关电路放置在同一深N阱上，一组开关电路对应I路，另一组开关电路对应Q路，I Q两路的隔离度较差。图9A为一种传统的混频器的版图结构。如图9A所示，第一开关电路和第二开关电路放置在同一个深N阱上，使得IQ两路的隔离度较差。图9B为本申请实施例提供的一种混频器的版图结构。如图9B所示，第一开关电路放置在DNW1上，第二开关电路放置在DNW2上。也就是说，第一开关电路和第二开关电路放置在不同的深N阱上，以便于增强IQ两路的隔离度。参阅图9B，图9B中的第一开关电路和第二开关电路设置在不同的深N阱上，该第一开关电路对应I路，该第二开关电路对应Q路，这样可以增强I Q两路的隔离度。
本申请提供的开关电路的版图结构是一种线性度性能较优的版图结构，不限于应用到混频器的版图结构中，还可以应用到其他电路中。本申请中，相等不限定于完全相等，而是允许存在一定的偏差。本申请的方案的一个目的是使得各MOS的栅极的走线的长度尽可能的相等，并不限定各MOS的栅极的走线的长度必须完全一致。以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (15)

  1. 一种开关电路，其特征在于，所述开关电路包括第一金属氧化物半导体MOS管、第二MOS管、第三MOS管以及第四MOS管，所述第一MOS管的栅极和所述第四MOS管的栅极均连接第一端口，所述第二MOS管的栅极和所述第三MOS管的栅极均连接第二端口；
    所述第一MOS管的栅极与所述第一端口之间的引线的长度、所述第二MOS管的栅极与所述第二端口之间的引线的长度、所述第三MOS管的栅极与所述第二端口之间的引线的长度、所述第四MOS管的栅极与所述第一端口之间的引线的长度均相等。
  2. 根据权利要求1所述的开关电路，其特征在于，
    所述第一MOS管的栅极和所述第四MOS管的栅极之间的第一引线经过第一位置，所述第二MOS管的栅极和所述第三MOS管的栅极之间的第二引线经过第二位置，所述第一位置和所述第二位置为所述开关电路中不同层的同一位置；所述第一MOS管的栅极至所述第一位置的引线的长度、所述第二MOS管的栅极至所述第二位置的引线的长度、所述第三MOS管的栅极至所述第二位置的引线的长度、所述第四MOS管的栅极至所述第一位置的引线的长度相等。
  3. 根据权利要求2所述的开关电路，其特征在于，
    所述第一MOS管和所述第三MOS管左右对齐且沿第一对称轴对称，所述第二MOS管和所述第四MOS管左右对齐且沿所述第一对称轴对称，所述第一MOS管和所述第二MOS管前后对齐且沿第二对称轴对称，所述第三MOS管和所述第四MOS管前后对齐且沿所述第二对称轴对称，所述第一对称轴和所述第二对称轴相互垂直。
  4. 根据权利要求3所述的开关电路，其特征在于，
    第三引线的一端连接所述第一引线的第三位置，另一端连接所述第一端口；第四引线的一端连接所述第二引线的第四位置，另一端连接所述第二端口；所述第三位置和所述第四位置沿所述第一对称轴对称；所述开关电路沿所述第一对称轴对称。
  5. 根据权利要求1至4任一项所述的开关电路，其特征在于，所述第一MOS管的栅极和所述第四MOS管的栅极直接连接形成所述第一引线，所述第二MOS管的栅极和所述第三MOS管的栅极直接连接形成所述第二引线，所述第一引线和所述第二引线均为直线。
  6. 根据权利要求4所述的开关电路，其特征在于，所述第三引线的一部分位于所述第一对称轴的一侧，所述第三引线的另一部分位于所述第一对称轴的另一侧；所述第四引线的一部分位于所述第一对称轴的一侧，所述第四引线的另一部分位于所述第一对称轴的另一侧；所述第三引线经过第五位置，所述第四引线经过第六位置，所述第五位置和所述第六位置为所述开关电路中不同层的同一位置。
  7. 根据权利要求6所述的开关电路，其特征在于，所述第三引线的第一部分和所述第二引线的一部分位于所述开关电路中不同层的同一位置，所述第三引线的第二部分平行于所述第一对称轴，所述第三引线的第三部分位于所述第一对称轴的两侧，所述第三引线的第四部分平行于所述第一对称轴；所述第四引线的第一部分和所述第一引线的一部分位于所述开关电路中不同层的同一位置，所述第四引线的第二部分平行于所述第一对称轴，所述第四引线的第三部分位于所述第一对称轴的两侧，所述第四引线的第四部分平行于所述第一对称轴；所述第三引线的第三部分经过所述第五位置，所述第四引线的第三部分经过所述第六位置。
  8. 根据权利要求5所述的开关电路，其特征在于，所述第三引线位于所述第一对称轴的一侧，所述第四引线位于所述第一对称轴的另一侧；所述第三引线的第一部分和所述第二引线的一部分位于所述开关电路中不同层的同一位置，所述第三引线的第二部分平行于所述第一对称轴；所述第四引线的第一部分和所述第一引线的一部分位于所述开关电路中不同层的同一位置，所述第四引线的第二部分平行于所述第一对称轴。
  9. 根据权利要求4或6或7或8任一项所述的开关电路，其特征在于，所述第三位置和所述第一位置为同一位置，所述第四位置和所述第二位置为同一位置。
  10. 一种混频器，其特征在于，包括权利要求1至9任一项所述的开关电路。
  11. 根据权利要求10所述的混频器，其特征在于，所述第一端口和所述第二端口均为接收驱动电压的本振端口；所述第一MOS管的源极和所述第二MOS管的源极均连接第一输入端口，所述第三MOS管的源极和所述第四MOS管的源极均连接第二输入端口；所述第一MOS管的漏极和所述第三MOS管的漏极均连接第一输出端口，所述第二MOS管的漏极和所述第四MOS管的漏极均连接第二输出端口。
  12. 根据权利要求11所述的混频器，其特征在于，所述第一输入端口和所述第二输入端口均连接低噪声放大器，所述第一输出端口和所述第二输出端口均连接跨阻放大器。
  13. 一种混频器，其特征在于，其特征在于，所述混频器包括第一MOS管组和第二MOS管组，所述第二MOS管组的电路结构和所述第一MOS管组的电路结构相同；所述第一MOS管组和所述第二MOS管组左右对齐且沿参考对称轴对称；所述第一MOS管组包括第一MOS管、第二MOS管、第三MOS管以及第四MOS管，所述第一MOS管的栅极和所述第四MOS管的栅极均连接第一本振端口，所述第二MOS管的栅极和所述第三MOS管的栅极均连接第二本振端口；
    所述第一MOS管的栅极与所述第一本振端口之间的引线的长度、所述第二MOS管的栅极与所述第二本振端口之间的引线的长度、所述第三MOS管的栅极与所述第二本振端口之间的引线的长度、所述第四MOS管的栅极与所述第一本振端口之间的引线的长度均相等。
  14. 根据权利要求13所述的版图结构，其特征在于，所述第一MOS管组和所述第二MOS管组放置在不同的深N阱上。
  15. 一种电子设备，其特征在于，包括权利要求10至14任一项所述的混频器。
PCT/CN2019/085335 2019-04-30 2019-04-30 开关电路、混频器及电子设备 WO2020220326A1 (zh)

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