WO2020220179A1 - Circuit et procédé de transformée inverse en ondelettes - Google Patents

Circuit et procédé de transformée inverse en ondelettes Download PDF

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WO2020220179A1
WO2020220179A1 PCT/CN2019/084919 CN2019084919W WO2020220179A1 WO 2020220179 A1 WO2020220179 A1 WO 2020220179A1 CN 2019084919 W CN2019084919 W CN 2019084919W WO 2020220179 A1 WO2020220179 A1 WO 2020220179A1
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row
line
wavelet
data
code block
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PCT/CN2019/084919
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English (en)
Chinese (zh)
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张健华
王志伟
赵文军
韩彬
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2019/084919 priority Critical patent/WO2020220179A1/fr
Priority to CN201980007856.2A priority patent/CN111567042B/zh
Publication of WO2020220179A1 publication Critical patent/WO2020220179A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
    • H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/184—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/63—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using sub-band based transform, e.g. wavelets

Definitions

  • This application relates to the field of image decoding, and more specifically, to a wavelet inverse transform circuit and method.
  • JPEG 2000 Joint Photographic Experts Group 2000 is a commonly used image coding standard.
  • JPEG 2000 uses wavelet transform and performs entropy coding based on optimized interception of embedded block coding (embedded block coding with optimized truncation, EBCOT), which has a higher compression ratio than JPEG, and supports progressive download and display.
  • EBCOT embedded block coding with optimized truncation
  • the wavelet inverse transform circuit of the traditional JPEG 2000 decoder decodes code blocks of wavelet transform coding at the same level in the order of row order first and column order second.
  • the calculation efficiency of the wavelet inverse transform process is low.
  • This application provides a wavelet inverse transform circuit and method, which can improve the calculation efficiency of the wavelet inverse transform process.
  • a wavelet inverse transform circuit which includes: a first interface circuit for obtaining decoded code block data; an inverse transform circuit for obtaining data according to the first row, the N+1th row, and the second row , Line N+2, ..., line N, line 2N, perform inverse wavelet transform on the j-th level wavelet transform data of the code block data line by line to obtain the j-th level of the code block data
  • N and j are both positive integers greater than 1, and the frequency component corresponding to the data in the N+1 row is different from the frequency component corresponding to the data in the first row.
  • a wavelet inverse transform method including: obtaining decoded code block data; according to the first row, the N+1th row, the second row, the N+2th row,..., the Nth row, In the order of the 2Nth line, perform inverse wavelet transform on the j-th level wavelet transform data of the code block data line by line to obtain the j-th level wavelet inverse transform result of the code block data, and both N and j are greater than 1.
  • N and j are greater than 1.
  • a decoder in a third aspect, includes the wavelet inverse transform circuit described in the first aspect.
  • a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium, which when run on a computer, cause the computer to execute the method described in the second aspect.
  • a computer program product containing instructions which when run on a computer, causes the computer to execute the method described in the second aspect.
  • the wavelet inverse transform circuit and method of the embodiment of the present application executes wavelet line by line in the order of line 1, line N+1, line 2, line N+2, ..., line N, line 2N Inverse transform, that is, adjust the processing sequence of wavelet inverse transform, so that wavelet train inverse transform and wavelet row inverse transform can be performed in parallel, which can improve the calculation efficiency of wavelet inverse transform process.
  • Fig. 1 is a schematic structural diagram of a decoder provided by an embodiment of the present application.
  • Figure 2 is a schematic structural diagram of another decoder provided by an embodiment of the present application.
  • Fig. 3 is a schematic diagram of the principle of wavelet transform of image blocks.
  • Fig. 4 is a schematic structural diagram of a wavelet inverse transform circuit of an embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of another wavelet inverse transform circuit according to an embodiment of the present application.
  • Fig. 6 is a schematic diagram of a decoding mode according to an embodiment of the present application.
  • Fig. 7 is a schematic diagram of another decoding mode according to an embodiment of the present application.
  • Fig. 8 is a schematic diagram of another decoding mode according to an embodiment of the present application.
  • Fig. 9 is a schematic diagram of another decoding mode according to an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a wavelet inverse transform method provided by an embodiment of the present application.
  • This application can be applied to the field of image coding and decoding, video coding and decoding, hardware video coding and decoding, dedicated circuit video coding and decoding, and real-time video coding and decoding.
  • the decoder provided in this application can be used to decode image lossy compression (lossy compression) and can also be used to decode image lossless compression (lossless compression).
  • the lossless compression can be a visually lossless compression (visually lossless compression) or a mathematically lossless compression (mathematically lossless compression).
  • the decoder 1 may include one or more of the following circuits: code stream reading circuit 11, code stream analysis circuit 12, decoding circuit 13, inverse quantization circuit 14, inverse transform circuit 15, output circuit 16.
  • the code stream reading circuit 11 can be used to read the code stream to be decoded.
  • the code stream reading circuit 11 can, for example, use an advanced extensible interface (AXI) to read the code stream to be decoded from an external memory (such as a memory).
  • AXI advanced extensible interface
  • the code stream parsing circuit 12 may also be referred to as a code stream header parser circuit (header parser).
  • the code stream analysis circuit 12 can parse various types of header information in the code stream, and separate parameters and code stream data related to decoding therefrom for use by the subsequent decoding circuit 13.
  • the decoding circuit 13 may include one decoding unit or parallel multiple decoding units (the specific number can be configured according to actual needs, for example, one parallel decoding unit can be configured). Each decoding unit in the decoding circuit 13 can independently perform entropy decoding on a code block.
  • a preprocessing circuit may be provided before the decoding circuit 13.
  • the preprocessing circuit can be used to distribute the decoding parameters, code stream data, etc. output by the code stream analysis circuit 12 to parallel multiple decoding units.
  • a post-processing circuit may also be provided.
  • the post-processing circuit can be used to reorganize the entropy decoded data output by the decoding circuit 13 and output the organized data to the subsequent circuit.
  • the inverse quantization circuit 14 can be used to inversely quantize the data obtained by entropy decoding by the decoding circuit 13.
  • the wavelet inverse transform circuit 15 can be used to perform wavelet inverse transform on the data output by the inverse quantization circuit 14.
  • the output circuit 16 can be used to write the data output by the wavelet inverse transform circuit 15 into an external memory.
  • the data output by the wavelet inverse transform circuit 15 can be written into an external memory through AXI.
  • the decoder 1 may also include a software configuration interface. Through the software configuration interface, the information in the internal registers of the decoder 1 can be configured or changed, so as to control the decoding mode of the decoder 1.
  • decoding the operations performed by the decoder 1 are collectively referred to as “decoding”, and the operations performed by the decoding circuit 13 are referred to as “entropy decoding”. If not explicitly indicated, “decoding” refers to the operations performed by the decoder 1. It will not be repeated in the embodiment.
  • Fig. 2 shows a schematic structural diagram of another decoder 2 provided by an embodiment of the present application.
  • the decoder 2 shown in FIG. 2 includes the following modules: a Din module 21, a header parser module 22, a pre-organizer module 23, a parallel decoding circuit 24, and a post-organizer module 25, IQUANT module 26, IDWT module 27, Dout module 28, Reg interface 29.
  • the Din module 21 is used to read a code stream from an external memory through AXI, and corresponds to the code stream reading circuit 11 in FIG. 1.
  • the header parser module 22 is used to parse the code stream, and corresponds to the code stream parsing circuit 12 in FIG. 1.
  • the pre-organizer module 23 is used to allocate the decoding parameters and code stream data output by the header parser module 22 to the parallel decoding circuit 24.
  • the pre-organizer module 23 may also be called a pre-processing circuit.
  • the parallel decoding circuit 24 includes 8 decoding units, including decoding unit 0, decoding unit 1,..., decoding unit 7, for example, DEC unit 0, DEC unit 1,..., DEC unit 7, and each decoding unit can be independently Entropy decoding the data of a code block.
  • the parallel decoding circuit 24 corresponds to the decoding circuit 13 in FIG. 1.
  • the Post-organizer module 25 is used to reorganize the entropy decoded data of the parallel decoding circuit 24 and output the organized data to the subsequent circuit.
  • the post-organizer module 25 may also be referred to as a post-processing circuit.
  • the IQUANT module 26 is used to inversely quantize the data from the Post-organizer module 25, corresponding to the inverse quantization circuit 14 in FIG. 1.
  • the IDWT module 27 is used to perform inverse wavelet transform on the inversely quantized data, corresponding to the inverse wavelet transform circuit 15 in FIG. 1.
  • the Dout module 28 is used to write the image recovered after the wavelet inverse transformation into the external memory, corresponding to the output circuit 16 in FIG. 1.
  • Reg interface 29 is the software configuration interface of decoder 2, which can be configured through the peripheral bus (advanced peripheral bus, APB) (or advanced high performance bus (AHB), or AXI) to configure the relevant control registers of decoder 2 to control Decoding behavior of decoder 2.
  • APB advanced peripheral bus
  • AXI advanced high performance bus
  • the decoder 2 only shows the deployment of 8 decoding units, and working at a frequency of 700Mhz can achieve 8192 ⁇ 4320 12bit 15fps RAW image decoding. If you want to support higher specifications, such as 30fps, etc., you only need to increase the number of decoding units in the parallel decoding circuit 24, and the pre- and post-processing modules can be slightly adjusted, which will not be repeated here.
  • the decoder 1 and the decoder 2 provided in the embodiment of the present application may perform decoding in units of tiles (tile). Take decoder 1 as an example. After decoder 1 reads the code stream from an external memory, the entire decoding process can be performed on-chip (because the embodiment of this application uses image blocks as the unit for decoding, the intermediate data is not too large and can be passed The on-chip cache is used for temporary storage) and does not interact with external memory to save system bandwidth. In addition, all levels of circuits in the decoder 1 can work in a pipeline manner to improve decoding efficiency. Decoder 2 is similar and will not be repeated.
  • the decoder 1 and the decoder 2 in the embodiments of the present application are based on the JPEG2000 standard, implement hardware decoding for various images (such as RAW domain images), can support resolution downsampling decoding, and support layered decoding.
  • JPEG 2000 uses wavelet transform and performs entropy coding based on optimized interception of embedded block coding (embedded block coding with optimized truncation, EBCOT), which has a higher compression ratio than JPEG, and supports progressive download and display.
  • the wavelet inverse transform circuit of the traditional JPEG 2000 decoder (such as the above decoder 1, decoder 2) decodes the wavelet transform coding code blocks of the same level in the order of row order first and column order second, and the wavelet inverse transform process The calculation efficiency is low.
  • the embodiment of the present application provides a new wavelet inverse transform circuit, which can improve the calculation efficiency of the wavelet inverse transform process.
  • Wavelet transform is generally performed by a wavelet transform circuit, which corresponds to the wavelet inverse transform circuit deployed in the decoder 1 and/or decoder 2, and the wavelet transform circuit is deployed in the encoder.
  • Fig. 3 is a schematic diagram of the principle of wavelet transform of image blocks. Assuming that the size of the image block shown in FIG. 3 is 256 ⁇ 256, the wavelet transform circuit usually divides the image block into several blocks for transformation, and each transformation will produce 4 intermediate results, namely 4 code blocks. Among them, for the last transformation, the generated 4 code blocks will be output at the same time. In other cases, 3 code blocks will be output (that is, the code blocks corresponding to the frequency components of HL, LH, and HH).
  • the image block shown in FIG. 3 is the result of performing three wavelet transforms.
  • the result of the first-level wavelet transform is the code blocks corresponding to 1LL, 1HL, 1LH, and 1HH (size Respectively 128 ⁇ 128).
  • the second-level wavelet transform is continued on the 1LL code block in the upper left corner, and the result is the code block corresponding to 2LL, 2HL, 2LH, and 2HH (the size is 64 ⁇ 64 respectively).
  • the third-level wavelet transform is the code block corresponding to 3LL, 3HL, 3LH, and 3HH (32 ⁇ 32 in size respectively).
  • wavelet transform is divided into wavelet row transform and wavelet row transform.
  • the wavelet transform circuit can perform wavelet row transform first, then wavelet row transform, or wavelet row transform first, then wavelet row transform.
  • inverse wavelet transform is divided into inverse wavelet row transform and inverse wavelet column transform. If the wavelet transform circuit first performs wavelet row transform on the image block, and then performs wavelet column transform, the wavelet inverse transform circuit needs to perform wavelet column first Inverse transformation, and then wavelet row inverse transformation; if the wavelet transform circuit performs wavelet column transformation on the image block first, and then wavelet row transformation, the wavelet inverse transform circuit needs to perform wavelet row inverse transformation first, and then wavelet column inverse transformation .
  • Fig. 4 shows a schematic structural diagram of a wavelet inverse transform circuit of an embodiment of the present application.
  • the wavelet inverse transform circuit 15 shown in FIG. 4 includes: a first interface circuit 31 and an inverse transform circuit 32.
  • the first interface circuit 31 is used to obtain the decoded code block data
  • the inverse transform circuit 32 is used to obtain the data according to the first row, the N+1th row, the second row, the N+2th row,..., the Nth row, In the order of the 2Nth line, perform inverse wavelet transform on the j-th level wavelet transform data of the code block data line by line to obtain the j-th level wavelet inverse transform result of the code block data, and both N and j are greater than 1.
  • the frequency component corresponding to the data in the N+1 row is different from the frequency component corresponding to the data in the first row.
  • the above-mentioned inverse wavelet transform operation is performed alternately for line data of at least two different frequency components. Due to coding, the wavelet transform operation will obtain 4 frequency components (LL, HL, LH and HH respectively) through de-interleaving.
  • the process of alternately performing wavelet inverse transform is equivalent to a data re-interleaving process. Therefore, in this application
  • the interleaving and the wavelet inverse transform can be performed at the same time. Compared with the separate and independent operations of the interleaving and the wavelet inverse transform, it saves more hardware resources such as memory, which is beneficial to improve calculation efficiency.
  • the above-mentioned j-th level wavelet transform may be the third level wavelet transform data (for example, 3LL, 3HL, 3LH and 3HH), or the second level wavelet transform (for example, 2LL, 3HH, 2HL, 2LH and 2HH).
  • the data of is not limited in the embodiment of this application.
  • the wavelet inverse transform circuit of the embodiment of the present application performs wavelet inverse transform on the data of the j-th wavelet transform of the code block data in a prescribed order, so that after the wavelet inverse transform is performed for a period of time, the data output by the wavelet inverse transform After satisfying the number of data processing of wavelet inverse transform, the inverse wavelet transform is started.
  • the inverse wavelet transform and the wavelet row inverse transform of the remaining data can be performed in parallel, which can improve the calculation efficiency of the wavelet inverse transform process.
  • both the data in the 1 row and the data in the N+1th row belong to the data in the frequency component LL after the j-1th level wavelet transform.
  • FIG. 5 shows a schematic structural diagram of another wavelet inverse transform circuit according to an embodiment of the present application.
  • the above-mentioned inverse transform circuit may include: a first inverse transform circuit 41, a transposition circuit 43, and a second inverse transform circuit 44.
  • the first inverse transform circuit 41 is used to: in the order of row 1, row N+1, row 2, row N+2, ..., row N, row 2N, row by row to the code
  • the j-th level wavelet transform data of the block data is subjected to wavelet line inverse transformation to obtain the j-th level wavelet line inverse transform result of the code block data.
  • the number of rows of the j-th wavelet transform data is 2N, where N is A positive integer greater than 1, j is a positive integer;
  • the transposition circuit 43 is used to: transpose the result of the j-th level wavelet row inverse transform of the code block data;
  • the second inverse transform circuit 44 is used to: Row, row N+1, row 2, row N+2, ..., row N, row 2N, the j-th level wavelet row inverse transformation of the transposed code block data row by row Perform the inverse wavelet transform on the result of to obtain the result of the j-th level wavelet inverse transform of the code block data.
  • the above-mentioned wavelet inverse transform circuit first performs wavelet inverse transform on the data of the j-th level of wavelet transform, then transposes the result of the j-th level of wavelet inverse transform, and executes the wavelet inverse transform. It should be understood that the wavelet inverse transform circuit may also first perform wavelet inverse transform on the j-th level of wavelet transform data, and then transpose the result of the j-th level of wavelet inverse transform, and perform wavelet row inverse transform. This is not limited.
  • the transposition circuit 43 may transpose the M rows of data after the result of the j-th level wavelet row inverse transform of the code block data includes M rows of data, so that the second inverse transform circuit 44 advances Perform inverse wavelet transformation on the transposed code block data.
  • M indicates that the second inverse transform circuit 44 can process at most M data in each clock cycle, and M is a positive integer.
  • the inverse wavelet transform is performed line by line in the order of line 1, line N+1, line 2, line N+2,..., line N, line 2N, the inverse wavelet transform is performed After M rows of data, the wavelet inverse transform can be executed. At this time, the first inverse transform circuit can continue to perform wavelet inverse transform on the remaining data. In this way, the wavelet inverse transform and wavelet inverse transform will be executed in parallel, which improves The computational efficiency of the wavelet inverse transform circuit.
  • the wavelet inverse transform circuit further includes: a first buffer 42 for storing the result of the j-th level wavelet row inverse transform of the code block data.
  • the transposition circuit 43 is further configured to obtain the result of the j-th level wavelet row inverse transformation of the code block data from the first buffer 42.
  • the above-mentioned first buffer 42 and transposition circuit 43 may also be a set of circuits.
  • the first buffer may be all or part of the memory in the transposition circuit 43.
  • the embodiment of the present application There is no restriction on this.
  • the wavelet inverse transform circuit further includes: a second buffer 45 for storing the result of the j-th level wavelet inverse transform of the code block data.
  • j is greater than 1
  • the first inverse transform circuit 41 is further configured to: obtain the j-th level wavelet inverse transform result of the code block data from the second buffer 45;
  • the result of the j-th level wavelet inverse transform is used as the LL data of the j-1 level wavelet transform, and the HL data, LH data, and HH data of the j-1 level wavelet transform of the code block data are combined as the code block
  • the inverse transform circuit is also used to: according to the first line, the 2N+1 line, the second line, the 2N+2 line,..., the 2Nth line, the 4Nth line In the order of lines, perform wavelet inverse transformation on the j-1 level wavelet transform data of the code block data line by line to obtain the j-1 level wavelet inverse transform result of the code block data.
  • the data of the first row and the data of the 2N+1th row both belong to the data in the original image block (ie, the image block before wavelet transform). If j is greater than 2, then the data in the first row and the data in the 2N+1 row belong to the data in the frequency component LL after the j-2th level wavelet transform.
  • the encoder performs the j-th level wavelet transform
  • the decoder when the decoder decodes the j-1th level wavelet transform data, it needs to decode the j-th level wavelet transform data first, and the wavelet inverse of the j-th level wavelet transform data
  • the transformation result will be stored in the second buffer 45. Therefore, when performing the j-1th level wavelet inverse transform processing, the inverse transform circuit can combine the jth level wavelet inverse transform results stored in the second buffer 45 and the remaining data of the j-1th level to perform wavelet inverse transform .
  • the first inverse transform circuit 41 shown in FIG. 5 can be used to: according to the first row, the 2N+1th row, the second row, the 2N+2th row,..., the 2Nth row, the 4Nth row In the order of rows, perform wavelet inverse transform on the j-1th level wavelet transform data of the code block data line by line to obtain the j-1th level wavelet line inverse transform result of the code block data; transposition circuit 43 It can be used to: transpose the result of the j-1th level wavelet row inverse transform of the code block data; the second inverse transform circuit 44 can be used to: according to the first row, the 2N+1 row, and the second row , Row 2N+2, ..., row 2N, row 4N, perform the wavelet column inverse transformation on the j-1 level wavelet row inverse transformation result of the transposed code block data row by row to obtain The result of the j-1th level wavelet inverse transform of the code block data.
  • level j-1 data is similar to that of level j data, and the transposition circuit 43 may also include M rows of data in the result of the j-1 level wavelet row inverse transformation of the code block data. After that, the M rows of data are transposed, so that the second inverse transform circuit 44 performs wavelet inverse transform on the transposed code block data in advance, which will not be repeated here.
  • decoder 1 or decoder 2 can select an appropriate decoding mode from the following four decoding modes according to requirements when decoding:
  • the wavelet inverse transform circuit will directly output the 3LL component (the size is 32 ⁇ 32) without any operation.
  • Decoding all the components of the third-level wavelet transform is equivalent to decoding 2LL (64 ⁇ 64 in size), as shown in Figure 7, the wavelet inverse transform circuit will first input the first row of data of 3LL+3HL (corresponding to the execution order 0 in the figure) ), a total of 64 data, 8 data input per clock cycle, the total overhead is 8 clock cycles.
  • 4 data belong to the 3LL component and 4 data belong to the 3HL component, that is, the data of different frequency components are simultaneously interleaved and inversely transformed. In this way, the data before wavelet transform can be interleaved and restored.
  • the wavelet inverse transform circuit inputs the first row of data of 3LH+3HH (corresponding to the execution order 1 in the figure), then inputs the second row of data of 3LL+3HL (corresponding to the execution order 2 in the figure), and then inputs 3LH+3HH The second row of data (corresponding to the execution order 3 in the figure), and so on, until all the components of the third-level wavelet transform have been input.
  • Decoding all the components of the second-level wavelet transform requires decoding all the components of the third-level wavelet transform (ie 3LL, 3HL, 3LH, and 3HH), and then decode the remaining components of the second-level wavelet transform (ie, 2HL, 2LH, and 2HH).
  • the decoding of all components of the third-level wavelet transform is as described in 2).
  • the wavelet inverse transform circuit can input the first row of 2HL data (64 data in total), and combine the 64 data of the first row of 2LL for processing (corresponding to the execution sequence 00 in the figure), and input 8 data per clock cycle.
  • the total overhead is 16 clock cycles.
  • 4 data belong to the 2LL component
  • 4 data belong to the 2HL component.
  • the wavelet inverse transform circuit inputs the first row of data of 2LH+2HH (corresponding to the execution order 11 in the figure), and then inputs the second row of data of 2LL+2HL (corresponding to the execution order 22 in the figure), and then inputs 2LH+2HH The second row of data (corresponding to the execution order 33 in the figure), and so on, until all the components of the second-level wavelet transform have been input.
  • the wavelet inverse transform circuit can input the first row of data of 1HL (128 data in total), and combine the 128 data of the first row of 1LL for processing (corresponding to the execution sequence 000 in the figure), and input 8 data per clock cycle.
  • the total overhead is 32 clock cycles. Among the 8 data input in each clock cycle, 4 data belong to 1LL component, and 4 data belong to 1HL component.
  • the wavelet inverse transform circuit inputs the first row of data of 1LH+1HH (corresponding to the execution order 111 in the figure), then inputs the second row of data of 1LL+1HL (corresponding to the execution order 222 in the figure), and then inputs 1LH+1HH The second row of data (corresponding to the execution sequence 333 in the figure), and so on, until all the components of the first-level wavelet transform have been input.
  • the wavelet inverse transform circuit of the embodiment of the present application performs wavelet inverse transform on the j-th wavelet transform data of the code block data in a prescribed order, so that the wavelet column inverse transform and the wavelet row inverse transform can be performed in parallel, which can improve the wavelet inverse transform The computational efficiency of the process.
  • the embodiment of the application also provides a wavelet inverse transform method.
  • the wavelet inverse transform method can be executed by the decoder 1, the decoder 2, or the wavelet inverse transform circuit 15 mentioned above.
  • the wavelet inverse transform method includes:
  • both the data in the 1 row and the data in the N+1th row belong to the data in the frequency component LL after the j-1th level wavelet transform.
  • the performing wavelet inverse transformation on the j-th wavelet transform data of the code block data line by line includes: according to the first line, the N+1th line, the second line, the N+2th line, ..., in the order of the Nth row and the 2Nth row, perform wavelet row inverse transformation on the j-th level wavelet transform data of the code block data line by line to obtain the j-th level wavelet line inverse transform result of the code block data ,
  • the number of rows of the j-th level wavelet transform data is 2N, N is a positive integer greater than 1, and j is a positive integer; transpose the result of the j-th level wavelet row inverse transform of the code block data; according to In the order of row 1, row N+1, row 2, row N+2, ..., row N, row 2N, the j-th level wavelet row of the transposed code block data is row by row
  • the result of the inverse transformation performs inverse wavelet transformation to obtain the result of the j-th level
  • the transposing the result of the j-th level wavelet row inverse transform of the code block data includes: after the result of the j-th level wavelet row inverse transform of the code block data includes M rows of data, Transpose the M rows of data, M indicates that each clock cycle can process at most M data, and M is a positive integer.
  • the method further includes: storing the j-th level wavelet row inverse transform result of the code block data in the In a buffer.
  • the method further includes: obtaining the j-th level wavelet of the code block data from the first buffer The result of the inverse transformation.
  • the method further includes: storing the j-th level wavelet inverse transform result of the code block data in a second buffer ⁇
  • j is greater than 1, and the method further includes: obtaining the result of the j-th level wavelet inverse transform of the code block data from the second buffer; and taking the result of the j-th level wavelet inverse transform as
  • the LL data of the j-1 level wavelet transform, combined with the HL data, LH data, and HH data of the j-1 level wavelet transform of the code block data, are used as the j-1 level wavelet transform of the code block data Data; in the order of row 1, row 2N+1, row 2, row 2N+2, ..., row 2N, row 4N, row by row the j-1 level wavelet of the code block data
  • the transformed data is subjected to inverse wavelet transform to obtain the result of the j-1th level wavelet inverse transform of the code block data.
  • the performing wavelet inverse transform on the j-1th level wavelet transform data of the code block data line by line includes: according to the first line, the 2N+1th line, the second line, and the 2N+2th line Row,..., 2Nth row, 4Nth row, perform wavelet row inverse transformation on the j-1th level wavelet transformed data of the code block data row by row to obtain the j-1th level of the code block data Wavelet inverse transform result; transpose the result of j-1 level wavelet inverse transform of the code block data; according to the first line, the 2N+1 line, the second line, the 2N+2 line,...
  • the 2Nth row and the 4Nth row perform wavelet column inverse transformation on the j-1th level wavelet row inverse transform result of the transposed code block data row by row to obtain the jth row of the code block data
  • the result of -1 level wavelet inverse transform is the result of -1 level wavelet inverse transform.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD)), etc.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)

Abstract

La présente invention concerne un circuit et un procédé de transformée inverse en ondelettes. Le circuit de transformée inverse en ondelettes comprend : un premier circuit d'interface utilisé pour obtenir des données de bloc de code décodées ; et un circuit de transformée inverse utilisé pour effectuer une transformée inverse en ondelettes sur les données de transformée en ondelettes au jème niveau des données de bloc de code, ligne par ligne, dans un ordre de la 1ère ligne, la (N+1)ème ligne, la 2ème ligne, la (N+2)ème ligne ..., la Nème ligne, la 2Nème ligne pour obtenir le résultat de la transformée inverse en ondelettes au jème niveau des données de bloc de code, N et j étant chacun des entiers positifs supérieurs à 1, et la composante de fréquence qui correspond aux données dans la (N +1)ème ligne étant différente de la composante de fréquence qui correspond aux données dans la 1re ligne. Selon le circuit de transformée inverse en ondelettes et le procédé du mode de réalisation de la présente invention, la séquence de transformée inverse en ondelettes est ajustée, de sorte que la transformée inverse de colonne en ondelettes et la transformée inverse de ligne en ondelettes peuvent être effectuées en parallèle, ce qui permet d'améliorer l'efficacité de calcul du processus de transformée inverse en ondelettes.
PCT/CN2019/084919 2019-04-29 2019-04-29 Circuit et procédé de transformée inverse en ondelettes WO2020220179A1 (fr)

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CN201980007856.2A CN111567042B (zh) 2019-04-29 2019-04-29 小波逆变换电路和方法

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CN101984666A (zh) * 2010-11-19 2011-03-09 南京邮电大学 一种基于提升小波变换的图像无损压缩和解压方法
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CN101984666A (zh) * 2010-11-19 2011-03-09 南京邮电大学 一种基于提升小波变换的图像无损压缩和解压方法
CN102572429A (zh) * 2011-12-29 2012-07-11 东南大学 一种二维离散小波变换的硬件架构
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