WO2020215610A1 - 磁性随机存储器的磁隧道结器件 - Google Patents

磁性随机存储器的磁隧道结器件 Download PDF

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WO2020215610A1
WO2020215610A1 PCT/CN2019/109109 CN2019109109W WO2020215610A1 WO 2020215610 A1 WO2020215610 A1 WO 2020215610A1 CN 2019109109 W CN2019109109 W CN 2019109109W WO 2020215610 A1 WO2020215610 A1 WO 2020215610A1
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layer
ferromagnetic
magnetic
random access
access memory
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French (fr)
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叶力
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中国科学院上海微系统与信息技术研究所
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials

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  • the present invention relates to the memory field of integrated circuit chips, in particular to a magnetic random access memory that can work at low and extremely low temperatures. It relates to a method for reducing the dynamic power consumption of a magnetic random access memory.
  • MRAM Magnetic Random Access Memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • flash flash memory
  • the existing magnetic random access memory chip is composed of an array of one or more memory cells 100.
  • the simplest basic memory cell 100 is shown in FIG. 1B, including a memory bit element 101 and a switching device. 102.
  • the switching device 102 can be a MOS field effect tube, a superconducting device or other three-terminal device with a switching function.
  • the switching device 2 is connected to the word line Z of the magnetic random access memory chip to switch on or off the unit; 101 and the switching device 102 are connected in series and connected to the bit line W and the source line Y of the magnetic random access memory. And thus, the basic memory unit 100 is periodically repeated in rows and columns to form a memory array.
  • the storage bit components 101, 101' generally use magnetic tunneling junction devices (MTJ, Magnetic Tunneling Junction).
  • the MTJ device is composed of two layers of ferromagnetic material sandwiching a very thin non-ferromagnetic insulating material, including memory layers 1011, 1011', insulating layers 1012, 1012', and reference layers 1013, 1013' that are stacked sequentially.
  • the single arrow in the middle represents the reference layer, the direction of the arrow indicates the direction of the magnetic moment, the double arrow indicates that the direction of the magnetic moment is variable, and the single arrow indicates that the direction of the magnetic moment is fixed.
  • the reference layer 1013, 1013' is a layer of ferromagnetic material with a fixed magnetization direction
  • the memory layer 1011, 1011' is another layer of ferromagnetic material with a variable magnetization direction, so the magnetization direction of the memory layer 1011, 1011' can be It is parallel or anti-parallel to the magnetization direction of the reference layer 1013, 1013'.
  • the direction of the magnetic moments of the memory layer 1011, 1011' and the reference layer 1013, 1013' can be parallel to the in-plane (such as the memory layer 1011 and the reference layer 1013) or perpendicular to the out-of-plane direction (such as the memory layer 1011' and the reference layer 1013) ').
  • the memory layer can be above or below the reference layer, and the insulating layer is always between the two layers.
  • the above-mentioned MTJ device is realized by etching a magnetic multilayer film material into a cylindrical device with a small size (1-1000 nanometers in diameter). Due to the quantum tunneling effect, current can pass through the tunnel barrier layer in the device, and the MTJ device can be regarded as a variable resistor whose resistance depends on the magnetization direction of the variable magnetization layer. The resistance is low when the magnetization directions are parallel, and the resistance is high when the magnetization directions are antiparallel.
  • the process of reading the magnetic random access memory is to measure the resistance of the memory bit component MTJ of the corresponding address.
  • the process of writing to the magnetic random access memory is to invert (operate) the magnetic moment of the memory layer by passing a suitable current on the storage bit element MTJ of the corresponding address.
  • Two different current directions, bottom-up and top-down, can respectively realize the magnetic moment parallel to antiparallel, and the magnetic moment antiparallel to parallel flip.
  • a read and write voltage is applied between the bit lines and source lines of each array of the magnetic random access memory, so that the readout circuit of the magnetic random access memory detects the resistance of the storage bit components 101, 101', and then obtains its memory layers 1011, 1011 'The direction of magnetization. Since the resistance of the storage bit components 101, 101' not only depends on the magnetization direction of the variable magnetization layer, but also drifts with temperature and position, etc., the general method is to use some of the chips that have been written as high resistance or low resistance.
  • the resistive storage bit components are used as reference devices.
  • a sense amplifier Sense Amplifier
  • the memory layers 1011, 1011' include ferromagnetic materials and non-magnetic materials.
  • the thickness of the magnetic layer in the prior art is generally 5-1.5 nm, and the non-magnetic materials It is generally one layer, and each layer is thick enough to reflect its own intrinsic properties.
  • the selected magnetic material is CoFeB alloy
  • the non-magnetic material is Cr, Cu, Mo, Ru
  • the structure is 1-2nm CoFeB/0.3-0.4nmW/0.4-1nm CoFeB. This will cause the memory layers 1011, 1011' to have higher switching magnetic moments. Therefore, the existing MTJ devices have the following disadvantages:
  • the way to operate the memory cell is to drive the reversal of the magnetic moment of the memory layer through sufficient write current, so the write operation requires considerable power consumption.
  • the way to read the memory cell is to sense the current change caused by the resistance change through the sensitive amplifier circuit.
  • the current required for the write operation is much greater than the current required for the read operation, and the dynamic power consumption of the chip comes from the write operation. Excessive write current will also affect the life of the memory.
  • a memory cell suitable for a room temperature magnetic random access memory will encounter obvious write operation difficulties under low and extremely low temperature environments.
  • the voltage required to flip the magnetic moment of the memory layer increases by about 60%. This is because the magnetic moment of the memory layer from room temperature to low temperature becomes larger, the directivity of the magnetic moment (magnetic anisotropy) becomes stronger, and the initial flip angle caused by thermal disturbance at low temperature becomes smaller.
  • the purpose of the present invention is to provide a magnetic tunnel junction device of a magnetic random access memory with low temperature and low power consumption, so as to reduce the difficulty of driving the magnetic moment inversion of the memory layer, so that the magnetic random access memory can work at low or extremely low temperature with low power consumption.
  • the present invention provides a magnetic tunnel junction device of a magnetic random access memory, which includes a reference layer, a tunneling dielectric layer and a memory layer stacked sequentially from bottom to top, and the memory layer is made by a physical vapor deposition method. It includes ferromagnetic materials, and non-magnetic materials doped into the ferromagnetic materials by means of deposition layer insertion and/or sputtering.
  • the memory layer includes a ferromagnetic diluted alloy, which is deposited by co-sputtering using a target of ferromagnetic material and a non-magnetic material or sputtering using a target of ferromagnetic diluted alloy.
  • the memory layer is deposited in multiple layers, and the thickness of each deposited layer is 0.1-2 nm.
  • composition of the non-ferromagnetic material is preferably 20%-80%.
  • the memory layer includes a first deposition layer with N layers spaced apart from each other, and a second deposition layer with N-1 layers interposed therebetween spaced apart from each other, and N is at least 3; wherein, the first deposition layer is all ferromagnetic Dilute the alloy, use all ferromagnetic layers or partially use ferromagnetic dilution alloys, partially use ferromagnetic layers, and use dilution auxiliary layers for the second deposition layer; or use one of ferromagnetic dilution alloys and ferromagnetic layers for the first deposition layer.
  • the second deposition layer adopts the other of a ferromagnetic dilution alloy and a ferromagnetic layer; the ferromagnetic dilution alloy is co-sputtered by using a target material of ferromagnetic material and a non-magnetic material or sputtering using a target material of a ferromagnetic dilution alloy
  • the material of the ferromagnetic layer is a ferromagnetic material
  • the material of the dilution auxiliary layer is a non-ferromagnetic material.
  • each deposition layer is different, and the first deposition layer and the second deposition layer of different layers use different materials.
  • the first deposition layer adopts a ferromagnetic layer
  • the second deposition layer adopts a dilution auxiliary layer
  • the ratio of the total thickness of the dilution auxiliary layer to the total thickness of the memory layer is not higher than 80%.
  • the ferromagnetic material is one or more of Fe, Co and FeB and CoFeB with variable composition; the non-ferromagnetic material is Ta, TaN, Ti, TiN, NiCr, Pt, W, Ru, Mo And one or more of Ir.
  • the reference layer includes a reference ferromagnetic layer, a ferromagnetic auxiliary layer, and a transition layer stacked in sequence.
  • the reference ferromagnetic layer and the ferromagnetic auxiliary layer are CoFeB materials with variable composition, the Co composition is 20-80%, and the Fe composition is 20-80%, B component 20-30%, thickness 0.5-2nm, the material of the transition layer 133 is one or more of Cr, Cu, Mo, Ru, Pd, Hf, Ta, W, Tb and Ir , The thickness is 0.2-1nm.
  • the material of the tunneling dielectric layer is Mg or Al-based oxide, and its thickness is 1-2 nm.
  • a seed layer and a pinning layer are sequentially stacked below the reference layer; an auxiliary layer, a protective layer, and a mask layer are stacked sequentially above the memory layer.
  • the magnetic random access memory of the present invention adopts more stacked layers and a thinner thickness of each layer, or a co-sputtering method, or a combination of the two methods, to achieve better non-magnetic materials.
  • Uniformly mixed into the magnetic material to gradually and controllably reduce the magnetic properties of the memory layer (including magnetic moment, Curie temperature, and anisotropy strength). Therefore, through the above design of the memory layer, the temperature at room temperature, low temperature or The current and power consumption required to flip the magnetic moment of the memory layer at extremely low temperatures enable the magnetic random access memory to work with low power consumption at room temperature, low temperature or extremely low temperature.
  • FIG. 1A is a schematic diagram of an array structure of a conventional magnetic random access memory chip.
  • FIG. 1B is a schematic diagram of the structure of a memory unit of a conventional magnetic random access memory chip.
  • FIG. 2A is a schematic structural diagram of an embodiment of a storage bit element of a storage unit of a conventional magnetic random access memory chip.
  • 2B is a schematic structural diagram of another embodiment of the storage bit element of the storage unit of the existing magnetic random access memory chip
  • FIG. 3 is a schematic diagram of the writing voltage of the memory cell of the existing magnetic random access memory at low and extremely low temperature changes with temperature;
  • FIG. 4A is a schematic structural diagram of a magnetic tunnel junction device of a magnetic random access memory according to an embodiment of the present invention.
  • FIG. 4B is a schematic structural diagram of a magnetic tunnel junction device of a magnetic random access memory according to another embodiment of the present invention.
  • 5A is a schematic structural diagram of a memory layer of a magnetic tunnel junction device of a magnetic random access memory according to an embodiment of the present invention
  • 5B is a schematic structural diagram of a memory layer of a magnetic tunnel junction device of a magnetic random access memory according to another embodiment of the present invention.
  • 5C is a schematic structural diagram of a memory layer of a magnetic tunnel junction device of a magnetic random access memory according to another embodiment of the present invention.
  • FIG. 5D is a schematic structural diagram of a memory layer of a magnetic tunnel junction device of a magnetic random access memory according to another embodiment of the present invention.
  • 4A-4B shows the magnetic tunnel junction device 1 of the magnetic random access memory according to the present invention, which is processed into a circular columnar shape by etching and includes a seed layer 11 and a pinning layer stacked sequentially from bottom to top 12.
  • the reference layer 13 and the memory layer 15 are ferromagnetic layers with magnetic moments
  • the tunneling dielectric layer 14 is a non-ferromagnetic insulating layer, which is used to generate the tunnel magnetoresistance effect and induce the perpendicular anisotropy of the interface, thereby forming a magnetic
  • the most basic structure of the tunnel junction produces the tunnel magnetoresistance effect and the spin torque flip effect.
  • the reference layer 13 is a ferromagnetic layer with a fixed magnetic moment, which includes a reference ferromagnetic layer 131, a ferromagnetic auxiliary layer 132 and a transition layer 133 stacked in sequence.
  • the reference ferromagnetic layer 131 and the ferromagnetic auxiliary layer 132 are CoFeB materials with variable compositions, with a Co composition of 20-80%, an Fe composition of 20-80%, a B composition of 20-30%, and a thickness of 0.5-2 nm.
  • the transition layer 133 may be one or more of Cr, Cu, Mo, Ru, Pd, Hf, Ta, W, Tb, and Ir, with a thickness of 0.2-1 nm.
  • the reference ferromagnetic layer 131 is directly adjacent to the tunneling dielectric layer to provide a tunnel magnetoresistance effect and a spin torque flip effect.
  • the ferromagnetic auxiliary layer 132 is used to assist in improving the crystallization condition of the tunnel junction, reduce grain boundary defects, and improve the quality and reliability of the tunnel junction.
  • the transition layer 133 is used to connect different lattice orientation structures on both sides to optimize the performance of the magnetic tunnel junction.
  • the material of the tunnel dielectric layer 14 is generally Mg or Al-based oxide, and its thickness is 1-2 nm.
  • the magnetic moment of the ferromagnetic material of the memory layer 15 can be reversed, and the direction of the magnetic moment is used to store binary information 0 and 1.
  • the memory layer 15 is made by a physical vapor deposition method, which includes a ferromagnetic material and a non-magnetic material doped with the ferromagnetic material through a deposition layer insertion method and/or a co-sputtering method.
  • the ferromagnetic materials are Fe, Co, and one or more of FeB and CoFeB with variable composition
  • the non-ferromagnetic materials are Ta, TaN, Ti, TiN, NiCr, Pt, W, Ru, Mo and Ir One or more of.
  • the physical vapor deposition method is realized by sputtering the corresponding target material under high vacuum degree by material deposition, and the physical vapor deposition method uses low sputtering pressure and heavy atomic mass sputtering gas as much as possible, so that the deposited material of each layer is kept flat Under the premise of high quality, it is as thin as possible (1-10 angstroms), so that non-magnetic materials are mixed into magnetic materials more uniformly.
  • the anisotropy of the memory layer 15 magnetic moment * magnetic anisotropy field.
  • the magnetic moment is reduced, and the equivalent anisotropy field It has a positive correlation with the magnetic moment, so the magnetic anisotropy field of the memory layer 15 decreases and also decreases.
  • the magnetism is diluted, and the ferromagnetic order strength (Curie temperature) is reduced, and the data non-volatility of the memory layer is reduced.
  • the present invention is suitable for SRAM type
  • the specific range of the magnetic dilution degree of the memory layer depends on the chip operating temperature required by the application scenario (low power consumption, high speed, weak non-volatility), or low temperature application scenario.
  • the memory layer 15 of the present invention adopts more stacked layers and a thinner thickness of each layer, or a co-sputtering method, or a combination of the two methods, to achieve a more uniform mixing of non-magnetic materials into magnetic materials, Therefore, the gradual control of the magnetic properties of the memory layer is realized, especially the gradual control of the magnetic decrease.
  • the memory layer 15 includes a ferromagnetic dilution alloy 151, which is deposited by co-sputtering with a target of ferromagnetic material and a non-magnetic material or sputtering with a target of a ferromagnetic dilution alloy. to make.
  • a more uniform mixing of non-magnetic materials into magnetic materials is achieved, thereby gradually and controllable reduction of the magnetic properties of the memory layer (including magnetic moment, Curie temperature, anisotropy).
  • the memory layer 15 is deposited in multiple layers, and the thickness of each deposited layer is 0.1-2 nm, and a non-magnetic material layer is not inserted separately for dilution.
  • a certain ferromagnetic material and non-magnetic material sputtering rate are selected to control the degree of ferromagnetic dilution in each layer to prepare a ferromagnetic dilution alloy.
  • the sputtering rate ratios of ferromagnetic materials and non-magnetic materials of different deposition layers can be different, the thickness of different deposition layers can be different, and the ferromagnetic dilution alloy selected for different deposition layers can be different and can be combined in any combination.
  • the composition of the non-ferromagnetic material is preferably 20%-80%, in order to achieve the purpose of low temperature and low power consumption of the present invention, while ensuring that the Curie temperature is still higher than the chip operating temperature.
  • the memory layer 15 includes a first deposition layer with N layers spaced apart from each other, and a second deposition layer with N-1 layers interposed therebetween spaced apart from each other, and N is at least 3.
  • the first deposition layer is all ferromagnetic dilution alloy 151, all ferromagnetic layer 152 or part of ferromagnetic dilution alloy 151 is partially ferromagnetic layer 152, and the second deposition layer is dilution auxiliary layer 153; or the first deposition layer One of the ferromagnetic dilution alloy 151 and the ferromagnetic layer 152 is used, and the second deposition layer is the other of the ferromagnetic dilution alloy 151 and the ferromagnetic layer 152; the ferromagnetic dilution alloy 151 adopts ferromagnetic materials and The target material of non-magnetic material is co-sputtered or deposited by the method of sputtering of the target material of ferromagnetic dilution alloy; the material of the ferromagnetic layer 152 is ferromagnetic material, and the material of the dilution auxiliary layer 153 is non-ferrous Magnetic material.
  • the memory layer 15 includes N layers of ferromagnetic layers 152 spaced apart from each other and N-1 layers inserted therein and a dilution auxiliary layer 153 spaced apart from each other.
  • the memory layer 15 includes N layers of ferromagnetic dilution alloy 151 spaced apart from each other, and N-1 layers inserted therein and a dilution auxiliary layer 153 spaced apart from each other.
  • FIG. 5B the memory layer 15 includes N layers of ferromagnetic dilution alloy 151 spaced apart from each other, and N-1 layers inserted therein and a dilution auxiliary layer 153 spaced apart from each other.
  • the memory layer 15 includes N first deposition layers spaced apart from each other and an N-1 diluting auxiliary layer 153 interposed therebetween, wherein the first deposition layer simultaneously uses The ferromagnetic dilution alloy 151 and the ferromagnetic layer 152 are added.
  • the thickness of each deposition layer is 0.1-2 nm, and the thickness of each deposition layer can be different.
  • the material of the ferromagnetic layer 152 is a ferromagnetic material
  • the material of the dilution auxiliary layer 153 is a non-ferromagnetic material.
  • the same material can be used for the first deposition layer and the second deposition layer of different layers, or different materials can be used.
  • the ratio of the total thickness of each of the ferromagnetic diluted alloy 151 and/or the non-magnetic material layer 152 to the total thickness of the memory layer 15 is determined according to the working temperature of the chip.
  • the working temperature of the chip depends on the requirements of the application scenario, and different temperature requirements correspond to different ratios.
  • the ratio of the total thickness of the dilution auxiliary layer 153 to the total thickness of the memory layer is at most 80%.
  • the seed layer 11 provides suitable flatness, crystal orientation, sufficient thermal stability and chemical stability, so that the magnetic tunnel junction device can obtain good performance after annealing.
  • the material of the seed layer 11 is one or a stack of at least two of Ta, TaN, Ti, TiN, NiCr, Pt, W, and Ru.
  • the thickness of the seed layer 11 is 1-20 nm.
  • the pinning layer 12 is used to pin the magnetic moment of the reference layer 13 in a fixed direction, so that the magnetic moment of the reference layer 13 is stable during reading and writing.
  • the thickness of the pinning layer 12 ranges from 1 to 10 nm.
  • the pinned layer 12 is a three-part synthetic antiferromagnetic, including two magnetic superlattices 121 and An antiferromagnetic coupling layer 122 between two ferromagnetic superlattices.
  • the superlattice material 121 is one of [Co
  • Ni]n and other multilayer film materials, or a mixture of two, and the number of repetitions is n 1-10;
  • the material of the antiferromagnetic coupling layer 122 is non-magnetic metal Ru.
  • the two parts of the magnetic superlattice 121 form a strong antiferromagnetic coupling through the antiferromagnetic coupling layer 122, and the magnetic superlattice 121 has strong perpendicular anisotropy, thereby ensuring the magnetic moment stability of the entire pinned layer 12 .
  • the pinned layer 12' includes a pinned ferromagnetic layer 121' and an antiferromagnetic layer adjacent to the reference layer 13
  • the antiferromagnetic layer 122' may be an antiferromagnetic alloy such as IrMn, PtMn, etc., with a thickness of about 10 nm.
  • the composite antiferromagnetic layer 123' includes a ferromagnetic metal next to the antiferromagnetic layer 122' and a coupling layer Ru next to the pinned ferromagnetic layer 121'.
  • the pinned layer 12' utilizes the exchange bias effect generated by the interface between the antiferromagnetic layer 122' and the pinned ferromagnetic layer 121', so that the magnetization direction of the pinned ferromagnetic layer 121' is fixed and parallel to the surface.
  • the auxiliary layer 16 is used to improve the perpendicular magnetic anisotropy and help the magnetic tunnel junction multilayer film material to form a suitable crystalline structure after annealing.
  • the material of the auxiliary layer 16 is Mg, MgO, or a stack of both to induce the perpendicular magnetic anisotropy of the magnetic layer.
  • the thickness of the auxiliary layer 16 is 0-2 nm.
  • the protective layer 17 is used for resisting etching and protecting the magnetic tunnel junction device 1 of the low-temperature and low-power magnetic random access memory of the present invention when the through hole is opened on the top, and prevents the process erosion of the hole etching. Its material is Ru and its thickness is 1-10nm.
  • the mask layer 18 is used to protect a part of the magnetic tunnel junction device 1 with the mask layer 18 when the MTJ cylinder is etched by the photolithography process, and etch away the rest.
  • the material of the mask layer 18 includes one of Ta, TaN, silicon oxide, or a stack of at least two.
  • the thickness of the mask layer 18 is in the range of 100-500 nm.

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Abstract

一种磁性随机存储器的磁隧道结器件，包括自下而上依次堆叠的参考层（13）、隧穿介电层（14）和记忆层（15），所述记忆层（15）采用物理气相沉积法制作，其包括铁磁材料，以及通过沉积层插入方式和/或共溅射方式来掺入该铁磁材料的非磁材料。磁性随机存储器的记忆层（15）相比于现有技术采用更多的叠层和更薄的每层厚度，或者共溅射的方法，或两种结合的方法，以实现非磁材料更均匀的混合进入磁性材料，以此来渐变可控地调节记忆层（15）的磁化强度、各向异性强度和居里温度，因此，通过记忆层（15）的上述设计，可以降低在低温或极低温度下翻转记忆层（15）磁矩的所需的电流和功耗，使得磁性随机存储器能够在室温、低温或极低温下以低功耗工作。

Description

磁性随机存储器的磁隧道结器件 技术领域
本发明涉及集成电路芯片的存储器领域，尤其涉及一种可在低温和极低温下工作的磁性随机存取存储器。涉及一种降低磁性随机存储器动态功耗的方法。
背景技术
随着材料科学、纳米科学的不断进步，一种新型高性能存储器磁性随机存储器(MRAM，Magnetic Random Access Memory)正在吸引人们的目光。它拥有静态随机存储器(SRAM)的高速读取写入能力，以及动态随机存储器(DRAM)的高集成度，而且几乎可以无限次地重复写入。磁性随机存储器采用磁性多层材料构成的纳米柱状器件中的磁矩方向来记录信息，而维持磁矩和磁矩的方向并不需要外加电源(相较于DRAM断电后存储数据完全丢失)，因此这种磁性随机存储器还具有闪存(Flash)的非易失性。上述多重优点使得该类基于磁性存储位元的存储器被业界看作下一代通用性存储的主要候选，广泛适用于各类应用场景。
与此同时，伴随摩尔定理逐渐接近极限，当前基于硅材料场效应管的集成电路功耗、速度等效能接近极限，业界亟待探索其新型的计算架构和元器件。包括基于约瑟夫森结的超导集成电路、通过量子比特操纵的量子计算机等。这些新型的计算机处理器都需要在极低温度下(液氦温度4.2K或更低)工作，而可以与之相兼容的低温存储器一直是实现有效计算功能的瓶颈。另外当前商用存储器一般仅支持至多零下40摄氏度的工作环境，而无法满足其他极端温度工作条件。
如图1A所示，现有的磁性随机存储器芯片由一个或多个存储单元100的阵列组成，其最简单的基本存储单元100如图1B所示，包括一个存储位元器件101和一个开关器件102。其中，开关器件102可以是MOS场效应管、超导器件或其他具有开关功能的三端器件，开关器件2连接到磁性随机存储器芯片的字线Z负责接通或切断这个单元；存储位元器件101和开关器件102 串联并连接接至磁性随机存储器的位线W和源线Y。并由此，通过行列周期性重复基本存储单位100形成存储阵列。
如图2A-2B所示，该存储位元器件101，101’一般采用磁性隧道结器件(MTJ，Magnetic Tunneling Junction)。MTJ器件是由两层铁磁性材料夹着一层非常薄的非铁磁绝缘材料所构成，包括依次堆叠的记忆层1011，1011’、绝缘层1012，1012’和参考层1013，1013’，图中单箭头代表参考层，箭头方向指磁矩方向，双箭头指磁矩方向可变，单箭头指磁矩方向固定不变。其中参考层1013，1013’为具有固定的磁化方向的一层铁磁材料，记忆层1011，1011’为磁化方向可变的另一层铁磁材料，因此记忆层1011，1011’的磁化方向可以和参考层1013，1013’的磁化方向平行或反平行。记忆层1011，1011’和参考层1013，1013’磁矩的方向可以是平行于面内(如记忆层1011和参考层1013)，或者垂直于面外方向(如记忆层1011’和参考层1013’)。其中，图2A-2B并不定义参考层和记忆层的上下层叠关系，实际情况中记忆层可在参考层上方或下方，绝缘层总是在两层之间。上述MTJ器件是将磁性多层薄膜材料经过刻蚀加工后形成微小尺寸(1-1000纳米直径)的圆柱状器件来实现的。由于量子隧穿效应，电流可以穿过器件中的隧道势垒层，MTJ器件可被视为一个可变电阻，其阻值依赖于可变磁化层的磁化方向。磁化方向平行时电阻低，磁化方向反平行时电阻高。读取磁性随机存储器的过程是对相应地址的存储位元器件MTJ的电阻进行测量。写入磁性随机存储器的过程是在相应地址的存储位元器件MTJ上通过合适的电流，来翻转(操作)记忆层的磁矩。自下而上和自上而下两种不同的电流方向可分别实现磁矩平行至反平行，以及磁矩反平行至平行的翻转。
磁性随机存储器的每个阵列的位线、源线之间施加有一读写电压，以使得磁性随机存储器的读出电路检测存储位元器件101，101’的电阻，进而得到其记忆层1011，1011’的磁化方向。由于存储位元器件101，101’的电阻除了依赖于可变磁化层的磁化方向，还会随着温度和位置等而漂移，一般的方法是使用芯片上的一些已经被写成高阻态或低阻态的存储位元器件作为参考器件。再使用一读出放大器(Sense Amplifier)来比较被检测的存储位元器件101，101’和参考器件的电阻。
对于现有的磁性随机存储器的存储位元器件101，101’，其记忆层1011，1011’包括铁磁材料和非磁材料，现有技术磁性层厚度范围一般是5-1.5nm，非磁材料一般为一层，且每一层的厚度足够厚以至于各自体现本征属性，以最常用的现有技术为例，选用的磁性材料是CoFeB合金，非磁性材料是Cr、Cu、Mo、Ru、Pd、Hf、Ta、W、Tb、Ir中的一种，结构为1-2nm CoFeB/0.3-0.4nmW/0.4-1nm CoFeB。这会导致记忆层1011，1011’的翻转磁矩较高。因此，现有的采用MTJ器件具有以下几方面缺点：
一方面是磁性随机存储器的功耗问题：操作存储单元的方式是通过足够的写入电流来驱动记忆层磁矩的翻转，因此写操作需要相当的功耗。读出存储单元的方式是通过灵敏放大电路感知电阻变化带来的电流变化。写操作所需的电流远大于读操作所需的电流，芯片的动态功耗更多来自于写操作。过大的写电流也会影响存储器的寿命。
另一方面，如图3所示，适用于室温磁性随机存储器的存储单元在低温和极低温环境下将遇到明显的写操作困难。如下图3的仿真结果，从室温300K到低温4.2K，翻转记忆层磁矩所需的电压增加了大约60％。这是因为从室温到低温记忆层的磁矩变大，磁矩的指向性(磁各向异性)变得更强，而且在低温热扰动所产生的翻转初始角变小，这些因素加在一起使得低温下的翻转电压提高，不仅使得功耗增加，耐久度降低，过高的写入电压也使得设计一个可工作的存储器变得难以实现。
发明内容
本发明的目的在于提供一种低温低功耗的磁性随机存储器的磁隧道结器件，以降低驱动记忆层磁矩翻转的难度，使得磁性随机存储器能够在低温或极低温下以低功耗工作。
为了实现上述目的，本发明提供一种磁性随机存储器的磁隧道结器件，包括自下而上依次堆叠的参考层、隧穿介电层和记忆层，所述记忆层采用物理气相沉积法制作，其包括铁磁材料，以及通过沉积层插入方式和/或溅射方式来掺入该铁磁材料的非磁材料。
记忆层包括铁磁稀释合金，其通过采用铁磁材料和非磁材料的靶材共溅 射或采用铁磁稀释合金的靶材溅射的方式沉积而成。
记忆层采用多层沉积，每一沉积层的厚度为0.1-2nm。
所述非铁磁材料的组分优选为20％-80％。
所述记忆层包括N层彼此间隔的第一沉积层，和插设于其中的N-1层彼此间隔的第二沉积层，N至少为3；其中，其中，第一沉积层全部采用铁磁稀释合金、全部采用铁磁层或部分采用铁磁稀释合金部分采用铁磁层，第二沉积层采用稀释辅助层；或第一沉积层采用铁磁稀释合金和铁磁层中的一种，第二沉积层采用铁磁稀释合金和铁磁层中的另一种；所述铁磁稀释合金通过采用铁磁材料和非磁材料的靶材共溅射或采用铁磁稀释合金的靶材溅射的方式沉积而成；所述铁磁层的材料为铁磁材料，所述稀释辅助层的材料为非铁磁材料。
各沉积层的厚度不同，且不同层的第一沉积层和第二沉积层均采用不同的材料。
第一沉积层采用铁磁层，第二沉积层采用稀释辅助层，且所述稀释辅助层的总厚度的厚度占记忆层总厚度的比例不高于80％。
所述铁磁材料为Fe、Co以及组分可变的FeB、CoFeB中的一种或多种；所述非铁磁材料为Ta、TaN、Ti、TiN、NiCr、Pt、W、Ru、Mo和Ir中的一种或多种。
所述参考层包括依次堆叠的参考铁磁层、铁磁辅助层和过渡层，参考铁磁层和铁磁辅助层是组分可变的CoFeB材料，Co组分20-80％，Fe组分20-80％，B组分20-30％，厚度0.5-2nm，过渡层133的材料为Cr、Cu、Mo、Ru、Pd、Hf、Ta、W、Tb和Ir中的一种或多种，厚度0.2-1nm。
所述隧穿介电层的材料为Mg或Al基的氧化物，且其厚度为1-2nm。
所述参考层下方设有依次堆叠的种子层和钉扎层；所述记忆层上方设有依次堆叠的辅助层、保护层和掩膜层。
本发明的磁性随机存储器，其记忆层相比于现有技术采用更多的叠层和更薄的每层厚度，或者共溅射的方法，或两种结合的方法，以实现非磁材料更均匀的混合进入磁性材料，以此来渐变可控地降低记忆层的磁性(包括磁矩、居里温度、各向异性强度)，因此，通过记忆层的上述设计，可以降低在 室温、低温或极低温度下翻转记忆层磁矩的所需的电流和功耗，使得磁性随机存储器能够在室温、低温或极低温下以低功耗工作。
附图说明
图1A为现有的磁性随机存储器芯片的阵列结构示意图。
图1B为现有的磁性随机存储器芯片的存储单元的结构示意图。
图2A为现有的磁性随机存储器芯片的存储单元的存储位元器件的一个实施例的结构示意图。
图2B为现有的磁性随机存储器芯片的存储单元的存储位元器件的另一个实施例的结构示意图；
图3为现有的磁性随机存储器的存储单元在低温和极低温下的写入电压随温度变化的示意图；
图4A为根据本发明的一个实施例的磁性随机存储器的磁隧道结器件的结构示意图；
图4B为根据本发明的另一个实施例的磁性随机存储器的磁隧道结器件的结构示意图；
图5A为根据本发明的一个实施例的磁性随机存储器的磁隧道结器件的记忆层的结构示意图；
图5B为根据本发明的另一个实施例的磁性随机存储器的磁隧道结器件的记忆层的结构示意图；
图5C为根据本发明的另一个实施例的磁性随机存储器的磁隧道结器件的记忆层的结构示意图；
图5D为根据本发明的另一个实施例的磁性随机存储器的磁隧道结器件的记忆层的结构示意图。
具体实施方式
以下结合具体实施例，对本发明做进一步说明。应理解，以下实施例仅用于说明本发明而非用于限制本发明的范围。
如图4A-4B所示为根据本发明的磁性随机存储器的磁隧道结器件1，其 采用刻蚀加工，加工为圆形柱状，其包括自下而上依次堆叠的种子层11、钉扎层12、参考层13、隧穿介电层14、记忆层15、辅助层16、保护层17和掩模层18。
其中，参考层13和记忆层15为具有磁矩的铁磁层，隧穿介电层14为非铁磁绝缘层，用于产生隧道磁阻效应并诱导界面垂直各向异性，由此构成磁隧道结最基本结构，产生隧道磁阻效应以及自旋扭矩翻转效应。
参考层13为磁矩固定不动的铁磁层，其包括依次堆叠的参考铁磁层131、铁磁辅助层132和过渡层133。参考铁磁层131和铁磁辅助层132是组分可变的CoFeB材料，Co组分20-80％，Fe组分20-80％，B组分20-30％，厚度0.5-2nm。过渡层133可以是Cr、Cu、Mo、Ru、Pd、Hf、Ta、W、Tb和Ir中的一种或多种，厚度0.2-1nm。参考铁磁层131同隧穿介电层直接相邻提供隧道磁阻效应和自旋扭矩翻转效应。铁磁辅助层132用于辅助提高隧道结的结晶状况，减少晶界缺陷，提高隧道结的质量和可靠性。过渡层133用于衔接两侧不同的晶格取向结构，优化磁隧道结性能。
隧穿介电层14的材料一般采用Mg或Al基的氧化物，其厚度为1-2nm。
记忆层15的铁磁材料的磁矩可来回翻转，并用磁矩的指向来记忆二进制信息0、1。所述记忆层15采用物理气相沉积法制作，其包括铁磁材料，以及通过沉积层插入方式和/或共溅射方式来掺入该铁磁材料的非磁材料。其中，铁磁材料为Fe、Co以及组分可变的FeB、CoFeB中的一种或多种；非铁磁材料为Ta，TaN，Ti，TiN，NiCr，Pt，W，Ru，Mo和Ir中的一种或多种。此外，物理气相沉积法通过材料沉积在高真空度下溅射相应靶材来实现，且物理气相沉积尽量采用低溅射气压和重原子质量溅射气体，使得每一层沉积的材料在维持平整度质量的前提下尽量薄(1-10埃)，以使得非磁材料更均匀的混入磁性材料。
由此，记忆层15的各向异性能＝磁矩*磁各向异性场，在记忆层15的铁磁材料中掺入非磁材料来进行稀释后，磁矩降低，等效各向异性场和磁矩正相关关系，因此记忆层15的磁各向异性场随之降低也降低。本发明的记忆层15的铁磁材料掺入非磁材料后，磁性被稀释体现为铁磁有序强度(居里温度)降低，记忆层数据非易失性降低，因此本发明适合于SRAM类型的应用场景 (低功耗，高速，弱非易失性)，或者低温应用场景，其记忆层的磁性稀释程度的具体范围取决于应用场景所要求的芯片工作温度。此外，由于本发明的记忆层15采用更多的叠层和更薄的每层厚度，或者共溅射的方法，或两种结合的方法，以实现非磁材料更均匀的混合进入磁性材料，因此实现了记忆层的磁性的渐变可控，尤其是其磁性降低的渐变可控。
在本发明的一些实施例中，记忆层15包括铁磁稀释合金151，其通过采用铁磁材料和非磁材料的靶材共溅射或采用铁磁稀释合金的靶材溅射的方式沉积而成。由此，实现非磁材料更均匀的混合进入磁性材料，以此来渐变可控的降低记忆层的磁性(包括：磁矩、居里温度、各向异性能)。在一个实施例中，如图5A所示，记忆层15采用多层沉积，每一所述沉积层的厚度为0.1-2nm，而不单独插入非磁材料层来进行稀释，每一层沉积时选用一定的铁磁材料和非磁材料的溅射速率，用以调控每一层中铁磁稀释的程度，以制得铁磁稀释合金。不同沉积层的铁磁材料和非磁材料的溅射速率比可以不同，不同沉积层的厚度可以不同，且不同沉积层选用的铁磁稀释合金可以不同，任意组合。其中，非铁磁材料的组分优选为20％-80％，以在达到本发明的低温低功耗的目的的同时，保证居里温度仍高于芯片工作温度。
在本发明的另一些实施例中，记忆层15包括N层彼此间隔的第一沉积层，和插设于其中的N-1层彼此间隔的第二沉积层，N至少为3。
其中，第一沉积层全部采用铁磁稀释合金151、全部采用铁磁层152或部分采用铁磁稀释合金151部分采用铁磁层152，第二沉积层采用稀释辅助层153；或第一沉积层采用铁磁稀释合金151和铁磁层152中的一种，第二沉积层采用铁磁稀释合金151和铁磁层152中的另一种；所述铁磁稀释合金151通过采用铁磁材料和非磁材料的靶材共溅射或采用铁磁稀释合金的靶材溅射的方式沉积而成；所述铁磁层152的材料为铁磁材料，所述稀释辅助层153的材料为非铁磁材料。
具体地，根据本发明的一个实施例，如图5B所示，记忆层15包括N层彼此间隔的铁磁层152和插设于其中的N-1层彼此间隔的稀释辅助层153。根据本发明的另一个实施例，如图5C所示，记忆层15包括N层彼此间隔的铁磁稀释合金151和插设于其中的N-1层彼此间隔的稀释辅助层153。根据 本发明的再一个实施例，如图5D所示，记忆层15包括N层彼此间隔的第一沉积层和插设于其中的N-1层稀释辅助层153，其中第一沉积层同时采用了铁磁稀释合金151和铁磁层152。
其中，每一沉积层的厚度为0.1-2nm，各沉积层的厚度可以不同。所述铁磁层152的材料为铁磁材料，所述稀释辅助层153的材料为非铁磁材料。不同层的第一沉积层和第二沉积层均可采用相同的材料，也可以采用不同的材料。所述铁磁稀释合金151和/或非磁材料层152各自的总厚度占记忆层15总厚度的比例根据芯片工作温度来确定，芯片工作温度取决应用场景的要求，不同温度要求对应不同的比例范围，一般而言，当记忆层15的第一沉积层采用铁磁层152，第二沉积层采用稀释辅助层153时，稀释辅助层153的总厚度的厚度占记忆层总厚度的比例至多为80％。
此外，再请参见图4A-图4B，种子层11提供合适的平整度、结晶取向、足够的热稳定性和化学稳定性，使得磁性隧道结器件在退火后获得良好的性能。种子层11的材料为Ta，TaN，Ti，TiN，NiCr，Pt，W，Ru中的一种或至少两种的层叠。种子层11的厚度1-20nm。
钉扎层12用于将参考层13的磁矩钉扎在固定方向，使得参考层13的磁矩在读写过程中稳固不动。钉扎层12的厚度范围为1-10nm。
如图4A所示，在一个实施例中，若参考层13的磁矩垂直于其表面，则钉扎层12为三部分组成的合成反铁磁，包括两个磁性超晶格121和设于两个铁磁超晶格之间的一个反铁磁耦合层122。超晶格材料121是[Co|Pt]n，[Co|Pd]n，[Co|Ni]n等多层膜材料其中一种或者两种的混合使用，其重复次数n＝1-10；反铁磁耦合层122的材料是非磁金属Ru。由此，两部分磁性超晶格121经过反铁磁耦合层122形成强反铁磁耦合，并且磁性超晶格121具有强垂直各向异性，因此保证了整个钉扎层12的磁矩稳定性。
如图4B所示，在另一个实施例中，若参考层13的磁矩在其面内方向，则钉扎层12’包括和参考层13相邻的钉扎铁磁层121’、反铁磁层122’以及位于钉扎铁磁层121’和反铁磁层122’的界面上的合成反铁磁层123’。反铁磁层122’可以是IrMn，PtMn等反铁磁合金，厚度约为10纳米。合成反铁磁层123’包括紧邻反铁磁层122’的铁磁金属和紧邻钉扎铁磁层121’的耦合层Ru。由 此，钉扎层12’利用反铁磁层122’和钉扎铁磁层121’界面所产生的交换偏置效果，使得钉扎铁磁层121’的磁化方向固定不变且平行于面内。
辅助层16用于提高垂直磁各向异性以及帮助磁隧道结多层膜材料在退火后形成合适的结晶结构。辅助层16的材料为Mg、MgO或两者的层叠，以诱导磁性层的垂直磁各向异性。辅助层16的厚度为0-2nm。
保护层17用于抵抗刻蚀，保护本发明的低温低功耗磁性随机存储器的磁隧道结器件1在顶上开通孔时，阻止开孔刻蚀的工艺侵蚀。其材料为Ru，其厚度为1-10nm。
掩膜层18用于在光刻工艺刻蚀MTJ圆柱时保护一部分具有掩模层18的磁隧道结器件1，并将其余部分都刻蚀掉。掩膜层18的材料包括包括Ta，TaN，硅氧化物中的一种，或至少两种的层叠。掩膜层18的厚度在100-500nm范围。
以上所述的，仅为本发明的较佳实施例，并非用以限定本发明的范围，本发明的上述实施例还可以做出各种变化。即凡是依据本发明申请的权利要求书及说明书内容所作的简单、等效变化与修饰，皆落入本发明专利的权利要求保护范围。本发明未详尽描述的均为常规技术内容。

Claims (11)

  1. 一种磁性随机存储器的磁隧道结器件，包括自下而上依次堆叠的参考层(13)、隧穿介电层(14)和记忆层(15)，其特征在于，所述记忆层(15)采用物理气相沉积法制作，其包括铁磁材料，以及通过沉积层插入方式和/或溅射方式来掺入该铁磁材料的非磁材料。
  2. 根据权利要求1所述的磁性随机存储器的磁隧道结器件，其特征在于，记忆层(15)包括铁磁稀释合金(151)，其通过采用铁磁材料和非磁材料的靶材共溅射或采用铁磁稀释合金的靶材溅射的方式沉积而成。
  3. 根据权利要求2所述的磁性随机存储器的磁隧道结器件，其特征在于，记忆层(15)采用多层沉积，每一沉积层的厚度为0.1-2nm。
  4. 根据权利要求2所述的磁性随机存储器的磁隧道结器件，其特征在于，所述非铁磁材料的组分优选为20％-80％。
  5. 根据权利要求1所述的磁性随机存储器的磁隧道结器件，其特征在于，所述记忆层(15)包括N层彼此间隔的第一沉积层，和插设于其中的N-1层彼此间隔的第二沉积层，N至少为3；
    其中，第一沉积层全部采用铁磁稀释合金(151)、全部采用铁磁层(152)或部分采用铁磁稀释合金(151)部分采用铁磁层(152)，第二沉积层采用稀释辅助层(153)；或第一沉积层采用铁磁稀释合金(151)和铁磁层(152)中的一种，第二沉积层采用铁磁稀释合金(151)和铁磁层(152)中的另一种；
    所述铁磁稀释合金(151)通过采用铁磁材料和非磁材料的靶材共溅射或采用铁磁稀释合金的靶材溅射的方式沉积而成；所述铁磁层(152)的材料为铁磁材料，所述稀释辅助层(153)的材料为非铁磁材料。
  6. 根据权利要求5所述的磁性随机存储器的磁隧道结器件，其特征在于，各沉积层的厚度不同，且不同层的第一沉积层和第二沉积层均采用不同的材料。
  7. 根据权利要求5所述的磁性随机存储器的磁隧道结器件，其特征在于， 第一沉积层采用铁磁层(152)，第二沉积层采用稀释辅助层(153)，且所述稀释辅助层(153)的总厚度的厚度占记忆层总厚度的比例至多为80％。
  8. 根据权利要求1所述的磁性随机存储器的磁隧道结器件，其特征在于，所述铁磁材料为Fe、Co以及组分可变的FeB、CoFeB中的一种或多种；所述非铁磁材料为Ta、TaN、Ti、TiN、NiCr、Pt、W、Ru、Mo和Ir中的一种或多种。
  9. 根据权利要求1所述的磁性随机存储器的磁隧道结器件，其特征在于，所述参考层(13)包括依次堆叠的参考铁磁层(131)、铁磁辅助层(132)和过渡层(133)，参考铁磁层(131)和铁磁辅助层(132)是组分可变的CoFeB材料，Co组分20-80％，Fe组分20-80％，B组分20-30％，厚度0.5-2nm，过渡层133的材料为Cr、Cu、Mo、Ru、Pd、Hf、Ta、W、Tb和Ir中的一种或多种，厚度0.2-1nm。
  10. 根据权利要求1所述的磁性随机存储器的磁隧道结器件，其特征在于，所述隧穿介电层(14)的材料为Mg或Al基的氧化物，且其厚度为1-2nm。
  11. 根据权利要求1所述的磁性随机存储器的磁隧道结器件，其特征在于，所述参考层(13)下方设有依次堆叠的种子层(11)和钉扎层(12)；所述记忆层上方设有依次堆叠的辅助层(16)、保护层(17)和掩膜层(18)。
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