WO2020211415A1 - 半导体装置、像素电路及其控制方法 - Google Patents

半导体装置、像素电路及其控制方法 Download PDF

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WO2020211415A1
WO2020211415A1 PCT/CN2019/126265 CN2019126265W WO2020211415A1 WO 2020211415 A1 WO2020211415 A1 WO 2020211415A1 CN 2019126265 W CN2019126265 W CN 2019126265W WO 2020211415 A1 WO2020211415 A1 WO 2020211415A1
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gate
electrode
semiconductor device
state
photosensitive device
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PCT/CN2019/126265
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English (en)
French (fr)
Inventor
刘清召
王国强
黄睿
王利忠
董水浪
卢鑫泓
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京东方科技集团股份有限公司
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Priority to US16/767,351 priority Critical patent/US11475833B2/en
Publication of WO2020211415A1 publication Critical patent/WO2020211415A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Definitions

  • This application generally relates to the field of display technology, and in particular to semiconductor devices (more specifically, dual-gate TFTs), pixel circuits and control methods thereof.
  • the display device combines image display and fingerprint recognition technology to form a display device with fingerprint recognition function.
  • the image display and fingerprint recognition in this display device both use independent thin film transistors (TFTs) as drive switches, which greatly reduces the pixel density and is not conducive to obtaining high-resolution display effects.
  • TFTs thin film transistors
  • an embodiment of the present application provides a dual-gate thin film transistor, which is disposed on a substrate, and the dual-gate thin film transistor further includes:
  • a first gate and a second gate provided on the substrate
  • the first electrode, the second electrode and the third electrode are arranged on the substrate.
  • the first electrode and the second electrode are electrically connected to the active layer through the first through hole and the second through hole respectively.
  • the third electrode is used for The device is electrically connected, wherein the third electrode and the first gate or the second gate are electrically connected through a third through hole; or, the third electrode and the active layer are electrically connected through a fourth through hole.
  • the present application provides a pixel circuit.
  • the pixel circuit includes the double-gate thin film transistor, photosensitive device, and organic light-emitting device as described in the first aspect, wherein the photosensitive device is indirectly electrically connected to the first gate or the second gate. ;
  • the double-gate thin film transistor is used to synchronously receive the first control signal via the first gate and the second gate, so that the double-gate thin film transistor works in the sub-threshold region;
  • the photosensitive device is used to simultaneously receive the second control signal while the double-gate thin film transistor receives the first control signal, so that the photosensitive device is in a reverse bias state;
  • the photosensitive device responds to the detected light signal and converts the light signal into a charge to bias the first gate, and make the double-gate thin film transistor generate under the bias
  • the first current value, the first current is used for fingerprint identification
  • the double-gate thin film transistor is used to synchronously receive the third control signal via the first gate and the second gate, so that the double-gate thin film transistor is in the on state to generate the second current value, and the second current value is used to drive the
  • the organic light emitting device performs pixel display.
  • the photosensitive device is also used for synchronously receiving a fourth control signal when the double-gate thin film transistor is in the on state, so that the photosensitive device is in a forward biased state.
  • the present application provides a pixel circuit.
  • the pixel circuit includes the double-gate thin film transistor, photosensitive device, and organic light emitting device as described in the first aspect, wherein the photosensitive device is indirectly electrically connected to the active layer;
  • the double-gate thin film transistor is used to synchronously receive the fifth control signal via the first gate and the second gate, so that the double-gate thin film transistor is in an off state;
  • the photosensitive device is used to receive the second control signal while the double-gate thin film transistor is in the off state, so that the photosensitive device is in a reverse bias state. At this time, the photosensitive device responds to the detected light signal and converts the light signal into a charge And accumulate charge;
  • the double-gate thin film transistor is also used to receive the third control signal via the first gate, and the second gate receives the fifth control signal, so that the double-gate thin film transistor is in the first partial conduction state to derive the charge as the third current value.
  • Three current values are used for fingerprint identification; or
  • the double-gate thin film transistor is used to synchronously receive the third control signal via the first gate and the second gate, so that the double-gate thin film transistor is in the on state to generate a fourth current value, which is used to drive the organic
  • the light-emitting device performs pixel display.
  • the photosensitive device is also used to synchronously receive the fourth control signal when the double-gate thin film transistor is in the first partial conduction state, so that the photosensitive device is in a forward bias state.
  • the double-gate transistor is also used to receive a fifth control signal via the first gate, and the second gate receives a third control signal, so that the double-gate thin film transistor is in the second partial conduction state to generate a fifth current value,
  • the fifth current value is used to drive the organic light emitting device for pixel display.
  • an embodiment of the present application also provides a pixel circuit control method.
  • the pixel circuit is as described in the second aspect, and the method includes:
  • the first gate and the second gate synchronously receive the first control signal, so that the double-gate thin film transistor works in the sub-threshold region;
  • the photosensitive device While receiving the first control signal, the photosensitive device synchronously receives the second control signal, so that the photosensitive device is in a reverse bias state;
  • the photosensitive device responds to the detected light signal and converts the light signal into a charge to bias the first gate, and make the double-gate thin film transistor generate under the bias
  • the first current value the first current value is used for fingerprint identification; or,
  • the first gate and the second gate synchronously receive the third control signal, so that the double-gate thin film transistor is turned on to generate a second current value, and the second current value is used to drive the organic light-emitting device for pixel display.
  • the method further includes:
  • the photosensitive device When the double-gate thin film transistor is in the on state, the photosensitive device synchronously receives the fourth control signal, so that the photosensitive device is in a forward bias state.
  • an embodiment of the present application also provides a pixel circuit control method.
  • the pixel circuit is as described in the third aspect, and the method includes:
  • the first gate and the second gate synchronously receive the fifth control signal, so that the double-gate thin film transistor is in the off state, and the photosensitive device receives the second control signal, so that the photosensitive device is in the reverse bias state. At this time, the photosensitive device responds to the detection The received optical signal, convert the optical signal into electric charge and accumulate the electric charge;
  • the first gate receives the third control signal, and the second gate receives the fifth control signal, so that the double-gate thin film transistor is in the first partial conduction state to derive the charge as the third current value, and the third current value is used for fingerprint identification; or,
  • the first gate and the second gate synchronously receive the third control signal, so that the double-gate thin film transistor is in an on state to generate a fourth current value, and the fourth current value is used to drive the organic light-emitting device for pixel display.
  • the method further includes: when the double-gate thin film transistor is in the first partial conduction state, the photosensitive device synchronously receives the fourth control signal, so that the photosensitive The device is in a forward biased state.
  • the double-gate thin film transistor provided by the embodiment of the application realizes that a double-gate thin film liquid crystal tube can be used as the switch of the photosensitive device and the organic light emitting device at the same time under different control signals, which greatly reduces the number of TFTs and helps to achieve high resolution .
  • the signal strength for fingerprint detection can also be enhanced.
  • a semiconductor device including: an active layer; a first insulating layer; a first gate and a second gate, which separate the first insulating layer and the organic A part of the source layer overlaps; a first electrode, a second electrode, and a third electrode, the first electrode and the second electrode are electrically connected to the first and second parts of the active layer, and the third electrode is used It is electrically connected to the photosensitive device, wherein the third electrode is electrically connected to the first gate or the second gate; or, the third electrode is electrically connected to the third part of the active layer .
  • the third electrode serves as an electrode of the photosensitive device.
  • the semiconductor device further includes a second insulating layer, wherein: the second insulating layer is disposed on the first, second, and third electrodes and the first and second gates Between, the first electrode and the second electrode pass through the first and second through holes of the first insulating layer and the second insulating layer, and the first and second parts of the active layer, respectively. Electrically connected; and the third electrode is electrically connected to the first gate or the second gate through a third through hole passing through the second insulating layer.
  • the semiconductor device further includes a second insulating layer, wherein: the second insulating layer is provided between the first, second, and third electrodes and the active layer, and the first An electrode and a second electrode are electrically connected to the first part and the second part of the active layer through first through holes and second through holes respectively passing through the first insulating layer and the second insulating layer; and The third electrode is electrically connected to the third portion of the active layer through a fourth through hole passing through the second insulating layer.
  • the first, second and third parts are different from each other.
  • a pixel circuit comprising the semiconductor device, the photosensitive device, and the light emitting device according to any embodiment, wherein the photosensitive device and the first gate Is electrically connected to one of the second gates, the light emitting device is connected to one of the first electrode and the second electrode; the semiconductor device is configured such that during the first period, the semiconductor device is Sub-threshold region; the photosensitive device is configured to: when the transistor in the semiconductor device is in the sub-threshold region, the photosensitive device is in a reverse biased state; when the photosensitive device is in a reverse biased state Next, the photosensitive device, in response to detecting the light signal, converts the light signal into electric charge so that the one of the first grid and the second grid is biased, and the The semiconductor device generates a first current under the action of the bias voltage.
  • the semiconductor device is configured such that during the second period, the semiconductor device is in a conductive state to generate a second current, and the second current is used to drive the light emitting device.
  • the photosensitive device is further configured such that when the semiconductor device is in a conductive state, the photosensitive device is in a forward biased state.
  • a pixel circuit including the semiconductor device, the photosensitive device, and the light emitting device according to any embodiment, wherein the photosensitive device is electrically connected to the active layer.
  • the light emitting device is connected to one of the first electrode and the second electrode; the semiconductor device is configured such that: during the third period, the semiconductor device is in an off state; the photosensitive The device is configured to: when the semiconductor device is in an off state, the photosensitive device is in a reverse-biased state to convert the optical signal into electric charge in response to detecting the optical signal; the semiconductor device is also configured
  • the method is: when the semiconductor device is in the first partial conduction state, the charge is derived as a third current.
  • the semiconductor device is further configured to: during the fourth period, when the semiconductor device is in a conducting state, generate a fourth current, and the fourth current is used to drive the light emission. Device.
  • the photosensitive device is further configured such that when the semiconductor device is in the first partial conduction state, the photosensitive device is in a forward biased state.
  • the semiconductor device is further configured to use a fifth current when the semiconductor device is in the second partial conduction state, and the fifth current is used to drive the light emitting device.
  • the pixel circuit is the pixel circuit according to any of the embodiments.
  • the method includes: passing the first gate and the second gate.
  • the electrode receives the first control signal, so that the semiconductor device works in the sub-threshold region; receives the second control signal through the photosensitive device, so that the photosensitive device is in the reverse-biased state; when the photosensitive device is in the reverse-biased state
  • the light signal is converted into an electric charge so that the one of the first grid and the second grid is biased, and the semiconductor The device generates a first current under the bias voltage.
  • the pixel circuit control method further includes: receiving a third control signal through the first gate and the second gate, so that the semiconductor device is in a conductive state to generate a second current , The second current is used to drive the light emitting device.
  • the pixel circuit control method further includes: when the semiconductor device is in a conductive state, receiving a fourth control signal through the photosensitive device, so that the photosensitive device is in a forward biased state.
  • a pixel circuit control method the pixel circuit is the pixel circuit according to any embodiment, the method includes: passing the first gate and the second gate Receiving a fifth control signal so that the semiconductor device is in a cut-off state; receiving a second control signal through the photosensitive device, so that the photosensitive device is in a reverse-biased state, to convert the optical signal in response to detecting the optical signal Receive a third control signal through the first gate, and receive a fifth control signal through the second gate, so that the semiconductor device is in the first partial conduction state to derive the charge as a third Current.
  • the pixel circuit control method further includes: receiving the third control signal through the first gate and the second gate, so that the semiconductor device is in a conductive state to generate a fourth current , The fourth current is used to drive the light emitting device.
  • the pixel circuit control method further includes: when the semiconductor device is in the first partial conduction state, receiving a fourth control signal through the photosensitive device, so that the photosensitive device is in a forward bias state .
  • FIG. 1 shows a schematic diagram of a pixel circuit provided by an embodiment of the present application
  • FIG. 2 shows a cross-sectional view of a dual gate thin film transistor provided by an embodiment of the present application
  • 3A shows a cross-sectional view of a dual-gate thin film transistor provided by another embodiment of the present application.
  • 3B shows a schematic diagram of a pixel circuit provided according to another embodiment of the present application.
  • FIG. 4 shows a schematic flowchart of a pixel circuit control method provided by an embodiment of the present application
  • FIG. 5 shows a schematic flowchart of a pixel circuit control method provided by another embodiment of the present application.
  • FIG. 6 shows an Id-Vg curve of a transistor according to some embodiments of the present disclosure
  • FIG. 7 shows a timing diagram of an exemplary operation of the transistor.
  • FIG. 1 shows a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • the pixel circuit may include a semiconductor device, such as a double-gate thin film transistor 101.
  • the pixel circuit may also include a photosensitive device 102 and an organic light emitting device 103.
  • the double-gate thin film transistor 101 includes a first electrode 101a, a second electrode 101b, a third electrode 101c, a first gate 101d, and a second gate 101e.
  • One end of the photosensitive device (such as a photodiode) 102 is electrically connected to the first gate 101d.
  • One end of the organic light emitting device (such as a light emitting diode) 103 is electrically connected to the first electrode 101a.
  • the double-gate thin film transistor 101 can drive the photosensitive device 102 to work, or drive the organic light-emitting device 103 to work, so as to realize the use of a double-gate thin film transistor 101, both as a switch for the photosensitive device 102 and as an organic light-emitting device.
  • the switch of the light emitting device 103 effectively saves the number of switches.
  • the photosensitive device 102 may also be electrically connected to the second gate 101e or the third electrode 101c.
  • the photosensitive device 102 may be a PIN photosensitive device, a PN photosensitive device or a Schottky type photosensitive device.
  • the photosensitive device 102 can be used for fingerprint recognition.
  • a finger approaches or touches the light-emitting surface of the display device, the light emitted by the display device is reflected back into the display device, and the light reflected by the fingerprint area can be received by the photosensitive device, and the light signal is converted into electric charge by the photosensitive device, and the data is read Read it out.
  • a finger includes a fingerprint valley and a fingerprint ridge; the current value generated by the corresponding reflected light in the photosensitive device is different, so that the purpose of fingerprint identification can be achieved by identifying the current value.
  • the organic light emitting device 103 may have the following structure.
  • a layer of transparent ITO (Indium Tin Oxide) anode Above the glass substrate is a layer of transparent ITO (Indium Tin Oxide) anode.
  • a thin layer of copper phthalocyanine dye can be plated on the ITO anode, which can passivate the surface of the ITO to increase its stability.
  • On the ITO anode is a layer of P-type and N-type organic semiconductor material, and on the layer of P-type and N-type organic semiconductor material is a cathode, for example, a magnesium-silver alloy cathode. This layer of metal cathode also plays a role in reflecting light. These coatings can be vapor-deposited on the glass substrate, so the thickness is very thin.
  • the organic light-emitting material can emit very bright light, which is emitted from the glass substrate, that is, downward.
  • the glass substrate can also be replaced by a flexible plastic substrate that is bendable. It should be understood that the light-emitting device 103 is not limited to the embodiment shown here, but various light-emitting devices known in the art or developed in the future may be used.
  • the circuit can also use the bias voltage generated by the photosensitive device to affect the gate voltage, so that the photosensitive device can detect the light signal through the drain output current of the double-gate thin film transistor, thereby increasing the signal strength.
  • FIG. 2 shows a cross-sectional view of a dual-gate thin film transistor 101 provided by some embodiments of the present application.
  • the double-gate thin film transistor 101 may be provided on the substrate 11.
  • the double-gate thin film transistor 101 may include an active layer 12, a first gate 101d and a second gate 101e, and a first electrode 101a, a second electrode 101b, and a third electrode 101c.
  • the active layer 12 is provided on the substrate 11.
  • the first electrode 101a and the second electrode 101b are electrically connected to the active layer 12 through the first through hole 13 and the second through hole 14, respectively.
  • the third electrode 101c and the photosensitive device 102 are electrically connected.
  • the third electrode 101c is also electrically connected to the first gate 101d or the second gate 101e through the third through hole 15.
  • the first electrode 101a is also electrically connected to the organic light emitting device 103 through the fourth through hole 16.
  • the double-gate thin film transistor 101 may further include a gate insulating layer 17.
  • the gate insulating layer (or at least a part thereof) is provided between the gate and the active layer.
  • the gate insulating layer 17 may be located above or below the active layer 12. In the embodiment shown in FIG. 2, the gate insulating layer 17 covers the active layer 12 and also covers a part of the surface of the substrate 17.
  • the double-gate thin film transistor 101 may further include a protective layer 18.
  • the protective layer 18 may be located above the layer where the first gate 101d and the second gate 101e are located or immediately above the active layer 12.
  • the protective layer 18 is provided on the gate insulating layer 17, and covers the first and second gates 101d and 101e.
  • the third electrode 101c is electrically connected to the gate 101d by passing through the protective layer 18 (not shown with reference numerals).
  • the first electrode 101a and the second electrode 101b are electrically connected to a part of the active layer 12 through vias 13 and 14 passing through the protective layer 18 and the gate insulating layer 107, respectively.
  • FIG. 2 also schematically shows an example of the photosensitive device 102.
  • the photosensitive device 102 may be, for example, a photosensitive diode.
  • the third electrode 101c may be connected to one end of the photosensitive device 102.
  • the third electrode 101c may also be used as an electrode of the photosensitive device 102, for example, a cathode electrode or an anode electrode of a photosensitive diode.
  • the other end (or another electrode) of the photosensitive device 102 may be connected to other devices, wiring, or circuits (not shown in the figure).
  • FIG. 2 also schematically shows an example of the light emitting device 103.
  • the first electrode 101a is electrically connected to the light emitting device 103 through the through hole 16.
  • FIG. 3A shows a cross-sectional view of a dual-gate thin film transistor 101 provided by another embodiment of the present application
  • FIG. 3B shows a schematic diagram of a pixel circuit according to this embodiment.
  • the double-gate thin film transistor 101 is disposed on the substrate 11.
  • the double-gate thin film transistor 101 may include an active layer 12, a first gate 101d and a second gate 101e, a first electrode 101a, a second electrode 101b, and a third electrode 101c.
  • the first gate 101d and the second gate 101e are arranged on the substrate; the active layer 12 is arranged above the first gate and the second gate; the first electrode 101a, the second electrode 101b And the third electrode 101c is disposed above the active layer.
  • the first electrode 101a, the second electrode 101b, and the third electrode 101c are electrically connected to the active layer 12 through the fifth through hole 21, the sixth through hole 22, and the seventh through hole 23, respectively.
  • the third electrode 101c is electrically connected to the photosensitive device 102.
  • the first electrode 101a is also electrically connected to the organic light emitting device 103 through the eighth through hole 24.
  • the double-gate thin film transistor 101 may further include a gate insulating layer 17. At least a part of the gate insulating layer 17 is provided between the first and second gates and the active layer 12. According to different embodiments, the gate insulating layer 17 may be located above or below the active layer 12. In the embodiment shown in FIG. 3A, the gate insulating layer 17 covers the first gate 101d and the second gate 101e, and also covers a part of the surface of the substrate 11.
  • the double-gate thin film transistor 101 may further include a protective layer 18.
  • the protective layer 18 may be located above or immediately above the active layer 12 where the first gate 101d and the second gate 101e are located.
  • the protective layer 18 may include one or more insulating materials. In the embodiment shown in FIG. 3A, the protective layer 18 includes two layers of dielectric materials and is formed on the active layer 12 and the gate insulating layer 17.
  • the above-mentioned double-gate thin film transistor 101 can also be adaptively modified based on the bottom gate and the top gate. For example, on the basis of FIG. 3A, it is achieved by extending a through hole or another through hole (not shown), so that the photosensitive device is electrically connected to the first gate or the second gate. Or, based on FIG. 2, for example, by changing the position of the through hole, the photosensitive device is connected to the active layer.
  • a manufacturing method of the dual gate thin film transistor 101 shown in FIG. 2 is also opened.
  • the method may include the steps described below.
  • the buffer layer may be composed of a SiN/SiO2 stack, for example, the thickness of SiN is 50-150 nm, and the thickness of SiO2 is 100-400 nm.
  • the active layer 12 is formed on the buffer layer 201.
  • the active layer 12 can be a-Si (amorphous silicon) or p-Si (polysilicon, for example, can be crystallized from a-Si to p-Si), or an oxide semiconductor active layer, for example, Indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), etc.
  • IGZO Indium gallium zinc oxide
  • IZO indium zinc oxide
  • the active layer 12 may be in an amorphous state, a quasi-crystalline state, or a crystalline state.
  • Conduction treatment can be performed on the area of the active layer 12 that is in contact with the drain and source and the first and second gates, for example, through processes such as doping, plasma treatment, and atmosphere annealing to increase current carrying To ensure that this part of the active layer and the corresponding electrode achieve ohmic contact.
  • a gate insulating (GI) layer 17 and a gate layer are formed on the active layer 12.
  • the GI layer may include SiO2 or a SiN/SiO2 stack with a thickness of 80-150 nm; the gate layer may be a metal with a thickness of 200-400 nm, such as Mo. It should be understood that the materials and values shown here and in the context are only exemplary, and the present disclosure is not limited thereto.
  • a protective layer 18 and a source-drain (SD) layer are formed.
  • the protective layer is a SiO2 layer or a SiN/SiO2 stack, and the thickness can be 80-150 nm; the SD layer can be formed of a metal of 200-400 nm, such as Mo.
  • the purpose of sharing the TFT SD layer and the PIN lower electrode layer can be achieved at the same time.
  • the source electrode and the drain electrode of the TFT and the lower electrode (in this embodiment, the third electrode 101c) for the photosensitive device (for example, a PIN diode) 102 can be prepared at the same time.
  • the source electrode and the drain electrode of the TFT and the lower electrode used for the photosensitive device (for example, a PIN diode) 102 may be made of the same material through the same process.
  • the PIN diode may include: an ITO layer, a P+ type a-Si layer, an a-Si layer, and an N+ type a-Si layer.
  • the third electrode 101c can be used as the lower electrode for the PIN diode.
  • some layers of PIN may be formed by PECVD. When necessary, the introduction of impurities in certain layers can be formed by an in-situ doping process or an additional doping process.
  • the P+a-Si layer may be, for example, 10-20 nm
  • the a-Si layer may be 500-1000 nm
  • the N+a-Si layer may be 10-50 nm.
  • the ITO layer can be used as a PIN window layer.
  • the ITO layer can function as a hard mask during the PIN patterning process.
  • the thickness of the ITO layer may be between 50 nm and 130 nm.
  • a flat layer PLN is prepared.
  • the thickness of the flat layer PLN may be slightly larger than the PIN, for example, between 1.2 and 3 ⁇ m.
  • a cover layer may also be formed at the sidewall of the PIN functional layer to protect the PIN sidewall.
  • the material of the covering layer can be SiO, SiN, etc., and its thickness can be about 50-150 nm.
  • FIG. 3A shows the manufacturing process of the double-gate thin film transistor 101, in which the photosensitive device is a light-emitting diode PIN tube as an example.
  • the process can include the steps described below.
  • a gate layer is formed on a glass substrate or a flexible substrate, such as a metal Mo layer of 200-400 nm as the gate layer.
  • a gate insulating layer GI is formed on the gate layer.
  • the layer may be composed of, for example, a SiN/SiO2 stack, where the thickness of SiN may be 50-150 nm, and the thickness of SiO2 may be 100-400 nm.
  • the active layer 12 is formed on the gate insulating layer GI.
  • the active layer may be a-Si or p-Si, such as p-Si crystallized from a-Si; or may also be an oxide active layer, such as indium gallium zinc oxide IGZO, indium Zinc oxide IZO etc.
  • the active layer 12 may be in an amorphous state, a quasi-crystalline state, or a crystalline state.
  • the portions of the active layer 12 that are in contact with the source S, the drain Dd, and the drain source Ds can be subjected to a conductive treatment, for example, the carrier concentration can be increased through processes such as doping, plasma treatment, and atmosphere annealing, to Ensure that this part of the active layer and the corresponding electrode achieve ohmic contact.
  • a first protective layer PVX1 and a source-drain (SD) layer are formed on the active layer 12.
  • the protective layer can be SiO2 or SiN/SiO2 laminated layer, and the thickness can be 80-150 nm.
  • the SD layer can be a 200-400nm metal, such as Mo.
  • the source electrode S and the drain electrode Dd serve as electrodes for controlling the switch of the pixel display function.
  • PVX2 can be a SiO2 layer or a SiN/SiO2 stack, and its thickness can be 80-150 nm.
  • Ds can be 200-400nm metal, such as Mo.
  • the source S and the drain Ds serve as electrodes for controlling the switching of the photosensitive device. In some embodiments, Ds can also be used as the lower electrode of the PIN tube.
  • the PIN tube or its required layers can be formed.
  • Some layers of PIN can be formed by PECVD.
  • the introduction of impurities in certain layers can be formed by an in-situ doping process or an additional doping process.
  • the P+a-Si layer may be, for example, 10-20 nm
  • the a-Si layer may be 500-1000 nm
  • the N+a-Si layer may be 10-50 nm.
  • the ITO layer can be used as a PIN window layer.
  • the ITO layer can act as a hard mask during the PIN patterning process.
  • the thickness of the ITO layer may be between 50 nm and 130 nm.
  • the thickness of the flat layer may be slightly larger than the PIN, for example, it may be between 1.2 and 3 ⁇ m.
  • FIG. 4 shows a schematic flowchart of a pixel circuit control method provided by an embodiment of the present application.
  • the double-gate thin film transistor 101 can be controlled to switch between controlling the photosensitive device 102 and controlling the organic light-emitting device 103.
  • the method may include some or all of the following steps.
  • the pixel circuit control method can be exemplarily divided into the following stages.
  • the dual-gate TFT is turned on to empty the charge.
  • the dual-gate TFT is in the sub-threshold region (SS region).
  • the photosensitive device such as a PIN tube
  • a light emitting device such as a light emitting diode
  • the pixel circuit control method may include one or more of the above stages.
  • the double-gate thin film crystal 101 is placed in a conducting state, so that the photosensitive device 102 receives the fourth control signal.
  • the fourth control signal may cause the photosensitive device to be in a forward-biased state.
  • the photosensitive device 102 when the double-gate thin film crystal 101 is in the on state, the photosensitive device 102 synchronously receives the fourth control signal, so that the photosensitive device is in a forward-biased state, so that the charge of the PIN tube in the forward-biased state is cleared .
  • the first gate and the second gate can receive the third control signal synchronously, so that the double-gate thin film transistor is in a conducting state.
  • the third control signal may be the first high level, for example +2V.
  • the fourth control signal may be a second high level, for example +5V.
  • the third control signal may be a control signal received synchronously by the first gate and the second gate.
  • the first gate 101d and the second gate 101e of the double-gate thin film transistor 101 receive the first control signal synchronously, so that the double-gate thin film transistor operates in the sub-threshold region.
  • the photosensitive device 102 can simultaneously receive the second control signal while the double-gate thin film transistor 101 receives the first control signal, so that the photosensitive device is in a reverse bias state.
  • the dual-gate TFT is in the sub-threshold region.
  • the PIN light signal can have a sufficiently large influence on the Id, which can increase the signal strength and simplify the circuit structure.
  • the first control signal may be a 0V voltage.
  • the second control signal may be -5V.
  • the first control signal may be a control signal received synchronously by the first gate and the second gate.
  • Step 403 During the time period when the photosensitive device is in the reverse bias state, the photosensitive device responds to the detected light signal and converts the light signal into electric charge to bias the first gate, and make the double-gate thin film transistor in the bias voltage
  • the first current value is generated under the action, and the first current value is used for fingerprint identification.
  • the PIN tube is used to realize fingerprint detection.
  • the double-gate thin film transistor 101 operates in the sub-threshold region.
  • the photosensitive device 102 is controlled by the -5V voltage signal to be in the reverse-biased state.
  • the reverse-biased state if a finger is pressed on the display device, the light from the finger is reflected on the photosensitive device.
  • the texture of the finger affects the light.
  • the degree of reflection is different, so that the bias value generated by the accumulated charge of the photosensitive device in the reverse bias state is different, and under the influence of the bias value, the voltage of the first gate 101d connected to the double-gate thin film transistor and the photosensitive device exhibits a negative value According to the amount of charge, the generated negative voltage value is different.
  • the first current value is output at the first electrode 101a, and the current value can be used for fingerprint detection.
  • step 404 the third control signal is synchronously received via the first gate and the second gate, so that the double-gate thin film transistor is turned on to generate a second current value.
  • the second current value can be used to drive the organic light emitting device for pixel display.
  • the third control signal may be +2V.
  • this stage ie, the fourth stage
  • pixel display is performed. With the circuit structure shown in FIG.
  • the double-gate thin film transistor 101 when the first gate 101d and the second gate 101e synchronously receive a voltage control signal of +2V, the double-gate thin film transistor 101 is turned on, and the image signal can be input through the second electrode 101b
  • the second current value used to drive the organic light-emitting device 103 for pixel display can be output through the first electrode 101a, so as to realize the display function.
  • Fig. 5 shows a schematic flowchart of a pixel circuit control method provided by another embodiment of the present application.
  • the pixel circuit can be as shown in FIG. 3A.
  • the double-gate thin film transistor 101 is controlled to switch between the photosensitive device 102 and the organic light-emitting device 103.
  • step 501 when the double-gate thin film transistor is in the first partial conduction state, the photosensitive device synchronously receives the fourth control signal, so that the photosensitive device is in a forward bias state.
  • the double-gate thin film transistor 101 can receive the third control signal through the first gate, and the fifth control signal through the second gate.
  • the third control signal may be a +2V voltage
  • the fourth control signal may be a +5V voltage
  • the fifth control signal may be a -2V voltage.
  • the dual-gate TFT is turned on to empty the charge.
  • the first part of the conduction state can be understood as the partial conduction of the double-gate thin film transistor. For example, taking the circuit structure shown in FIG.
  • the second gate 101e receives -2V voltage, Then, under the control of the electric field of the first gate, a channel can be formed between the first electrode 101a and the third electrode 101c, so that the charge of the PIN tube in the forward bias is removed.
  • the second part of the dual-gate TFT controlled by the second gate 101e is turned off.
  • the first part and the second part can be interchanged, as long as they work according to the principles taught in the present application.
  • the first gate 101d may receive a voltage of -2V and the second gate 101e may receive a voltage of +2V; in this case, the second gate 101e, the second electrode 101b, and the third electrode 101c may also be defined As the first part, the part defined by the first gate 101d, the first electrode 101a, and the third electrode 101c is used as the second part.
  • step 502 the first gate and the second gate synchronously receive the fifth control signal, so that the double-gate thin film transistor is in an off state.
  • the dual-gate TFT switch is turned off.
  • Step 503 while the double-gate thin film transistor is in the off state, the photosensitive device receives the second control signal, so that the photosensitive device is in a reverse bias state. At this time, the photosensitive device responds to the detected light signal to convert the light signal into charge and accumulate it Charge.
  • the first gate receives the third control signal, and the second gate receives the fifth control signal, so that the double-gate thin film transistor is in the first partial conduction state to derive the charge as the third current value.
  • the third current value can be used for fingerprint recognition.
  • the first gate 101d receives a +2V voltage
  • a channel is formed between the first electrode 101a and the third electrode 101c, and the charge accumulated by the PIN is exported to the first electrode 101a
  • the first electrode 101a outputs the third current value for fingerprint identification.
  • Steps 503 and 504 are the third stage, in which the PIN tube is used to realize fingerprint detection. Similarly, the first part and the second part are not restricted.
  • the part defined by the second gate 101e, the second electrode 101b, and the third electrode 101c may be used as the first part, and the first gate The portion defined by 101d, the first electrode 101a, and the third electrode 101c serves as the second portion.
  • step 505 the first gate and the second gate synchronously receive the third control signal, so that the double-gate thin film transistor is turned on to generate a fourth current value.
  • the fourth current value can be used to drive the organic light emitting device for pixel display.
  • pixel display is performed. Taking the circuit structure shown in FIG. 3A as an example, when the first gate 101d and the second electrode 101e receive a voltage of +2V, a channel is formed between the first electrode 101a and the second electrode 101b, and the image signal passes through the second electrode. 101b is input, and the fourth current value output by the first electrode 101a is used to drive the organic light emitting device for pixel display.
  • the fourth stage it is also possible to control the pixel display by receiving the control signal only at the second gate, so that the first gate, the first electrode and the third electrode are used as single gate TFTs.
  • FIG. 6 shows an Id-Vg curve of a transistor according to some embodiments of the present disclosure
  • FIG. 7 shows a timing diagram of an exemplary operation of the transistor.
  • the transistor may be a double-gate transistor according to any of the above-mentioned embodiments of the present disclosure.
  • a first voltage for example, 2V
  • the first gate for example, 101 and the second gate
  • a voltage for example, 5V
  • a second voltage for example, 0.2V
  • a third voltage for example, 0V
  • a voltage for example, -5V
  • the TFT when there is no light, the TFT can be considered unaffected, and Id is the current under the corresponding gate voltage in the SS region.
  • Ion the turn-on current
  • Ioff the turn-off current
  • the left side of the vertical line shown is the sensor sensing work area, and the right side is the display work area.
  • a voltage for example, a voltage of 2V
  • the gate voltage change caused by the voltage difference (about 0.1V) caused by the PIN has a negligible effect on Id.
  • the open area of TFT such as the change from 2V to 1.9V
  • the Id will not change correspondingly because it is in the saturation area.
  • the PIN will not affect the display effect.
  • one TFT can be used to control display and sensing respectively.

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Abstract

一种半导体装置、像素电路及其控制方法，所述半导体装置包括：有源层（12）；第一绝缘层；第一栅极（101d）和第二栅极（101e），其分别隔着所述第一绝缘层与所述有源层（12）的一部分重叠；第一电极（101a）、第二电极（101b）和第三电极（101c），所述第一电极（101a）和第二电极（101b）分别与所述有源层（12）的第一和第二部分电连接，所述第三电极（101c）用于与光敏器件（102）电连接，其中，所述第三电极（101c）与所述第一栅极（101d）或所述第二栅极（101e）电连接；或者，所述第三电极（101c）与所述有源层（12）的第三部分电连接。

Description

半导体装置、像素电路及其控制方法
相关申请的交叉引用
本申请要求于2019年4月17日提交的中国申请No.201910310959.8的优先权，并通过引用将其全部内容并入在此。
技术领域
本申请一般涉及显示技术领域，尤其涉及半导体装置(更具体地，双栅TFT)、像素电路及其控制方法。
背景技术
随着显示技术的发展，显示装置的显示效果越来越好。但人们对显示装置的要求也随之提高，不仅局限于显示效果，还要求显示其具有多样化的功能。
例如显示装置将图像显示和指纹识别技术结合起来，形成具有指纹识别功能的显示装置。但是这种显示装置中图像显示和指纹识别都是通过独立的薄膜晶体管TFT(Thin Film Transistor)，作为驱动开关，这样导致像素密度被大大地降低了，也不利于获得高分辨率的显示效果。
发明内容
第一方面，本申请实施例提供了一种双栅薄膜晶体管，其设置在衬底上，该双栅薄膜晶体管还包括：
设置在衬底上的有源层；
设置在衬底上的第一栅极和第二栅极；
设置在衬底上的第一电极、第二电极和第三电极，第一电极和第二电极分别通过第一通孔和第二通孔与有源层电连接，第三电极用于与光敏器件电连接，其中，第三电极与所述第一栅极或第二栅极通过第三通孔电连接；或者，第三电极与有源层通过第四通孔电连接。
第二方面，本申请提供了一种像素电路，像素电路包括如第一方面描述的双栅薄膜晶体管、光敏器件、有机发光器件，其中光敏器件间接与第一栅极或第二栅极电连 接；
双栅薄膜晶体管用于经第一栅极和第二栅极同步接收第一控制信号，使得双栅薄膜晶体管工作在亚阈值区域；
光敏器件用于在双栅薄膜晶体管接收第一控制信号的同时，同步接收第二控制信号，使得光敏器件处于反偏状态；
在光敏器件处于反偏状态的时间周期内，光敏器件响应于检测到的光信号，将光信号转换成电荷以使得第一栅极产生偏压，并使得双栅薄膜晶体管在偏压作用下产生第一电流值，第一电流用于指纹识别；
或者，双栅薄膜晶体管用于经第一栅极和第二栅极同步接收第三控制信号，使得双栅薄膜晶体管处于导通状态，以产生第二电流值，第二电流值用于驱动所述有机发光器件进行像素显示。
进一步地，光敏器件还用于在所述双栅薄膜晶体管处于导通状态时，同步接收第四控制信号以使得所述光敏器件处于正偏状态。
第三方面，本申请提供了一种像素电路，像素电路包括如第一方面描述的双栅薄膜晶体管、光敏器件、有机发光器件，其中光敏器件间接与有源层电连接；
双栅薄膜晶体管用于经第一栅极和第二栅极同步接收第五控制信号，使得双栅薄膜晶体管处于截止状态；
光敏器件用于在双栅薄膜晶体管处于截止状态的同时，光敏器件接收第二控制信号，使得光敏器件处于反偏状态，此时，光敏器件响应于检测到的光信号，将光信号转换成电荷并积累电荷；
双栅薄膜晶体管还用于经第一栅极接收第三控制信号，第二栅极接收第五控制信号，使得双栅薄膜晶体管处于第一部分导通状态，以导出电荷作为第三电流值，第三电流值用于指纹识别；或者
双栅薄膜晶体管用于经第一栅极和第二栅极同步接收第三控制信号，使得双栅薄膜晶体管处于导通状态，以产生第四电流值，第四电流值用于驱动所述有机发光器件进行像素显示。
进一步地，光敏器件还用于在双栅薄膜晶体管处于第一部分导通状态时，同步接收第四控制信号，使得光敏器件处于正偏状态。
进一步地，双栅晶体管还用于经第一栅极接收第五控制信号，第二栅极接收第三 控制信号，使得双栅薄膜晶体管处于第二部分导通状态，以产生第五电流值，第五电流值用于驱动有机发光器件进行像素显示。
第四方面，本申请实施例还提供了一种像素电路控制方法，像素电路如第二方面描述，则该方法包括：
第一栅极和第二栅极同步接收第一控制信号，使得双栅薄膜晶体管工作在亚阈值区域；
在接收第一控制信号的同时，光敏器件同步接收第二控制信号，使得光敏器件处于反偏状态；
在光敏器件处于反偏状态的时间周期内，光敏器件响应于检测到的光信号，将光信号转换成电荷以使得第一栅极产生偏压，并使得双栅薄膜晶体管在偏压作用下产生第一电流值，第一电流值用于指纹识别；或者，
第一栅极和第二栅极同步接收第三控制信号，使得双栅薄膜晶体管处于导通状态，以产生第二电流值，第二电流值用于驱动有机发光器件进行像素显示。
进一步地，在第一栅极和第二栅极同步接收第一控制信号之前，该方法还包括：
在双栅薄膜晶体管处于导通状态时，光敏器件同步接收第四控制信号，使得光敏器件处于正偏状态。
第五方面，本申请实施例还提供了一种像素电路控制方法，像素电路如第三方面描述的，则该方法包括：
第一栅极和第二栅极同步接收第五控制信号，使得双栅薄膜晶体管处于截止状态，同时光敏器件接收第二控制信号，使得光敏器件处于反偏状态，此时，光敏器件响应于检测到的光信号，将所述光信号转换成电荷并积累所述电荷；
第一栅极接收第三控制信号，第二栅极接收第五控制信号，使得双栅薄膜晶体管处于第一部分导通状态，以导出电荷作为第三电流值，第三电流值用于指纹识别；或者，
第一栅极和第二栅极同步接收第三控制信号，使得双栅薄膜晶体管处于导通状态，以产生第四电流值，第四电流值用于驱动有机发光器件进行像素显示。
进一步地，在第一栅极和第二栅极同步接收第五控制信号之前，该方法还包括：在双栅薄膜晶体管处于第一部分导通状态时，光敏器件同步接收第四控制信号，使得光敏器件处于正偏状态。
本申请实施例提供的双栅薄膜晶体管在不同的控制信号驱动下，实现一个双栅薄 膜液晶管同时作为光敏器件和有机放光器件的开关，大大减少了TFT数量，有助于实现高分辨率。
进一步地，通过光敏器件与双栅薄膜液晶管的其中一个栅极连接，还可以增强用于指纹检测的信号强度。
根据本公开的一个方面，还提供了一种半导体装置，包括：有源层；第一绝缘层；第一栅极和第二栅极，其分别隔着所述第一绝缘层与所述有源层的一部分重叠；第一电极、第二电极和第三电极，所述第一电极和第二电极分别与所述有源层的第一和第二部分电连接，所述第三电极用于与光敏器件电连接，其中，所述第三电极与所述第一栅极或所述第二栅极电连接；或者，所述第三电极与所述有源层的第三部分电连接。
在一些实施例中，所述第三电极作为所述光敏器件的一个电极。
在一些实施例中，所述半导体装置还包括第二绝缘层，其中：所述第二绝缘层设置在所述第一、第二和第三电极与所述第一栅极和第二栅极之间，所述第一电极和第二电极分别通过穿过所述第一绝缘层和第二绝缘层的第一通孔和第二通孔与所述有源层的第一部分和第二部分电连接；以及所述第三电极通过穿过所述第二绝缘层的第三通孔与所述第一栅极或所述第二栅极电连接。
在一些实施例中，所述半导体装置还包括第二绝缘层，其中：所述第二绝缘层设置在所述第一、第二和第三电极与所述有源层之间，所述第一电极和第二电极分别通过穿过所述第一绝缘层和所述第二绝缘层的第一通孔和第二通孔与所述有源层的第一部分和第二部分电连接；以及所述第三电极通过穿过所述第二绝缘层的第四通孔与所述有源层的第三部分电连接。
在一些实施例中，所述第一、第二和第三部分彼此不同。
根据本公开的一个方面，还提供了一种像素电路，所述像素电路包括如任意实施例所述的半导体装置、所述光敏器件、发光器件，其中所述光敏器件与所述第一栅极和第二栅极中的一个电连接，所述发光器件连接到所述第一电极和第二电极中的一个；所述半导体装置被配置为：在第一周期期间，所述半导体装置处在亚阈值区域；所述光敏器件被配置为：用于在所述半导体装置中的晶体管处于亚阈值区域的情况下，所述光敏器件处于反偏状态；在所述光敏器件处于反偏状态的情况下，所述光敏器件响应于检测到光信号，将所述光信号转换成电荷以使得所述第一栅极和所述第二栅极中的所述的一个产生偏压，并使得所述半导体装置在所述偏压作用下产生第一电流。
在一些实施例中，所述半导体装置被配置为：在第二周期期间，所述半导体装置处于导通状态，以产生第二电流，所述第二电流用于驱动所述发光器件。
在一些实施例中，所述光敏器件还被配置为：在所述半导体装置处于导通状态的情况下，所述光敏器件处于正偏状态。
根据本公开的一个方面，还提供了一种像素电路，所述像素电路包括根据任意实施例所述的半导体装置、所述光敏器件、发光器件，其中所述光敏器件与所述有源层电的第三部分连接，所述发光器件连接到所述第一电极和第二电极中的一个；所述半导体装置被配置为：在第三周期期间，所述半导体装置处于截止状态；所述光敏器件被配置为：在所述半导体装置处于截止状态的情况下，所述光敏器件处于反偏状态，以响应于检测到光信号，将所述光信号转换成电荷；所述半导体装置还被配置为：在所述半导体装置处于第一部分导通状态，导出所述电荷作为第三电流。
在一些实施例中，所述半导体装置还被配置为：在第四周期期间，在所述半导体装置处于导通状态的情况下，产生第四电流，所述第四电流用于驱动所述发光器件。
在一些实施例中，所述光敏器件还被配置为：在所述半导体装置处于所述第一部分导通状态的情况下，所述光敏器件处于正偏状态。
在一些实施例中，所述半导体装置还被配置为：在所述半导体装置处于第二部分导通状态，以第五电流，所述第五电流用于驱动所述发光器件。
根据本公开的一个方面，还提供了一种像素电路的控制方法，所述像素电路是如任意实施例所述的像素电路，该方法包括：通过所述第一栅极和所述第二栅极接收第一控制信号，使得所述半导体装置工作在亚阈值区域；通过所述光敏器件接收第二控制信号，使得所述光敏器件处于反偏状态；在所述光敏器件处于反偏状态的情况下，通过所述光敏器件响应于检测到的光信号，将光信号转换成电荷以使得所述第一栅极和所述第二栅极中所述的一个产生偏压，并使得所述半导体装置在所述偏压作用下产生第一电流。
在一些实施例中，所述像素电路控制方法还包括：通过所述第一栅极和所述第二栅极接收第三控制信号，使得所述半导体装置处于导通状态，以产生第二电流，所述第二电流用于驱动所述发光器件。
在一些实施例中，所述像素电路控制方法还包括：在所述半导体装置处于导通状态时，通过所述光敏器件接收第四控制信号，使得所述光敏器件处于正偏状态。
根据本公开的一个方面，还提供了一种像素电路控制方法，所述像素电路是如任 意实施例所述的像素电路，该方法包括：通过所述第一栅极和所述第二栅极接收第五控制信号，使得所述半导体装置处于截止状态；通过所述光敏器件接收第二控制信号，使得所述光敏器件处于反偏状态，以响应于检测到光信号，将所述光信号转换成电荷；通过所述第一栅极接收第三控制信号，并通过所述第二栅极接收第五控制信号，使得所述半导体装置处于第一部分导通状态，以导出所述电荷作为第三电流。
在一些实施例中，所述像素电路控制方法还包括：通过所述第一栅极和第二栅极接收所述第三控制信号，使得所述半导体装置处于导通状态，以产生第四电流，所述第四电流用于驱动所述发光器件。
在一些实施例中，所述像素电路控制方法还包括：在所述半导体装置处于第一部分导通状态的情况下，通过所述光敏器件接收第四控制信号，使得所述光敏器件处于正偏状态。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本申请的其它特征、目的和优点将会变得更明显：
图1示出了本申请实施例提供像素电路的示意性图；
图2示出了本申请实施例提供的双栅薄膜晶体管的截面示图；
图3A示出了本申请又一实施例提供的双栅薄膜晶体管的截面示图；
图3B示出了根据本申请又一实施例提供的像素电路的示意图；
图4示出了本申请实施例提供的像素电路控制方法的流程示意图；
图5示出了本申请又一实施例提供的像素电路控制方法的流程示意图；
图6示出了根据本公开一些实施例的晶体管的Id-Vg曲线，图7示出了该晶体管的示例性操作的时序图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关公开，而非对该公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与公开相关的部分。
需要说明的是，在适合的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
请参考图1，图1示出了本申请实施例提供像素电路的示意性结构图。
如图1所示，像素电路可以包括一种半导体装置，例如双栅薄膜晶体管101。像素电路还可以包括光敏器件102和有机发光器件103。
双栅薄膜晶体管101包括第一电极101a、第二电极101b、第三电极101c、第一栅极101d和第二栅极101e。
光敏器件(诸如光电二极管)102的一端与第一栅极101d电连接。
有机发光器件(诸如发光二极管)103的一端与第一电极101a电连接。
双栅薄膜晶体管101在不同控制信号下，可以驱动光敏器件102工作，或者驱动有机发光器件103工作，从而实现利用一个双栅薄膜晶体管101，既作为用于光敏器件102的开关又作为用于有机发光器件103的开关，有效地节省了开关的数量。在某些实施例中，光敏器件102还可以与第二栅极101e或第三电极101c电连接。
光敏器件102可以是PIN光敏器件、PN光敏器件或者肖特基型光敏器件。光敏器件102可以用于指纹识别。当有手指靠近或接触显示装置的发光面，显示装置发出的光被反射回显示装置内，可以通过光敏器件接收指纹区域反射回的光，经光敏器件将光信号转换成电荷，被数据读取线读取出来。例如，手指包括指纹谷和指纹脊；与之对应的反射光在光敏器件中产生的电流值大小不同，从而可以通过识别电流值的大小来实现指纹识别的目的。
在一些实施例中，作为示例有机发光器件103可以具有如下的结构。玻璃基板上面是一层透明的ITO(氧化铟锡)阳极。可以在ITO阳极上镀一薄层铜酞菁染料，它能使ITO的表面钝化，以增加其稳定性。在ITO阳极上是P型和N型有机半导体材料层，在P型和N型有机半导体材料层上是阴极，例如，镁银合金阴极。这一层金属阴极也起到反光的作用。这些涂层都可以是蒸镀到玻璃基板上的，因此厚度非常薄。在电极两端加上5V～10V的电压，有机发光材料就可以发出相当明亮的光，光是从玻璃基板、也就是向下发出的。所述玻璃基板也可以用可弯曲的柔性塑料基板代替。应理解，发光器件103并不限于这里所示的实施例，而是可以采用本领域已知的或未来开发的各种发光器件。
通过光敏器件102与双栅薄膜晶体管101的栅极电连接，不仅可以实现1个TFT同时控制光敏器件102用于指纹识别，还可以控制有机发光器件103实现像素显示。进一步地，该电路还可以利用光敏器件感光后产生的偏压对栅极电压形成影响，使得光敏器件将光信号可以通过双栅薄膜晶体管的漏极输出电流来实现检测，从而提高了 信号强度。
图2示出了本申请一些实施例提供的双栅薄膜晶体管101的截面示图。
双栅薄膜晶体管101可以设置在衬底11上。双栅薄膜晶体管101可以包括：有源层12，第一栅极101d和第二栅极101e，以及第一电极101a、第二电极101b和第三电极101c。
有源层12设置在衬底11上。
第一电极101a和第二电极101b分别通过第一通孔13和第二通孔14与有源层12电连接。第三电极101c和光敏器件102电连接。第三电极101c还与第一栅极101d或第二栅极101e通过第三通孔15电连接。第一电极101a还与有机发光器件103通过第四通孔16电连接。
双栅薄膜晶体管101还可以包括栅极绝缘层17。栅极绝缘层(或其至少一部分)设置在栅极和有源层之间。在不同实施例中，栅极绝缘层17可以位于有源层12的上方或者有源层12的下方。在图2所示的实施例中，栅极绝缘层17覆盖有源层12，并还覆盖衬底17的部分表面。
双栅薄膜晶体管101还可以包括保护层18。根据不同的实现方式，保护层18可以位于第一栅极101d和第二栅极101e所在层的上方或者紧邻有源层12的上方。在图2所示的实施例中，保护层18设置在栅极绝缘层17之上，并且覆盖第一和第二栅极101d和101e。
如图2所示，第三电极101c通过穿过保护层18的通过(未以附图标记标示出)与栅极101d电连接。第一电极101a和第二电极101b分别通过穿过保护层18和栅极绝缘层107的通路13和14与有源层12的一部分电连接。
图2还示意性地示出了光敏器件102的实例。光敏器件102可以是例如光敏二极管。第三电极101c可以连接到光敏器件102的一端。在替代的实现方式中，第三电极101c也可以作为光敏器件102的电极，例如光敏二极管的阴极电极或阳极电极。光敏器件102的另一端(或另一电极)可以连接到其他器件、布线或电路(图中未示出)。
图2还示意性地示出了发光器件103的实例。在该实施例中，第一电极101a通过通孔16电连接到发光器件103。
图3A示出了本申请又一实施例提供的双栅薄膜晶体管101的截面示图；图3B示出了根据该实施例的像素电路的示意图。如图中所示，双栅薄膜晶体管101设置在衬底11上。
根据该实施例的双栅薄膜晶体管101可以包括：有源层12，第一栅极101d和第二栅极101e，第一电极101a、第二电极101b和第三电极101c。
如图3A中所示，第一栅极101d和第二栅极101e设置在衬底上；有源层12设置在第一栅极和第二栅极上方；第一电极101a、第二电极101b和第三电极101c设置在有源层上方。第一电极101a、第二电极101b和第三电极101c与有源层12分别通过第五通孔21、第六通孔22、第七通孔23电连接。第三电极101c与光敏器件102电连接。第一电极101a还与有机发光器件103通过第八通孔24电连接。
双栅薄膜晶体管101还可以包括栅极绝缘层17。栅极绝缘层17的至少一部分设置第一和第二栅极与有源层12之间。根据不同实施例，栅极绝缘层17可以位于有源层12的上方或者有源层12的下方。在图3A所示的实施例中，栅极绝缘层17覆盖第一栅极101d和第二栅极101e，并且还覆盖衬底11的部分表面。
双栅薄膜晶体管101还可以包括保护层18。根据不同实施例，保护层18可以位于第一栅极101d和第二栅极101e所在层的上方或者紧邻有源层12的上方。此外，根据不同的实施例，保护层18可以包括一层或多个绝缘材料。在图3A所示的实施例中，保护层18包括两层电介质材料，并且形成在有源层12和栅极绝缘层17之上。
上述双栅薄膜晶体管101也可以基于底栅和顶栅作出适应性修改。例如在图3A的基础上通过延长通孔或者另外的通孔(未示出)，使得光敏器件与第一栅极或第二栅极电连接来实现。或者，在图2基础上，通过例如改变通孔的位置，使得光敏器件与有源层连接。
根据本公开一些实施例，还通开了图2示出的双栅薄膜晶体管101的一种制作方法。以光敏器件为发光二极管PIN管为例，该方法可以包括如下描述的步骤。
在玻璃衬底或柔性衬底上，沉积缓冲层(buffer)。该缓冲层可以由SiN/SiO2叠层组成，例如其中SiN厚度50～150nm，SiO2为100～400nm。
在缓冲层201上形成有源层12。该有源层12可以为a-Si(非晶硅)或p-Si(多晶硅，例如，可以由a-Si晶化为p-Si)，也可以为氧化物半导体有源层，例如可以包括铟镓锌氧化物(IGZO)、铟锌氧化物(IZO)等。该有源层12可以为非晶态或是准晶态、晶态。可以对有源层12的与漏极和源极接触部分及第一栅极和第二栅极接触的区域进行导体化处理，例如通过掺杂、等离子处理、气氛退火等工艺，来增加载流子浓度，以保证此部分有源层和相应电极实现欧姆接触。
在有源层12上形成栅极绝缘(GI)层17和栅极层(其包括第一栅极101d和第二 栅极101e)。在一些实施例中，GI层可以包括SiO2或是SiN/SiO2叠层，厚度可以为80～150nm；栅极层可以为200～400nm厚的金属，如Mo等。应理解，这里以及上下文中所示出的材料和数值仅仅是示例性，本公开并不限于此。
然后，形成保护层18和源极-漏极(SD)层(在本实施例中，即包括第一电极101a和第二电极101b的层)。在一些实施例中，保护层为SiO2层或是SiN/SiO2叠层，厚度可以为80～150nm；SD层可以由200～400nm的金属，如Mo等形成。
本申请实施例中，在SD层制备时，可以同时实现TFT SD层和PIN下电极层共用的目的。在本申请的一些实施例中，可以同时制备TFT的源极电极和漏极电极以及和用于光敏器件(例如，PIN二极管)102的下电极(在本实施例中，第三电极101c)。换而言之，TFT的源极电极和漏极电极以及和用于光敏器件(例如，PIN二极管)102的下电极可以由相同材料通过同一工艺制备。
接着，形成用于PIN二级管的各层。在一些实施例中，PIN二极管可以包括：ITO层，P+型a-Si层，a-Si层，N+型a-Si层。在图2所示的实施例中，第三电极101c可以作为用于PIN二极管的下电极。根据不同的实施例，PIN的一些层可以通过PECVD形成。在需要时，某些层的杂质的引入可以通过原位掺杂工艺形成，也可通过额外的掺杂工艺形成。在一些实施例中，P+a-Si层可以为例如10～20nm，a-Si层可以为500～1000nm，和N+a-Si层可以为10～50nm。
ITO层可以作为PIN窗口层。在一些实施例中，在PIN图案化过程中ITO层可以起硬掩模(hard mask)作用。在一些实施例中，ITO层的厚度可以在50～130nm之间。
在将用于PIN的上述层图案化后，制备平坦层PLN。在一些实施例中，平坦层PLN的厚度可以比PIN稍大，例如在1.2～3μm之间。在一些实施例中，在形成PLN层之前，也可以在PIN的功能层的侧壁处形成覆盖层以保护PIN侧壁。作为例子，覆盖层的材料可以选用SiO、SiN等，其厚度可以为50～150nm左右。
图3A示出的双栅薄膜晶体管101的制作过程，其中光敏器件以发光二极管PIN管为例。该过程可以包括如下描述的步骤。
在玻璃衬底或柔性衬底上形成栅极层，如金属200～400nm的Mo层作为栅极层。
在栅极层上形成栅极绝缘层GI，该层可以由例如SiN/SiO2叠层组成，其中SiN厚度可以为50～150nm，SiO2的厚度可以为100～400nm。
在栅极绝缘层GI上形成有源层12。作为示例，该有源层可以为a-Si或p-Si，例如由a-Si晶化为p-Si；或者也可以为氧化物有源层，例如可以包括铟镓锌氧化物IGZO、 铟锌氧化物IZO等。根据不同实施例，有源层12可以为非晶态或是准晶态、晶态。有源层12的与源极S、漏极Dd、漏极源极Ds接触的部分可以进行导体化处理，例如可以通过掺杂、等离子处理、气氛退火等工艺，来增加载流子浓度，以保证此部分有源层和相应电极实现欧姆接触。
在有源层12上形成第一保护层PVX1和源极-漏极(SD)层。保护层可以为SiO2或是SiN/SiO2叠层，厚度可以为80～150nm。SD层可以为200～400nm金属，如Mo等。源极S和漏极Dd作为用于控制像素显示功能的开关的电极。
沉积第二保护层PVX2和漏极Ds。PVX2可以为SiO2层或是SiN/SiO2叠层，其厚度可以为80～150nm。Ds可以为200～400nm金属，如Mo等。源极S和漏极Ds作为用于控制光敏器件的开关的电极。在一些实施例中，Ds也可作为PIN管的下电极。
之后可以形成PIN管或其所需的各层。PIN的一些层可以由PECVD形成。在需要时，某些层的杂质的引入可以通过原位掺杂工艺形成，也可通过额外的掺杂工艺形成。在一些实施例中，P+a-Si层可以为例如10～20nm，a-Si层可以为500～1000nm，和N+a-Si层可以为10～50nm。
ITO层可以作为PIN窗口层。另外，ITO层在PIN的图案化过程中可以起硬掩模的作用。在一些实施例中，ITO层的厚度可以在50～130nm之间。
PIN图案化后，制备平坦层PLN。在一些实施例中，平坦层的厚度可以比PIN稍大，例如可以在1.2～3μm之间。
图4示出了本申请实施例提供的像素电路控制方法的流程示意图。根据本实施例的方法，可以控制双栅薄膜晶体管101来在控制光敏器件102和控制有机发光器件103之间切换。如图4所示，该方法可以包括以下步骤中的一些或全部。
在一些实施例中，所述像素电路控制方法可以示例性地划分为下列几个阶段。在第一阶段，双栅TFT开启以清空电荷。在第二阶段，双栅TFT处于亚阈值区域(SS区)。在第三阶段，使能光敏器件(例如PIN管)以实现指纹检测。在第四阶段，使得发光器件(例如发光二极管)以进行像素显示。应理解，根据不同的实现方式，所述像素电路控制方法可以包括上述阶段中的一个或多个。
步骤401，使双栅薄膜晶体101处于导通状态，以使得光敏器件102接收第四控制信号。在一些实施例中，该第四控制信号可以使光敏器件处于正偏状态。在一更具体实施例中，在双栅薄膜晶体101处于导通状态时，光敏器件102同步接收第四控制信号，使得光敏器件处于正偏状态，从而使得处于正偏的PIN管的电荷被清除。第一 栅极和第二栅极可以同步接收第三控制信号，以使得双栅薄膜晶体管处于导通状态。在该阶段(即第一阶段)双栅TFT开启以清空电荷。第三控制信号可以为第一高电平，例如+2V。第四控制信号可以为第二高电平，例如+5V。第三控制信号可以是第一栅极和第二栅极同步接收的控制信号。
步骤402，双栅薄膜晶体管101的第一栅极101d和第二栅极101e同步接收第一控制信号，使得双栅薄膜晶体管工作在亚阈值区域。光敏器件102可以在双栅薄膜晶体管101接收第一控制信号的同时，同步接收第二控制信号，使得光敏器件处于反偏状态。在该阶段(即第二阶段)，双栅TFT处于亚阈值区域。这里，通过使TFT工作在亚阈值区域，可以使PIN光信号对Id影响足够大，从而可以提高信号强度，简化电路结构。在一些实施例中，第一控制信号可以是0V电压。第二控制信号可以为-5V。第一控制信号可以是第一栅极和第二栅极同步接收的控制信号。
步骤403，在光敏器件处于反偏状态的时间周期内，光敏器件响应于检测到的光信号，将光信号转换成电荷以使得第一栅极产生偏压，并使得双栅薄膜晶体管在偏压作用下产生第一电流值，第一电流值用于指纹识别。在该阶段(即，第三阶段)利用PIN管实现指纹检测。以图2示出的电路结构为例，当第一栅极101d和第二栅极101e同步接收0v电压的控制信号时，双栅薄膜晶体管101工作在亚阈值区域。此时光敏器件102受-5V电压信号控制处于反偏状态，在反偏状态过程中，如果有手指按压在显示装置上，则手指的光线反射到光敏器件上，由于手指上的纹理对光线的反射程度不同，使得光敏器件在反偏状态下积累电荷产生的偏压值不同，进而在偏压值的影响下，双栅薄膜晶体管与光敏器件连接的第一栅极101d的电压呈现出负值，根据电荷数量，产生的负电压值不同，在负电压值的作用下，在第一电极101a处输出第一电流值，该电流值可以用于指纹检测。
步骤404，经第一栅极和第二栅极同步接收第三控制信号，使得双栅薄膜晶体管处于导通状态，以产生第二电流值。第二电流值可以用于驱动有机发光器件进行像素显示。在一些实施例中，第三控制信号可以为+2V。在该阶段(即，第四阶段)，进行像素显示。以图2示出的电路结构，当第一栅极101d和第二栅极101e同步接收到+2V的电压控制信号时，使得双栅薄膜晶体管101导通，图像信号可以通过第二电极101b输入，用于驱动有机发光器件103进行像素显示的第二电流值可以通过第一电极101a输出，从而实现显示功能。
如图5所示，图5示出了本申请又一实施例提供的像素电路控制方法的流程示意 图。该像素电路可以如图3A所示。控制双栅薄膜晶体管101在光敏器件102和有机发光器件103切换。
步骤501，在双栅薄膜晶体管处于第一部分导通状态时，光敏器件同步接收第四控制信号，使得光敏器件处于正偏状态。使得双栅薄膜晶体管101处于第一部分导通状态可以通过第一栅极接收第三控制信号，第二栅极接收第五控制信号。在一些实施例中，第三控制信号可以为+2V电压，第四控制信号可以为+5V电压，第五控制信号可以为-2V电压。在该阶段(即第一阶段)双栅TFT开启清空电荷。第一部分导通状态可以理解为双栅薄膜晶体管的部分导通，例如以图3A示出的电路结构为例，当第一栅极101d接收+2V电压，第二栅极101e接收-2V电压，则在第一栅极的电场控制下，可以在第一电极101a和第三电极101c之间形成沟道，使得处于正偏的PIN管的电荷被清除。第二栅极101e控制的双栅TFT的第二部分则处于截止状态。对于所述第一部分和第二部分没有限制，在其他实施例中，第一部分和第二部分可以互换，只要其按照本申请教导的原理工作即可。例如，也可以第一栅极101d接收-2V电压，第二栅极101e接收+2V电压；在这种情况下也可以以第二栅极101e，第二电极101b，第三电极101c限定的部分作为第一部分，以第一栅极101d，第一电极101a，第三电极101c限定的部分作为第二部分。
步骤502，第一栅极和第二栅极同步接收第五控制信号，使得双栅薄膜晶体管处于截止状态。在该阶段(即第二阶段)，双栅TFT开关断开。
步骤503，在双栅薄膜晶体管处于截止状态同时，光敏器件接收第二控制信号，使得光敏器件处于反偏状态，此时，光敏器件响应于检测到的光信号，将光信号转换成电荷并积累电荷。
步骤504，第一栅极接收第三控制信号，第二栅极接收第五控制信号，使得双栅薄膜晶体管处于第一部分导通状态，以导出电荷作为第三电流值。第三电流值可以用于指纹识别。以图3A示出的电路结构为例，当第一栅极101d接收+2V电压时，在第一电极101a与第三电极101c之间形成沟道，将PIN积累的电荷导出至第一电极101a，第一电极101a输出第三电流值，用于指纹识别。步骤503和504为第三阶段，在阶段利用PIN管实现指纹检测。类似地，对于第一部分，第二部分不作约束限定，在其他实施例中，也可以以第二栅极101e，第二电极101b，第三电极101c限定的部分作为第一部分，以第一栅极101d，第一电极101a，第三电极101c限定的部分作为第二部分。
步骤505，第一栅极和第二栅极同步接收第三控制信号，使得双栅薄膜晶体管处于导通状态，以产生第四电流值。该第四电流值可以用于驱动有机发光器件进行像素显示。在该阶段(即第四阶段)进行像素显示。以图3A示出的电路结构为例，在第一栅极101d和第二电极101e接收+2V电压时，在第一电极101a和第二电极101b之间形成沟道，图像信号经过第二电极101b输入，第一电极101a输出的第四电流值，用于驱动有机发光器件进行像素显示。
在第四阶段，还可以通过仅在第二栅极接收控制信号，使得第一栅极与第一电极和第三电极作为单栅TFT控制像素显示。
图6示出了根据本公开一些实施例的晶体管的Id-Vg曲线，图7示出了该晶体管的示例性操作的时序图。该晶体管可以为根据本公开上述任意实施例的双栅晶体管。
以所述双栅TFT具有如图6所示的Id-VG曲线为例，在第一栅极(Gate1，例如101和第二栅极处施加第一电压(例如，2V)打开TFT，并在Bias处加电压(例如，5V)以使得PIN正偏，去除PIN中残余电荷。
然后，如图7所示，在第一栅极处施加第二电压(例如，为0.2V)，在第二栅极施加第三电压(例如，为0V)，以使TFT处于亚阈值摆幅区(SS区，见图6)，并在Bias加电压(例如，-5V)，使PIN反偏。
受光后PIN中积累电荷并产生偏压，进而改变第二栅极电势，例如将变为-0.1V。最终体现在Id在SS区的变化如E-12A→E-15A，体现出光生偏压的效果。
之后，当Bias的加压变为0V时，PIN正偏放电，起复位(reset)效果。
之后，无光照时，可认为TFT不受影响，Id为SS区相应栅极电压下的电流。若以氧化物半导体TFT为例，TFT的开启电流(Ion)与截止电流(Ioff)之比Ion/Ioff为E-5/E-14＝E9。而对于非晶硅(例如，a-Si:H)PIN，光照电流Iphoto/暗态电流Idark为E-9/E-14＝E5。因此，根据本申请实施例，信号强度约比传统PIN大4个数量级。
在图7中，在示出的垂直线左侧为传感器感测工作区，右侧为显示工作区。在需要进行显示操作时，在第一栅极和第二栅极处施加电压(例如，都施加2V的电压)，以使TFT完全处于开启工作区域(例如，在图6的SS区的右侧区域)时，PIN产生的压差(约0.1V)造成的栅极电压变化对Id的影响可忽略。在TFT打开区，如2V到1.9V的变化，Id因处于饱和区，不会发生相应的变化。此时PIN不会对显示效果造成影响。 根据本申请的实施例，可以通过1个TFT来分别控制显示和感测。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离前述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (18)

  1. 一种半导体装置，包括：
    有源层；
    第一绝缘层；
    第一栅极和第二栅极，其分别隔着所述第一绝缘层与所述有源层的一部分重叠；
    第一电极、第二电极和第三电极，所述第一电极和第二电极分别与所述有源层的第一和第二部分电连接，所述第三电极用于与光敏器件电连接，其中，所述第三电极与所述第一栅极或所述第二栅极电连接；或者，所述第三电极与所述有源层的第三部分电连接。
  2. 根据权利要求1所述的半导体装置，其中所述第三电极作为所述光敏器件的一个电极。
  3. 根据权利要求2所述的半导体装置，还包括第二绝缘层，其中：
    所述第二绝缘层设置在所述第一、第二和第三电极与所述第一栅极和第二栅极之间，
    所述第一电极和第二电极分别通过穿过所述第二绝缘层的第一通孔和第二通孔与所述有源层的第一部分和第二部分电连接；以及
    所述第三电极通过穿过所述第一绝缘层和所述第二绝缘层的第三通孔与所述第一栅极或所述第二栅极电连接。
  4. 根据权利要求2所述的半导体装置，还包括第二绝缘层，其中：
    所述第二绝缘层设置在所述第一、第二和第三电极与所述有源层之间，
    所述第一电极和第二电极分别通过穿过所述第一绝缘层和所述第二绝缘层的第一通孔和第二通孔与所述有源层的第一部分和第二部分电连接；以及
    所述第三电极通过穿过所述第二绝缘层的第四通孔与所述有源层的第三部分电连接。
  5. 根据权利要求1所述的半导体装置，其中，所述第一、第二和第三部分彼此不同。
  6. 一种像素电路，所述像素电路包括如权利要求1所述的半导体装置、所述光敏器件、发光器件，
    其中所述光敏器件与所述第一栅极和第二栅极中的一个电连接，所述发光器件连接到所述第一电极和第二电极中的一个；
    所述半导体装置被配置为：在第一周期期间，所述半导体装置处在亚阈值区域；
    所述光敏器件被配置为：用于在所述半导体装置中的晶体管处于亚阈值区域的情况下，所述光敏器件处于反偏状态；
    在所述光敏器件处于反偏状态的情况下，所述光敏器件响应于检测到光信号，将所述光信号转换成电荷以使得所述第一栅极和所述第二栅极中的所述的一个产生偏压，并使得所述半导体装置在所述偏压作用下产生第一电流。
  7. 根据权利要求6所述的像素电路，其中所述半导体装置被配置为：在第二周期期间，所述半导体装置处于导通状态，以产生第二电流，所述第二电流用于驱动所述发光器件。
  8. 根据权利要求7所述的像素电路，其中所述光敏器件还被配置为：在所述半导体装置处于导通状态的情况下，所述光敏器件处于正偏状态。
  9. 一种像素电路，所述像素电路包括如权利要求1所述的半导体装置、所述光敏器件、发光器件，
    其中所述光敏器件与所述有源层的第三部分电连接，所述发光器件连接到所述第一电极和第二电极中的一个；
    所述半导体装置被配置为：在第三周期期间，所述半导体装置处于截止状态；
    所述光敏器件被配置为：在所述半导体装置处于截止状态的情况下，所述光敏器件处于反偏状态，以响应于检测到光信号，将所述光信号转换成电荷；
    所述半导体装置还被配置为：在所述半导体装置处于第一部分导通状态，导出所述电荷作为第三电流。
  10. 根据权利要求9所述的像素电路，其中所述半导体装置还被配置为：在第四周期期间，在所述半导体装置处于导通状态的情况下，产生第四电流，所述第四电流用于驱动所述发光器件。
  11. 根据权利要求9所述的像素电路，
    所述光敏器件还被配置为：在所述半导体装置处于所述第一部分导通状态的情况下，所述光敏器件处于正偏状态。
  12. 根据权利要求9所述的像素电路，所述半导体装置还被配置为：在所述半导体装置处于第二部分导通状态，以产生第五电流，所述第五电流用于驱动所述发光器件。
  13. 一种像素电路的控制方法，所述像素电路是如权利要求6-8中任意一项所述的像素电路，该方法包括：
    通过所述第一栅极和所述第二栅极接收第一控制信号，使得所述半导体装置工作在亚阈值区域；
    通过所述光敏器件接收第二控制信号，使得所述光敏器件处于反偏状态；
    在所述光敏器件处于反偏状态的情况下，通过所述光敏器件响应于检测到的光信号，将光信号转换成电荷以使得所述第一栅极和所述第二栅极中所述的一个产生偏压，并使得所述半导体装置在所述偏压作用下产生第一电流。
  14. 根据权利要求13所述的像素电路控制方法，还包括：
    通过所述第一栅极和所述第二栅极接收第三控制信号，使得所述半导体装置处于导通状态，以产生第二电流，所述第二电流用于驱动所述发光器件。
  15. 根据权利要求13所述的像素电路控制方法，，该方法还包括：
    在所述半导体装置处于导通状态时，通过所述光敏器件接收第四控制信号，使得所述光敏器件处于正偏状态。
  16. 一种像素电路控制方法，所述像素电路是如权利要求9-12中任意一项所述的像素电路，该方法包括：
    通过所述第一栅极和所述第二栅极接收第五控制信号，使得所述半导体装置处于截止状态；
    通过所述光敏器件接收第二控制信号，使得所述光敏器件处于反偏状态，以响应于检测到光信号，将所述光信号转换成电荷；
    通过所述第一栅极接收第三控制信号，并通过所述第二栅极接收第五控制信号，使得所述半导体装置处于第一部分导通状态，以导出所述电荷作为第三电流。
  17. 根据权利要求16所述的像素电路控制方法，还包括：
    通过所述第一栅极和第二栅极接收所述第三控制信号，使得所述半导体装置处于导通状态，以产生第四电流，所述第四电流用于驱动所述发光器件。
  18. 根据权利要求17所述的像素电路控制方法，该方法还包括：
    在所述半导体装置处于第一部分导通状态的情况下，通过所述光敏器件接收第四控制信号，使得所述光敏器件处于正偏状态。
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