WO2020206609A1 - 一种差分振荡器 - Google Patents

一种差分振荡器 Download PDF

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Publication number
WO2020206609A1
WO2020206609A1 PCT/CN2019/081920 CN2019081920W WO2020206609A1 WO 2020206609 A1 WO2020206609 A1 WO 2020206609A1 CN 2019081920 W CN2019081920 W CN 2019081920W WO 2020206609 A1 WO2020206609 A1 WO 2020206609A1
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Prior art keywords
tail
varactor
inductor
voltage
capacitor
Prior art date
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PCT/CN2019/081920
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English (en)
French (fr)
Inventor
张津海
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980090008.2A priority Critical patent/CN113330682B/zh
Priority to EP19924376.7A priority patent/EP3923469A4/en
Priority to PCT/CN2019/081920 priority patent/WO2020206609A1/zh
Publication of WO2020206609A1 publication Critical patent/WO2020206609A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
    • H03B5/1246—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising transistors used to provide a variable capacitance
    • H03B5/1253—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising transistors used to provide a variable capacitance the transistors being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/1262—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements
    • H03B5/1265—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements switched capacitors

Definitions

  • This application relates to the field of circuits, and more specifically, to a differential oscillator.
  • the clock is an important part of the communication system.
  • High-precision communication systems require high clock accuracy.
  • the oscillator can be used to generate the clock for the circuit.
  • High-quality oscillators play an important role in achieving high-precision communication.
  • the capacitance and inductance of the main resonant circuit, the capacitance and inductance of the tail resonant circuit, and the substrate of the cross-coupled metal-oxide-semiconductor (MOS) device are connected to the power supply or ground, and the power supply line and
  • MOS metal-oxide-semiconductor
  • This application provides a differential oscillator.
  • the inductor in the differential oscillator By arranging the inductor in the differential oscillator on both sides of the power line and the ground line, the distance between the power line and the ground line is reduced, thereby ensuring that the power line and the ground line are both AC "ground” can reduce the phase noise of the differential oscillator.
  • a differential oscillator including: a power line, which is arranged on a chip; a ground line, which is arranged on the chip and is parallel to the power line; and a main resonance circuit, which is arranged on the chip, includes a first inductor and a second Two inductors, the first inductor and the second inductor are arranged on the side of the power line away from the ground; the main resonance circuit is connected with the power line; the tail resonance circuit is arranged on the chip and is connected with the main resonance circuit and the ground.
  • the embodiment of the present application arranges the inductance of the main resonant circuit on the power line away from the ground line.
  • the distance between the power line and the ground line can be reduced. The smaller distance makes the impedance of the parasitic parameters generated by the decoupling capacitor set between the power line and the ground line smaller, which can reduce the AC impedance between the ground line and the power line, making the ground line and the power line closer to the AC" Land".
  • Many components in the differential oscillator are connected to the power line or the ground line.
  • the tail resonant circuit includes: a tail inductor, the tail inductor includes a tail inductor main body and a tail inductor connection part, the tail inductor main body is arranged on the side of the ground line away from the power line, and the tail inductor is connected The part is used to connect the tail inductor main body and the main resonant circuit.
  • the distance between the ground wire and the power wire is less than or equal to a first preset value.
  • the differential oscillator further includes a decoupling capacitor, which is arranged between the ground line and the power line and connected to the power line and the ground line.
  • the decoupling capacitor is arranged between the ground line and the power line, which is easy to implement in process, can reduce parasitic effects, and can reduce the occupation of chip area.
  • a smaller decoupling capacitor between the ground wire and the power wire can meet the circuit design requirements.
  • the smaller decoupling capacitor occupies a smaller area, which reduces the occupation of chip resources.
  • the tail inductance connecting portion is arranged in parallel with the ground wire, and the tail inductance connecting portion is located at the part between the tail inductance main body and the ground wire.
  • the differential oscillator further includes: a cross-coupled metal oxide semiconductor MOS tube.
  • the cross-coupled MOS tube is used to provide negative resistance for the main resonance circuit.
  • the main resonance circuit includes a first capacitor, and the first capacitor includes a first fixed capacitor, a first varactor MOS transistor, a second varactor MOS transistor, and a second fixed capacitor connected in series. ;
  • the sum of the capacitance values of the first fixed capacitor and the first variable capacitance MOS tube is equal to the sum of the capacitance values of the second variable capacitance MOS tube and the second fixed capacitance;
  • the first fixed capacitance is connected to the gate of the first variable capacitance MOS tube ,
  • the second fixed capacitor is connected to the gate of the second varactor MOS tube;
  • the control voltage is the bias voltage of the source and drain of the first varactor MOS tube and the second varactor MOS tube;
  • the first bias voltage is The gate of the first varactor MOS tube provides a DC bias, and the second bias voltage provides a DC bias for the gate of the second varactor MOS tube.
  • the first bias voltage and the second bias voltage are The bias voltage obtained by the power supply voltage provided by the power supply line.
  • the fixed capacitor and the variable capacitance MOS tube are connected in series to realize the voltage division between the fixed capacitance and the variable capacitance MOS tube, which can reduce the influence of power supply noise on the gate capacitance of the variable capacitance MOS tube, thereby reducing the influence of power supply noise on the frequency of the oscillator. Phase noise.
  • the first varactor MOS transistor when the first bias voltage is within a first voltage range, the first varactor MOS transistor under at least one voltage value state of the control voltage The gate capacitance does not change with the voltage at the end of the connection between the first fixed capacitor and the first inductor.
  • the capacitances of the first fixed capacitor and the first fixed capacitor are equal, the process parameters of the first varactor MOS tube and the second varactor MOS tube are the same, and the first bias voltage is equal to The second bias voltages are equal.
  • a differential oscillator including: a main resonant circuit; the main resonant circuit includes a first fixed capacitor and a first varactor metal oxide semiconductor MOS transistor connected in series between two differential output terminals of the oscillator , The second varactor MOS tube, the second fixed capacitor; the first fixed capacitor is connected to the gate of the first variable capacitance MOS tube, the second fixed capacitor is connected to the gate of the second variable capacitance MOS tube; the control voltage controls the first The bias voltages of the source and drain of the varactor MOS tube and the second varactor MOS tube, the first bias voltage and the second bias voltage are the bias voltages obtained by the power supply voltage provided by the power line The first bias voltage provides a DC bias for the gate of the first varactor MOS tube, and the second bias voltage provides a DC bias for the gate of the second varactor MOS tube.
  • the capacitance array formed by the varactor MOS tube forms the capacitance in the main oscillation circuit.
  • the noise on the power supply line will affect the gate voltage of the varactor MOS tube, which will cause the capacitance of the varactor MOS tube to change and cause greater phase noise.
  • the embodiment of the application realizes the voltage division of the fixed capacitor and the variable capacitance MOS transistor by adding a fixed capacitor in series with the variable capacitance MOS transistor. It can reduce the influence of power supply noise on the gate capacitance of the varactor MOS tube, thereby weakening the influence of power supply noise on the oscillator frequency and reducing phase noise.
  • the gate capacitance of the first varactor MOS transistor under at least one state of the control voltage does not change with the differential oscillator The output voltage changes.
  • the capacitances of the first fixed capacitor and the first fixed capacitor are equal
  • the first varactor MOS transistor is the same as the second varactor MOS transistor
  • the first bias voltage is the same as the second The bias voltages are equal.
  • the differential oscillator further includes: a cross-coupled metal oxide semiconductor MOS transistor.
  • the cross-coupled MOS tube is used to provide negative resistance for the main resonance circuit.
  • the differential oscillator further includes: a power line, which is arranged on the chip; a ground line, which is arranged on the chip and is parallel to the power line; the main resonance circuit also includes: a second inductor , The first inductance and the second inductance are arranged on the side of the power line away from the ground line; the main resonance circuit is connected with the power line; the tail resonance circuit is arranged on the chip.
  • the tail resonant circuit includes: a tail inductor, the tail inductor includes a tail inductor main body and a tail inductor connection part, the tail inductor main body is arranged on the side of the ground line away from the power line, and the tail inductor is connected The part is used to connect the tail inductor main body and the main resonant circuit.
  • the distance between the ground wire and the power wire is less than or equal to the first preset value.
  • the differential oscillator further includes: a decoupling capacitor, which is arranged between the ground line and the power line and connected to the power line and the ground line.
  • the tail inductor connection portion is arranged in parallel with the ground wire, and the tail inductor connection portion is located between the tail inductor main body and the ground wire.
  • a chip including the differential oscillator described above.
  • Figure 1 is a schematic diagram of the circuit structure of a differential oscillator using tail inductance resonance technology.
  • FIG. 2 is a schematic diagram of parasitic parameters of the circuit structure of a differential oscillator using tail inductance resonance technology.
  • FIG. 3 is a schematic diagram of the circuit structure and layout of a differential oscillator provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of the circuit structure and layout of a differential oscillator provided by another embodiment of the present application.
  • Figure 5 is a schematic diagram of the AC equivalent circuit of the tail resonant network of a differential oscillator using tail inductance resonance technology.
  • Fig. 6 is a schematic diagram of the AC equivalent circuit of the tail resonant network of another differential oscillator using tail inductance resonance technology.
  • Fig. 7 is a schematic diagram of an AC equivalent circuit of a tail resonant network of another differential oscillator using tail inductance resonance technology.
  • Fig. 8 is a schematic circuit diagram of an adjustable capacitor of a differential oscillator.
  • FIG. 9 is a schematic circuit diagram of an adjustable capacitor provided by an embodiment of the present application.
  • FIG. 10 is a schematic circuit diagram of an adjustable capacitor provided by another embodiment of the present application.
  • Figure 11 is a schematic diagram of the relationship between the gate voltage and the gate capacitance of a MOS tube.
  • FIG. 12 is a schematic diagram of the relationship between gate voltage and gate capacitance of another MOS tube.
  • FIG. 13 is a schematic diagram of the circuit structure and layout of a differential oscillator according to another embodiment of the present application.
  • Fig. 14 is a schematic circuit diagram of an adjustable capacitor for a differential oscillator.
  • FIG. 15 is a schematic diagram of a test result of a differential oscillator provided by an embodiment of the present application.
  • the clock is an important part of the communication system.
  • the main functions of the clock include: (1) work together with the mixer to complete the up-conversion of the signal; (2) the analog to digital converter (ADC), digital to analog converter, DAC ) Provide a sampling clock to complete digital-to-analog signal conversion.
  • the oscillator is the core part of realizing high-quality clock. Both high-quality communication and high-precision ADC/DAC put strict requirements on high-performance oscillators.
  • the oscillator may be a voltage controlled oscillator (VCO) or a digital controlled oscillator (DCO).
  • VCO voltage controlled oscillator
  • DCO digital controlled oscillator
  • An oscillator that realizes a high-quality clock is essential for high-precision communication systems.
  • Figure 1 is a schematic diagram of the circuit structure of a traditional differential oscillator using tail inductance resonance technology.
  • the differential oscillator circuit using tail inductance resonance technology includes a main resonance circuit 110 and a tail resonance circuit 120.
  • the main resonance circuit 110 includes a negative resistance 111, and the negative resistance 111 includes a cross-coupled metal-oxide-semiconductor (MOS) field effect transistor (FET). MOSFET is also called MOS transistor, MOS tube or MOS device.
  • the main resonance circuit 110 may include a first capacitor C, a first inductance L c1 and a second inductance L c2 having the same inductance value.
  • the tail resonance circuit 120 may include a tail inductance L t and a tail capacitance C t .
  • the cross-coupled MOS transistor is equivalent to a linear negative resistance, and provides energy to the main resonance circuit 110, compensates for the loss of the main resonance circuit 110, and maintains oscillation.
  • the main resonance circuit 110 can be regarded as two parts with symmetrical structure.
  • L c1 L c2
  • C C c1 + C c2
  • C c1 C c2 .
  • the voltage at the junction of C c1 and C c2 can be regarded as the ground of the AC signal, that is, the voltage at the junction of C c1 and C c2 is 0 for the AC signal.
  • One resonant circuit includes L c1 -C c1
  • the other resonant circuit includes L c2 -C c2 .
  • the resonant frequencies of the two resonant circuits are equal.
  • This resonant frequency may be referred to as the oscillation frequency of the main resonant circuit 110.
  • one end of L c1 and C c1 is grounded, and the other end is the output voltage V o1 ; one end of L c2 and C c2 is grounded, and the other end is the output voltage V o2 .
  • the DC voltages at Vo1 and Vo2 are equal, the amplitude of the AC voltage is equal, and the phase is opposite.
  • the tail resonance circuit 120 may include tail inductors and capacitors.
  • the oscillation frequency of the tail resonance circuit 120 is twice the oscillation frequency of the main resonance circuit 110.
  • the oscillation frequency of the tail resonance circuit 120 deviates from twice the oscillation frequency of the main resonance circuit 110, as the difference between the oscillation frequency of the tail resonance circuit 120 and the 2 times the oscillation frequency of the main resonance circuit 110 increases, the oscillation frequency of the oscillator Phase noise increases.
  • Fig. 2 is a schematic diagram of the circuit layout of a conventional differential oscillator using tail inductance resonance technology.
  • the part 210 connected to the power supply includes a power line 211 and a power line connection part 212.
  • the power cord connection part 212 can be used to connect the power cord 211 with other components of the differential oscillator.
  • the inductor 220 includes a first inductor, a second inductor, and a tail inductor.
  • the first inductor includes a first inductor main body 221 and a first inductor connecting portion 224.
  • the second inductor includes a second inductor main body 222 and a second inductor connecting portion 225.
  • the tail inductor includes a tail inductor main body 223 and a first tail inductor connecting portion 226.
  • the first inductance connecting portion 224 may be used to connect the first MOS transistor.
  • the second inductance connecting portion 225 can be used to connect the second MOS transistor.
  • the first tail inductor connecting portion 226 may be used to connect the tail inductor main body 223 and the tail capacitor.
  • the first tail inductor connecting portion 226 can also be used to connect the inductor main body 223 with the first MOS transistor and the second MOS transistor.
  • the tail inductor may further include a second tail inductor connecting portion 227 for connecting the tail inductor main body 223 and the first tail inductor connecting portion 226.
  • the first tail inductor connecting portion 226 may connect the tail inductor main body 223 and the tail capacitor via the second tail inductor connecting portion 227.
  • the portion 230 connected to the ground includes a ground wire 231 and a ground wire connection portion 232.
  • the ground connection part 232 can be used to connect the ground 231 to other components of the differential oscillator.
  • the ground connection portion 232 can be used to connect the ground 231 and the tail inductor 223, and the ground 231 and the tail capacitor.
  • a first inductor 221, a second inductor 222, a tail inductor 223, a capacitor, a MOS tube, and other devices are arranged between the power line 211 and the ground line 231, and the power line 211 is far away from the ground line 231.
  • the power line 211 is connected to the first inductor 221 and the second inductor 222 through the power connection portion 212.
  • the ground wire 231 is connected to the tail inductor 223 through the ground connection portion 232.
  • a large decoupling capacitor needs to be arranged around the circuit. Larger decoupling capacitors take up more area and waste chip resources.
  • the tail resonance circuit 120 may include a tail inductor 223 and a tail capacitor.
  • the oscillation frequency of the tail resonance circuit 120 is twice the oscillation frequency of the main resonance circuit 110, the phase noise is the smallest. It is impossible to guarantee that the power line and the ground line are both AC "ground”, which will lead to the inability to accurately design the tail resonant circuit in the circuit, resulting in greater phase noise.
  • this application proposes a differential oscillator, which can obtain accurate parasitic parameters of the oscillator, so that the phase noise of the oscillator can be reduced through reasonable design.
  • FIG. 3 is a schematic diagram of the circuit structure and layout of a differential oscillator provided by an embodiment of the present application.
  • the differential oscillator includes a power line 311, a ground line 331, a main resonance circuit 110, and a tail resonance circuit 120.
  • the oscillator is a differential oscillator.
  • the differential oscillator is located on the chip.
  • the power line 311 is arranged on the chip.
  • the ground line 331 is arranged on the chip and is parallel to the power line 311.
  • the ground line 331 is parallel to the power line 311, and it can be understood that the ground line 331 is approximately parallel to the power line 311.
  • the main resonance circuit 110 is arranged on the chip and includes a first inductor 321 and a second inductor 322.
  • the main resonance circuit is connected to a power line.
  • the tail resonance circuit 120 is provided on the chip.
  • the tail resonance circuit 120 is connected to the main resonance circuit and the ground.
  • connection in this application refers to electrical connection.
  • the connection between A and B means that A and B are electrically connected, that is, A and B can be connected via interconnection lines, or there are other components connected between A and B, such as A via C and B.
  • the components in the chip are connected by interconnecting wires.
  • the interconnection lines may also be referred to as wires, interconnection wires, metal wires, and so on.
  • the tail resonance circuit 120 includes a tail inductor and a tail capacitor 341.
  • the tail inductor includes a tail inductor main body 323 and a tail inductor connecting portion 326.
  • the tail inductor connecting portion 326 is used to connect the tail inductor main body 323 and the tail capacitor.
  • the tail inductor connecting portion 326 can also be used to connect the tail inductor main body 323 and the main resonance circuit.
  • the power line 311 and the ground line 331 divide the chip area where the differential oscillator is located into the first part located between the power line and the ground line, and the power line 311 and the ground line 331 are located respectively.
  • the second part and the third part of the side are located respectively.
  • the first inductor and the second inductor may be located in the second part.
  • the tail inductor main body 323 may be located in the second part or the third part.
  • the tail inductor main body 323 is located in the third part, which can further reduce the distance between the power line 311 and the ground line 331, that is, make the power line 311 and the ground line 331 closer to the AC "ground”.
  • the tail inductor main body 323 is arranged on the side of the ground wire away from the power line, that is, the tail inductor main body 323 is located in the third part for description.
  • the second part may be the side away from the power line 311, and the third part may be the side away from the ground line 331.
  • the third part may be a side away from the power line 311, and the second part may be a side away from the ground line 331.
  • the second part is the side far away from the ground wire 331 and the third part is the side far away from the power wire 311 as an example for description. That is, as shown in FIG. 3, the first inductor 321 and the second inductor 322 are arranged on the side of the power line 311 away from the ground line 331, and the tail inductor main body 323 is arranged on the side of the ground line away from the power line.
  • the first inductor 321, the second inductor 322, and the tail inductor main body 323 are respectively located on both sides of the ground line 331 and the power line 311, and the distance between the ground line 331 and the power line 311 can be small, resulting in a relatively large capacitance.
  • the impedance between the ground line 331 and the power line 311 is relatively small. That is, it can be ensured that both the ground wire 331 and the power wire 311 are AC "grounds".
  • the distance between the ground wire 331 and the power wire 311 can be very small. Arranging a decoupling capacitor between the power wire 311 and the ground wire 331 produces less parasitic parameters, making the ground wire 331 and the power wire 311 closer to the AC ground ". The distance between the ground line 331 and the power line 311 can be small, which reduces the need for decoupling capacitors of the differential oscillator. A smaller decoupling capacitor between the ground line 331 and the power line 311 can meet the circuit design requirements. The smaller decoupling capacitor occupies a smaller area, which reduces the occupation of chip resources.
  • ground line 331 or the power line 311 such as the capacitance and inductance of the main resonance circuit, the capacitance and inductance of the tail resonance circuit, and the substrate of the cross-coupled MOS device.
  • the ground wire 331 and the power wire 311 are close to the AC “ground”, so that the parasitic parameters of the components connected to the ground wire 331 or the power wire 311 in the differential oscillator can be determined more accurately.
  • the difference between the oscillation frequency of the tail resonant circuit and the oscillation frequency of the main resonant circuit 110 can be reduced by two times, and the phase noise of the oscillator can be reduced.
  • the distance between the ground line 331 and the power line 311 is less than or equal to a first preset value.
  • the distance between the ground line 331 and the power line 311 can also be understood as the width of the first portion.
  • the differential oscillator may include decoupling capacitors.
  • the decoupling capacitor is used to increase the capacitance value between the power line 311 and the ground line 331, thereby reducing the impedance between the power line 311 and the ground line 331 relative to the AC signal.
  • the two ends of the decoupling capacitor are respectively connected to the power line 311 and the ground line 331.
  • the embodiment of the present application does not limit the position of the decoupling capacitor, and the decoupling capacitor may be provided in the first part, the second part, or the third part, for example.
  • Decoupling capacitors can be metal-oxide-metal (MOM) capacitors, metal-insulator-metal (MIM) capacitors, or polysilicon-insulator-polysilicon (polysilicon-insulator-polysilicon, PIP) capacitance, etc.
  • MOM metal-oxide-metal
  • MIM metal-insulator-metal
  • PIP polysilicon-insulator-polysilicon
  • Decoupling capacitors formed by MOM capacitors can reduce the area occupied by the capacitors.
  • the decoupling capacitor is arranged between the ground line and the power line, that is, the decoupling capacitor is arranged in the first part, which is easy to realize in process, reduces parasitic effects, and can reduce the occupation of chip area.
  • a relatively large capacitance will be generated between the power line 311 and the ground line 331 arranged adjacently, thereby reducing the demand for decoupling capacitors.
  • Arranging a small decoupling capacitor around the power line and the ground line can make the AC impedance between the power line 311 and the ground line 331 meet the requirements of circuit design.
  • the tail capacitor can be a MOM capacitor, MIM capacitor, or PIP capacitor.
  • the tail inductance connecting portion 326 is arranged in parallel with the ground wire 331. Parallel can be approximately parallel.
  • the inductance connecting portion 326 and the ground wire 331 are arranged in parallel to reduce the difficulty in the process of implementing the tail capacitor.
  • the tail inductor connecting portion 326 may be located in the first part, the second part or the third part.
  • the tail inductance connecting portion 326 is located in the part between the tail inductance and the ground in the third part, which can reduce the difficulty in the process of the tail capacitor and reduce the area occupied by the tail capacitor.
  • the main resonant circuit in the differential oscillator also includes cross-coupled MOS devices.
  • the first MOS transistor 351 and the second MOS transistor 352 that are cross-coupled can serve as the negative resistance of the differential oscillator.
  • the process parameters of the first MOS tube 351 and the second MOS tube 352 are the same.
  • the cross-coupled MOS tube can be equivalent to a linear negative resistance.
  • the cross-coupled MOS tube can provide energy to the main resonant circuit 110, compensate for the loss of the main resonant circuit 110, and maintain oscillation.
  • MOS devices are four-terminal devices, including a source (source), a drain (drain), a gate (gate), and a substrate (bulk).
  • the first MOS tube 351 and the second MOS tube 352 may both be N-channel MOS (n-channel MOS, NMOS) tubes, or both may be P-channel MOS (p-channel MOS, PMOS) tubes.
  • the substrate of the NMOS tube is connected to the low potential of the chip, that is, connected to the "ground”.
  • the substrate of the NMOS tube can be connected to the ground line 331.
  • the substrate of the PMOS tube is connected to a high potential, that is, to the power supply voltage.
  • the substrate of the NMOS tube can be connected to the power line 311. As shown in FIG.
  • the sources of the first MOS tube 351 and the second MOS tube 352 are connected to the tail resonance circuit, and the substrate is grounded, that is, the substrate is connected to the ground.
  • Line 331 the drain is connected to the first inductor 321 and the second inductor 322 in the main resonance circuit, the gate of the first MOS transistor 351 is connected to the drain of the second MOS transistor 352, and the gate of the second MOS transistor 352 is connected to the first The drain of the MOS tube 351.
  • the substrates of the first MOS tube 351 and the second MOS tube 352 are connected to the power supply voltage, that is, connected to the power line 311, the source is connected to the power line 311, and the drain
  • the poles are respectively connected to the first inductor 321 and the second inductor 322 in the main resonance circuit, the gate of the first MOS transistor 351 is connected to the drain of the second MOS transistor 352, and the gate of the second MOS transistor 352 is connected to the first MOS transistor 351. Drain.
  • the parasitic capacitance of MOS devices includes: the drain line capacitance C db between the drain and the substrate, the gate-source capacitance C gs between the gate and the source, the gate-drain capacitance C gd between the gate and the source, and the source The source substrate capacitance C sb between the electrode and the substrate.
  • the differential oscillator may further include a first inductance connection part 324, a second inductance connection part 325, and a tail inductance connection part 326.
  • the first inductor connecting portion 324 may be used to connect the first inductor 321 with other components, for example, connect the first inductor 321 with the first MOS transistor.
  • the second inductance connecting portion 325 can be used to connect the first inductance 322 to other components, for example, to connect the second inductance 322 to the second MOS transistor.
  • the inductor component 310 may include a first inductor 321, a second inductor 322, a tail inductor main body 323, a first inductor connecting portion 324, a second inductor connecting portion 325, and a tail inductor connecting portion 326.
  • the inductance components 310 may be located on the same or different metal layers.
  • Each of the inductance components 320 may also be located on the same or different metal layers.
  • part of the metal in the tail inductor main body 323 may be located on the same metal layer as the ground connection portion 332, and another part may be located on a different metal layer from the ground connection portion 332.
  • the tail inductor may further include a connecting portion 327 for connecting the tail inductor main body 323 and the tail inductor connecting portion 326.
  • the embodiment of the present application does not limit the positions of the first inductance connecting portion 324, the second inductance connecting portion 325, and the tail inductance connecting portion 326.
  • the first inductance connecting portion 324 may be located in the second part.
  • the first inductor connecting portion 324 may be located on the same or different metal layer as the power component 310 and the first inductor 321.
  • the first inductance connecting portion 324 may be partly located in the second part and partly located in the first part.
  • the first inductance connecting portion 324 and the power line 311 may be located on a different metal layer.
  • the power supply part 310 may include a power cord 311 and a power cord connection part 312.
  • the power supply components 310 may be located on the same or different metal layers.
  • the ground wire component 330 may include a ground wire 331 and a ground wire connection part 332.
  • the ground component 330 may be located on the same or different metal layer.
  • the power component 310 and the ground component 330 may be arranged on the same or different metal layers. Considering that the line width of the metal line is smaller than the thickness of the metal layer, the power line 311 and the ground line 331 are located in the same metal layer, and when the width W of the first part is the same, the actual distance between the power line 311 and the ground line 331 can be reduced. Increase the parasitic capacitance between the power line 311 and the ground line 331.
  • the power component 310, the ground component 330, the first inductor 321, the second inductor 322, and the tail inductor body 323 are located on the same metal layer, which can reduce the number of metal layers in the oscillator, reduce interconnection parasitic parameters, and reduce manufacturing costs .
  • the power component 310, the ground component 330, and the inductance component 310 may be located on the same metal layer as much as possible.
  • the inductance values of the first inductor 321 and the second inductor 332 in the main resonance circuit 110 are equal.
  • the first inductor 321 and the second inductor 332 may be symmetrically arranged.
  • the first inductor 321 and the second inductor 332 may be respectively arranged in a surrounding shape such as an octagon or a hexagon.
  • the first inductor 321 and the second inductor 332 can also form an octagonal or hexagonal shape together.
  • the connection location to the power line connection portion 312 may be one end of the inductor, and the location connected to the cross-coupled MOS device may be the other end of the inductor.
  • the main resonance circuit 110 includes a first capacitor 341.
  • the first capacitor 341 may be an adjustable capacitor.
  • the first capacitor 341 can be an adjustable capacitor, which can realize VCO/DCO.
  • the embodiment of the present application does not limit the structure of the adjustable capacitor, and various existing or future capacitor structures may be used. A detailed description will be given below in conjunction with specific embodiments, and will not be described in detail here.
  • the first capacitor 341 may include a fixed capacitor.
  • the fixed capacitor may be a MOM capacitor, MIM capacitor, or PIP capacitor.
  • the embodiment of the present application does not limit the position of the first capacitor 341.
  • the first capacitor 341 can be located anywhere on the chip.
  • the fixed capacitor in the first capacitor may be located in the second part.
  • the fixed capacitor may be a MOM capacitor, and the metal line constituting the first capacitor may be arranged in parallel with the power line 311.
  • the fixed capacitor adopts the above-mentioned layout method, which can improve the utilization of chip area.
  • the first inductance, the second inductance, and the tail inductance can refer to the single-turn inductance shown in Figures 2 and 3, that is, the metal wires that form the first and second inductances can be approximately circled, and the metal wires that form the tail inductance can be The arrangement is approximately round.
  • FIG. 4 is a schematic diagram of the circuit structure and layout of a differential oscillator proposed by an embodiment of the present application.
  • the first inductance, the second inductance, and the tail inductance can also be double-turn inductance or multi-turns, that is, the metal wire forming the first inductance and the second inductance can be approximately surrounded by two or more turns, and the metal wire forming the tail inductance can be approximately surrounded Two or more laps.
  • the first inductor and the second inductor adopt double coil inductors and multiple coils, and the common mode inductance of the first inductor and the second inductor is lower.
  • the common mode resonance component F c the common mode inductance is reduced, which can weaken the relationship between the common mode resonance component F c and the frequency, which is beneficial to the design of the differential oscillator.
  • the tail inductor connecting portion 326 is arranged in parallel with the ground wire 331. Parallel can be approximately parallel. The parallel arrangement of the inductance connecting portion 326 and the ground wire 331 reduces the difficulty in the process of implementing the tail capacitor.
  • the tail inductance connecting portion 326 may be located in the part between the tail inductance and the ground in the third part, which can reduce the difficulty in process realization of the tail capacitor and reduce the area occupied by the tail capacitor.
  • FIG. 5 is a schematic diagram of parasitic parameters of the circuit structure of a differential oscillator using tail inductance resonance technology.
  • the power supply line voltage of the differential oscillator can be represented by V dl
  • the ground voltage of the differential oscillator can be represented by V sl
  • the inductance between the power line of the differential oscillator and the power supply module can be represented by L dr
  • the inductance between the ground line of the differential oscillator and the ground of the chip can be represented by L sr .
  • L dl The parasitic inductance of the power line of the oscillator and the inductance terminal is represented by L dl ;
  • C c represents the common mode component of the resonant capacitor of the differential oscillator, which can represent one-half of the capacitance value of the capacitor C in Figure 1;
  • C d represents the decoupling capacitor (decoupling capacitor, decap), decoupling capacitor It is the coupling capacitance between the power supply of the circuit and the ground of the circuit;
  • the tail capacitance C t and the tail inductance L t are the tuning part of the tail resonant network.
  • the power supply module provides power to the power supply line of the differential oscillator.
  • the output of the power supply module can be used as the power supply voltage of the power supply line of the differential oscillator, that is, the output terminal of the power supply module can be connected to the power supply voltage of the power supply line of the differential oscillator via an interconnection wire.
  • the output terminal of the power supply module may also be connected to the power line of the differential oscillator after passing through a DC-DC converter, a low dropout regulator (LDO), etc.
  • LDO low dropout regulator
  • the parasitic parameters between the power supply line and the ground line can be accurately determined.
  • Multiple parasitic parameters of the MOS tube are connected to the power line and the ground line.
  • the parasitic parameters between the power line and the ground wire can be accurately determined, and the parasitic parameters of the cross-coupled MOS tube in the differential oscillator can be accurately determined, so that the oscillation frequency of the tail resonant circuit can be made to match that of the main resonant circuit through a reasonable design.
  • the 2 times difference of the oscillation frequency is reduced, reducing the phase noise of the oscillator.
  • the differential oscillator using tail inductance resonance technology realizes the function of the oscillator by resonating the tail inductance and capacitance at twice the oscillation frequency.
  • the following analyzes the influence of parasitic parameters on the performance of the oscillator.
  • Fig. 6 is a schematic diagram of an AC equivalent circuit of a tail resonant network of a traditional differential oscillator using tail inductance resonance technology.
  • C sb represents the parasitic capacitance between the source and the substrate of the cross-coupled negative resistance MOS device
  • C gs represents the parasitic capacitance between the gate and source of the MOS
  • C gd represents the parasitic capacitance between the gate and source of the MOS Parasitic capacitance
  • C db characterizes the parasitic capacitance between the drain of the MOS and the substrate.
  • Fig. 7 is a schematic diagram of an AC equivalent circuit of a tail resonant network of a differential oscillator using tail inductance resonance technology.
  • Figure 5 is a simplified structure of the AC equivalent circuit in Figures 3 and 4.
  • Figure 6 further simplifies the structure in Figure 5.
  • the tail resonant network includes a parallel tail resonant inductor L tail , an additional capacitance C t , a parasitic capacitance C sb , and a common mode resonance component F c .
  • the common mode resonance component F c can represent the impedance of L 1 and C 1 connected in parallel and then in series with C 0 .
  • the common mode resonance component F c can be expressed by the parameters in Fig. 6, that is, the common mode resonance component F c can be expressed as:
  • the phase noise is the smallest when the tail inductor and capacitor resonate at twice the oscillation frequency.
  • the parasitic parameters C db , C gs , C gd , L dl , L c , C sb , C c and so on are connected to the "ground" in the AC, so accurate parameters between the power supply and the ground are required.
  • the inductance in the main resonant circuit and the tail inductance in the tail resonant circuit are respectively located on both sides of the power line and the ground line, and the distance between the power line and the ground line is reduced, which can accurately Make sure that the parameters between the power line and the ground wire are small, that is, ensure that the parasitic parameters such as C db , C gs , C gd , L dl , L c , C sb , and C c are connected to the AC "ground” to accurately determine these parasitics parameter. Therefore, by reasonably designing the resonant inductance L t and the tail capacitance C t , the phase noise of the oscillator can be reduced.
  • Fig. 8 is a schematic circuit diagram of an adjustable capacitor used in the main resonant circuit of a differential oscillator.
  • the differential oscillator can include a main oscillator circuit, a cross-coupled MOS tube, and a tail circuit.
  • the embodiment of the present application does not specifically limit the structure of the tail circuit.
  • the tail circuit can refer to the tail resonant circuit in Figure 1, and the tail circuit can also use a constant current source or other circuit structures.
  • the adopted differential oscillator with adjustable capacitance can adjust the oscillation frequency, making the oscillator suitable for a wider frequency range. But the adjustable capacitor introduces a larger phase noise.
  • the adjustable capacitor used in the main resonance circuit of the differential oscillator is a capacitor array including a plurality of capacitor units.
  • the adjustable capacitor includes N capacitor units, and N is a positive integer greater than or equal to 1.
  • Each capacitor unit of the capacitor array includes two varactor MOS transistors.
  • the process parameters of the two varactor MOS tubes are the same.
  • the variable capacitance MOS tube can form a voltage-controlled capacitor. It can be understood that the process parameters of the two varactor MOS tubes are the same, including the process parameters of the two varactor MOS tubes are approximately the same.
  • the substrates of the two varactor MOS transistors are connected to the same potential.
  • the source and drain of the two MOS transistors are both connected to the same potential, and the source and drain potentials of the two MOS transistors are controlled by the control voltage.
  • the two varactor MOS tubes can be arranged symmetrically.
  • the gate capacitances of the first variable capacitance MOS tube and the second variable capacitance MOS tube are connected to the circuit to form a part of the adjustable capacitance in the main resonance circuit.
  • Point N and Point P are the two output terminals of the differential oscillator respectively.
  • point N and Point P can be respectively Vo1 and Vo2 .
  • Point N and Point P are respectively connected to the gates of two varactor MOS transistors. The source and drain of the two MOS transistors are controlled by the switching voltage.
  • the control voltage may be represented by a switch (SW).
  • the control voltage can also be referred to as the switching voltage.
  • the two MOS transistors may both be N-channel MOS (n-channel MOS, NMOS) transistors, or both may be P-channel MOS (p-channel MOS, PMOS) transistors.
  • the signal output by each output terminal of the differential oscillator includes a DC signal and an AC signal.
  • the capacitance value of the variable capacitance MOS tube is related to the gate voltage of the variable capacitance MOS tube.
  • the gate voltage of the MOS tube is the voltage of the gate of the MOS tube.
  • the gate of the variable capacitance MOS tube is connected to the output terminal of the oscillator, and power supply noise may affect the voltage at the output terminal of the oscillator.
  • the voltage at the output of the oscillator is the gate voltage of the varactor MOS tube.
  • this application proposes a differential oscillator, which improves the adjustable capacitor, including the main resonance circuit and cross-coupled MOS transistors.
  • the main resonance circuit includes a first capacitor.
  • the first capacitor includes a first fixed capacitor, a first varactor MOS tube, a second varactor MOS tube, and a second fixed capacitor connected in series.
  • the first fixed capacitor is connected with the gate of the first varactor MOS transistor
  • the second fixed capacitor is connected with the gate of the second varactor MOS transistor.
  • the control voltage is the bias voltage of the source and drain of the first varactor MOS transistor and the source and drain of the second varactor MOS transistor.
  • the first bias voltage VB1 provides a DC bias for the gate of the first varactor MOS transistor
  • the second bias voltage VB2 provides a DC bias for the gate of the second varactor MOS transistor.
  • the sum of the capacitance values of the first fixed capacitor and the first variable capacitance MOS tube is equal to the sum of the capacitance values of the second variable capacitance MOS tube and the second fixed capacitance.
  • the first bias voltage and the second bias voltage are bias voltages obtained from the power supply voltage provided by the power supply line.
  • first bias voltage and the second bias voltage are the bias voltages obtained through the power supply voltage provided by the power supply line, which means that both the first bias voltage and the second bias voltage and the power supply line are powered by the chip.
  • the module provides electrical energy.
  • the first bias voltage and the second bias voltage may be obtained by converting the power supply voltage provided by the power line, or may be obtained by converting the voltage at a point between the power supply module and the power line.
  • the point between the power supply module and the power line may refer to a point on the interconnection line between the power supply module and the power line, or a point on the component between the power supply module and the power line.
  • the first fixed capacitor is connected with the gate of the first varactor MOS transistor
  • the second fixed capacitor is connected with the gate of the second varactor MOS transistor.
  • the control voltage is the bias voltage of the source and drain of the first varactor MOS transistor and the second varactor MOS transistor.
  • the first bias voltage provides a DC bias for the gate of the first varactor MOS tube
  • the second bias voltage provides a DC bias for the gate of the second variable capacitance MOS tube.
  • the fixed capacitor and the variable capacitance MOS tube are connected in series to divide the voltage, which can reduce the change in the gate voltage of the variable capacitance MOS tube caused by power supply noise. Therefore, the phase noise of the differential oscillator can be reduced.
  • FIG. 9 is a schematic structural diagram of a capacitor for a differential oscillator provided by an embodiment of the present application.
  • the capacitor used for the differential oscillator includes: the main resonance circuit, which is arranged on the chip; the main resonance circuit includes a first fixed capacitor, a first varactor MOS tube, a second varactor MOS tube, and a second fixed capacitor.
  • the first fixed capacitor is connected with the gate of the first varactor MOS transistor
  • the second fixed capacitor is connected with the gate of the second varactor MOS transistor.
  • the control voltage is the bias voltage of the source and drain of the first varactor MOS transistor and the source and drain of the second varactor MOS transistor.
  • the first bias voltage VB1 provides a DC bias for the gate of the first varactor MOS transistor
  • the second bias voltage VB2 provides a DC bias for the gate of the second varactor MOS transistor.
  • the sum of the capacitance values of the first fixed capacitor and the first variable capacitance MOS tube is equal to the sum of the capacitance values of the second variable capacitance MOS tube and the second fixed capacitance.
  • the gate capacitances of the first variable capacitance MOS tube and the second variable capacitance MOS tube are connected to the circuit, forming part of the first capacitance.
  • the control voltage controls the source and drain voltages of the first and second varactor MOS transistors, thereby controlling the gate capacitance of the first and second varactor MOS transistors.
  • the first varactor MOS transistor and the second varactor MOS transistor can both be N-channel MOS (n-channel MOS, NMOS), or both can be P-channel MOS (p-channel MOS, PMOS), or One is NMOS tube and the other is PMOS tube.
  • the control voltage can control the gate capacitance of the first varactor MOS transistor and the second varactor MOS transistor.
  • the gate capacitance of the MOS tube is the capacitance of the gate of the MOS tube.
  • the gate capacitance of the MOS tube includes a gate-source capacitance C gs , a gate-drain capacitance C gs , and a gate liner capacitance C gb in parallel.
  • the control voltage may also be called a switch (SW) or switch voltage.
  • SW is 0 means SW is low level, SW is 1 means SW is high level.
  • the low-level voltage can be the ground voltage.
  • the high-level voltage may be the voltage of the power line.
  • the fixed capacitor and the variable capacitance MOS tube are connected in series to divide the voltage, which can reduce the change in the gate voltage of the variable capacitance MOS tube caused by power supply noise. Therefore, the phase noise of the oscillator can be reduced.
  • the first bias voltage and the second bias voltage can be obtained by converting the output voltage of the power supply module. For example, it can be obtained by using one or more voltage conversion circuits.
  • the power supply module can provide power for other circuits in the chip.
  • the power supply voltage provided by the power supply module can be converted through the power management module.
  • a direct current (DC)-DC conversion circuit can convert the power supply voltage provided by the power supply module.
  • the DC-DC conversion circuit can be set on the chip.
  • the power cord is connected to the power supply module.
  • the first bias voltage VB1 and the second bias voltage VB2 may be bias voltages obtained from the power supply voltage provided by the power line. It should be understood that the first bias voltage and the second bias voltage are the bias voltages obtained through the power supply voltage provided by the power supply line, which means that both the first bias voltage and the second bias voltage and the power supply line are powered by the chip.
  • the module provides electrical energy.
  • the first bias voltage and the second bias voltage may be obtained by converting the power supply voltage provided by the power line, or may be obtained by converting the voltage at a point between the power supply module and the power line.
  • the point between the power supply module and the power line may refer to a point on the interconnection line between the power supply module and the power line, or a point on the component between the power supply module and the power line.
  • the above methods for obtaining the first bias voltage and the second bias voltage can all be understood as the first bias voltage and the second bias voltage are the bias voltages obtained by the power supply voltage provided by the power line.
  • the capacitance value of the series connection of the first fixed capacitor and the first variable capacitance MOS tube is equal to the capacitance value of the series connection of the second variable capacitance MOS tube and the second fixed capacitance. Equality can be understood as approximately equal.
  • the first variable capacitance MOS transistor and the second variable capacitance MOS transistor may be MOS transistors with the same or different process parameters.
  • the first bias voltage may be equal to the second bias voltage; if the first varactor MOS tube is different from the second variable capacitance MOS tube, the first bias voltage may be different from the second bias voltage.
  • the two ends N and P of the capacitor used for the differential oscillator can be respectively connected to the two output terminals of the differential oscillator.
  • the bias voltage can be connected to the gate of the varactor MOS transistor via a resistor. That is, the first bias voltage can be connected to the gate of the first varactor MOS transistor via a resistor, and the second bias voltage can be connected to the gate of the second varactor MOS transistor via a resistor.
  • the first bias voltage may be within the first voltage range. In the first voltage range, the gate capacitance of the first varactor MOS transistor under at least one control voltage does not change with the output voltage of the differential oscillator.
  • the second bias voltage may be in the second voltage range.
  • the gate capacitance of the second varactor MOS transistor under at least one control voltage does not change with the output voltage of the differential oscillator. If the process parameters of the first varactor MOS tube and the second varactor MOS tube are the same, the first voltage range is the same as the second voltage range.
  • FIG. 10 is a schematic structural diagram of a capacitor for a differential oscillator provided by an embodiment of the present application.
  • the capacitor used for the differential oscillator includes: a first fixed capacitor, a capacitor array, and a second fixed capacitor connected in series between the two differential output terminals of the differential oscillator.
  • the capacitor array includes a plurality of capacitor units. Each capacitor unit includes two varactor MOS transistors. The connection of a capacitor unit is explained.
  • the first fixed capacitor is connected to the gate of the first varactor MOS transistor, and the second fixed capacitor is connected to the gate of the second varactor MOS transistor.
  • the control voltage controls the bias voltages of the source and drain of the first varactor MOS transistor and the second varactor MOS transistor.
  • the bias voltage VB provides a DC bias for the gates of the first variable capacitance MOS transistor and the second variable capacitance MOS transistor.
  • the capacitance of the first fixed capacitor is equal to the capacitance of the second fixed capacitor.
  • the process parameters of the first varactor MOS tube and the second varactor MOS tube are the same.
  • the bias voltage may be in the first voltage range. In the first voltage range, the gate capacitance of the first varactor MOS transistor in at least one state of the control voltage does not change with the output voltage of the oscillator.
  • the bias voltage VB can be connected to the gates of the two MOS transistors via a resistor.
  • the source and drain of the two varactor MOS transistors are controlled by the switching voltage.
  • variable capacitance MOS tube works in a depleted state or an inverted state. In the depletion state and the inversion state, the gate capacitance of the varactor MOS transistor is different.
  • the two MOS transistors may both be N-channel MOS (n-channel MOS, NMOS) transistors, or both may be P-channel MOS (p-channel MOS, PMOS) transistors.
  • FIG. 11 is a schematic diagram of the relationship between the gate voltage and the gate capacitance of a varactor MOS tube.
  • V represents the gate voltage of the MOS tube
  • C represents the gate capacitance of the MOS tube.
  • the bias voltage of the gate of the varactor MOS transistor is within the range of A1 or A3
  • the case of SW is 0 and the case of SW of 1 have the same capacitance of the varactor MOS transistor gate, and it is impossible to realize the SW for the varactor MOS transistor gate capacitance. control. Therefore, in order to realize the digital control of the gate capacitance of the varactor MOS, the bias voltage of the varactor is set in the range of B1, A2 or B2. Equality can be approximately equal.
  • the two ends N and P of the adjustable capacitor are connected to the circuit respectively.
  • the two ends N and P of the adjustable capacitor can be respectively connected to the two output terminals of the differential oscillator.
  • the change of the power supply voltage will affect the voltages of N and P at both ends of the adjustable capacitor, that is, the power supply noise affects the gate voltage of the varactor MOS tube.
  • the gate capacitance of the varactor MOS tube changes with the change of the gate voltage of the varactor MOS tube.
  • Power supply noise will affect the output voltage of the oscillator, and then affect the gate voltage of the varactor MOS tube, which causes the capacitance of the varactor MOS tube to change and affects the oscillation frequency of the oscillator. Therefore, when SW is 1, and the bias voltage of the gate of the varactor MOS transistor in the range of B2 is used, the power supply noise will affect the oscillation frequency of the oscillator, that is, the power supply sensitivity of the oscillator is relatively high, and the phase noise is relatively large. .
  • the gate voltage and control voltage of the MOS tube can be two different input voltages.
  • the bias voltage of the gate of the MOS tube is almost independent of the control voltage SW. Therefore, when the gate of the varactor MOS transistor is biased within the range of B1 or B2, the phase noise is relatively large.
  • the gate capacitance of the varactor MOS tube may change slowly with the gate voltage, and there is no voltage range of A2.
  • FIG. 12 is a schematic diagram of the relationship between the gate voltage and the gate capacitance of a varactor MOS tube.
  • V represents the gate voltage of the MOS tube
  • C represents the gate capacitance of the variable capacitance MOS tube.
  • the bias voltage of the varactor is set in the range of B1, A2 or B2.
  • the bias voltage of the gate of the MOS tube is almost independent of SW. Therefore, when the gate bias of the varactor MOS transistor is within the range of C1, no matter whether SW is 0 or SW is 1, the phase noise of the differential oscillator is relatively large.
  • the voltage bias region in which the gate capacitance of the varactor MOS tube changes drastically with the gate voltage is a high power supply sensitive region (high k push region) for the oscillator, that is, a region with high power supply sensitivity.
  • the voltage range of the high power sensitive area can be determined by the voltage value of SW and the physical parameters of the varactor MOS transistor. For the situation shown in FIG. 12, the C1 range is a high power supply sensitivity region (high k push region).
  • the gate bias voltage of the varactor MOS tube can be reasonably designed to reduce the power supply.
  • the influence of noise on the oscillation frequency of the oscillator reduces the phase noise of the oscillator.
  • the bias voltage can be within the first voltage range.
  • the gate capacitance of the first varactor MOS tube in at least one state of the control voltage does not change with the output voltage of the oscillator; the control voltage is used to control the first variable
  • the control voltage can be referred to as SW.
  • the state of the control voltage may include a state where SW is 0 or SW is 1. According to the voltage value of the control voltage, the state of the control voltage may also include other states. The embodiments of this application do not limit this.
  • Fig. 13 is a differential oscillator provided by an embodiment of the present application.
  • the oscillator uses tail inductance resonance technology.
  • the oscillator includes a power line 311 and a ground line 331, a main resonance circuit 110, a tail resonance circuit 120, and a voltage regulator 1303.
  • the power cord 311 is provided on the chip.
  • the ground line 331 is provided on the chip and is parallel to the power line 311.
  • the power line 311 and the ground line 331 divide the chip area where the differential oscillator is located into a first part located between the power line 311 and the ground line 331, a second part and a second part located on both sides of the power line 311 and the ground line 331, respectively. three parts.
  • the voltage provided by the power supply module of the chip can be connected to the power line after passing through the voltage regulator 1303. It supplies power to the entire oscillator circuit and provides a stable voltage bias.
  • the voltage regulator 1303 may be a low dropout regulator (LDO) or the like. LDO can output ultra-low noise voltage. After the voltage provided by the power supply module passes through the voltage stabilizer 1303, the noise is small.
  • LDO low dropout regulator
  • the main resonance circuit is provided on the chip.
  • the main resonance circuit may include a first capacitor 341, and the first capacitor 341 may be an adjustable capacitor.
  • the main resonance circuit may include a first inductor 321 and a second inductor 322 having the same inductance value.
  • the first adjustable capacitor 1301 and the second adjustable capacitor 1302 in the adjustable capacitor are connected in parallel.
  • the first inductor 321 and the second inductor 321 are arranged in the second part.
  • the first inductor 321 and the second inductor 322 are arranged on the side of the power line 311 away from the ground line 331.
  • the first inductor 321 and the second inductor 322 in the main resonance circuit may be arranged symmetrically. Symmetry includes approximate symmetry.
  • the first inductor 321 and the second inductor 322 may be respectively arranged in a surrounding shape such as an octagon or a hexagon.
  • the first inductor 321 and the second inductor 322 may also form an octagonal or hexagonal surrounding shape together, and the lower edge of the surrounding shape may not be connected.
  • the first adjustable capacitor 1301 in the main resonance circuit can refer to the capacitor structure shown in FIG. 14.
  • the second adjustable capacitor 1302 in the main resonance circuit can refer to the capacitor structure shown in FIG. 10.
  • the tail resonance circuit includes a tail inductor and a tail capacitor 342.
  • the tail resonance circuit is arranged on the chip.
  • the tail inductor includes a tail inductor main body 323 and a tail inductor connecting portion 326.
  • the tail inductor main body 323 is disposed in the third part.
  • the tail inductor main body 323 is disposed on a side of the ground line 331 away from the power line 311.
  • the tail inductor connecting portion 326 is used to connect the tail inductor main body 323 and the tail capacitor.
  • the tail inductor body 323 may be arranged in a surrounding shape such as an octagon or a hexagon.
  • the main resonance circuit includes a negative resistance 111, which can be a cross-coupled MOS transistor.
  • the process parameters of the first MOS tube 351 and the second MOS tube 352 are the same, and they are cross-coupled.
  • Cross-coupled MOS transistors can be used as negative resistance.
  • the cross-coupled MOS tube can be equivalent to a linear negative resistance.
  • the cross-coupled MOS tube can provide energy for the main resonant circuit, compensate the loss of the main resonant circuit, and maintain oscillation.
  • the cross-coupled MOS device 111 may be provided on the chip.
  • a capacitor can be formed on the chip as the capacitor in the main resonant circuit and/or the capacitor in the tail resonant circuit.
  • a MOM capacitor or MIM capacitor can be formed on the chip using the above-mentioned layout.
  • the distance between the ground wire and the power wire may be less than or equal to the first preset value.
  • the decoupling capacitor can be set in the first part.
  • the main resonant circuit and the tail resonant circuit can be reasonably designed to make the tail resonant circuit resonate at twice the oscillation frequency and reduce the phase noise.
  • the tail inductor connection part 326 is arranged in parallel with the ground line 331, and the tail inductor connection part is used to connect the tail inductor main body 323 and other components in the oscillator.
  • the tail inductor connection part can be used for the tail inductor main body 323 and the tail capacitor 342 to cross-couple. MOS tube connection.
  • the tail inductor connecting portion 326 is located between the tail inductor main body 323 and the ground wire 331.
  • Fig. 14 is a schematic circuit diagram of an adjustable capacitor of a differential oscillator.
  • the size of the capacitor C can be changed by digital control.
  • "0" is usually used for low level and "1" for high level.
  • the low level can be the "ground” in the circuit, that is, the zero potential, and the high level can be the power supply voltage.
  • the adjustable capacitor includes two fixed capacitors and a MOS tube as a voltage-controlled capacitor.
  • MOS is controlled by SW.
  • the MOS tube can be a switch MOS tube to realize a voltage-controlled capacitor.
  • the capacitance C ds between the source and drain of the MOS tube is connected in series with two fixed capacitances.
  • the gate of the MOS tube is controlled by SW.
  • the SW is connected to the gate of the MOS tube through a two-stage inverter, which can improve the driving capability of the SW.
  • the voltage of the source and drain of the MOS tube is controlled by SW.
  • the SW is connected to the source and drain of the MOS tube through a stage inverter.
  • the point N and the point P are respectively connected to the first inductor 321 and the second inductor 322 of the main resonance circuit, that is, the point N and the point P are respectively connected to the two output terminals of the differential oscillation circuit.
  • a fixed capacitor is connected to point N and point P respectively.
  • the two fixed capacitors can be MOM capacitors or other types of capacitors. Two fixed capacitors are respectively connected to the source and drain of the MOS tube.
  • the MOS is controlled by SW.
  • the MOS tube can be a switching MOS tube.
  • the MOS tube When the MOS tube is turned on, the impedance between the source and drain of the MOS tube is very small, and the MOM capacitor is connected in series to the circuit, and the capacitance value is large.
  • the MOS transistor When the MOS transistor is turned off, the impedance between the source and drain of the MOS transistor is very large.
  • the MOM and the capacitance and the parasitic capacitance C ds of the MOS are connected to the circuit. Since the capacitance value of C ds is small, the capacitance between point N and point P Smaller.
  • the size of the adjustable capacitor is controlled by the switch to change the frequency and complete the function of digital control of the frequency.
  • FIG. 15 is a schematic diagram of a test result of a differential oscillator provided by an embodiment of the application. Test the differential oscillator provided in Figure 13, and the test results are shown in Figure 15. The frequency of this oscillator can cover 2.33GHz ⁇ 3.07GHz. When the frequency of the oscillator is 3GHz, the measured value of phase noise at 800kHz offset frequency is -130dBc/Hz. Achieved the industry's best oscillator phase noise results.
  • the embodiment of the present application provides a chip including the differential oscillator described above.
  • At least one refers to one or more
  • multiple refers to two or more.
  • And/or describes the association relationship of the associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean that A exists alone, A and B exist at the same time, and B exists alone. Among them, A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects are in an “or” relationship.
  • “The following at least one item” and similar expressions refer to any combination of these items, including any combination of single items or plural items.
  • At least one of a, b, and c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

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Abstract

本申请提供了一种差分振荡器，包括：电源线，设置在芯片上；地线，设置在所述芯片上，并且与所述电源线平行；主谐振电路，设置在所述芯片上，包括：并联的第一电感和第二电感，所述第一电感和所述第二电感设置在所述电源线远离所述地线的一侧；所述主谐振电路与所述电源线连接；尾谐振电路，设置在所述芯片上，与所述主谐振电路和所述地线连接。通过将振荡器中电感设置在电源线和地线的两侧，保证电源线和地线均为交流"地"，能够减小振荡器的相位噪声。

Description

一种差分振荡器 技术领域
本申请涉及电路领域，更具体地，涉及一种差分振荡器。
背景技术
时钟是通信系统的重要组成部分。高精度通信系统对时钟的精确度要求较高。振荡器可以用于产生电路的时钟。高质量的振荡器对实现高精度通信具有重要作用。传统采用尾电感谐振技术的差分振荡器，对于交流信号，不能保证振荡器电路中的电源线和地线均为交流“地”，即电源线和地线之间的交流阻抗较大。振荡器电路中，主谐振电路的电容和电感、尾谐振电路中的电容和电感、交叉耦合金属氧化物半导体(metal-oxide-semiconductor，MOS)器件的衬底与电源或地连接，电源线和地线之间较大的交流阻抗导致不能精确地确定的电路中元件的交流阻抗，从而很难保证尾谐振电路谐振在主谐振电路振荡频率的2倍，造成了差分振荡器较大的相位噪声。
发明内容
本申请提供一种差分振荡器，通过将差分振荡器中电感设置在电源线和地线的两侧，减小了电源线和地线之间的距离，从而能够保证电源线和地线均为交流“地”，能够减小差分振荡器的相位噪声。
第一方面，提供一种差分振荡器，包括：电源线，设置在芯片上；地线，设置在芯片上，并且与电源线平行；主谐振电路，设置在芯片上，包括第一电感和第二电感，第一电感和第二电感设置在电源线远离地线的一侧；主谐振电路与电源线连接；尾谐振电路，设置在芯片上，与主谐振电路和地线连接。
与传统的差分振荡器在电源线和地线之间设置主谐振电路的电感和尾谐振电路的电感的布局方式相比，本申请实施例通过将主谐振电路的电感布置在电源线远离地线的一侧，可以减小电源线和地线之间的距离。较小的距离使得电源线和地线之间设置去耦电容产生的寄生参数的阻抗较小，从而能够减小地线和电源线之间的交流阻抗，使得地线和电源线更加接近交流“地”。差分振荡器中的器件很多与电源线或地线连接。地线和电源线之间存在较小的交流阻抗，才能够较为精确地确定差分振荡器中的器件的交流寄生参数。通过合理设计，能够使得尾谐振电路的振荡频率与主谐振电路的振荡频率的2倍差值减小，减小振荡器的相位噪声。地线和电源线之间的距离较小，减小了差分振荡器对去耦电容的需求。
结合第一方面，在一些可能的实现方式中，尾谐振电路包括：尾电感，尾电感包括尾电感主体和尾电感连接部，尾电感主体设置在地线远离电源线的一侧，尾电感连接部用于连接尾电感主体和主谐振电路。通过将主谐振电路和尾谐振电路分别设置在电源线和地线的两侧，进一步减小电源线和地线之间的距离，减小振荡器的相位噪声。
结合第一方面，在一些可能的实现方式中，所述地线和所述电源线之间的距离小于或等于第一预设值。
结合第一方面，在一些可能的实现方式中，差分振荡器还包括：去耦电容，所述去耦电容设置在地线和电源线之间，并与电源线和地线连接。将去耦电容设置在地线和电源线之间，工艺上容易实现，能够减小寄生效应，同时能够减小对芯片面积的占用。地线和电源线之间通过较小的去耦电容就可以满足电路设计要求。较小的去耦电容占用面积较小，减小了对芯片资源的占用。
结合第一方面，在一些可能的实现方式中，尾电感连接部与地线平行布置，尾电感连接部位于尾电感主体与地线之间的部分。
结合第一方面，在一些可能的实现方式中，差分振荡器还包括：交叉耦合金属氧化物半导体MOS管。交叉耦合MOS管用于为主谐振电路提供负阻。
结合第一方面，在一些可能的实现方式中，主谐振电路包括第一电容，第一电容包括串联的第一固定电容、第一变容MOS管、第二变容MOS管、第二固定电容；第一固定电容、第一变容MOS管的电容值之和等于第二变容MOS管、第二固定电容的电容值之和；第一固定电容与第一变容MOS管的栅极连接，第二固定电容与第二变容MOS管的栅极连接；控制电压为第一变容MOS管和第二变容MOS管的源极和漏极的偏置电压；第一偏置电压为第一变容MOS管的栅极提供直流偏置，第二偏置电压为第二变容MOS管的栅极提供直流偏置，所述第一偏置电压和所述第二偏置电压为通过所述电源线提供的电源电压得到的偏置电压。通过固定电容与变容MOS管串联，实现了固定电容与变容MOS管分压，可以减小电源噪声对变容MOS管的栅电容的影响，从而减弱电源噪声对振荡器频率的影响，降低相位噪声。
结合第一方面，在一些可能的实现方式中，所述第一偏置电压在第一电压范围内时，在所述控制电压的至少一种电压值状态下的所述第一变容MOS管的栅电容不随所述第一固定电容与所述第一电感连接的一端的电压变化。通过将变容MOS管的栅电压偏置在第一电压范围，可以减小电源噪声对变容MOS管的栅电容的影响，从而减弱电源噪声对振荡器频率的影响，降低相位噪声。
结合第一方面，在一些可能的实现方式中，第一固定电容与第一固定电容的容值相等，第一变容MOS管与第二变容MOS管工艺参数相同，第一偏置电压与第二偏置电压相等。
第二方面，提供一种差分振荡器，包括：主谐振电路；主谐振电路包括在振荡器的两个差分的输出端之间串联的第一固定电容、第一变容金属氧化物半导体MOS管、第二变容MOS管、第二固定电容；第一固定电容与第一变容MOS管的栅极连接，第二固定电容与第二变容MOS管的栅极连接；控制电压控制第一变容MOS管和第二变容MOS管的源极和漏极的偏置电压，所述第一偏置电压和所述第二偏置电压为通过所述电源线提供的电源电压得到的偏置电压；第一偏置电压为第一变容MOS管的栅极提供直流偏置，第二偏置电压为第二变容MOS管的栅极提供直流偏置。
在传统的差分振荡器中，变容MOS管形成的电容阵列形成了主振荡电路中的电容。电源线上的噪声会影响变容MOS管的栅极电压，从而导致变容MOS管的电容变化，引起较大的相位噪声。本申请实施例通过增加固定电容与变容MOS管串联，实现了固定电容与变容MOS管分压。可以减小电源噪声对变容MOS管的栅电容的影响，从而减弱电 源噪声对振荡器频率的影响，降低相位噪声。
结合第二方面，在一些可能的实现方式中，第一偏置电压在第一电压范围内时，在在控制电压的至少一种状态下的第一变容MOS管的栅电容不随差分振荡器的输出电压变化。
结合第二方面，在一些可能的实现方式中，第一固定电容与第一固定电容的容值相等，第一变容MOS管与第二变容MOS管相同，第一偏置电压与第二偏置电压相等。
结合第二方面，在一些可能的实现方式中，差分振荡器还包括：交叉耦合金属氧化物半导体MOS管。交叉耦合MOS管用于为主谐振电路提供负阻。
结合第二方面，在一些可能的实现方式中，差分振荡器还包括：电源线，设置在芯片上；地线，设置在芯片上，并且与电源线平行；主谐振电路还包括：第二电感，第一电感和第二电感设置电源线远离地线的一侧；主谐振电路与电源线连接；尾谐振电路，设置在芯片上。
结合第二方面，在一些可能的实现方式中，尾谐振电路包括：尾电感，尾电感包括尾电感主体和尾电感连接部，尾电感主体设置在地线远离电源线的一侧，尾电感连接部用于连接尾电感主体和主谐振电路。
结合第二方面，在一些可能的实现方式中，地线和电源线之间的距离小于或等于第一预设值。
结合第二方面，在一些可能的实现方式中，差分振荡器还包括：去耦电容，去耦电容设置在地线和电源线之间，并与电源线和地线连接。
结合第二方面，在一些可能的实现方式中，尾电感连接部与地线平行布置，尾电感连接部位于尾电感主体与地线之间。
第三方面，提供一种芯片，包括前文所述的差分振荡器。
附图说明
图1是一种采用尾电感谐振技术的差分振荡器的电路结构示意图。
图2是一种采用尾电感谐振技术的差分振荡器的电路结构的寄生参数的示意图。
图3是本申请一个实施例提供的一种差分振荡器的电路结构和布局的示意图。
图4是本申请另一个实施例提供的一种差分振荡器的电路结构和布局的示意图。
图5是一种采用尾电感谐振技术的差分振荡器的尾部谐振网络的交流等效电路示意图。
图6是另一种采用尾电感谐振技术的差分振荡器的尾部谐振网络的交流等效电路示意图。
图7是又一种采用尾电感谐振技术的差分振荡器的尾部谐振网络的交流等效电路示意图。
图8是一种差分振荡器的可调电容的电路示意图。
图9是本申请一个实施例提供的一种可调电容的电路示意图。
图10是本申请另一个实施例提供的一种可调电容的电路示意图。
图11是一种MOS管栅压与栅电容的关系的示意图。
图12是另一种MOS管栅压与栅电容的关系的示意图。
图13是本申请又一个实施例提供的一种差分振荡器的电路结构和布局的示意图。
图14是一种用于差分振荡器的可调电容的电路示意图。
图15是对本申请一个实施例提供的差分振荡器的测试结果的示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
时钟是通信系统的重要组成部分。时钟的主要作用包括：(1)和混频器共同作用，完成信号的上下变频；(2)为模数转换器(analog to digital converter，ADC)、数模转换器(digital to analog converter、DAC)提供采样时钟，完成数模信号转换。振荡器是实现高质量时钟的核心部分。无论高质量通信还是高精度ADC/DAC都对高性能的振荡器提出了严格的要求。振荡器可以是压控振荡器(voltage controlled oscillator，VCO)或数控振荡器(digital controlled oscillator，DCO)等。实现高质量时钟的振荡器对高精度通信系统至关重要。
图1是一种传统采用尾电感谐振技术的差分振荡器的电路结构示意图。
采用尾电感谐振技术的差分振荡器电路包括主谐振电路110，尾谐振电路120。主谐振电路110包括负阻111，负阻111包括交叉耦合的金属氧化物半导体(metal-oxide-semiconductor，MOS)场效应晶体管(field effect transistor，FET)。MOSFET也称为MOS晶体管、MOS管或MOS器件。主谐振电路110可以包括第一电容C，电感值相等的第一电感L c1和第二电感L c2。尾谐振电路120可以包括尾电感L t，尾电容C t。
交叉耦合的MOS管等效为线性负电阻，并为主谐振电路110提供能量，补偿主谐振电路110的损耗，维持振荡。
不考虑工艺偏差，可以将主谐振电路110看作是结构对称的两部分。L c1＝L c2，C＝C c1+C c2，C c1＝C c2。C c1与C c2连接处的电压可以看作是交流信号的地，即C c1与C c2连接处对于交流信号电压为0。一个谐振电路包括L c1-C c1，另一个谐振电路包括L c2-C c2，两个谐振电路的谐振频率相等，该谐振频率可以称为主谐振电路110的振荡频率。对于交流信号，L c1和C c1一端接地，另一端为输出电压V o1；L c2和C c2一端接地，另一端为输出电压V o2。V o1与V o2处的直流电压相等，交流电压的振幅相等，相位相反。
尾谐振电路120可以包括尾部电感和电容。尾谐振电路120的振荡频率为主谐振电路110的振荡频率的2倍。当尾谐振电路120的振荡频率偏离主谐振电路110的振荡频率的2倍，随着尾谐振电路120的振荡频率与主谐振电路110的振荡频率的2倍之间的差距增大，振荡器的相位噪声增加。
图2传统的采用尾电感谐振技术的差分振荡器的电路布局的示意图。
在传统的采用尾电感谐振技术的差分振荡器的电路布局中，与电源连接的部分210包括电源线211、电源线连接部212。电源线连接部212可以用于电源线211与差分振荡器其他部件的连接。
电感220包括第一电感、第二电感、尾电感。第一电感包括第一电感主体221、第一电感连接部224。第二电感包括第二电感主体222、第二电感连接部225。尾电感包括尾电感主体223、第一尾电感连接部226。第一电感连接部224可以用于连接第一MOS管。第二电感连接部225可以用于连接第二MOS管。第一尾电感连接部226可以用于连接尾 电感主体223和尾电容。第一尾电感连接部226还可以用于将电感主体223与第一MOS管、第二MOS管连接。尾电感还可以包括第二尾电感连接部227，用于连接尾电感主体223和第一尾电感连接部226。第一尾电感连接部226可以经第二尾电感连接部227连接尾电感主体223和尾电容。
与地连接的部分230包括地线231、地线连接部232。地线连接部232可以用于地线231与差分振荡器其他部件的连接。例如，地线连接部232可以用于地线231与尾电感223、地线231与尾电容的连接。
电源线211与地线231之间布置有第一电感221、第二电感222、尾电感223、电容、MOS管等器件，电源线211与地线231距离较远。电源线211通过电源连接部212与第一电感221、第二电感222连接。地线231通过地连接部232与尾电感223连接。为了减小电源线与地线的交流阻抗，需要在电路的周围布置很大的去耦电容。较大的去耦电容占用了较多的面积，浪费芯片的资源。并且由于寄生效应，对于交流信号，很难保证电源线和地线的电压均为0。也就是说，无法保证电源线和地线均为交流“地”。“布置”也可以理解为“设置”、“放置”、“配置”等，可以表示元器件位于芯片上，还可以表示元器件之间的位置关系。
尾谐振电路120可以包括尾电感223和尾电容。尾谐振电路120的振荡频率为主谐振电路110的振荡频率的2倍时，相位噪声最小。无法保证电源线和地线均为交流“地”，将导致无法精确设计电路中的尾谐振电路，产生较大的相位噪声。
为了解决上述问题，本申请提出了一种差分振荡器，能够获得精确的振荡器的寄生参数，从而可以通过合理设计减小振荡器的相位噪声。
图3是本申请实施例提供的一种差分振荡器的电路结构和布局的示意图。
差分振荡器包括电源线311，地线331，主谐振电路110，尾谐振电路120。在本申请实施例中，振荡器是差分振荡器。
差分振荡器位于芯片上。
电源线311，设置在芯片上。
地线331，设置在芯片上，并且与电源线311平行。地线331与电源线311平行，可以理解为地线331与所述电源线311近似平行。
主谐振电路110，设置在芯片上，包括：第一电感321和第二电感322，主谐振电路与电源线连接。
尾谐振电路120，设置在芯片上。尾谐振电路120与所述主谐振电路和所述地线连接。
应当理解，本申请中的“连接”指电连接。A与B连接，是指A与B电连接，即A与B之间可以经互连线连接，或A与B之间连接有其他元器件，如A经过C与B连接。芯片中元器件通过互连线连接。互连线也可以称为导线、互连导线、金属线等。
尾谐振电路120包括：尾电感、尾电容341，尾电感包括尾电感主体323和尾电感连接部326。尾电感连接部326用于连接尾电感主体323和尾电容。
尾电感连接部326还可以用于连接尾电感主体323和主谐振电路。
可以理解，所述电源线311和所述地线331将差分振荡器所在的芯片区域划分为位于所述电源线和所述地线之间的第一部分、分别位于电源线311和地线331两侧的第二部分和第三部分。
在一种可能的实现方式中，所述第一电感和所述第二电感可以位于所述第二部分。尾电感主体323可以位于第二部分或第三部分。尾电感主体323位于第三部分，可以进一步减小电源线311与地线331之间的距离，即使得电源线311与地线331更接近于交流“地”。下文以尾电感主体323设置在所述地线远离所述电源线的一侧，即尾电感主体323位于第三部分为例进行说明。
第二部分可以是远离电源线311的一侧，第三部分可以是远离地线331的一侧。或者，第三部分可以是远离电源线311的一侧，第二部分可以是远离地线331的一侧。下文中以第二部分是远离地线331的一侧，第三部分是远离电源线311的一侧为例进行说明。也就是图3所示，第一电感321和第二电感322设置在电源线311远离地线331的一侧，尾电感主体323设置在所述地线远离所述电源线的一侧的情况。
第一电感321、第二电感322、尾电感主体323分别位于地线331和电源线311的两侧，地线331和电源线311之间的距离可以很小，产生了较大的电容。
对于交流信号，地线331和电源线311之间的阻抗较小。即可以保证地线331和电源线311均为交流“地”。
地线331和电源线311之间的距离可以很小，在电源线311与地线331之间布置去耦电容，产生的寄生参数较小，使得地线331和电源线311更加接近交流“地”。地线331和电源线311之间的距离可以很小，减小了差分振荡器对去耦电容的需求。地线331和电源线311之间通过较小的去耦电容就可以满足电路设计要求。较小的去耦电容占用面积较小，减小了对芯片资源的占用。
差分振荡器中的器件很多与地线331或电源线311相连，例如主谐振电路的电容和电感、尾谐振电路中的电容和电感、交叉耦合MOS器件的衬底等。地线331和电源线311接近交流“地”，从而可以更加准确地确定差分振荡器中的与地线331或电源线311连接的元器件的寄生参数。通过合理设计，能够使得尾谐振电路的振荡频率与主谐振电路110的振荡频率的2倍差值减小，减小振荡器的相位噪声。
可选地，地线331和电源线311之间的距离小于或等于第一预设值。地线331和电源线311之间的距离也可以理解为所述第一部分的宽度。
可选地，差分振荡器可以包括去耦电容。去耦电容用于增加电源线311和地线331之间的电容值，从而减小电源线311和地线331之间相对于交流信号的阻抗。去耦电容的两端分别连接电源线311和地线331。通过布置去耦电容，可以减小电源线311和地线331之间的交流阻抗，使得电源线311和地线331更接近于交流“地”。
本申请实施例对去耦电容的位置不作限定，去耦电容例如可以设置在第一部分、第二部分或第三部分。去耦电容可以是金属-氧化物-金属(metal-oxide-metal，MOM)电容、金属-绝缘体-金属(metal-insulator–metal，MIM)电容或多晶硅-绝缘体-多晶硅(polysilicon-1nsulator-polysilicon，PIP)电容等。通过MOM电容形成去耦电容，可以减小电容占用的面积。去耦电容设置在所述地线和所述电源线之间，即去耦电容设置在第一部分，工艺上容易实现，减小寄生效应，同时能够减小对芯片面积的占用。
临近布置的电源线311和地线331之间会产生较大的电容，从而可以减小对于去耦电容的需求。在电源线和地线周围布置较小的去耦电容，就能够使得电源线311和地线331之间的交流阻抗满足电路设计的需求。
尾电容可以为MOM电容、MIM电容、或PIP电容等。
可选地，尾电感连接部326与地线331平行布置。平行可以是近似平行。平行布置电感连接部326与地线331，降低尾电容的工艺实现难度。尾电感连接部326可以位于第一部分、第二部分或第三部分。尾电感连接部326位于所述第三部分中所述尾电感与所述地线之间的部分，可以降低尾电容的工艺实现难度，减少尾电容占用的面积。
差分振荡器中的主谐振电路还包括交叉耦合的MOS器件。交叉耦合连接的第一MOS管351与第二MOS管352可以作为差分振荡器的负阻。第一MOS管351与第二MOS管352的工艺参数相同。交叉耦合的MOS管可以等效为线性负电阻。交叉耦合的MOS管可以为主谐振电路110提供能量，补偿主谐振电路110的损耗，维持振荡。
MOS器件是四端器件，包括源极(source)、漏极(drain)、栅极(gate)、衬底(bulk)。第一MOS管351和第二MOS管352可以均为N沟道MOS(n-channel MOS，NMOS)管，也可以均为P沟道MOS(p-channel MOS，PMOS)管。NMOS管的衬底连接至芯片的低电位，即连接至“地”。NMOS管的衬底可以与地线331连接。PMOS管的衬底连接至高电位，即连接至电源电压。NMOS管的衬底可以与电源线311连接。如图3所示，如果第一MOS管351和第二MOS管352为NMOS管，第一MOS管351和第二MOS管352的源极连接尾谐振电路，衬底接地，即衬底连接地线331，漏极分别连接主谐振电路中的第一电感321和第二电感322，第一MOS管351的栅极连接第二MOS管352漏极，第二MOS管352的栅极连接第一MOS管351的漏极。如果第一MOS管351和第二MOS管352为PMOS管，第一MOS管351和第二MOS管352的衬底连接电源电压，即与电源线311连接，源极与电源线311连接，漏极分别连接主谐振电路中的第一电感321和第二电感322，第一MOS管351的栅极连接第二MOS管352漏极，第二MOS管352的栅极连接第一MOS管351的漏极。
MOS器件的寄生电容包括：漏极和衬底之间的漏衬电容C db，栅极和源极之间的栅源电容C gs，栅极和源极之间的栅漏电容C gd，源极和衬底之间的源衬电容C sb等。
差分振荡器还可以包括第一电感连接部324，第二电感连接部325，尾电感连接部326。第一电感连接部324可以用于将第一电感321与其他部件连接，例如将第一电感321与第一MOS管连接。第二电感连接部325可以用于将第一电感322与其他部件连接，例如将第二电感322与第二MOS管连接。
电感部件310可以包括第一电感321、第二电感322、尾电感主体323、第一电感连接部324，第二电感连接部325，尾电感连接部326。电感部件310可以位于相同或不同的金属层。电感部件320中的每一个部件也可以位于相同或不同的金属层。例如尾电感主体323中部分金属可以位于与地线连接部332相同的金属层，另一部分可以位于与地线连接部332不同的金属层。
尾电感还可以包括连接部327，用于连接尾电感主体323和尾电感连接部326。
本申请实施例对于第一电感连接部324，第二电感连接部325，尾电感连接部326的位置不作限定。以第一电感连接部324为例，第一电感连接部324可以位于第二部分。此时，第一电感连接部324可以与电源部件310、第一电感321位于相同或不同的金属层。第一电感连接部324可以部分位于第二部分，部分位于第一部分。此时，第一电感连接部324可以与电源线311位于不同的金属层。
电源部件310可以包括电源线311、电源线连接部312。电源部件310可以位于相同或不同的金属层。
地线部件330可以包括地线331、地线连接部332。地线部件330可以位于相同或不同的金属层。
电源部件310与地线部件330可以布置在相同或不同的金属层。考虑到金属线的线宽小于金属层的厚度，电源线311和地线331位于相同的金属层，第一部分的宽度W相同时，可以减小电源线311和地线331之间的实际距离，增加电源线311和地线331之间的寄生电容。
电源部件310、地线部件330、第一电感321、第二电感322、尾电感主体323位于相同的金属层，可以减小振荡器中的金属层数量，减小互连寄生参数，降低制造成本。电源部件310、地线部件330、电感部件310可以尽可能位于同一金属层。
主谐振电路110中的第一电感321和第二电感332的电感值相等。第一电感321和第二电感332可以对称布置。第一电感321和第二电感332可以分别布置为八边形或六边形等环绕的形状。
第一电感321和第二电感332也可以共同形成一个八边形或六边形等环绕的形状。对于第一电感321和第二电感332，与电源线连接部312的连接的位置可以是电感的一端，与交叉耦合MOS器件连接的位置可以是电感的另一端。
主谐振电路110包括第一电容341。第一电容341可以是可调电容。第一电容341可以是可调电容，可以实现VCO/DCO。本申请实施例对可调电容的结构不作限定，可以采用现有的或将来可能出现的各种电容结构。下文会结合具体的实施例进行详细描述，此处暂不详述。
第一电容341可以包括固定电容。固定电容可以为MOM电容、MIM电容、或PIP电容等。本申请实施例对第一电容341的位置不作限定。第一电容341可以位于芯片的任意位置。
可选地，第一电容中的固定电容可以位于第二部分。固定电容可以是MOM电容，构成第一电容的金属线可以与电源线311平行布置。固定电容采用上述布局方式，可以提高芯片面积的利用率。
第一电感、第二电感、尾电感可参考如图2、图3所示的单圈电感，即构成第一电感、第二电感的金属线可以近似环绕一圈，构成尾电感的金属线可以布置为近似环绕一圈。
图4是本申请实施例提出的一种差分振荡器的电路结构和布局的示意图。
第一电感、第二电感、尾电感也可采用双圈电感或多圈，即构成第一电感、第二电感的金属线可以近似环绕两圈或多圈，构成尾电感的金属线可以近似环绕两圈或多圈。
相对于单圈电感，第一电感、第二电感采用双圈电感、多圈，第一电感、第二电感的共模电感较低。根据共模谐振分量F c的表达式，共模电感降低，可以减弱共模谐振分量F c与频率的关系，有利于差分振荡器的设计。
尾电感连接部326与地线331平行布置。平行可以是近似平行。平行布置的电感连接部326与地线331，降低尾电容的工艺实现难度。尾电感连接部326可以位于所述第三部分中所述尾电感与所述地线之间的部分，可以降低尾电容的工艺实现难度，减少尾电容占用的面积。
图5是采用尾电感谐振技术的差分振荡器的电路结构的寄生参数的示意图。
对于图2、图3、图4中的采用尾电感谐振技术的差分振荡器，在实际生产的电路中，由于制造工艺的影响，会产生大量的寄生参数。
在差分振荡器的电路结构中，差分振荡器的电源线电压可以用V dl表示，差分振荡器的地电压可以用V sl表示。差分振荡器的电源线和供电模块之间的电感可以用L dr表示，差分振荡器的地线和芯片的地之间的电感用L sr表示。振荡器的电源线和电感引出端的寄生电感用L dl表示；L c表示差分振荡器的谐振电感的共模分量，可以表示图1中电感L c1和L c2的电感值，即L c1＝L c2＝L c；C c表示差分振荡器谐振电容的共模分量，可以表示图1中电容C的电容值的二分之一；C d表示去耦电容(decoupling capacitor，decap)，去耦电容是电路的电源和电路的地之间的耦合电容；尾电容C t、尾电感L t是尾部谐振网络的调谐部分。供电模块为差分振荡器的电源线提供电能。供电模块的输出可以作为差分振荡器的电源线的电源电压，即供电模块的输出端可以经互连导线连接至差分振荡器的电源线的电源电压。供电模块的输出端也可以经过DC-DC转换器、低压差线性稳压器(low dropout regulator，LDO)等之后连接至差分振荡器的电源线。
作为负阻的交叉耦合的MOS管，其寄生参数对差分振荡器的性能产生较大影响。
通过采用图3中的差分振荡器电路的布局，可以从而能够精确的确定电源线与地线之间的寄生参数。MOS管的多个寄生参数与电源线与地线连接。精确的确定电源线与地线之间的寄生参数，可以精确地确定差分振荡器中的交叉耦合MOS管的寄生参数，从而可以通过合理设计，能够使得尾谐振电路的振荡频率与主谐振电路的振荡频率的2倍差值减小，减小振荡器的相位噪声。
采用尾电感谐振技术的差分振荡器，通过尾部电感和电容谐振在2倍的振荡频率，实现振荡器的功能。尾部电感和电容的振荡频率与2倍的振荡频率越接近，振荡器的相位噪声越小。下面分析寄生参数对振荡器的性能产生的影响。
图6是传统采用尾电感谐振技术的差分振荡器的尾部谐振网络的交流等效电路示意图。C sb表示交叉耦合负阻MOS器件的源极和衬底之间的寄生电容，C gs表示MOS的栅极和源极之间的寄生电容，C gd表示MOS的栅极和源极之间的寄生电容，C db表征MOS的漏极和衬底之间的寄生电容。用C 0表示寄生电容2C gs与2C gd串联连接后再与2C gs并联的电容值，用C 1表示2C db与2C c并联的电容值，L 1表示L c/2与L dl串联的电感值。尾部谐振网络的交流等效电路可以用图6的电路结构表示。
图7是一种采用尾电感谐振技术的差分振荡器的尾部谐振网络的交流等效电路示意图。图5是图3、图4中交流等效电路的简化结构。图6对图5中的结构进一步简化。尾部谐振网络，包括并联的尾部谐振电感L tail，附加电容C t，寄生电容C sb，和共模谐振分量F c。共模谐振分量F c可以表示L 1与C 1并联连接后再与C 0串联的阻抗。共模谐振分量F c可以用图6中的参数表示，即共模谐振分量F c可以表示为：
Figure PCTCN2019081920-appb-000001
尾电感谐振技术中，尾部电感和电容谐振在2倍的振荡频率时，相位噪声最小。为了精确设计确定尾电感的谐振电感L t和尾电容C t，首先需要确定C db，C gs，C gd，L dl，L c，C sb，C c等寄生参数。这些寄生参数与交流中的“地”相连接，因此，需要与电源和地之间 的精确的参数。
本申请实施例提供的差分振荡器，主谐振电路中的电感与尾谐振电路中的尾电感分别位于电源线与地线的两侧，电源线与地线之间的距离减小，可以精确的确定电源线与地线之间的参数较小，即保证C db，C gs，C gd，L dl，L c，C sb，C c等寄生参数与交流“地”连接，精确的确定这些寄生参数。从而，通过合理设计谐振电感L t和尾电容C t，可以减小振荡器的相位噪声。
图8是一种用于差分振荡器主谐振电路的可调电容的电路示意图。
差分振荡器的电路结构可以参考图1至图4。差分振荡器的布局可以参考图2至图4。差分振荡器可以包括主振荡电路、交叉耦合的MOS管、尾电路。本申请实施例对尾电路的结构不作具体限定。尾电路可以参考图1中的尾谐振电路，尾电路也可以采用恒流电流源或其他电路结构。
采用的可调电容的差分振荡器，可以对振荡频率的调整，使振荡器适用于更宽的频率范围。但可调电容引入了较大的相位噪声。
用于差分振荡器主谐振电路的可调电容为包括多个电容单元的电容阵列，例如可调电容为包括N个电容单元，N为大于等于1的正整数。电容阵列的每个电容单元包括两个变容(varactor)MOS管。两个变容MOS管的工艺参数相同。变容MOS管可以构成压控电容。可以理解，两个变容MOS管的工艺参数相同包括两个变容MOS管的工艺参数近似相同。两个变容MOS管的衬底连接至相同电位。两个MOS管的源极和漏极均并连接至相同的电位，两个MOS管的源极和漏极电位受控制电压的控制。两个变容MOS管可以对称布置。第一变容MOS管和第二变容MOS管的栅电容连接至电路，形成主谐振电路中可调电容的一部分。
两个变容MOS管的栅极分别连接N点和P点。N点和P点分别为差分振荡器的两个输出端，例如在如图1所示的采用尾电感谐振技术的差分振荡器中，N点和P点可以分别为V o1和V o2。N点和P点分别连接两个变容MOS管的栅极。两个MOS管的源极和漏极均受开关电压的控制。
在本申请实施例中，控制电压可以用开关(switch，SW)表示。控制电压也可以称为开关电压。可以用SW＝1和SW＝0表示控制电压的两种电压值状态，其中一种电压值状态表示控制电压为高电平，另一种电压值状态表示控制电压为低电平。变容MOS管作为压容器件，在开关电压SW＝1，SW＝0两种偏置下容值不同，因此可以用于调整振荡器主谐振电路的谐振频率。
两个MOS管可以均为N沟道MOS(n-channel MOS，NMOS)管，也可以均为P沟道MOS(p-channel MOS，PMOS)管。
差分振荡器的每个输出端输出的信号包括直流信号和交流信号。变容MOS管的容值与变容MOS管的栅压有关。MOS管的栅压即MOS管栅极的电压。变容MOS管的栅极与振荡器的输出端连接，而电源噪声可能对振荡器的输出端的电压产生影响。振荡器的输出端的电压就是变容MOS管的栅压，随着振荡器的输出端电压的变化，用于差分振荡器主谐振电路的可调电容的容值变化。因此，电源噪声可能导致变容MOS管电容的变化，从而使得差分振荡器的相位噪声较大。
为了解决上述问题，本申请提出来一种差分振荡器，通过对可调电容进行改进，包括 主谐振电路，交叉耦合的MOS管。主谐振电路包括第一电容。
第一电容包括串联的第一固定电容、第一变容MOS管、第二变容MOS管、第二固定电容。第一固定电容与第一变容MOS管的栅极连接，第二固定电容与第二变容MOS管的栅极连接。控制电压为第一变容MOS管的源极和漏极以及第二变容MOS管的源极和漏极的偏置电压。第一偏置电压VB1为第一变容MOS管的栅极提供直流偏置，第二偏置电压VB2为第二变容MOS管的栅极提供直流偏置。第一固定电容、第一变容MOS管的电容值之和等于第二变容MOS管、第二固定电容的电容值之和。第一偏置电压和第二偏置电压为通过电源线提供的电源电压得到的偏置电压。
应理解，第一偏置电压和第二偏置电压为通过电源线提供的电源电压得到的偏置电压，是指第一偏置电压和第二偏置电压与电源线均由芯片中的供电模块提供电能。第一偏置电压和第二偏置电压可以是电源线提供的电源电压经过转化得到的，也可以对供电模块与电源线之间的一点的电压进行转换得到的。供电模块与电源线之间的一点可以是指供电模块与电源线之间的互连线上的一点，或供电模块与电源线之间的元器件上的一点。
第一固定电容与所述第一变容MOS管的栅极连接，第二固定电容与所述第二变容MOS管的栅极连接。控制电压为第一变容MOS管和第二变容MOS管的源极和漏极的偏置电压。第一偏置电压为第一变容MOS管的栅极提供直流偏置，第二偏置电压为第二变容MOS管的栅极提供直流偏置。
固定电容与变容MOS管串联分压，可以减小电源噪声引起的对变容MOS管栅压的变化。因此，能够减小差分振荡器的相位噪声。
第一电容的结构可以参考图9和图10。
图9是本申请实施例提供的一种用于差分振荡器的电容的示意性结构图。
用于差分振荡器的电容包括：主谐振电路，设置在芯片上；主谐振电路包括第一固定电容、第一变容MOS管、第二变容MOS管、第二固定电容。
第一固定电容与第一变容MOS管的栅极连接，第二固定电容与第二变容MOS管的栅极连接。控制电压为第一变容MOS管的源极和漏极以及第二变容MOS管的源极和漏极的偏置电压。第一偏置电压VB1为第一变容MOS管的栅极提供直流偏置，第二偏置电压VB2为第二变容MOS管的栅极提供直流偏置。第一固定电容、第一变容MOS管的电容值之和等于第二变容MOS管、第二固定电容的电容值之和。
第一变容MOS管和第二变容MOS管的栅电容连接至电路，形成第一电容的部分。控制电压控制第一变容MOS管和第二变容MOS管的源极和漏极的电压，从而控制第一变容MOS管和第二变容MOS管的栅电容。
第一变容MOS管和第二变容MOS管可以均为N沟道MOS(n-channel MOS，NMOS)管，也可以均为P沟道MOS(p-channel MOS，PMOS)管，也可以一个是NMOS管另一个是PMOS管。
控制电压可以控制所述第一变容MOS管和所述第二变容MOS管的栅电容。MOS管的栅电容是MOS管的栅极的电容。MOS管的栅电容包括并联的栅源电容C gs、栅漏电容C gs、栅衬电容C gb。控制电压也可以称为开关(switch，SW)或开关电压。SW为0表示SW为低电平，SW为1表示SW为高电平。低电平的电压可以是地线的电压。高电平的电压可以是电源线的电压。
固定电容与变容MOS管串联分压，可以减小电源噪声引起的对变容MOS管栅压的变化。因此，能够减小振荡器的相位噪声。
第一偏置电压和第二偏置电压可以对供电模块的输出电压进行转换得到。例如，可以采用一个或多个电压转换电路得到。供电模块可以为芯片中的其他电路提供电能。通过电源管理模块可以对供电模块提供的电源电压进行转换。例如，通过直流(direct current，DC)-DC转换电路可以对供电模块提供的电源电压进行转换。DC-DC转换电路可以设置在芯片上。电源线与供电模块连接。
第一偏置电压VB1和第二偏置电压VB2可以是通过所述电源线提供的电源电压得到的偏置电压。应理解，第一偏置电压和第二偏置电压为通过电源线提供的电源电压得到的偏置电压，是指第一偏置电压和第二偏置电压与电源线均由芯片中的供电模块提供电能。第一偏置电压和第二偏置电压可以是电源线提供的电源电压经过转化得到的，也可以对供电模块与电源线之间的一点的电压进行转换得到的。供电模块与电源线之间的一点可以是指供电模块与电源线之间的互连线上的一点，或供电模块与电源线之间的元器件上的一点。以上获取第一偏置电压和第二偏置电压的方式均可以理解为第一偏置电压和第二偏置电压是通过电源线提供的电源电压得到的偏置电压。
第一固定电容、第一变容MOS管串联的电容值与第二变容MOS管、第二固定电容串联的电容值相等。相等可以理解为近似相等。
如果第一固定电容与第二固定电容相等，第一变容MOS管与第二变容MOS管可以是工艺参数相同或不同的MOS管。
为了使得第一固定电容、第一变容MOS管串联的电容值与第二变容MOS管、第二固定电容串联的电容值相等，如果第一变容MOS管与第二变容MOS管的工艺参数相同，第一偏置电压可以与第二偏置电压相等；如果第一变容MOS管与第二变容MOS管不同，第一偏置电压可以与第二偏置电压可以不相等。
用于差分振荡器的电容的两端N、P可以分别连接至差分振荡器的两个输出端。
可选地，偏置电压可以经电阻连接至变容MOS管的栅极。即第一偏置电压可以经电阻连接至第一变容MOS管的栅极，第二偏置电压可以经电阻连接至第二变容MOS管的栅极。
合理设计第一偏置电压和第二偏置电压的电压值，可以减小振荡器的相位噪声。
第一偏置电压可以在第一电压范围内。在第一电压范围内，在至少一种控制电压下的第一变容MOS管的栅电容不随所述差分振荡器的输出电压变化。
第二偏置电压可以在第二电压范围内。在第二电压范围内，在至少一种控制电压下的第二变容MOS管的栅电容不随所述差分振荡器的输出电压变化。如果第一变容MOS管和第二变容MOS管的工艺参数相同，第一电压范围与第二电压范围相同。
下文会结合具体的实施例进行详细描述，此处暂不详述。
图10是本申请实施例提供的一种用于差分振荡器的电容的示意性结构图。
用于差分振荡器的电容包括：在差分振荡器的两个差分的输出端之间串联的第一固定电容、电容阵列、第二固定电容。
电容阵列包括多个电容单元。每个电容单元包括两个变容MOS管。以一个电容单元的连接情况进行说明。
所述第一固定电容与所述第一变容MOS管的栅极连接，所述第二固定电容与所述第二变容MOS管的栅极连接。控制电压控制所述第一变容MOS管和所述第二变容MOS管的源极和漏极的偏置电压。偏置电压VB为所述第一变容MOS管和所述第二变容MOS管的栅极提供直流偏置。
第一固定电容的容值等于第二固定电容的容值。第一变容MOS管与第二变容MOS管的工艺参数相同。
合理设计偏置电压VB的电压值，可以减小振荡器的相位噪声。所述偏置电压可以在第一电压范围内。在第一电压范围内，在所述控制电压的至少一种状态下的所述第一变容MOS管的栅电容不随所述振荡器的输出电压变化。下文会结合具体的实施例进行详细描述，此处暂不详述。
可选地，偏置电压VB可以经电阻连接至两个MOS管的栅极。
两个变容MOS管的源极和漏极均受开关电压的控制。
变容MOS管工作在耗尽状态或反型状态。耗尽状态与反型状态下，变容MOS管的栅极电容不同。变容MOS管的栅极电压在SW＝1，SW＝0两种状态下容值不同，因此可以用于调整振荡器主谐振电路的谐振频率。SW＝1和SW＝0是控制电压的两种状态。
两个MOS管可以均为N沟道MOS(n-channel MOS，NMOS)管，也可以均为P沟道MOS(p-channel MOS，PMOS)管。
图11是一种变容MOS管栅压与栅电容的关系的示意图。V表示MOS管的栅压，C表示MOS管的栅电容。
变容MOS管栅极的偏置电压在A1或A3范围内时，SW为0的情况与SW为1的情况下的变容MOS管栅电容相等，无法实现SW对于变容MOS管栅电容的控制。因此，为了实现对变容MOS管栅电容的数字控制，变容管的偏置电压设置在B1、A2或B2的范围。相等可以是近似相等。
参考图8至图10中的用于差分振荡器主谐振电路的可调电容，可调电容的两端N、P分别连接至电路。可调电容的两端N、P可以分别连接至差分振荡器的两个输出端。电源电压的变化会对可调电容的两端N、P的电压产生影响，也就是说，电源噪声影响变容MOS管的栅压。
当SW为0，变容MOS管栅极的偏置电压在B1范围内时，变容MOS管的栅电容随变容MOS管栅压的变化而发生变化。电源噪声会对振荡器输出的输出电压产生影响，进而对变容MOS管的栅压产生影响，使得变容MOS管的电容发生变化，影响振荡器的振荡频率。因此，当SW为0，采用B1范围内的变容MOS管栅极的偏置电压，电源噪声会对振荡器的振荡频率产生影响，也就是振荡器的电源敏感度较高，相位噪声较大。
当SW为1，变容MOS管栅极的偏置电压在B2范围内时，变容MOS管的栅电容随变容MOS管栅压的变化而发生变化。电源噪声会对振荡器输出的输出电压产生影响，进而对变容MOS管栅压产生影响，使得变容MOS管的电容发生变化，影响振荡器的振荡频率。因此，当SW为1，采用B2范围内的变容MOS管栅极的偏置电压，电源噪声会对振荡器的振荡频率产生影响，也就是振荡器的电源敏感度较高，相位噪声较大。
MOS管的栅压与控制电压可以是两个不同的输入电压。一般情况下，MOS管栅极的偏置电压几乎与控制电压SW无关。因此，当变容MOS管栅极偏置在B1或B2范围内， 相位噪声较大。
对于同一个MOS管，SW为“0”和SW为“1”和的电压值差距越大，B1和B2之间的差值越大，即A2的电压范围越大。
由于工艺的限制，变容MOS管的栅电容随栅压可能变化较为缓慢，不存在A2的电压范围。
图12是一种变容MOS管栅压与栅电容的关系的示意图。V表示MOS管的栅压，C表示变容MOS管的栅电容。
对于图9或图10所示的可调电容，变容MOS管栅极的偏置电压在A1或A3范围时，SW为0的情况与SW为1的情况下的变容MOS管栅电容相等，无法实现SW对于变容MOS管栅电容的控制。因此，为了实现对变容MOS管栅电容的数字控制，变容管的偏置电压设置在B1、A2或B2的范围。
变容MOS管栅极的偏置电压在B1范围时，SW为0的情况，电源噪声会对振荡器输出的输出电压产生影响，进而对变容MOS管的栅压产生影响，使得变容MOS管的电容随电源噪声发生变化。SW为1的情况，电源噪声不会对振荡器输出的输出电压产生影响，变容MOS管的电容不随电源噪声变化。
变容MOS管栅极的偏置电压在B2范围时，SW为1的情况，电源噪声会对振荡器输出的输出电压产生影响，进而对变容MOS管栅压产生影响，使得变容MOS管的电容随电源噪声发生变化。SW为0的情况，电源噪声不会对振荡器输出的输出电压产生影响，变容MOS管的电容不随电源噪声变化。
变容MOS管栅极的偏置电压在C1范围时，SW为0的情况和SW为1的情况，电源噪声均会对振荡器输出的输出电压产生影响，进而对变容MOS管栅压产生影响，使得变容MOS管的电容随电源噪声发生变化。
一般情况下，MOS管栅极的偏置电压几乎与SW无关。因此，当变容MOS管栅极偏置在C1范围内，不论SW为0或SW为1，差分振荡器的相位噪声较大。
变容MOS管的栅电容随栅压剧烈变化的电压偏置区域对振荡器而言是高电源敏感区(high kpush region)，即电源敏感度高的区域。高电源敏感区的电压范围可以由SW的电压值以及变容MOS管的物理参数确定。对于图12所示的情况，C1范围为高电源敏感度区(high kpush region)。
结合图11和图12变容MOS管栅压与栅电容的关系，对于采用图10所示的可调电容的差分振荡器，合理设计变容MOS管的栅极偏置电压，可以减小电源噪声对振荡器振荡频率的影响，降低振荡器的相位噪声。
可以使偏置电压在第一电压范围内。在第一电压范围内，在控制电压的至少一种状态下的所述第一变容MOS管的栅电容不随所述振荡器的输出电压变化；所述控制电压用于控制所述第一变容MOS管的栅电容。控制电压可以指SW。控制电压的状态可以包括SW为0或SW为1的状态。根据控制电压的电压取值，控制电压的状态还可以包括其他状态。本申请实施例对此不作限定。
图13是本申请一个实施例提供的一种差分振荡器。该振荡器采用尾电感谐振技术。
该振荡器包括电源线311和地线331，主谐振电路110，尾谐振电路120，稳压器1303。
电源线311设置在芯片上。地线331设置在所述芯片上，并且与电源线311平行。电 源线311和地线331将差分振荡器所在的芯片区域划分为位于电源线311和地线331之间的第一部分、分别位于所述电源线311和地线331两侧的第二部分和第三部分。
芯片的供电模块提供的电压可以经过稳压器1303后连接至电源线。为整个振荡电路供电，提供稳定的电压偏置。稳压器1303可以是低压差线性稳压器(low dropout regulator，LDO)等。LDO可以输出超低噪声的电压。供电模块提供的电压可以经过稳压器1303后，噪声较小。
主谐振电路设置在所述芯片上。主谐振电路可以包括第一电容341，第一电容341可以是可调电容。主谐振电路可以包括电感值相等的第一电感321和第二电感322。可调电容中的第一可调电容1301与第二可调电容1302并联连接。第一电感321和第二电感321设置在所述第二部分。例如，第一电感321和第二电感322设置在电源线311远离地线331的一侧。
主谐振电路中的第一电感321和第二电感322可以对称布置。对称包括近似对称。第一电感321和第二电感322可以分别布置为八边形或六边形等环绕的形状。第一电感321和第二电感322也可以共同形成一个八边形或六边形等环绕的形状，环绕的形状的下方边沿可以不连通。
主谐振电路中的第一可调电容1301可以参考图14所示的电容结构。
主谐振电路中的第二可调电容1302可以参考图10所示的电容结构。
尾谐振电路包括尾电感和尾电容342。
尾谐振电路设置在芯片上。尾电感包括尾电感主体323和尾电感连接部326，尾电感主体323设置在第三部分，例如尾电感主体323设置在地线331远离电源线311的一侧。尾电感连接部326用于连接连接尾电感主体323和尾电容。尾电感主体323可以设置为八边形或六边形等环绕的形状。
主谐振电路包括负阻111，负阻可以是交叉耦合MOS管。第一MOS管351和第二MOS管352的工艺参数相同，且交叉耦合连接。交叉耦合MOS管可以作为负阻。交叉耦合的MOS管可以等效为线性负电阻。交叉耦合的MOS管可以为主谐振电路提供能量，补偿主谐振电路的损耗，维持振荡。交叉耦合MOS器件111可以设置在芯片上。
可选地，可以在芯片上形成电容，作为主谐振电路中的电容和/或尾谐振电路中的电容，例如，可以在采用上述布局方式的芯片上形成MOM电容或MIM电容。
地线和电源线之间的距离可以小于或等于第一预设值。
由于电源线311和地线331之间的距离较小，在电源线311和地线331之间布置较小的去耦电容，就能够使得电源线和地线交流阻抗满足电路设计的需求。因此，电源线和地线临近布置可以减小振荡器对于去耦电容的需求。去耦电容可以设置在第一部分。
由于电源线和地线之间的距离较小，电源线311和地线331之间的寄生电容较大。对于交流信号而言，就可以使得电源线和地线之间具有较小的阻抗，获得MOS管精确的寄生参数。通过精确的交叉耦合MOS器件的寄生参数，可以合理设计主谐振电路和尾谐振电路，使尾谐振电路谐振在2倍的振荡频率，减小相位噪声。
尾电感连接部326与地线331平行布置，尾电感连接部用于尾电感主体323与振荡器中其他部件的连接，例如尾电感连接部可以用于尾电感主体323与尾电容342、交叉耦合MOS管的连接。尾电感连接部326位于尾电感主体323与地线331之间。
图14是一种差分振荡器的可调电容的电路示意图。
在数控振荡器中，可以通过数字控制改变电容C的大小。对于数字控制的方式，通常用“0”表示低电平，用“1”表示高电平。低电平可以是电路中的“地”，即零电位，高电平可以是电源电压。
可调电容包括两个固定电容和一个作为压控电容的MOS管。MOS管受SW的控制。MOS管可以是开关MOS管，实现压控电容。MOS管的源极和漏极之间的电容C ds与两个固定电容串联连接。MOS管栅极由SW控制。SW经两级反相器连接至MOS管栅极，可以提高SW的驱动能力。同时，由SW控制MOS管的源极和漏极的电压。SW经一级反相器连接至MOS管的源极和漏极。N点和P点分别连接至主谐振电路的第一电感321和第二电感322，也就是说，N点和P点分别连接至差分振荡电路的两个输出端。N点和P点分别连接一个固定电容。这两个固定电容的可以是MOM电容，也可以是其他类型的电容。两个固定电容分别连接MOS管的源极和漏极。
MOS管受SW的控制。MOS管可以是开关MOS管。MOS管导通时，MOS管源极与漏极的阻抗很小，MOM电容串联接入电路，容值较大。MOS管关断时，MOS管源极与漏极的阻抗很大，MOM和电容和MOS的寄生电容C ds接入电路，由于C ds容值较小，因此N点与P点之间的电容较小。
通过开关控制可调电容的大小，从而改变频率，完成数字控制频率的功能。
图15是本申请实施例提供的差分振荡器的测试结果的示意图。对图13中提供的差分振荡器进行测试，测试结果如图15所示。该振荡器的频率可以覆盖2.33GHz～3.07GHz。该振荡器的频率为3GHz时，800kHz频偏(offset frequency)时的相位噪声的测试值为-130dBc/Hz。达到了业界最优秀的振荡器的相位噪声结果。
本申请实施例提供一种芯片，包括前文中的差分振荡器。
本申请实施例中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示单独存在A、同时存在A和B、单独存在B的情况。其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项”及其类似表达，是指的这些项中的任意组合，包括单项或复数项的任意组合。例如，a，b和c中的至少一项可以表示：a,b,c,a-b,a-c,b-c,或a-b-c，其中a,b,c可以是单个，也可以是多个。所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种差分振荡器，其特征在于，包括：
    电源线，设置在芯片上；
    地线，设置在所述芯片上，并且与所述电源线平行；
    主谐振电路，设置在所述芯片上，包括：第一电感和第二电感，所述第一电感和所述第二电感设置在所述电源线远离所述地线的一侧；所述主谐振电路与所述电源线连接；
    尾谐振电路，设置在所述芯片上，与所述主谐振电路和所述地线连接。
  2. 根据权利要求1所述的差分振荡器，其特征在于，
    所述尾谐振电路包括：尾电感，所述尾电感包括尾电感主体和尾电感连接部，所述尾电感主体设置在所述地线远离所述电源线的一侧，所述尾电感连接部用于连接所述尾电感主体和所述主谐振电路。
  3. 根据权利要求1或2所述的差分振荡器，其特征在于，还包括：去耦电容，所述去耦电容设置在所述地线和所述电源线之间，并与所述电源线和所述地线连接。
  4. 根据权利要求1-3中任一项所述的差分振荡器，其特征在于，所述尾电感连接部与所述地线平行布置，所述尾电感连接部位于所述尾电感主体与所述地线之间。
  5. 根据权利要求1-4中任一项所述的差分振荡器，其特征在于，所述主谐振电路包括：交叉耦合金属氧化物半导体MOS管，所述交叉耦合MOS管用于为所述主谐振电路提供负阻。
  6. 根据权利要求1-5中任一项所述的差分振荡器，其特征在于，
    所述主谐振电路包括第一电容，所述第一电容包括第一固定电容、第一变容MOS管、第二变容MOS管、第二固定电容，其中：
    所述第一固定电容与所述第一变容MOS管的栅极连接，所述第二固定电容与所述第二变容MOS管的栅极连接；控制电压为所述第一变容MOS管源极和漏极以及所述第二变容MOS管的源极和漏极的偏置电压；第一偏置电压为所述第一变容MOS管的栅极提供直流偏置，第二偏置电压为所述第二变容MOS管的栅极提供直流偏置，所述第一偏置电压和所述第二偏置电压为通过所述电源线提供的电源电压得到的偏置电压；所述第一固定电容、所述第一变容MOS管的电容值之和等于所述第二变容MOS管、所述第二固定电容的电容值之和。
  7. 根据权利要求6所述的差分振荡器，其特征在于，所述第一偏置电压在第一电压范围内时，在所述控制电压的至少一种电压值状态下的所述第一变容MOS管的栅电容不随所述第一固定电容与所述第一电感连接的一端的电压变化。
  8. 根据权利要求6或7所述的差分振荡器，其特征在于，所述第一固定电容与所述第二固定电容的容值相等，所述第一变容MOS管与所述第二变容MOS管工艺参数相同，所述第一偏置电压与所述第二偏置电压相等。
  9. 一种差分振荡器，其特征在于，包括：主谐振电路，设置在芯片上；
    所述主谐振电路包括第一固定电容、第一变容金属氧化物半导体MOS管、第二变容MOS管、第二固定电容；
    所述第一固定电容与所述第一变容MOS管的栅极连接，所述第二固定电容与所述第二变容MOS管的栅极连接；控制电压为所述第一变容MOS管的源极和漏极以及所述第二变容MOS管的源极和漏极的偏置电压；第一偏置电压为所述第一变容MOS管的栅极提供直流偏置，第二偏置电压为所述第二变容MOS管的栅极提供直流偏置，所述第一偏置电压和所述第二偏置电压为通过所述电源线提供的电源电压得到的偏置电压；所述第一固定电容、所述第一变容MOS管的电容值之和等于所述第二变容MOS管、所述第二固定电容的电容值之和。
  10. 根据权利要求9所述的差分振荡器，其特征在于，所述主谐振电路包括第一电感；所述第一偏置电压在第一电压范围内时，在所述控制电压的至少一种电压值状态下的所述第一变容MOS管的栅电容不随第一固定电容与所述第一电感连接的一端的电压变化。
  11. 根据权利要求9或10所述的差分振荡器，其特征在于，所述第一固定电容与所述第二固定电容的容值相等，所述第一变容MOS管与所述第二变容MOS管工艺参数相同，所述第一偏置电压与所述第二偏置电压相等。
  12. 根据权利要求9-11中任一项所述的差分振荡器，其特征在于，包括：交叉耦合金属氧化物半导体MOS管，所述交叉耦合MOS管用于为所述主谐振电路提供负阻。
  13. 根据权利要求9-12中任一项所述的差分振荡器，其特征在于，包括：
    电源线，设置在所述芯片上；
    地线，设置在所述芯片上，并且与所述电源线平行；
    所述主谐振电路还包括：第二电感，所述第一电感和所述第二电感设置所述电源线远离所述地线的一侧；所述主谐振电路与所述电源线连接；
    尾谐振电路，设置在所述芯片上。
  14. 根据权利要求13所述的差分振荡器，其特征在于，
    所述尾谐振电路包括：尾电感，所述尾电感包括尾电感主体和尾电感连接部，所述尾电感主体设置在所述地线远离所述电源线的一侧，所述尾电感连接部用于所述连接尾电感主体和所述主谐振电路。
  15. 根据权利要求13或14所述的差分振荡器，其特征在于，包括：去耦电容，所述去耦电容设置在所述地线和所述电源线之间，并与所述电源线和所述地线连接。
  16. 根据权利要求13-15中任一项所述的差分振荡器，其特征在于，所述尾电感连接部与所述地线平行布置，所述尾电感连接部位于所述尾电感主体与所述地线之间。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116403800A (zh) * 2023-06-09 2023-07-07 麦斯塔微电子(深圳)有限公司 电感装置、谐振电路

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117240220A (zh) * 2023-11-13 2023-12-15 成都明夷电子科技有限公司 一种射频压控振荡器及电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103404032A (zh) * 2011-03-03 2013-11-20 高通股份有限公司 在低相位噪声vco 中的温度补偿和粗调组开关
CN104852732A (zh) * 2015-05-28 2015-08-19 中国科学技术大学先进技术研究院 一种低功耗低噪声高线性增益的压控振荡器
CN106505948A (zh) * 2016-10-28 2017-03-15 中国科学技术大学 基于尾电容调谐结构的高调频分辨率数控振荡器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4667924B2 (ja) * 2005-03-29 2011-04-13 富士通セミコンダクター株式会社 可変容量回路および可変容量回路の制御方法
US20070241834A1 (en) * 2006-03-28 2007-10-18 Kun-Seok Lee Frequency fine- tuning circuit and voltage-controlled oscillator including the same
KR100877688B1 (ko) * 2006-07-14 2009-01-09 한국전자통신연구원 선형적인 가변 커패시턴스 모듈 및 이를 이용한 ｌｃ 공진 회로
US20090295492A1 (en) * 2008-05-27 2009-12-03 Salvatore Finocchiaro Biased varactor networks and methods to use the same
US8410830B2 (en) * 2009-05-02 2013-04-02 Silicon Laboratories Inc. Injection locked frequency divider and associated methods
US10381981B2 (en) * 2017-09-15 2019-08-13 Qualcomm Incorporated Degeneration for a wideband voltage-controlled oscillator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103404032A (zh) * 2011-03-03 2013-11-20 高通股份有限公司 在低相位噪声vco 中的温度补偿和粗调组开关
CN104852732A (zh) * 2015-05-28 2015-08-19 中国科学技术大学先进技术研究院 一种低功耗低噪声高线性增益的压控振荡器
CN106505948A (zh) * 2016-10-28 2017-03-15 中国科学技术大学 基于尾电容调谐结构的高调频分辨率数控振荡器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3923469A4 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116403800A (zh) * 2023-06-09 2023-07-07 麦斯塔微电子(深圳)有限公司 电感装置、谐振电路

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