WO2020200111A1 - 网络设备 - Google Patents

网络设备 Download PDF

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Publication number
WO2020200111A1
WO2020200111A1 PCT/CN2020/081745 CN2020081745W WO2020200111A1 WO 2020200111 A1 WO2020200111 A1 WO 2020200111A1 CN 2020081745 W CN2020081745 W CN 2020081745W WO 2020200111 A1 WO2020200111 A1 WO 2020200111A1
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Prior art keywords
data
main control
control board
conversion device
interrupt
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PCT/CN2020/081745
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English (en)
French (fr)
Inventor
丁元翕
慕长林
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新华三技术有限公司
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Publication of WO2020200111A1 publication Critical patent/WO2020200111A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Definitions

  • Network equipment (such as routers, switches, firewalls, etc.) includes a main control board and an interface board.
  • the main control board can include PCI-E (Peripheral Component Interconnect Express) interfaces, and the interface board can also include PCI-E (Peripheral Component Interconnect Express) interfaces.
  • E interface based on this, the main control board can be connected to the interface board through the PCI-E bus, that is, both sides of the PCI-E bus are PCI-E interfaces.
  • the interface board does not have a PCI-E interface, but has a low-speed interface (such as a local bus interface).
  • the conversion device has a PCI-E interface and a low-speed interface
  • the main control board is connected to the conversion device through a PCI-E bus
  • the interface board is connected to the conversion device through a low-speed bus (such as a local bus).
  • the main control board in order to read data 1-data 10 from the interface board, the main control board sends a read command to the conversion device, and the conversion device reads data 1 from the interface board and returns data 1 to the main control board. After the main control board obtains data 1, it sends a read command to the conversion device. The conversion device reads data 2 from the interface board, and returns data 2 to the main control board, and so on, until data 1-data is successfully read 10.
  • FIG. 1 is a schematic diagram of the hardware structure of a network device in an embodiment of the present application
  • FIG. 2 is a schematic diagram of the hardware structure of a conversion device in an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the hardware structure of a network device in another embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a data transmission method in an embodiment of the present application.
  • the network device may include a main control board, an interface board, and a conversion device.
  • FIG. 1 it is a schematic structural diagram of the network device.
  • the network device may include, but is not limited to: a main control board 10, a conversion device 20, an interface board 30, and an interface board 40.
  • the main control board 10 can be connected to the interface board 40, the main control board 10 can also be connected to the conversion device 20, and the conversion device 20 can be connected to the interface board 30.
  • the conversion device 20 and the main control board 10 may be deployed on the same single board, that is, a single board includes the conversion device 20 and the main control board 10 at the same time.
  • the conversion device 20 may be deployed on a separate single board, that is, the conversion device 20 and the main control board 10 are deployed on different single boards.
  • the position of the conversion device 20 is not limited.
  • the conversion device 20 may also be deployed on the same single board as the interface board 30, or, for network equipment including a main control board, a network board, and an interface board, the conversion device 20 may also be deployed on the same single board as the network board. There is no restriction on this.
  • the description is given by taking the conversion device 20 deployed on a separate single board as an example.
  • the main control board 10 includes a CPU (Central Processing Unit) implemented based on SOC (System on Chip), and the CPU communicates with the interface board 30/interface board 40, that is, to the interface board 30/interface board 40 writes data, and reads data from the interface board 30/interface board 40.
  • a CPU Central Processing Unit
  • SOC System on Chip
  • some interface boards have high-speed interfaces (such as PCI-E interfaces, SGMII (Serial Gigabit Media Independent, serial Gigabit Media Independent) interfaces, etc.).
  • -E interface is taken as an example for description
  • the main control board 10 has a PCI-E interface
  • the main control board 10 and the interface board 40 are directly connected, that is, the main control board 10 and the interface board 40 can pass through a high-speed bus (
  • PCI-E bus such as PCI-E bus, SGMII bus, etc., in Fig. 1, the PCI-E bus is taken as an example for illustration
  • some interface boards can have low-speed interfaces (such as local bus interface, TDM (Time Division Multiplexing, time division multiplexing) interface, etc.).
  • the local bus interface Take an example for description), but it does not have a PCI-E interface. Since the main control board 10 has a PCI-E interface but does not have a local bus interface, the main control board 10 can be connected to the interface board 30 through the conversion device 20 In other words, the main control board 10 is not directly connected to the interface board 30.
  • the conversion device 20 can have a PCI-E interface and a local bus interface. Therefore, the conversion device 20 can be connected to the main control board 10 through the PCI-E interface, that is, the conversion device 20 and the main control board 10 can be connected through the PCI-E interface. -E bus connection.
  • the conversion device 20 can be connected to the interface board 30 through a local bus interface, that is, the conversion device 20 and the interface board 30 can be connected through a low-speed bus (such as a local bus, a TDM bus, etc.).
  • the local bus is taken as an example in FIG. Description) Connect.
  • the communication process between the main control board 10 and the interface board 40 may include: the main control board 10 writes data to the interface board 40 via the PCI-E bus, and the main control board 10 uses the PCI-E bus The data is read from the interface board 40, and the data writing process and the data reading process are not repeated here.
  • the communication process between the main control board 10 and the interface board 30 may include: the main control board 10 sends data to the conversion device 20 through the PCI-E bus, and the conversion device 20 writes data to the interface board 30 through the local bus. This data writing process will not be repeated.
  • the main control board 10 sends a read command to the conversion device 20 via the PCI-E bus.
  • the conversion device 20 reads data from the interface board 30 via the local bus, and returns the data to the main control board 10 via the PCI-E bus. In the example, this data reading process is introduced.
  • the main control board 10 sends a read command to the conversion device 20, and the conversion device 20 reads the data from the interface board 30 through the local bus.
  • the data bit width of the local bus is 8. Therefore, the conversion device 20 only reads 8-bit data from the interface board 30 and sends the data to the main control board 10. After receiving the 8-bit data, the main control board 10 continues to send the read command to the conversion device 20 if it has not read all the data, and so on.
  • the main control board 10 needs to send 10 read commands, the conversion device 20 reads data from the interface board 30 10 times, and the conversion device 20 sends data to the main control board 10 10 times. Obviously, the data reading operation takes a long time. During this period, the main control board 10 is always occupied and cannot process other tasks. Other tasks can only wait, which wastes the resources of the main control board 10.
  • the conversion device 20 after the conversion device 20 receives the interrupt sent by the interface board 30, it no longer forwards the interrupt to the main control board, but directly reads the data from the interface board 30 through the local bus, and reads The fetched data is stored in the buffer.
  • the conversion device 20 can read data from the interface board 30 multiple times, and only sends the data in the buffer to the main control board until the data upload condition is met. For example, if the interface board 30 includes 80 bits of data, the conversion device 20 reads the data 10 times from the interface board 30, and reads 8 bits each time. In this way, a total of 80 bits of data are read and the read All data is stored in the buffer. After the data reading is completed, the conversion device 20 sends the data in the buffer to the main control board.
  • the main control board 10 does not participate, and In other words, the main control board 10 is not occupied and can continue to process other tasks during the data reading operation, thereby saving resources of the main control board 10, reducing the occupancy rate of the main control board 10, and improving the overall performance of the network device.
  • an embodiment of the present application proposes a conversion device.
  • the conversion device can be applied to a network device.
  • the network device can also include a main control board (such as a main control board with a first type interface) and an interface board (for example, an interface board with a second type of interface), the conversion device may include a first type of interface and a second type of interface, the conversion device is connected to the main control board through the first type of interface, and the conversion device is connected to the interface board through the second type of interface connection.
  • the first type of interface can be a high-speed interface (such as PCI-E interface, SGMII interface, etc., in Figure 1 taking the PCI-E interface as an example)
  • the second type of interface can be a low-speed interface (such as local bus interface , TDM interface, etc., take the local bus interface as an example in Figure 1 for illustration).
  • the conversion device 20 may include, but is not limited to: an interrupt processing unit 21, a read processing unit 22, a buffer 23, and DMA (Direct Memory Access) control ⁇ 24.
  • the buffer 23 is a storage area inside the conversion device 20, which may include but is not limited to RAM (Random Access Memory, random access memory).
  • the interrupt processing unit 21 is configured to receive an interrupt sent by the interface board 30; it is prohibited to send the interrupt to the main control board 10, and output control commands to the read processing unit 22.
  • the read processing unit 22 is configured to send a read operation command to the interface board 30 when receiving the control command, so that the interface board 30 returns data according to the read operation command;
  • the buffer 23 is used to store the return of the interface board 30 DMA controller 24, used to obtain operating parameters, when the operating parameters meet the data upload conditions, the data in the buffer 23 is sent to the main control board 10.
  • the DMA controller 24 obtains operating parameters in each cycle, and determines whether the data uploading conditions are met according to the operating parameters. If it is, all data in the buffer 23 is sent to the main control board 10. If not, the data in the buffer 23 is not sent to the main control board 10, but waits for the next cycle, continues to obtain the operating parameters, and judges whether the data upload conditions are met according to the operating parameters, and so on.
  • the DMA controller 24 determines that the operating parameters meet the data upload conditions, it is specifically used to:
  • Case 1 If the operating parameter is the amount of data in the buffer 23, when the amount of data in the buffer 23 reaches a preset threshold, it can be determined that the operating parameter meets the data upload condition.
  • Case 3 If the operating parameter includes the amount of data in the buffer 23 and the interrupt interval time, when the amount of data in the buffer 23 reaches the preset threshold, it is determined that the operating parameter meets the data upload condition; or, when the interrupt When the processing unit 21 does not receive the interrupt sent by the interface board within the preset time, it determines that the operating parameter satisfies the data upload condition.
  • the DMA controller 24 when the DMA controller 24 sends the data in the buffer 23 to the main control board 10, it is specifically used to: store all the data in the buffer 23 into the memory corresponding to the main control board 10; after the data storage is completed That is, after all data in the buffer 23 are stored in the memory, the DMA completion interrupt is sent to the main control board 10, so that the main control board 10 obtains data from the memory after receiving the DMA completion interrupt.
  • the DMA controller 24 sends a DMA completion interrupt to the main control board 10, so that the main control board 10, after receiving the DMA completion interrupt, is specifically used to obtain data from the memory:
  • the DMA controller 24 sends a DMA completion interrupt to the main control board 10, and sends the BD information and data length corresponding to the data in the buffer 23 to the main control board 10, so that the main control board 10 can respond to the BD information and the data length. , Get data from memory.
  • the conversion device after receiving the interrupt sent by the interface board, the conversion device does not send the interrupt to the main control board, but directly reads data from the interface board.
  • the process of fetching data does not need to be initiated by the main control board.
  • the conversion device stores the read data in the buffer, and after the data is read, the data in the buffer is sent to the main control board.
  • the above method can prevent the main control board from initiating the data reading process, reduce the time consumed by the data reading operation, avoid the main control board being occupied by the data reading operation for a long time, save the main control board resources, improve the bandwidth utilization, and improve the main control board.
  • the efficiency of data acquisition by the control board improves the overall performance of network equipment and reduces the occupancy rate of the main control board.
  • the conversion device 20 may include: an interrupt processing unit 21, a read processing unit 22, a buffer 23, and a DMA controller 24.
  • the conversion device 20 may include, but is not limited to, logic chips, such as FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), ASIC (Application Specific Integrated Circuit), Application specific integrated circuit), etc., the type of the conversion device 20 is not specifically limited here.
  • the interface board 30 when the interface board 30 has data to be read (that is, data that needs to be sent to the main control board 10), the interface board 30 sends an interrupt to the interrupt processing unit 21 of the conversion device 20 through the interrupt channel.
  • the interrupt processing unit 21 After receiving the interrupt, the interrupt processing unit 21 does not forward the interrupt to the main control board 10, but the interrupt processing unit 21 itself responds to the interrupt. That is to say, the interrupt processing unit 21 prohibits the interrupt after receiving the interrupt.
  • the interrupt is sent to the main control board 10, and it is determined based on the interrupt that data needs to be read from the interface board 30.
  • the interrupt processing unit 21 may output a control command to the read processing unit 22, and the control command is used to instruct the read processing unit 22 to read data from the interface board 30.
  • the read processing unit 22 may send a read operation command to the interface board 30 so that the interface board 30 returns data to the buffer 23 of the conversion device 20 according to the read operation command, such as 8-bit data. Specifically, the read processing unit 22 may only send a read operation command to the interface board 30. After receiving the read operation command, the interface board 30 may return data to the buffer 23 of the conversion device 20 through the local bus interface. After receiving the data, the data can be stored.
  • the interface board 30 After the interface board 30 sends the data to the buffer 23, if the interface board 30 still has data to be read, the interface board 30 continues to send an interrupt to the interrupt processing unit 21. After the interrupt processing unit 21 receives the interrupt, it outputs a control command to the read processing unit 22. When the read processing unit 22 receives the control command, it sends a read operation command to the interface board 30 so that the interface board 30 sends a read operation command to the buffer according to the read operation command. 23 returns data, and so on, until there is no data to be read on the interface board 30, it stops sending interrupts. After the interrupt processing unit 21 does not receive the interrupt, it will not output control commands to the read processing unit 22. The read processing unit 22 no longer sends a read operation command to the interface board 30, thereby no longer reading data from the interface board.
  • the DMA controller 24 can obtain the operating parameters in each statistical period (the interval of the statistical period can be configured based on experience), and determine whether the data uploading condition is satisfied according to the operating parameters. If it is satisfied, the DMA controller 24 can send all the data in the buffer 23 to the main control board 10. If not, the DMA controller 24 does not currently send the data in the buffer 23 to the main control board 10, but waits for the next cycle, continues to obtain the operating parameters, and judges whether the data upload conditions are met according to the operating parameters. And so on.
  • the operating parameter may be the amount of data in the buffer 23, and the operating parameter may also be the interrupt interval time. There is no restriction on the operating parameter, and the above process will be described in the following manner.
  • the operating parameter is the amount of data in the buffer 23.
  • the DMA controller 24 acquires the amount of data in the buffer 23 in each statistical period. If the amount of data reaches a preset threshold (the preset threshold can be configured according to experience, such as 95% of the maximum storage capacity of the buffer 23, there is no limit to this preset threshold), it means that a large amount of data has been stored in the buffer 23. These data already occupy the storage space of the buffer 23. Therefore, the DMA controller 24 determines that the data upload condition is satisfied, and sends all the data in the buffer 23 to the main control board 10. If the amount of data does not reach the preset threshold, it means that the storage space in the buffer 23 is still unoccupied. Therefore, the DMA controller 24 determines that the data upload condition is not met, and currently does not send the data in the buffer 23 to the master. The board 10 waits for the next cycle to obtain the amount of data in the buffer 23.
  • a preset threshold can be configured according to experience, such as 95% of the maximum storage capacity of the buffer 23, there
  • the operating parameter is the interrupt interval time, that is, the difference between the current time and the time when the interrupt processing unit 21 received the interrupt last time.
  • the DMA controller 24 obtains the interrupt interval time of the interrupt processing unit 21 in each statistical period. If the interrupt processing unit 21 is determined to be at the preset time according to the interrupt interval time (the preset time can be configured according to experience, there is no restriction on this) When no interrupt is received, the DMA controller 24 determines that the data upload condition is met, and sends all the data in the buffer 23 to the main control board 10.
  • the DMA controller 24 determines that the data upload condition is not met, and currently does not send the data in the buffer 23 to the main control board 10. , Wait for the next cycle, and obtain the interrupt interval time of the interrupt processing unit 21.
  • the interface board 30 when the interface board 30 has data to be read, the interface board 30 sends an interrupt to the conversion device 20 every time length A (time length A is an empirical value, there will be errors), and the preset time can be greater than or equal to the time length A. Take time length B as an example later, time length B is greater than time length A.
  • the DMA controller 24 can record the receiving moment of the interrupt. For example, when the interrupt processing unit 21 receives an interrupt at time 1, the DMA controller 24 records the receiving time of the interrupt as time 1; when the interrupt processing unit 21 receives an interrupt at time 2, the DMA controller 24 records the receiving time of the interrupt as time 2, and delete the previously recorded time 1, and so on.
  • the DMA controller 24 determines the difference between the current time and the receiving time of the most recent interrupt (for example, time 2) in each statistical period. If the difference is greater than the time length B, it means that the interface board 30 did not send an interrupt to the interrupt processing unit 21 within the time length B, and the interrupt processing unit 21 did not receive the interrupt within the time length B. The reason may be that the interface board 30 has been There is no data to be read, that is, the read processing unit 22 of the logic device 20 has read all the data from the interface board 30. Therefore, the DMA controller 24 determines that the data upload condition is satisfied, and the data in the buffer 23 All data is sent to the main control board 10.
  • the DMA controller 24 determines that the data upload condition is not satisfied.
  • Mode 3 The operating parameters are the amount of data in the buffer 23 and the interrupt interval time.
  • the DMA controller 24 obtains the amount of data in the buffer 23 and the interrupt interval time in each statistical period. If the amount of data reaches the preset threshold, the DMA controller 24 determines that the data upload condition is met, and sends all the data in the buffer 23 to the main control board 10. Or, if it is determined according to the interrupt interval time that the interrupt processing unit 21 does not receive an interrupt within the preset time, the DMA controller 24 determines that the data upload condition is met, and sends all the data in the buffer 23 to the main control board 10.
  • the DMA controller 24 can send all the data in the buffer 23 to the main control board 10. Specifically, the DMA controller 24 stores all data in the buffer 23 into the memory corresponding to the main control board 10. For example, the DMA controller 24 directly moves all the data in the buffer 23 to the memory corresponding to the main control board 10 through a DMA write operation.
  • the DMA write operation is implemented based on DMA technology, and the DMA controller 24 is writing to the memory
  • the main control board 10 is not required to participate, so the operation of the main control board 10 is omitted, and the interaction between the DMA controller 24 and the main control board 10 is not involved.
  • the DMA controller 24 only needs to move the data to the main control board 10.
  • the corresponding memory is fine.
  • the DMA controller 24 moves all the data in the buffer 23 to the memory corresponding to the main control board 10. This operation does not require the participation of the main control board 10, and there is no restriction on this process.
  • the DMA controller 24 can also send DMA completion interrupts (such as PCI-E in-band interrupts), BD (Buffer Descriptor) to the main control board 10. , Buffer descriptor) information and data length.
  • DMA completion interrupts such as PCI-E in-band interrupts
  • BD Buffer Descriptor
  • the BD information may include, but is not limited to, the starting address of the data in the buffer 23 in the memory. Of course, the BD information may also include other content, which is not limited.
  • the data length is the data length of the data in the buffer 23.
  • the main control board 10 After receiving the DMA completion interrupt, the BD information, and the data length, the main control board 10 determines that data needs to be obtained from the memory based on the DMA completion interrupt. In order to obtain data from the memory, the main control board 10 uses the BD information to determine the starting address of the data in the memory, and then, starting from this starting address, reads the data matching the length of the data. In this way, the main control board 10 The data of the interface board 30 is successfully obtained.
  • the conversion device after receiving the interrupt sent by the interface board, the conversion device does not send the interrupt to the main control board, but directly reads data from the interface board. In this way, the data is read from the interface board.
  • the process does not need to be initiated by the main control board, the conversion device stores the read data in the buffer, and after the data is read, the data in the buffer is sent to the main control board.
  • the above method can prevent the main control board from initiating the data reading process, that is, the main control board does not need to participate in the data acquisition.
  • the main control board only reads data from the memory after receiving the DMA completion interrupt, thereby releasing the main control
  • the large amount of resources of the board prevents the main control board from being occupied by data reading operations for a long time, saves the resources of the main control board, improves bandwidth utilization, improves the efficiency of the main control board to obtain data, improves the overall performance of the network equipment, and reduces the occupation of the main control board rate.
  • an embodiment of the present application also proposes a network device.
  • the network device may include a main control board, an interface board, and a conversion device.
  • the conversion device may be connected to the main control board through the first type of interface, and the conversion device may Connect with the interface board through the second type of interface; among them:
  • Interface board used to send interrupt to the conversion device
  • the conversion device is used to receive the interrupt sent by the interface board; it is forbidden to send the interrupt to the main control board and send a read operation command to the interface board so that the interface board returns data according to the read operation command; after receiving the data returned by the interface board , Store the data in the buffer of the conversion device;
  • the conversion device is also used to obtain the operating parameters, and when the operating parameters meet the data upload conditions, the data in the buffer is sent to the main control board.
  • the operating parameter is the amount of data
  • the conversion device determines that the operating parameter satisfies the data upload condition, it is specifically used to determine the operation when the amount of data in the buffer reaches a preset threshold.
  • the parameters meet the data upload conditions.
  • the operating parameter is the interrupt interval time
  • the conversion device determines that the operating parameter meets the data upload condition, it is specifically used: when the conversion device does not receive the data sent by the interface board within the preset time When interrupted, it is determined that the operating parameters meet the data upload conditions.
  • the conversion device when the conversion device sends the data in the buffer to the main control board, it is specifically used to: store all the data in the buffer into the memory corresponding to the main control board; the conversion device, It is also used to send DMA completion interrupt to the main control board after data storage is completed;
  • the main control board is used to receive the DMA completion interrupt sent by the conversion device, and obtain data from the memory after receiving the DMA completion interrupt.
  • the conversion device is also used to send the buffer descriptor BD information and data length corresponding to the data in the buffer to the main control board after sending the DMA completion interrupt to the main control board ;
  • the main control board obtains data from the memory, it is specifically used to: receive BD information and data length, and obtain data from the memory according to the BD information and data length.
  • the conversion device and the main control board may be deployed on the same single board; or, the conversion device may be deployed on a separate single board.
  • this embodiment of the application also proposes a data transmission method that can be applied to network equipment.
  • the network equipment includes a main control board, an interface board, and a conversion device.
  • the conversion device passes the first type
  • the interface is connected to the main control board, and the conversion device is connected to the interface board through the second type of interface.
  • the method may include:
  • Step 401 The interface board sends an interrupt to the conversion device.
  • Step 402 The conversion device receives the interrupt sent by the interface board; it is forbidden to send the interrupt to the main control board, and send a read operation command to the interface board.
  • Step 403 After receiving the read operation command, the interface board sends data to the conversion device.
  • step 404 after receiving the data returned by the interface board, the conversion device stores the data in the buffer of the conversion device.
  • Step 405 The conversion device acquires the operating parameters, and when the operating parameters meet the data upload conditions, the data in the buffer is sent to the main control board.
  • the conversion device determines that the operating parameter satisfies the data upload condition, which may include: determining the operating parameter when the amount of data in the buffer reaches a preset threshold Meet the data upload conditions.
  • the conversion device determines that the operating parameter satisfies the data upload condition, which may include: when the conversion device does not receive an interrupt from the interface board within a preset time When, it is determined that the operating parameters meet the data upload conditions.
  • the conversion device sends the data in the buffer to the main control board, which may include: storing all the data in the buffer into the memory corresponding to the main control board; after the data storage is completed Then, send a DMA completion interrupt to the main control board, so that the main control board obtains data from the memory after receiving the DMA completion interrupt.
  • the conversion device sends a DMA completion interrupt to the main control board, so that the main control board obtains data from the memory after receiving the DMA completion interrupt, which may include: sending to the main control board DMA completes the interrupt, and sends the buffer descriptor BD information and data length corresponding to the data in the buffer to the main control board, so that the main control board obtains data from the memory according to the BD information and data length.
  • a typical implementation device is a computer.
  • the specific form of the computer can be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email receiving and sending device, and a game control A console, a tablet computer, a wearable device, or a combination of any of these devices.
  • the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.
  • a computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • these computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device,
  • the instruction device realizes the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operating steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so that the computer or other programmable equipment is executed
  • the instructions provide steps for implementing functions specified in a flow or multiple flows in the flowchart and/or a block or multiple blocks in the block diagram.

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Abstract

一种转换装置（20）、网络设备及数据传输方法，转换装置（20）包括中断处理单元（21）、读处理单元（22）、缓冲区（23）、DMA控制器（24）；中断处理单元（21），用于在每次接收到接口板（30）发送的中断时，禁止将中断发送给主控板（10），并向读处理单元（22）输出控制命令；读处理单元（22），用于在每次接收到控制命令时，向接口板（30）发送读操作命令，以使接口板根据读操作命令返回数据；缓冲区（23），用于存储接口板（30）返回的数据；DMA控制器（24），用于获取运行参数，当运行参数满足数据上送条件时，则将缓冲区（23）中的数据发送给主控板（10）。上述装置可以节约主控板资源，提高带宽利用率，降低主控板（10）的占用率。

Description

网络设备
本申请要求于2019年03月29日提交中国专利局、申请号为201910251487.3发明名称为“一种转换装置、网络设备及数据传输方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
背景技术
网络设备(如路由器、交换机、防火墙等)包括主控板和接口板，主控板可以包括PCI-E(Peripheral Component Interconnect Express，外设部件互连标准快速)接口，接口板也可以包括PCI-E接口，基于此，主控板可以通过PCI-E总线与接口板连接，也就是说，该PCI-E总线的两侧均为PCI-E接口。
在某些应用场景下，接口板不具有PCI-E接口，而是具有低速接口(如本地总线接口)，为了使主控板与接口板交互，则需要在主控板与接口板之间部署转换装置，该转换装置具有PCI-E接口和低速接口，主控板通过PCI-E总线与转换装置连接，接口板通过低速总线(如本地总线)与转换装置连接。
在上述应用场景下，为了从接口板读取数据1-数据10，则主控板向转换装置发送读取命令，由转换装置从接口板读取数据1，将数据1返回给主控板。主控板在获取到数据1后，向转换装置发送读取命令，由转换装置从接口板读取数据2，将数据2返回给主控板，以此类推，直到成功读取数据1-数据10。
附图简要说明
为了更清楚地说明本申请实施例和现有技术的技术方案，下面对本申请实施例和现有技术中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一种实施方式中的网络设备的硬件结构示意图；
图2是本申请一种实施方式中的转换装置的硬件结构示意图；
图3是本申请另一种实施方式中的网络设备的硬件结构示意图；
图4是本申请一种实施方式中的数据传输方法的流程示意图。
具体实施方式
为使本申请实施例的目的、技术方案、及优点更加清楚明白，以下参照附图并举实施例，对本申请实施例进一步详细说明。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例中提出一种网络设备(如路由器、交换机、防火墙、服务器等)，该网络设备可以包括主控板、接口板和转换装置。参见图1所示，为该网络设备的结构示意图，该网络设备可以包括但不限于：主控板10、转换装置20、接口板30和接口板40。其中，主控板10可以与接口板40连接，主控板10还可以与转换装置20连接，且转换装置20可以与接口板30连接。
在一种可实现方式中，转换装置20与主控板10可以部署在同一个单板，也就是说，一个单板同时包括转换装置20与主控板10。或者，转换装置20可以部署在单独的单板，即转换装置20与主控板10部署在不同的单板。当然，上述只是两个示例，对此转换装置20的位置不做限制。例如，转换装置20还可以与接口板30部署在同一个单板，或者，针对包括主控板、网板和接口板的网络设备，转换装置20还可以与网板部署在同一个单板，对此不做限制。
参见图1所示，以转换装置20部署在单独的单板为例进行说明。
其中，主控板10包括基于SOC(System on Chip，系统芯片)实现的CPU(Central Processing Unit，中央处理器)，由CPU与接口板30/接口板40通信，即向接口板30/接口板40写入数据，并从接口板30/接口板40读取数据。
在一种可实现方式中，某些接口板(如接口板40)具有高速接口(如PCI-E接口、SGMII(Serial Gigabit Media Independent，串行千兆介质无关)接口等，图1中以PCI-E接口为例进行说明)，由于主控板10具有PCI-E接口，因此，主控板10与接口板40直接连接，也就是说，主控板10与接口板40可以通过高速总线(如PCI-E总线、SGMII总线等，图1中以PCI-E总线为例进行说明)连接。
在另一种可实现方式中，某些接口板(如接口板30)可以具有低速接口 (如本地总线接口、TDM(Time Division Multiplexing，时分复用)接口等，在图1中以本地总线接口为例进行说明)，但是，其不具有PCI-E接口，由于主控板10具有PCI-E接口，但是不具有本地总线接口，因此，主控板10可以通过转换装置20与接口板30连接，也就是说，主控板10不是与接口板30直接进行连接。
进一步的，转换装置20可以具有PCI-E接口和本地总线接口，因此，转换装置20可以通过PCI-E接口与主控板10连接，也就是说，转换装置20与主控板10可以通过PCI-E总线连接。此外，转换装置20可以通过本地总线接口与接口板30连接，也就是说，转换装置20与接口板30可以通过低速总线(如本地总线、TDM总线等，在图1中以本地总线为例进行说明)连接。
在上述应用场景下，针对主控板10与接口板40之间的通信过程，可以包括：主控板10通过PCI-E总线向接口板40写入数据，主控板10通过PCI-E总线从接口板40读取数据，对此数据写入过程和数据读取过程，均不再赘述。
针对主控板10与接口板30之间的通信过程，可以包括：主控板10通过PCI-E总线将数据发送给转换装置20，转换装置20通过本地总线向接口板30写入数据，对此数据写入过程不再赘述。主控板10通过PCI-E总线向转换装置20发送读取命令，转换装置20通过本地总线从接口板30读取数据，并通过PCI-E总线将数据返回给主控板10，在后续实施例中，介绍这个数据读取过程。
在传统方式中，为了从接口板30读取数据，主控板10向转换装置20发送读取命令，转换装置20通过本地总线从接口板30读取数据，由于本地总线的数据位宽为8比特，因此，转换装置20只从接口板30读取8比特的数据，将数据发送给主控板10。主控板10在接收到8比特的数据数据后，若未读取到所有数据，则继续向转换装置20发送读取命令，以此类推。
假设接口板30包括80个比特的数据，则主控板10需要发送10次读取命令，转换装置20从接口板30读取10次数据，转换装置20向主控板10发送10次数据。显然，数据读取操作需要耗费较长的时间，这段时间内，主控板10始终被占用，无法处理其它任务，其它任务只能等待，浪费主控板10的资源。
针对上述发现，本申请实施例中，转换装置20接收到接口板30发送的中断后，不再将中断转发给主控板，而是直接通过本地总线从接口板30读取数据，并将读取的数据存储到缓冲区中。转换装置20可以从接口板30读取多次数据，一直到满足数据上送条件，才将缓冲区中的数据发送给主控板。例如，接口板30包括80个比特的数据，则转换装置20从接口板30读取10次数据，每次读取8个比特，这样，一共读取80个比特的数据，并将读取的所有数据存储到缓冲区中。在数据读取完成后，转换装置20将缓冲区中的数据发送给主控板。
综上可以看出，在转换装置20从接口板30读取数据，将数据存储到缓冲区中，将缓冲区中的数据发送给主控板10的过程，主控板10并不参与，也就是说，数据读取操作耗费的时间，主控板10未被占用，能够继续处理其它任务，从而节约主控板10的资源，降低主控板10的占用率，提高网络设备整体性能。
为了实现上述功能，本申请实施例中提出一种转换装置，该转换装置可以应用于网络设备，该网络设备还可以包括主控板(如具有第一类接口的主控板)和接口板(如具有第二类接口的接口板)，转换装置可以包括第一类接口和第二类接口，转换装置通过该第一类接口与主控板连接，转换装置通过该第二类接口与接口板连接。其中，该第一类接口可以为高速接口(如PCI-E接口、SGMII接口等，图1中以PCI-E接口为例进行说明)，该第二类接口可以为低速接口(如本地总线接口、TDM接口等，图1中以本地总线接口为例进行说明)。
参见图2所示，为转换装置20的结构示意图，该转换装置20可以包括但不限于：中断处理单元21、读处理单元22、缓冲区23、DMA(Direct Memory Access，直接内存存取)控制器24。缓冲区23是转换装置20内部的存储区域，可以包括但不限于RAM(Random Access Memory，随机存取存储器)等。
在一种可实现方式中，中断处理单元21，用于接收接口板30发送的中断；禁止将该中断发送给主控板10，并向读处理单元22输出控制命令。读处理单元22，用于在接收到该控制命令时，则可以向接口板30发送读操作命令，以使接口板30根据该读操作命令返回数据；缓冲区23，用于存储接口板30返 回的数据；DMA控制器24，用于获取运行参数，当运行参数满足数据上送条件时，则将缓冲区23中的数据发送给主控板10。
可选的，DMA控制器24在每个周期获取运行参数，并根据该运行参数判断是否满足数据上送条件。如果是，则将缓冲区23中的所有数据发送给主控板10。如果否，则不将缓冲区23中的数据发送给主控板10，而是等待下一周期，继续获取运行参数，根据运行参数判断是否满足数据上送条件，以此类推。
可选的，DMA控制器24确定运行参数满足数据上送条件时具体用于：
情况一、若该运行参数为缓冲区23中的数据量，当该缓冲区23中的数据量达到预设阈值时，则可以确定该运行参数满足数据上送条件。
情况二、若该运行参数为中断间隔时间，当中断处理单元21在预设时间内未接收到接口板发送的中断时，则可以确定该运行参数满足数据上送条件。
情况三、若该运行参数包括缓冲区23中的数据量和中断间隔时间，当该缓冲区23中的数据量达到预设阈值时，则确定该运行参数满足数据上送条件；或者，当中断处理单元21在预设时间内未接收到接口板发送的中断时，则确定该运行参数满足数据上送条件。
可选的，DMA控制器24将缓冲区23中的数据发送给主控板10时具体用于：将缓冲区23中的所有数据存储到主控板10对应的内存中；在数据存储完成后，即缓冲区23中的所有数据均存储到该内存后，向主控板10发送DMA完成中断，以使主控板10在接收到DMA完成中断后，从内存中获取数据。
进一步的，DMA控制器24向主控板10发送DMA完成中断，以使主控板10在接收到DMA完成中断后，从内存中获取数据时具体用于：
DMA控制器24向主控板10发送DMA完成中断，并将缓冲区23中的数据对应的BD信息和数据长度发送给主控板10，以使主控板10根据该BD信息和该数据长度，从内存中获取数据。
基于上述技术方案，本申请实施例中，转换装置在接收到接口板发送的中断后，不将所述中断发送给主控板，而是直接从接口板读取数据，这样，从接口板读取数据的过程，就不需要主控板发起，转换装置将读取的数据存 储到缓冲区中，在数据读取完成后，将缓冲区中的数据发送给主控板。显然，上述方式可以避免主控板发起数据读取过程，减少数据读取操作所耗费的时间，避免主控板长期被数据读取操作占用，节约主控板资源，提高带宽利用率，提高主控板获取数据的效率，提高网络设备的整体性能，降低主控板的占用率。
以下结合图2所示的应用场景，对上述方案进行详细说明。参见图2所示，转换装置20可以包括：中断处理单元21、读处理单元22、缓冲区23、DMA控制器24。其中，转换装置20可以包括但不限于逻辑芯片，例如，FPGA(Field Programmable Gate Array，现场可编程门阵列)、CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)、ASIC(Application Specific Integrated Circuit，专用集成电路)等，对此转换装置20的类型，在此不做具体限制。
在一种可实现方式中，当接口板30存在待读取数据(即需要发送给主控板10的数据)时，接口板30通过中断通道向转换装置20的中断处理单元21发送中断。
中断处理单元21在接收到该中断后，并不向主控板10转发该中断，而是由中断处理单元21自身响应该中断，也就是说，中断处理单元21在接收到该中断后，禁止将该中断发送给主控板10，而是基于该中断确定需要从接口板30读取数据。为了从接口板30读取数据，则中断处理单元21可以向读处理单元22输出控制命令，该控制命令用于指示读处理单元22从接口板30读取数据。
读处理单元22在接收到该控制命令时，可以向接口板30发送读操作命令，以使接口板30根据该读操作命令向转换装置20的缓冲区23返回数据，如返回8比特的数据。具体的，读处理单元22可以只向接口板30发送一个读操作命令，接口板30在接收到该读操作命令后，可以通过本地总线接口向转换装置20的缓冲区23返回数据，缓冲区23在接收到该数据后，可以存储该数据。
接口板30将数据发送给缓冲区23后，若接口板30仍然存在待读取数据，则接口板30继续向中断处理单元21发送中断。中断处理单元21接收到中断 后，向读处理单元22输出控制命令，读处理单元22接收到控制命令时，向接口板30发送读操作命令，以使接口板30根据该读操作命令向缓冲区23返回数据，以此类推，一直到接口板30不存在待读取数据，则停止发送中断，中断处理单元21未接收到中断后，则不会向读处理单元22输出控制命令，读处理单元22不再向接口板30发送读操作命令，从而不再从接口板读取数据。
在一种可实现方式中，DMA控制器24在每个统计周期(统计周期的间隔可以根据经验进行配置)，均可以获取运行参数，并根据该运行参数判断是否满足数据上送条件。如果满足，则DMA控制器24可以将缓冲区23中的所有数据发送给主控板10。如果不满足，则DMA控制器24当前不将缓冲区23中的数据发送给主控板10，而是等待下一个周期，继续获取运行参数，并根据该运行参数判断是否满足数据上送条件，以此类推。
其中，该运行参数可以是缓冲区23中的数据量，该运行参数也可以是中断间隔时间，对此运行参数不做限制，结合如下方式对上述过程进行说明。
方式一、运行参数是缓冲区23中的数据量。DMA控制器24在每个统计周期，获取缓冲区23中的数据量。若该数据量达到预设阈值(预设阈值可以根据经验配置，如缓冲区23的最大存储量的95％，对此预设阈值不做限制)，则表示缓冲区23中已经存储大量数据，这些数据已经要占满缓冲区23的存储空间，因此，DMA控制器24确定满足数据上送条件，并将缓冲区23中的所有数据发送给主控板10。若该数据量未达到预设阈值，则表示缓冲区23中仍然存储空间未被占用，因此，DMA控制器24确定不满足数据上送条件，当前不将缓冲区23中的数据发送给主控板10，等待下一个周期，获取缓冲区23中的数据量。
方式二、运行参数是中断间隔时间，即当前时刻与中断处理单元21最近一次接收到中断的时刻的差值。DMA控制器24在每个统计周期，获取中断处理单元21的中断间隔时间，若根据该中断间隔时间确定中断处理单元21在预设时间(预设时间可以根据经验配置，对此不做限制)内未接收到中断时，则DMA控制器24确定满足数据上送条件，并将缓冲区23中的所有数据发送给主控板10。若根据该中断间隔时间确定中断处理单元21在预设时间内 已接收到中断时，则DMA控制器24确定不满足数据上送条件，当前不将缓冲区23中的数据发送给主控板10，等待下一个周期，获取中断处理单元21的中断间隔时间。
例如，当接口板30存在待读取数据时，接口板30每隔时间长度A(时间长度A是经验值，会存在误差)向转换装置20发送一次中断，预设时间可以大于或者等于时间长度A，后续以时间长度B为例，时间长度B大于时间长度A。
中断处理单元21每次接收到中断时，DMA控制器24可以记录中断的接收时刻。例如，中断处理单元21在时刻1接收到中断时，DMA控制器24记录中断的接收时刻为时刻1；中断处理单元21在时刻2接收到中断时，DMA控制器24记录中断的接收时刻为时刻2，并删除之前记录的时刻1，以此类推。
DMA控制器24在每个统计周期，确定当前时刻与最近一个中断的接收时刻(如时刻2)的差值。若该差值大于时间长度B，则说明接口板30在时间长度B内未向中断处理单元21发送中断，中断处理单元21在时间长度B内未接收到中断，其原因可能是接口板30已经不存在待读取数据，也就是说，逻辑装置20的读处理单元22已经从接口板30读取了所有数据，因此，DMA控制器24确定满足数据上送条件，并将缓冲区23中的所有数据发送给主控板10。
若该差值小于时间长度B，则说明接口板30在时间长度B内向中断处理单元21发送中断，中断处理单元21在时间长度B内接收到中断，即接口板30仍然存在待读取数据。因此，DMA控制器24确定不满足数据上送条件。
方式三、运行参数是缓冲区23中的数据量和中断间隔时间。
DMA控制器24在每个统计周期，获取缓冲区23中的数据量和中断间隔时间。若该数据量达到预设阈值，DMA控制器24确定满足数据上送条件，并将缓冲区23中的所有数据发送给主控板10。或者，若根据该中断间隔时间确定中断处理单元21在预设时间内未接收到中断时，则DMA控制器24确定满足数据上送条件，并将缓冲区23中的所有数据发送给主控板10。
在一种可实现方式中，当满足数据上送条件时，则DMA控制器24可以 将缓冲区23中的所有数据发送给主控板10。具体的，DMA控制器24将缓冲区23中的所有数据存储到主控板10对应的内存中。例如，DMA控制器24通过DMA写操作，将缓冲区23中的所有数据直接搬移到主控板10对应的内存中，DMA写操作是基于DMA技术实现，DMA控制器24在向内存中写入数据时，不需要主控板10的参与，因此省去了主控板10的操作，不涉及DMA控制器24与主控板10的交互，DMA控制器24只要将数据搬移到主控板10对应的内存即可。
综上所述，DMA控制器24是将缓冲区23中的所有数据搬移到主控板10对应的内存中，这个操作不需要主控板10的参与，对此过程不做限制。
在数据存储完成后，即缓冲区23中的所有数据均存储到该内存后，DMA控制器24还可以向主控板10发送DMA完成中断(如PCI-E带内中断)、BD(Buffer Descriptor，缓冲描述符)信息和数据长度等内容，该BD信息可以包括但不限于缓冲区23中的数据在内存中的起始地址，当然，BD信息还可以包括其它内容，对此不做限制。该数据长度是缓冲区23中的数据的数据长度。
主控板10在接收到该DMA完成中断、BD信息和数据长度后，基于该DMA完成中断，确定需要从内存中获取数据。为了从内存中获取数据，主控板10利用该BD信息确定数据在内存中的起始地址，然后，从这个起始地址开始，读取与该数据长度匹配的数据，这样，主控板10成功获取到接口板30的数据。
基于上述技术方案，本申请实施例中，转换装置在接收到接口板发送的中断后，不将中断发送给主控板，而是直接从接口板读取数据，这样，从接口板读取数据的过程，就不需要主控板发起，转换装置将读取的数据存储到缓冲区中，在数据读取完成后，将缓冲区中的数据发送给主控板。显然，上述方式可以避免主控板发起数据读取过程，即不需要主控板参与数据的获取，主控板只在接收到DMA完成中断后，才去内存中读取数据，从而释放主控板的大量资源，避免主控板长期被数据读取操作占用，节约主控板资源，提高带宽利用率，提高主控板获取数据的效率，提高网络设备的整体性能，降低主控板的占用率。
参见图3所示，本申请实施例中还提出一种网络设备，该网络设备可以包括主控板、接口板和转换装置，转换装置可以通过第一类接口与主控板连接，转换装置可以通过第二类接口与接口板连接；其中：
接口板，用于向转换装置发送中断；
转换装置，用于接收接口板发送的中断；禁止将中断发送给主控板，并向接口板发送读操作命令，以使接口板根据读操作命令返回数据；在接收到接口板返回的数据后，将数据存储到转换装置的缓冲区中；
转换装置，还用于获取运行参数，当运行参数满足数据上送条件时，则将缓冲区中的数据发送给主控板。
可选的，在一种可实现方式中，若运行参数为数据量，转换装置确定运行参数满足数据上送条件时具体用于：当缓冲区中的数据量达到预设阈值时，则确定运行参数满足数据上送条件。
可选的，在一种可实现方式中，若运行参数为中断间隔时间，转换装置确定运行参数满足数据上送条件时具体用于：当转换装置在预设时间内未接收到接口板发送的中断时，则确定运行参数满足数据上送条件。
可选的，在一种可实现方式中，转换装置将缓冲区中的数据发送给主控板时具体用于：将缓冲区中的所有数据存储到主控板对应的内存中；转换装置，还用于在数据存储完成后，向主控板发送DMA完成中断；
主控板，用于接收转换装置发送的DMA完成中断，并在接收到DMA完成中断后，从内存中获取数据。
可选的，在一种可实现方式中，转换装置，还用于在向主控板发送DMA完成中断后，将缓冲区中的数据对应的缓冲描述符BD信息和数据长度发送给主控板；主控板从内存中获取数据时具体用于：接收BD信息和数据长度，并根据BD信息和数据长度，从内存中获取数据。
可选的，在一种可实现方式中，转换装置与主控板可以部署在同一个单板；或者，转换装置可以部署在单独的单板。
其中，网络设备中各部件的功能，可以参见上述实施例，在此不再赘述。
基于与上述网络设备、转换装置同样的申请构思，本申请实施例还提出一种数据传输方法，可以应用于网络设备，网络设备包括主控板、接口板和 转换装置，转换装置通过第一类接口与主控板连接，转换装置通过第二类接口与接口板连接，参见图4所示，该方法可以包括：
步骤401，接口板向转换装置发送中断。
步骤402，转换装置接收接口板发送的中断；禁止将中断发送给主控板，并向接口板发送读操作命令。
步骤403，接口板在接收到所述读操作命令后，向转换装置发送数据。
步骤404，转换装置在接收到接口板返回的数据后，将数据存储到转换装置的缓冲区中。
步骤405，转换装置获取运行参数，当运行参数满足数据上送条件时，则将缓冲区中的数据发送给主控板。
可选的，在一种可实现方式中，若运行参数为数据量，转换装置确定运行参数满足数据上送条件，可以包括：当缓冲区中的数据量达到预设阈值时，则确定运行参数满足数据上送条件。
可选的，在一种可实现方式中，若运行参数为中断间隔时间，转换装置确定运行参数满足数据上送条件，可以包括：当转换装置在预设时间内未接收到接口板发送的中断时，则确定运行参数满足数据上送条件。
可选的，在一种可实现方式中，转换装置将缓冲区中的数据发送给主控板，可以包括：将缓冲区中的所有数据存储到主控板对应的内存中；在数据存储完成后，向主控板发送DMA完成中断，以使主控板在接收到DMA完成中断后，从内存中获取数据。
可选的，在一种可实现方式中，转换装置向主控板发送DMA完成中断，以使主控板在接收到DMA完成中断后，从内存中获取数据，可以包括：向主控板发送DMA完成中断，并将缓冲区中的数据对应的缓冲描述符BD信息和数据长度发送给主控板，以使主控板根据BD信息和数据长度，从内存中获取数据。
上述实施例阐明的设备、装置、部件或单元，具体可以由计算机芯片或实体实现，或者由具有某种功能的产品来实现。一种典型的实现设备为计算机，计算机的具体形式可以是个人计算机、膝上型计算机、蜂窝电话、相机电话、智能电话、个人数字助理、媒体播放器、导航设备、电子邮件收发设 备、游戏控制台、平板计算机、可穿戴设备或者这些设备中的任意几种设备的组合。
为了描述的方便，描述以上装置时以功能分为各种单元分别描述。当然，在实施本申请时可以把各单元的功能在同一个或多个软件和/或硬件中实现。
本领域内的技术人员应明白，本申请的实施例可提供为方法、设备、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备、和计算机程序产品的流程图和/或方框图来描述的。应理解可以由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其它可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其它可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
而且，这些计算机程序指令也可以存储在能引导计算机或其它可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或者多个流程和/或方框图一个方框或者多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其它可编程数据处理设备上，使得在计算机或者其它可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其它可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
以上实施例仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (10)

  1. 一种转换装置，所述转换装置应用于网络设备，所述网络设备还包括主控板和接口板，所述转换装置通过第一类接口与所述主控板连接，所述转换装置通过第二类接口与所述接口板连接，其中：所述转换装置包括中断处理单元、读处理单元、缓冲区、直接内存存取DMA控制器；
    所述中断处理单元，用于接收所述接口板发送的中断；禁止将所述中断发送给所述主控板，并向所述读处理单元输出控制命令；
    所述读处理单元，用于在接收到所述控制命令时，向所述接口板发送读操作命令，以使所述接口板根据所述读操作命令返回数据；
    所述缓冲区，用于存储所述接口板返回的数据；
    所述DMA控制器，用于获取运行参数，当所述运行参数满足数据上送条件时，则将所述缓冲区中的数据发送给所述主控板。
  2. 根据权利要求1所述的转换装置，所述运行参数为数据量；所述DMA控制器确定所述运行参数满足数据上送条件时具体用于：
    当所述缓冲区中的数据量达到预设阈值时，则确定所述运行参数满足数据上送条件。
  3. 根据权利要求1所述的转换装置，所述运行参数为中断间隔时间；所述DMA控制器确定所述运行参数满足数据上送条件时具体用于：
    当所述中断处理单元在预设时间内未接收到接口板发送的中断时，则确定所述运行参数满足数据上送条件。
  4. 根据权利要求1所述的转换装置，所述DMA控制器将所述缓冲区中的数据发送给所述主控板时具体用于：
    将所述缓冲区中的所有数据存储到所述主控板对应的内存中；
    在数据存储完成后，向所述主控板发送DMA完成中断，以使所述主控板在接收到所述DMA完成中断后，从所述内存中获取数据。
  5. 根据权利要求4所述的转换装置，所述DMA控制器向所述主控板发送 DMA完成中断，以使所述主控板在接收到所述DMA完成中断后，从所述内存中获取数据时具体用于：
    向所述主控板发送DMA完成中断，并将所述缓冲区中的数据对应的缓冲描述符BD信息和数据长度发送给所述主控板，以使所述主控板根据所述BD信息和数据长度，从所述内存中获取数据。
  6. 一种网络设备，所述网络设备包括主控板、接口板和转换装置，所述转换装置通过第一类接口与所述主控板连接，所述转换装置通过第二类接口与所述接口板连接；其中：
    所述接口板，用于向所述转换装置发送中断；
    所述转换装置，用于接收所述接口板发送的中断；禁止将所述中断发送给所述主控板，并向所述接口板发送读操作命令，以使所述接口板根据所述读操作命令返回数据；在接收到所述接口板返回的数据后，将所述数据存储到所述转换装置的缓冲区中；
    所述转换装置，还用于获取运行参数，当所述运行参数满足数据上送条件时，则将所述缓冲区中的数据发送给所述主控板。
  7. 根据权利要求6所述的网络设备，所述转换装置将所述缓冲区中的数据发送给所述主控板时具体用于：将所述缓冲区中的所有数据存储到所述主控板对应的内存中；
    所述转换装置，还用于在数据存储完成后，向主控板发送DMA完成中断；
    所述主控板，用于接收所述转换装置发送的所述DMA完成中断，并在接收到所述DMA完成中断后，从所述内存中获取数据。
  8. 根据权利要求7所述的网络设备，所述转换装置，还用于在向主控板发送DMA完成中断后，将所述缓冲区中的数据对应的缓冲描述符BD信息和数据长度发送给所述主控板；
    所述主控板从所述内存中获取数据时具体用于：接收所述BD信息和数据长度，并根据所述BD信息和数据长度，从所述内存中获取数据。
  9. 根据权利要求6-8任一项所述的网络设备，所述转换装置与所述主控板 部署在同一个单板；或者，所述转换装置部署在单独的单板。
  10. 一种数据传输方法，应用于网络设备，所述网络设备包括主控板、接口板和转换装置，所述转换装置通过第一类接口与主控板连接，所述转换装置通过第二类接口与接口板连接，所述方法包括：
    所述接口板向所述转换装置发送中断；
    所述转换装置接收所述接口板发送的中断；禁止将所述中断发送给所述主控板，并向所述接口板发送读操作命令；
    所述接口板在接收到所述读操作命令后，向所述转换装置发送数据；
    所述转换装置在接收到所述接口板返回的数据后，将所述数据存储到所述转换装置的缓冲区中；
    所述转换装置获取运行参数，当所述运行参数满足数据上送条件时，则将所述缓冲区中的数据发送给所述主控板。
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