WO2020187843A1 - Dispositif et procédé pour la programmation à distance - Google Patents

Dispositif et procédé pour la programmation à distance Download PDF

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Publication number
WO2020187843A1
WO2020187843A1 PCT/EP2020/057130 EP2020057130W WO2020187843A1 WO 2020187843 A1 WO2020187843 A1 WO 2020187843A1 EP 2020057130 W EP2020057130 W EP 2020057130W WO 2020187843 A1 WO2020187843 A1 WO 2020187843A1
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WIPO (PCT)
Prior art keywords
sequence
executable
action
node
course
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PCT/EP2020/057130
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German (de)
English (en)
Inventor
Jan Sören EMMERICH
Michael Ten Hompel
Christian Hammermeister
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Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
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Publication of WO2020187843A1 publication Critical patent/WO2020187843A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/30—Creation or generation of source code
    • G06F8/34—Graphical or visual programming
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0426—Programming the control sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration

Definitions

  • the present invention relates to an apparatus and a method for remote programming.
  • the present invention relates in particular to a remote-programmable device for rule-based applications or to a remote-programmable device with Turing-complete parameter set for rule-based applications (FPGRA).
  • loT devices or loT devices can be used in a wide variety of flexible ways.
  • One and the same hardware configuration can have different use cases and also switch between them.
  • a device whose application changes must be reprogrammed.
  • a new program code is loaded onto the device and written to the permanent memory (EEPROM).
  • Radio-based devices that can be used flexibly with little energy consumption would therefore be desirable.
  • the object of the present invention is therefore to create devices which can be used or programmed flexibly by means of data communication with little expenditure of energy.
  • the inventors have recognized that it is particularly advantageous to store and keep the functionalities to be implemented by a device in the form of sequence parts, which each describe at least one operating instruction.
  • a function or functionality to be implemented later by the device can be determined by receiving a configuration signal which merely specifies the sequence and linking of the sequence parts already stored in the device.
  • the device can thus be reprogrammed by re-sorting the predefined and already stored sequence parts, which is possible with little energy expenditure and at the same time enables a very high degree of flexibility.
  • a device comprises an input interface which is designed to receive a configuration signal.
  • the device comprises a data memory in which a plurality of executable process parts is stored, each process part describing at least one operating instruction.
  • a generator is designed to create a course of action which comprises a sequence of sequence parts of the plurality of stored sequence parts, which are specified in the configuration signal.
  • An interface of the device is designed to communicate with a periphery.
  • a processor is designed to address the peripherals in accordance with the course of action.
  • a device comprises an output interface that is designed to send a configuration signal, a signal generator that is designed to provide the configuration signal, so that the configuration signal describes a sequence of executable sequence parts of a plurality of executable sequence parts.
  • the sequence of executable process parts clearly describes a course of action with a plurality of instructions.
  • FIG. 1 shows a schematic block diagram of a device according to an embodiment
  • FIG. 2 shows a schematic block diagram of a data memory according to an exemplary embodiment
  • FIG. 3 shows a schematic block diagram of a device according to an exemplary embodiment that has interfaces in order to provide both wireless communication and wired communication;
  • FIG. 4 shows a schematic representation of an exemplary course of action according to an exemplary embodiment
  • FIG. 5 shows a schematic block diagram of part of a rule tree according to a
  • 6a shows a schematic block diagram of an interconnection of a process node in a rule tree according to an exemplary embodiment
  • 6b shows a schematic representation of a linkage of a process node in one
  • Rule tree the implemented operation being an arithmetic operation according to one embodiment
  • 6c shows a schematic representation of a link of the process node in the
  • 6d shows a schematic representation of the process node according to an exemplary embodiment, in which information inputs obtained by means of links, according to an exemplary embodiment, result in an action to be carried out; 7 shows an exemplary representation of computer-implemented instructions according to an exemplary embodiment for the exemplary representation of different functions implemented by nodes;
  • FIG. 8 shows an exemplary illustration of code according to an exemplary embodiment of
  • 9a-c show examples of code according to an exemplary embodiment for
  • FIG. 10a shows an exemplary code according to an exemplary embodiment in which a maximum number of nodes in the course of action is defined
  • 10b shows an exemplary code according to an exemplary embodiment, which indicates that a node number is run through in full up to a maximum number of nodes or actions;
  • 10c shows an exemplary code according to an exemplary embodiment for executing a course of action by a processor
  • 10d shows an exemplary illustration of code according to an exemplary embodiment of
  • 10e shows exemplary code according to an embodiment that instructs a processor to determine the next node to be executed
  • FIG. 11 shows a schematic block diagram of a device according to an exemplary embodiment, which comprises inputs, outputs and an internal logic
  • FIG. 12 shows a schematic block diagram of a device in accordance with an exemplary embodiment, the peripherals being connected to the outputs in the form of a switch by wire or wirelessly;
  • 13 shows a schematic block diagram of a device according to an exemplary embodiment, in which the inputs are connected to any number of sensors in order to receive sensor signals;
  • FIG. 14 shows a schematic block diagram of a device according to an exemplary embodiment, which is connected to the periphery and which is configured as a sensor / actuator logic or as a transmitter and receiver, for example for a smart home device;
  • FIG. 15 shows a schematic block diagram of a system in accordance with an exemplary embodiment, which comprises the device from FIG. 1 by way of example;
  • 16 shows a schematic block diagram of a system in accordance with an exemplary embodiment, which comprises devices which are designed to exchange a data flow for exchanging logic and / or parameters or setpoint values;
  • FIG. 17 shows a schematic flow diagram of a method according to an exemplary embodiment, which can be carried out, for example, by a remotely programmable device described herein, such as the device;
  • FIG. 19 shows a schematic block diagram of a device according to an exemplary embodiment, which can function as a movement tracker
  • FIG. 20 shows a schematic block diagram of a device in accordance with an exemplary embodiment, which can function as an anti-theft device
  • FIG. 21 shows a schematic block diagram of a device in accordance with an exemplary embodiment that can provide an intelligent heart rate monitor.
  • Some of the exemplary embodiments described below are implemented using or on the basis of an exemplary programming language, i. H. described by code. Details of these exemplary embodiments, which result, for example, on the basis of the semantics and / or on the basis of the specific command implementations, are only to be understood as examples and inserted for better understanding.
  • the selected code implementations do not restrict the exemplary embodiments either to the selected programming language or to the specific command sequence or the designation of variables, unless this is explicitly stated otherwise.
  • the exemplary embodiments explained herein relate to alternative or additional exemplary embodiments with the same, similar and, in particular, equivalent technical effect.
  • loT denotes the term “Internet of Things” and stands for devices that are connected via a usually narrow-band channel communicate with other facilities, both direct connections (peer-to-peer) and infrastructure-based networks can be used for this purpose.
  • the exemplary embodiments described here are not restricted to this, in particular since the advantages of flexibility and energy savings can also be obtained with broadband channels. From this it is also clear that the exemplary embodiments described here can be used in the field of classic mobile communications (e.g. 3G / 4G / LTE - Long Term Evolution - or 5G), but that other wireless communication protocols can be implemented, such as local wireless networks (WLAN ), large area wireless networks (WMAN) or any other wireless communication protocols that the advantages described can also be obtained in the field of wired communication.
  • WLAN local wireless networks
  • WMAN large area wireless networks
  • the following exemplary embodiments relate to the use of integer numbers, ie, whole-number values, for example for the results of nodes of courses of action or their graphic representation. Although this is in terms of storage efficiency is advantageous, the present exemplary embodiments are not limited thereto. Rather, it is possible that operations of a node use other values, such as floating point values (e.g. data type "float").
  • floating point values e.g. data type "float”
  • the one data field which is designated with "res”, for example, and can represent the result of the node, can even remain an integer, since the information (i.e. the bits) in the "res" field is represented by what is known as " cast “(evaluate) can simply be interpreted as float (floating point number!) without suffering any loss of information.
  • the device 10 comprises an input interface 12 which is designed to receive a configuration signal 14.
  • the input interface 12 can be a wireless or wired communication interface or interface, so that the configuration signal can accordingly be a wired signal or a wireless signal.
  • the device 10 comprises a data memory in which a multiplicity of executable sequence parts 18 are stored, which are represented by way of example as “a”, “b”, “c”, “d”, or “e”, although any number is arbitrary, for example at least three, at least four, at least 10, at least 50 or higher, approximately at least 100.
  • Each process part 18i to 185 can be understood as a code segment or code section that describes at least one operating instruction, for example processing or manipulation of an input variable to an output variable, whereupon will be discussed in detail later.
  • the sequence parts 181 to 18 5 can, however, be clearly distinguished from one another and represent, for example, partial programs or partial codes.
  • the device 10 comprises a generator 22 which is designed to create a course of action 24.
  • the course of action 24 can be a combination of several sequence parts 181 to 185, each sequence part 181 to 185 optionally being able to occur in the course of action 24, which includes the possibility of multiple occurrences.
  • the sequence of actions 24 comprises a number of four sequence parts 183, 181, 184 and 182 in the order mentioned, which can be represented as c, a, d, b. Both the selected sequence and the number of process parts 181 to 184 in the course of action 24 are selected here by way of example.
  • a number of M sequence parts in the action sequence 24 can also have any value, the number of M sequence parts 18 in the action sequence 24 being a subset of the N sequence parts stored in the data memory 16, whereby within the subset M one sequence part can occur multiple times.
  • the process parts implemented in the course of action are a subset of the stored course of action.
  • the course of action 24 can thus comprise at least a subset of the plurality of executable sequence parts stored in the data memory.
  • the processor 31 can be designed to run through the subset of executable process parts according to the course of action 24 in order to address the periphery 32 and to process at least one input variable in a first process part in order to obtain an output variable and to use the output variable as an input variable of a second process part to be used, as is explained in more detail, for example, with reference to FIG.
  • the generator 22 is designed to read the sequence parts to be used for the action sequence 24 from the data memory 16 and to link them to the action sequence 24, which includes both the implementation of a sequence of the sequence parts 18i to 18 and a linking of the individual sequence parts.
  • an output variable of a first sequence part, for example 18i can be an input variable of a subsequent sequence part, for example 184, so that the parameters can be transferred by means of corresponding memory references.
  • the applicable rule with regard to the links can be part of the configuration signal 14, which can have information 26i to 264 indicated, for example, as c, a ‘, d‘ or b ‘.
  • information 263 (c ′) can reproduce an instruction for using the sequence part 183 in the action sequence 24.
  • the presence of an item of information 26 1 (a ′) can reproduce an instruction for using the sequence part I81 in the sequence of actions 24.
  • Information 264 (d ') and 262 (b') can similarly include instructions for using sequence parts 1 84 and 182 in action sequence 24.
  • a sequence of the sequence parts 18 1 to 18 4 in the action sequence 24 can be specified explicitly in the configuration signal 14, but can also be implicitly contained in a sequence of the information 263, 26i, 264 and 262, which enables an additional reduction in transmitted data.
  • the generator 22 is designed to evaluate the configuration signal 14 for the information 26 and to create the course of action 24 in such a way that it comprises a sequence of sequence parts 18 indicated in the configuration signal by the information 26, which are stored in the data memory 16.
  • the processor 22 can be designed to create a new or first course of action upon receipt of a possibly first configuration signal.
  • the processor 22 can be designed to replace the course of action 24 with a new, further or different course of action that is in accordance with the updated configuration signal 14 when a new, further or different configuration signal 14 is received. This means that the device 10 is reprogrammed without the need for new program code.
  • the data memory 34 for example as a volatile data memory, a small amount of energy can be used in order to obtain the reprogramming.
  • the configuration signal 14 can have a sequence of information that contains an identifier for each node to be used ( Node number) as well as a type and memory areas for inputs and outputs, so that a node of the course of action 24 can be clearly identified by a total of six parameters and can be reprogrammed via the specified parameters, so that individual nodes as well as the entire course of action can be reprogrammed using the configuration signal 14 is possible to get a new, second course of action.
  • Node number an identifier for each node to be used
  • type and memory areas for inputs and outputs
  • the generator can be designed to redefine at least one executable sequence part of the first course of action based on the second configuration signal in order to obtain a second course of action, that is to say an updated or redefined course of action.
  • the redefinition of the course of action can be Turing-complete as well as the first course of action.
  • the generator can be designed to evaluate the second configuration signal for the six parameters mentioned, which determine the at least one executable sequence part for the redefinition.
  • the device 10 comprises an interface 28, which enables a wired or wireless connection to a peripheral 32.
  • the periphery 32 can include any number, ie, zero or more in each case, but one or more in total, of sensors, actuators, motors, data output devices, data processing devices, such as servers, switches and / or data input devices.
  • the sensors include, for example, temperature sensors, humidity sensors, rotation rate sensors or any other sensors.
  • Actuators can be, for example, control elements that are used in the field of fluid control, generate any other movements, such as switches or Motors or the like, while data input devices include scanners, keys, keyboards or touchpads, data output devices can be displays, lights or displays, for example.
  • the device 10 comprises a processor 32 which is designed to address the peripherals 32 in accordance with the course of action 24.
  • the processor 31 is configured to execute the process parts 18i to 18 4 in the sequence defined by the process process 24, the process process 24 being able to relate to the interaction with the periphery as well as intermediate or intermediate processing steps.
  • the generator 22 and the processor 31 are shown as separate elements, the generator 22 and the processor 31 can also be part of a common control unit implemented, for example, as a processor, micro-controller, field-programmable gate array (FPGA) or the like is. Alternatively, each of the elements 22 and 31 can be implemented in this way by itself.
  • FPGA field-programmable gate array
  • the course of action 24 can be stored in a data memory 34, which can be separate from the data memory 16.
  • the data memories 16 and 34 can be memory areas of the same data memory.
  • MRAM magnetoresistive main memory
  • the data memory 34 can be a volatile or non-volatile memory, since with knowledge of the configuration signal 14 the course of action 24 can be restored by accessing the data memory. Exemplary embodiments can provide for information of the configuration signal 14 to be stored in the data memory 16 and / or the data memory 34.
  • the device 10 enables a high degree of flexibility in applications to be obtained and, depending on the implementation of the data memory 34, of writing a new program code can be dispensed with for reprogramming the device 10 Codes in a read-only memory such as an EEPROM can be dispensed with, which is particularly advantageous for the ultra-low-power range, but the exemplary embodiments are not limited to this.
  • Embodiments are based on the knowledge that the The device activity specified by the user / programmer is only a small part of the total program code. In simplified terms, a very large part is only used to control and integrate the hardware / peripherals.
  • loT devices especially in the ultra-low-power segment, are of a fairly simple nature; recursive programs on calls or complex nested loops are only used in rare cases, which is partly due to hardware limitations.
  • a certain proportion or a high proportion can be represented with concepts according to "If X, then Y, otherwise Z", where X can definitely be the result of a more complex operation and Y and Z a function call or another logic query.
  • FIG. 2 shows a schematic block diagram of a data memory 36, which acts as a common data memory for the data memories 16 and 34.
  • a common data memory is not restricted to the fact that the data memories 16 and 34, which act as a first memory section and second memory section, are based on the same memory principles.
  • the memory section or data memory 16 is designed to store the multiplicity of executable sequence parts 18, that is, the prefabricated or predefined code sections.
  • the data memory or memory section 34 can be designed to store the course of action 24.
  • the generator 22 can be designed to store the created course of action 24 in the memory section 34.
  • the data memory 16 is formed as a non-volatile memory and the data memory 34 is formed as a volatile memory.
  • FIG. 3 shows a schematic block diagram of a device 30 according to an exemplary embodiment, which has interfaces 12i and 12 2 in order to provide both wireless communication via interface 12i and wired communication via interface 12 2 .
  • the interfaces 12i and / or 12 2 can enable bidirectional communication, as can the interface 12 of the device 10. For example, a result of internal calculations or evaluated sensors or nodes can be reported back.
  • the device 30 comprises a control device 38, for example a central processing unit (CPU, a micro-controller or the like), which is connected to the exemplary non-volatile data memory 16 and the exemplary volatile data memory 34 and both the generator 22 and the also the processor 31 of the Device 10 implemented.
  • the control device 38 can be connected to any number> 1 clock generators (real-time clock - RTC).
  • a cut 28i can be configured to detect a number of 0,... V inputs, where V is any number> 0.
  • the v inputs of the interface 28i can provide any information or data.
  • An optional further interface 282 can be connected to a number of 0,...
  • W sensors so that when sensors are connected, corresponding sensor signals can reach the control device 38, that is, the control device 38 can access the optional inputs and the have optional sensors. It is pointed out that preferably at least one of the values v or w> 0 and the device 30 or the periphery has at least one input or at least one sensor.
  • Other systems can be controlled via an interface 28 3 , for example via a communication bus or an energy transmission bus.
  • the device 30 can have an optional interface 284 for parallel (Par) and / or serial (Ser) communication.
  • An interface 28 5 can optionally be provided and provide a number of outputs that are connected, for example, to a display device and / or an actuator and / or provide control signals for sensors or the like.
  • the device 30 can be designed to receive the configuration signal via the interface 12i and / or the interface 12 2 , that is to say via a wired or wireless communication network.
  • the configuration signal is preferably received via a wireless network, since this offers a high degree of flexibility for the device 30, in particular with regard to the positioning of the same.
  • the interface 12 2 can provide a connection to a wireless or wired network.
  • the wireless network can comprise a radio network, which is understood to mean cellular radio applications, for example 3G, 4G or 5G.
  • the configuration signal is designed in such a way that a sequence of executable process parts is displayed or contained in the configuration signal and both indicates the subset of the process parts stored in the data memory 16 and clearly defines a sequence of the selected process parts in the action process 24. This means that the sequence of executable process parts and thus the course of action are clearly defined in the configuration signal, even if the program code to be executed itself is not necessarily part of the configuration signal.
  • Components connected to inputs 28i to 28 can also belong to the periphery, as can the components connected to outputs 28s.
  • the course of action 24 can have one or more rule trees 44i and 44 2 or be represented by the rule trees, the number of rule trees 441 and / or 44 2 in the course of action 24 being any number of 1 can be.
  • the rule trees 44i and 44 2 can be processed in parallel or one after the other, ie sequentially, and can relate, for example, to different functions of the device implementing the course of action 24.
  • one of the rule trees can describe a sensor evaluation and another rule tree can describe an actuator control or a data display or data transmission.
  • the rule trees 44i and 44 2 comprise at least one start node 46i or 46 2 and in each case at least one end node (NULL) 48i and 48 2 or 48 3 .
  • Process nodes or execution nodes 52 are arranged between the start node 46 and the end node 48, each rule tree 44i and 44 2 comprising at least one process node 52.
  • At least each of the execution nodes 52, optionally the start node 46 and also optionally the end node 48 can implement one of the executable process parts 18, so that the nodes 52, 46 and possibly 48 shown can be viewed as representations of the process parts.
  • Each node may implement or represent one of the executable flow parts included in the storyline. Alternatively or additionally, a node can also represent a combination of several executable process parts.
  • Each execution node 52 is linked to at least one preceding node by a corresponding link 52 and is linked to at least one subsequent node via a corresponding link 54.
  • the execution node 52i of the rule tree 44i is linked to the start node 46i via the link 54i, which indicates that an output of the node refers to a subsequent node, for example using a pointer / pointer.
  • This subsequent node can in turn access a memory area in which a result of the preceding node can be stored.
  • Different outputs can have values for different pointers, so that, for example, depending on which output of the node is reached (e.g. true or false, larger or smaller, etc.) different pointers take effect, ie different subsequent nodes are called.
  • a node has, for example, two outputs, each output being able to be linked to an execution node 522 or 52s via a corresponding link 54 2 or 54 3 .
  • the outputs can be results of an OR link, so that an input variable is output to the execution node 52 2 or 52 a based on the respective result of the OR link.
  • start nodes 46 have no link to a preceding node, for example, while end nodes 48 can be executed without a link to a subsequent node.
  • Execution nodes 52 preferably have at most two inputs and at most two outputs.
  • Each execution node 52, optionally each start node 46 and optionally each end node 48 can be assigned a predefined identifier, such as a node number, within the action sequence 24, via which the sequence part that can be executed by the node 52, 46 or 48 can be clearly addressed.
  • the processor of the device can be designed to address each executable sequence part of the plurality of executable sequence parts via this predefined node number.
  • the node number can, for example, indicate a memory area in which the instructions to be implemented and / or the variables to be processed are stored.
  • rule trees 44i and 44 2 are shown in such a way that a predecessor node always references a successor node, the present exemplary embodiments are not restricted to this. Rather, nodes can also enter a direct or indirect predecessor node as successors or reference them by means of a link.
  • the execution node 52 2 could reference the node 46i or the execution node 52i, which means that an output of the node could point to an input of the node or to the node itself.
  • Such constructs can be used, for example, to implement loops and counters.
  • the evaluation of the graph can be ended by returning from the function. For example, starting from node 48i or 48 2, it is possible to jump to the next rule tree 44 2 .
  • the processor can be configured to execute the plurality of executable process parts of the course of action from the starting point of the course of action to an end of the course of action.
  • the configuration signal can contain information for this. sen, which defines the at least one starting node of the course of action.
  • the processor can evaluate the configuration signal for these variables.
  • the starting point can be the starting node 46i or 46 2 , but can alternatively also be any other node of a rule tree 44i or 44 2 or of the course of action 24.
  • the course of action can be implemented by one or more individual graphs or rule trees.
  • a single graph can be a start node (first layer) from which the evaluation of the rule tree begins.
  • a single node has a maximum of two outputs that can be implemented in the form of pointers that point to the next node to be executed. As soon as a selected output points to 0, e.g. a zero pointer, the evaluation of the graph can be finished.
  • the program, the course of action can consist of more than one graph.
  • Each graph can have its own start node assigned to the graph, with the graphs being able to be completely separate but also connected to one another, for example having a common subgraph. Alternatively, this can also be understood to mean that a rule tree can have more than one start node.
  • the start nodes of all graphs or rule trees can, for example, be called up one after the other in a kind of main function of the program code implemented as constant or unchangeable.
  • the course of action (graph) or a part of it, the rule tree, can consist of different nodes that perform different tasks and / or represent modes of operation.
  • the graph does not have to be connected, but rather all linked nodes form a rule tree that is processed.
  • the complete course of action can consist of several rule trees that work independently of one another or be represented by them.
  • the so-called start nodes or first-layer nodes can be evaluated periodically, possibly triggered by different timers. Which nodes are the starting nodes can be communicated to the device via a corresponding interface, for example the input interface 12.
  • the further course of the program can be determined based on events by the nodes themselves, since each individual node clearly points to the next node to be evaluated and thus specifies the sequence.
  • the evaluation of a rule tree terminates when the pointer of the next node to be evaluated is set to a null ID, an end node 48.
  • 5 shows a schematic block diagram of part of a rule tree 44 according to an exemplary embodiment, two executable process parts 18i (a) and 18 2 (b) being represented by process nodes 52i and 52 2 , respectively.
  • the execution node 52i has two inputs 56i and 66 2 , via which input quantities or input information from preceding nodes can be obtained by means of corresponding links 54i and 54 2, respectively.
  • the execution node 52i on two outputs 58i and 682 which may be connected via respective links 54s and 54 4 with subsequent nodes.
  • the output 58 2 is connected to an input 56s of the execution node 52 2 by means of the link 54.
  • the process node 52 2 can also have a further input 56 4 , which is linked to another node via a link 54 s .
  • the drain node 52 2 may have one or two output node 58 3 and / or 4 comprise 58 to corresponding outputs via links 54 e and 54 provide. 7
  • the outputs of 58i to 58 4 each may be understood as the starting pointer of the respective nodes and, for example, as a pointer subsequent nodes are implemented on the index numbers, which eg. In, in conjunction with FIGS. 9a-explained "next_t / f'field of the Nodes are saved.
  • the pointers can indicate the next node to be executed. In the exemplary embodiments explained here, all connections which represent the output of a node can therefore be understood as pointers.
  • a node number 62i can be uniquely assigned to the process node 52i.
  • a node number 62 2 can be uniquely assigned to the process node 52 2 , so that the process nodes 52i and 52 2 can both be distinguished and addressed separately, even with the same or identical function.
  • FIG. 6a shows a schematic block diagram of an interconnection of a process node 52 in a rule tree according to an exemplary embodiment.
  • Inputs 56i and 56 2 can be connected to different memory areas 64i and 64 2 via links 54i and 54 2 , whereby memory areas 64i and 64 2 can be any areas in data memories 16, 34 or 36 that provide corresponding input variables for node 52 .
  • Nodes of a graph can implement a function that defines a processing of at least one input variable of the corresponding executable sequence part.
  • compare an operator of node 52 may be 641 and 64 2 stored values.
  • Pointers can be output at the outputs 58i and 58 2 , which point to a subsequent node by means of the corresponding links 54s or 54 4 , in the event that the result of the operator is fulfilled (true) or not fulfilled ( false).
  • the control flow, i.e. H. the next node to be evaluated is influenced by the result of the comparison.
  • FIG. 6b shows a schematic representation of a link of a process node 52 in a rule tree, the implemented operation being an arithmetic operation. These include, for example, addition, subtraction, multiplication or division.
  • the values in the memory areas 64i and 64 2 can be linked so that a result can be made available to a subsequent node by means of the link 54a.
  • the result can be stored in a further memory area and a pointer to this memory area can be transmitted by means of the link 54a.
  • Fig. 6b shows an arithmetic node. Arithmetic or mathematical operations can be carried out with values in two memory areas, e.g. B. +, -, x, /, modulo, amount and the like. The result is made available in a separate memory area assigned to the node and externally addressable. A single pointer indicates the control flow, i.e. the next node to be evaluated. It is pointed out once again that each node, if necessary, can be assigned a memory area where the assigned result can be stored, for example the “res” -Fe! D in the structure according to FIG. 9a.
  • Exactly this memory area can be set as an input in another node in order to pass on the result, which occurs, for example, when the index number of the node is set as the input of another node.
  • the inputs and outputs of the nodes can thus be completely independent of one another.
  • 6c shows a schematic representation of a link of the process node 52 in the rule tree, in which the implemented function is a memory operation, that is, the node 52 stores a value of the memory area 64i and / or 64 2 in another memory area and transmits it using the Link 54a at output 58 has a pointer which points to the memory area in which the value is stored.
  • An input variable can be written to the memory area of the other input variable or to the output node.
  • Fig. 6c shows a storage node.
  • the value from memory area 1 is stored in a dedicated memory area assigned to the node and externally addressable.
  • the value from memory area 1 can be written to the address of memory area 2, regardless of the value it contains. Both memory operations can also be carried out combinatorially. Saving in memory area 2 can be used to carry out comparisons with old values.
  • a single pointer can indicate the control flow, i.e. the next node to be evaluated.
  • 6d shows a schematic representation of the process node 52 according to an exemplary embodiment in which information inputs obtained by means of links 54i and 54 2 , for example directly or through access to memory areas 64, result in an action to be carried out, for example an activation of the peripherals via the output 58 is issued.
  • Fig. 6d shows an action node.
  • An action node can differ from the other main groups of nodes in that there is no evaluation here of operations on memory areas takes place.
  • This node can be used to call functions in the program code from a list of possible selectable functions, the selection of functions which the device has can be hardware-specific or device-specific.
  • the interface can be used to ensure that the selectable action nodes match the device functions.
  • the functions called up in the program code are so-called normal implemented functions and can therefore be used for all possible functions, such as controlling actuators, setting variables and memories, external communication and the like.
  • a single pointer can specify the control flow, i.e. the next node to be evaluated.
  • FIG. 7 shows an exemplary representation of computer-implemented instructions, that is to say code, for the exemplary representation of different functions implemented by nodes.
  • 15 different arithmetic functions are defined using two input variables a, b, which can be distinguished from one another by a function identification 661 to 6615.
  • the arithmetic functions include, for example, addition, subtraction, multiplication, division, the absolute sum of the individual amounts of a, b, the semi-absolute sum using the amount value of the operator a or b, the absolute -Difference as the difference between the absolute values, the semi-absolute difference using only one amount, the digit 1 standard sum as the amount of addition, the digit 1 standard difference as the amount of the difference, the absolute multiplication, that means the magnitude of the multiplication, the half-absolute multiplication using only one magnitude value of the operators a or b, the absolute division, i. H. the amount of division and the modulo operator mod.
  • 12 comparison functions with the function IDs 16 to 27 are defined as an example, which include an equal comparison, a non-equal comparison (unequal), a smaller comparison, a less than or equal comparison, an equal value comparison , a half-amount-equal comparison, a not-amount-equal comparison, an amount-not-equal comparison, an amount-less-amount comparison, an amount-less comparison, may include an amount less than or equal to amount comparison and / or an amount less than or equal to comparison.
  • 9 logic functions which can also be assigned to the comparison operations, can be defined as examples.
  • the function IDs 6628 to 66 36 (previously 66 «to 66 27 ) describe functions of the link as logical And, logical Or, logical exclusive Or (XOR), one-sided negative And, one-sided negative Or, one-sided negative exclusive-Or, Both sides denied And, both sides denied Or, and both sides denied Exclusive Or.
  • a negation (! A) setting to the value true (true) by a && 1 or setting to the value false (false) by a && 0 can be carried out .
  • Such functions or logic operations can also be carried out for operator b.
  • the function IDs 66 3 7, 663s and 66 3 9 can exemplarily describe functions that take place using only one input variable and are thus assigned to nodes that only have one input.
  • a type or function of the executable sequence part of the large number of executable sequence parts can be clearly defined by five parameters. These parameters can be contained in the configuration signal. The use of integer numbers is advantageous because they have a small memory area and at the same time have a sufficiently high range of values. According to alternative exemplary embodiments, at least one of the parameters can be defined differently than an integer number. The five parameters can be sufficient to clearly define the type of process part that can be executed. One of the parameters, such as the function ID, can define the function of the executable process part. A second and a third parameter can define a first and second memory area, respectively, which is associated with the first and second input of the executable sequence part, respectively.
  • a fourth and fifth parameter can define corresponding memory areas which are associated with the outputs 58i and / or 58 2 and 58, respectively.
  • the generator 22 can be designed to contain the integer numbers that represent the five or six parameters of the
  • Play node each uniquely associated with a memory area of the data memory. This makes it possible to ensure that each node accesses a data storage area assigned to it in order to receive input variables or to store output variables
  • Unnecessary parameters e.g. if only one of the outputs is required, can be left out or set to 0.
  • the generator can be designed to check the configuration signal for the corresponding parameters.
  • the corresponding parameters in particular the integer numbers, can each be uniquely associated with a memory area of the data memory 16, so that it is sufficient to only specify the memory area which specifies the further information to be implemented.
  • the information 26 contained in the configuration signal can have a sequence of integer numbers, which represents a small amount of data that has to be transmitted.
  • FIG. 7 shows an exemplary assignment of node types or functions to function IDs 66.
  • FIG. 8 shows an exemplary representation of code which reproduces instructions which instruct the generator 22 of the device 10 or the control device 38 of the device 30 to send the configuration signal 14 to the function ID 66, which is described in connection with FIG. 7 to evaluate.
  • the generator can be designed to evaluate the parameters contained in the configuration signal and to configure the graph as a function of their value.
  • the node with ID i can be evaluated as which node type it is configured as, here conf_typ [i] specifies the type, see line 6.
  • Further properties of the node, such as inputs and / or outputs and / or memory areas for storage of results can also be specified, see line 7ff.
  • 9a shows an exemplary illustration of code for defining a node structure and thus a structure which the executable process parts 18 follow.
  • “Int16_t” or “uint16_t” can be used to designate signed or unsigned 16-bit integer numbers that are used to generate a result (res), input variables (inp_1, inp_2) and references or pointers to define subsequent nodes for the case of a positive (true) or negative (false) result (next_t, next_f), which has already been discussed in connection with FIG.
  • “type” it is possible to specify the type of nodes it is the present node. It becomes clear that the respective memory requirements can be adapted to the number of different values, for example the parameter type can be adequately writable with 8-bit integer numbers, while otherwise signed or unsigned, i.e.
  • a node can be uniquely defined or determined by only five of these properties.
  • the sixth parameter in the node structure which is not required for the unambiguous definition, can describe the result of the operation by the node and is indicated, for example, by the "res" field. The result does not have to be specified externally when defining the graph can arise, for example, when the node is executed, so only five parameters are required for definition, even if there are six variables in the node structure.
  • the nodes of the graph can be represented as a structure (struct) in the program.
  • the structure can contain the variable "type” or equivalent, which defines the type of node.
  • the variable "res” saves, for example, the result of an arithmetic operation or a comparison and the variables "input_1 / input_2" and “next_t / next_f” basically act as pointers for the input variables and the next node to be executed.
  • memory efficiency An integer value can be used instead of a pointer. This is possible because the maximum number of nodes and variables that can be used is limited and is defined a priori, ie is predefined.
  • the zero pointer can be represented by the largest representable number in the data system.
  • the data type "node” can be defined in such a way that it is made up of
  • Arithmetic, action and storage nodes can only use one of the two outputs, e.g. out_t, so that, for example, out_f can be set to NULL-ID.
  • a predefined number of nodes, variables and actions can exist. All of them can be organized in the form of arrays and arranged one behind the other in the memory. This enables unique addressing via an integer number, which can be referred to as an index number.
  • the index numbers can be used like general pointers and can generally be seen as such. This type of implementation only saves resources when addressing memory areas. Similar to a zero pointer, a zero ID can exist.
  • the maximum number of nodes (MAX_KNOTS), the maximum number of variables (MAX_VARS), the number of sensors (N_SENSORS), the number of actions (N_ACTIONS), the number of nodes of a first layer or layer , so for example. Entry node in a graph or rule tree, (N_First_Layer), NULLJD, d. H. the null pointer, and any other variables can be defined, such as distinctions as to whether it is an arithmetic node for performing an arithmetic operation (IS_ARI) and / or whether it is a comparison node for performing a comparison operation (IS_VGL).
  • IS_ARI arithmetic node for performing an arithmetic operation
  • IS_VGL comparison node for performing a comparison operation
  • a corresponding pointer can also require 32 bits in the memory.
  • 32 bits By implementing it as an integer value with 16 bits, for example, 4 * 16 bits, ie 8 bytes, can be saved in each node. This is particularly advantageous when fewer than 2 16 nodes, variables and actions are used.
  • the advantage can also be achieved if a data reduction of another category is carried out, for example when using a 64-bit controller for which 32-bit variables are used.
  • the first inputs are dereferenced as nodes, for example (or the memory area of the "res" field of a node), everything above or after are then sensors, then actions, everything above is treated as variables.
  • This can result from the sequence shown in FIG. 9b, in which the nodes, variables (VARS), sensors and actions one after the other.
  • the order shown is arbitrary or arbitrary. However, it is necessary that it is defined once and then remains identical or adhered to. The information gained in this way can thus be saved within the configuration signal 14, since the structure is known on both sides.
  • T_SEN node types below the previously defined value
  • T_SEN nodes.
  • Values are T_SEN nodes.
  • Values ä T_SEN and ⁇ T_AKT are sensors. Starting from this value, all values of a T_AKT and ⁇ T_THR are actions. Anything beyond this, that means a T_THR, are variables.
  • T_MAX indicates the maximum possible number in the system.
  • the "type" variable in the node struct can determine what exactly the node has to do as soon as it is called.
  • This can also be used to define the type of node, for example as an arithmetic node in which the ID 661 to 6615 is used, which is explained in connection with FIG.
  • the type of node can be divided into different groups.
  • arithmetic nodes can be implemented that are used for arithmetic operations such as B. "+” or " * " is set up. The values of the two input memory areas, the inputs, are used and the result of the operation is saved in the "res" field of the node struct.
  • the values of the two input memory areas can also be used here and the result of the operation can be saved in the "res" field.
  • this also allows exceptions, for example a negation or a comparison to “true” or “false” (true / false), since these only use one input variable.
  • one or more storage nodes can be defined that use the value at the address of one of the inputs and write this, for example, to the address of the other input or in a “res” field specially provided for this purpose, as is the case with the Fig. 6c is described.
  • Storage nodes can be used, for example, to store sensor values (which can change over time).
  • action nodes can be provided which can be used to call up previously implemented functions in the program code.
  • the two input variables can be used as transfer parameters for the called function, although this is optional.
  • Action nodes can be relevant to enable more complex program structures. For example, sending a value can be represented via an action node.
  • the available actions are partly hardware-dependent, since a device for sending a WLAN message requires a WLAN module.
  • the action nodes can accordingly be specially implemented or set up for the hardware used. All functions that can be called up by the user in the program code can be linked to a respectively assigned action node and numbered, for example using a corresponding identifier that is comparable to the function ID. An action with a certain number then always corresponds to the same function in the actual program code and this is called as soon as an action node with the corresponding identifier, which can be represented via the "type" field, is called or triggered in the graph.
  • 10a shows an exemplary code in which a maximum number of nodes in the course of action is defined in line 2, which means that the list of nodes always has the same length within this configuration.
  • Line 5 defines a list of actions for the node.
  • Line 8 defines a list of nodes in a first layer, which will be discussed later.
  • different variables such as threshold values or buffers, are defined.
  • Sensor values are defined in line 14.
  • the maximum number of possible nodes and actions as well as sensors and variables is specified a priori. Therefore, before the start of the main function, the memory area for the corresponding structures can be allocated, i.e. associated.
  • the first-layer nodes or start nodes just mentioned can be an important element for evaluating the courses of action implemented on the device.
  • a list of pointers to the node structure can be used to define the starting nodes, as described in line 8 of the code in FIG. 10a.
  • the start node can, for example, be a node 46 of the respective rule tree 44, as described in connection with FIG. 4.
  • 10b shows an exemplary code which indicates that a node number i up to a maximum number N_ACTIVE_FL of nodes or actions is run through the graph and the corresponding node is executed (doKnot).
  • the generator of a device can be designed to create the course of action in such a way that it comprises at least one start node at which the course of action is started by the processor.
  • the course of action comprises several rule trees
  • such a start node can be provided for each rule tree.
  • the processor is designed to periodically evaluate the at least one start node in order to obtain an evaluation result. This means that each rule tree is started periodically at the correspondingly assigned start node.
  • the processor can be designed to process the multiplicity of executable process parts of the course of action from the starting point, d. H. the start node of the course of action, to be carried out to an end of the course of action, as is shown, for example, in FIG. 4.
  • FIG. 10c shows exemplary code for execution by the processor.
  • a received value k is evaluated, the value k representing, for example, a pointer to the node which is currently to be executed.
  • the values can be read from the associated node.
  • the expression “k-> type” can, for example, return the type of the node, ie in lines 3, 7 and 12, for example, the type of the node is evaluated.
  • the expression "k->inp_1" in line 14 is an example of containing the index number of the first input.
  • the value of the input can be provided by the “getlnput provided” function in lines 14 and 15, which transfers the index numbers of the inputs to the associated values.
  • the "getPointer defined" function in line 10 can work in the same way; this takes the index number of the output ("k->next_t” or "k->next_f") and delivers the associated pointer to the next node. If the “type” variable in “k” determines that it is an action, the associated action is not called up via the value “k”, but via the value “k-> type”, since each action is unique is determined by the type numbers.
  • a corresponding embodiment can be obtained, for example, in that, in accordance with the explanations in connection with FIGS. 7 and 10d, nodes are defined in such a way that values of k of 64 and larger define actions to be carried out.
  • the check carried out in line 7 thus differentiates whether it is an action if the value k is at least 64, with any other configurations being possible.
  • the return value of the function (which is linked to the action) is not considered here as an example.
  • the pointer that is returned in the specified line 10 is the pointer to the next node, which is provided by the mechanism described above.
  • Line 17 shows that a node intended as a storage node can be treated as a special case in which the value 1 is written into the "res" field, see line 19, or into the storage area of the other input value, see lines 21 and 22 .
  • the start nodes can be evaluated one after the other in the main function of the program code.
  • This routine can always be identical, regardless of the graphs that then provide the actual functionality of the device. This ensures that the program code in the EEPROM, i. H. the data memory 16, can remain unchanged even if the device is reprogrammed.
  • the function that evaluates the nodes is also always identical and firmly encapsulated in the program code, which means stored in the data memory 16. It can, for example, be called initially by the main function for the start nodes and then cling to the output pointers of the individual nodes until the end of the graph (zero pointer or node 48) is reached.
  • the processor can be designed to evaluate a node to be executed according to which type it is and then to execute the corresponding operation linked to the node, as is described with reference to FIG. 10d.
  • FIG. 10d shows an exemplary representation of code which reproduces instructions which instruct the processor 31 of the device 10 or the control device 38 of the device 30 to forward the result of the evaluation of the node type (k-> type) from FIG. 10c. to lead.
  • k-> type node type
  • the expression “k-> res” indicates that a result res is obtained based on the function defined below.
  • control device 38 or the processor 31 can evaluate the node or the function to determine what type it is and then carry out the corresponding operation linked to the node.
  • the results of the node or the function can be stored in the "res" field of the structure. If a node is set as an input by another node, the node behind it reads the memory area of the "res” field from the input node. This allows results to be passed on by simply linking nodes in the graph.
  • the successor is dependent on the result of the “res” field of the previous node, in particular in the case of comparisons and logical operations, which is illustrated in FIG. 10e, which shows an exemplary code in which for the case of the node type as an arithmetic node (IS_ARI) the pointer for the next node is retrieved, see line 4.
  • IS_ARI arithmetic node
  • the pointer is received depending on the result obtained true / false, see lines 9 to 12. This means the next one to be executed Knot determined.
  • Embodiments of the present invention are based on the knowledge that the graph can be reconfigured while the device is running in order to represent any functions or programs, that is, to maintain flexibility of the device. Since the structures for the nodes, actions and variables for a piece of hardware can be fixed and are stored in volatile memory at runtime, it can be sufficient to correctly link and configure them one after the other in order to represent a new program. Such information can be indicated in the configuration signal. For example, all nodes can be initialized to type 0, ie not initialized, set. This can, for example, be controlled or triggered via a suitable event, that is, a corresponding instruction, for example from a central control device or a server. Each node of a rule tree can be addressable via an integer number.
  • Each node can also be clearly defined using five integer numbers. Two values for input and output and one for the type. So six integer values can be used per node used, namely the five integer numbers mentioned for the configuration of the node and a sixth value for the node number.
  • the configuration signal can have the six integer values. It is possible, but not required, to send one message per node. It is possible to use six consecutive values in the message for a node and to define any number of nodes within a configuration signal.
  • the configuration signal or a further configuration signal it can be defined which node or which nodes function as start nodes.
  • This information can in principle also be part of the configuration message of the nodes, for example it can be placed at the end, but is preferably clearly separated from the other integer values.
  • 256 * 16 bits when using 16-bit integrators for the consecutive numbering of nodes and variables
  • 512 bytes of information are transmitted and optionally a few more bytes depending on the number of starting nodes used. After successful configuration by the generator, the graph can be used immediately.
  • Fig. 1 1 shows a schematic block diagram of a device 110 according to one embodiment, the inputs (interface 28i), "Outputs" (interface 28 5) and an internal logic which comprises the act outlet 24.
  • inputs for. B. serve sensors, switches / buttons or other controls.
  • the inner logic can implement the program to be run, which the user has previously specified through the interface. This can for example be carried out in a continuous loop in normal operation.
  • Outputs can include, for example, actuators of various types, switches, motors, external communication, for example send value XY to server N, but can alternatively or additionally also set / change timers and interrupts on the hardware of the device and / or change Include memory areas in the volatile memory of the hardware.
  • An algorithm or a program or a sequence of machine-readable instructions can be represented by the internal logic, which inputs ge and outputs but also variables, timers and internal elements of the microprocessor. Any program can be represented and set up by the structure according to the invention.
  • FIG. 12 shows a schematic block diagram of a device 120 according to an exemplary embodiment, which can be formed similarly to the device 10 or the device 30 or the device 110, the peripherals 32 being connected to the outputs 28s in the form of a switch by wire or wirelessly, which can be controlled in different states, either "anVaus" or the like.
  • Control signals 68 1 and / or 68 2 can be received from external devices 72i and / or 72 2 , such as servers or the like, via inputs 28i.
  • the control signals 68 1 and / or 68 2 can have an instruction for switching on or off the switch of the peripherals 32.
  • the course of action implemented in the device 120 can be implemented such that the peripherals are controlled in accordance with the control signals 68 1 and 68 2 .
  • FIG. 12 shows an example of how the logic in the device links inputs and outputs with one another and for which exemplary embodiments can be used.
  • the device 120 is designed, for example, as a pure actuator.
  • the internal logic can be designed in such a way that in the event that the external device 72i instructs to switch on the switch or, if the external device 72 2 instructs to switch the switch 32 on, the device 120 then controls the peripherals 32 accordingly. Otherwise the switch at output 28 5 is switched to "off".
  • FIG. 13 shows a schematic block diagram of a device 130 according to an exemplary embodiment, in which the inputs 28i are connected to sensors 74 t and 74 2 in any number, 1 in order to receive sensor signals 76i and 76 2 with corresponding sensor values.
  • the device 130 can be designed to evaluate the sensor signals 76 t and 76 2 and to control the peripherals by means of an output signal 78, which include a server, for example, in order to store the evaluated data there.
  • FIG. 13 shows a configuration of the device 130 as a pure sensor with communication.
  • the internal logic can be designed, for example, in such a way that a new value is stored by the sensor 74i regularly, approximately every 60 minutes. A new value is stored by the sensor 74 2 in an identical or different time interval, approximately every 120 minutes.
  • the internal logic can be designed in such a way that, if, for example, a certain number of measured values, for example 100, are present, a minimum and a maximum of the values from sensor 74i and / or a mean value of the values from sensor 74 2 is calculated. A corresponding result is sent to the server. Alternatively or additionally, the old values can be deleted and a new series of measurements can be started.
  • the sensor 74 can be set up, for example, to detect a temperature; a server 82 can control, for example, an additional switch or valve or heating valve 84, the device 140 being designed to control various switches 86 1 and / or 86 2 to open or close the heating valve 84 and thereby receive information from switches 86 1 , sensors 74 and / or servers 82.
  • the sensor 74 can be set up as a temperature sensor in order to measure a temperature, any other configuration also being implementable.
  • the internal logic can e.g. B. be designed so that if the value of the switch 86 1 is changed or the temperature is changeable, for example has changed by more than 10 degrees, then a new state is sent to the server 82 and the corresponding values are stored. If, for example, the server 82 sets the controller 68 to “on”, the temperature can for example be checked and compared with a setpoint value; if the temperature is below the setpoint value, then the heating valve 84 can be opened, otherwise closed . If the server sets the control to "on”, a state of the input switch 861 can be passed on to the output switch 86 2 , for example, otherwise the output can be switched to "off".
  • Figures 12, 13 and 14 describe different configurations of devices. It should be noted that these configurations can be implemented by one and the same device, for example by reconfiguration or reconfiguration or reconfiguration by means of a configuration signal. If the device is implemented in such a way that all configurations can be mapped by the hardware, each of the examples can thus only be reconfigured into the other configuration by means of the configuration signal. If the graph, ie the course of action, is to be changed, a message with the structure described below can be sent for each node used and / or a combinatorial message with information relating to several or all nodes is sent, either all nodes in total or all to changing knot. The length of the message can be designed depending on the communication protocol used. A node can be redefined using six numerical values each.
  • Either only individual nodes can be changed / redefined or the device can be informed via a special delete message that it should completely reset its current graph.
  • the six numerical values that define a node can, for example, be arranged in a defined manner, whereby an order can be configured as desired, as long as it is known to the device in order to enable correct decoding:
  • index number Since all nodes and variables can be uniquely addressed by their index number, four numbers can be sufficient to describe the structure of the graph, i.e. H. to change the link between the nodes and with variables by changing the index numbers of the memory areas of the inputs and outputs.
  • a further index number can indicate which node is to be redefined and the type of node can be changed with an additional sixth integer value.
  • the most naive method is to send the complete program over the communication interface. This method offers the greatest flexibility, since hardware drivers can be exchanged here.
  • the biggest disadvantage is that, on the one hand, the program code is very large and, on the other hand, the microprocessor has to be re-programmed. has to be programmed or flashed.
  • the flash process during operation is extremely complex and very energy-intensive (which makes the process unusable on hardware with limited resources / energy harvesting) and also represents a risk if it cannot be completed in full (in this case the device may then be “bricked” and no longer accessible from the outside, unless the processor is reconnected to a PC via a debugger for the processor family).
  • the scenario / parameterization variant tries to "pre-program" a selection of possible programs that the user wants to use - that is, there are several small sub-programs on the device, all of which exist on the hardware when it is compiled for delivery change its functionality, it can be told that it should now select a different scenario / program.
  • An interpreter is a program that is able to convert code in the so-called "interpreter language” into a high-level language equivalent (e.g. C ++). The conversion takes place line by line; d.
  • Interpreters tend to be very complex programs, but they provide maximum flexibility thanks to their 1-to-1 conversion into high-level program code.
  • the disadvantage here analogous to the method of reflashing, is that the transmitted program code (despite the interpreter language) is very large. Furthermore, this variant requires a great deal of memory, since the code to be interpreted must be kept permanently in memory, as well as the elements of the program to be executed.
  • Interpreters are generally used on “fixed hardware” (desktop PCs etc.).
  • FPGRA embodiments according to the invention allow a high degree of flexibility, little transmission and do not require an energy-consuming flash process. These advantages can possibly go hand in hand with a somewhat poorer execution efficiency of the program, since, to put it simply, the detour via the graph and the node data type is always taken, which, however, is less important for the area of application. For example, sending or receiving a message over the air consumes far more energy than executing code on the main processor - the flash process and other advantages are also obtained. As a result, the described concept is ideally suited to be used on hardware with limited resources in the form of energy and devices with energy harvesting.
  • Every GOTO program can be represented by nodes, which means that every Turing-complete program can be represented by the node structure.
  • Some exemplary embodiments are described below.
  • One embodiment relates to a loT-based heating thermostat in which the periphery has a temperature sensor and an actuator or actuator around the positions of a heating valve.
  • a generator or part of a control device is designed to create a course of action based on a configuration signal received from the loT-based heating thermostat, the graphic representation of which has a first graph that causes a repeated, possibly cyclical query of the temperature sensor.
  • the sensor signals read out can be saved locally and / or transmitted to a server.
  • the course of action causes the actuator to be controlled as a function of the determined temperature, for example to close a valve if a target temperature is reached or exceeded and / or to open the valve if the temperature falls below this.
  • a device can also be used for cooling devices, for example air conditioning systems, the valve then being opened when a target temperature is exceeded and closed when the target temperature is reached or below.
  • 15 shows a schematic block diagram of a system 150 according to an exemplary embodiment, which by way of example includes device 10, but alternatively or additionally can also include other devices described herein, for example device 30, 110, 120, 130 or 140.
  • the system 150 further includes a device 155 that has an output interface that is configured to send the configuration signal 14 to the device 10.
  • the device 155 comprises a signal generator 92 which is designed to provide the configuration signal, at least in a baseband version thereof.
  • the configuration signal 14 is preferably provided by the signal generator 92 in such a way that it describes a sequence of executable process parts of a plurality of executable process parts, i.e. selects a subset of the executable process parts stored in the device 10 and specifies their interconnection.
  • the specified sequence of executable process parts clearly describes a course of action, for example the course of action 24.
  • the device 155 can be designed to receive a user input 94 which describes the course of action to be created.
  • a graphic representation 96 of the course of action 24 can be provided, which the user can create or configure on a device 98 provided for this purpose.
  • the device 98 can be part of the device 155, but can also use access to a web interface 102 of the device 155, so that the user input 94 can be received via a network connection from the device 98 connected via the network connection.
  • the graphic representation 96 is only one of several possible configurations, which alternatively or additionally can also include programming in text form.
  • a workflow can include the following: a) Compiling the logic / graph to be run or the course of action on a computer via, for example, a web interface or a program:
  • the system 160 can comprise the devices 98 (block B) and 155 (block C), which are designed to exchange a data flow for the exchange of logic and / or parameters or setpoint values, as is indicated by the letter a.
  • the device 155 i.e. the encoder, can be connected to one or more devices 10i and / or IO2 via a communication network (block D), such as the Internet, as can the device 98.
  • the peripheral 32 (block E) can are also in communication with the devices 10i and / or IO2 via the communication network 104.
  • meta information for the periphery can also be created, for example a name or virtual addresses, as is represented by the letter e.
  • Further information such as hardware-specific information such as IDs (identifications), specifications and / or hardware-related assignments, can be exchanged between the devices 10i and IO2 and the device 98, as shown by the letter b.
  • the devices 10i and I O2 can exchange output values, sensor values or actual parameters (letter c) and / or setpoint parameters (letter b) with the periphery 32 using the communication network 104.
  • An exchange of logic information or parameterizations can take place between the devices 98 and 155 and using the communication network 104 with the devices 10i and IO2, as shown by the letter a. This includes the configuration signal, for example.
  • the periphery 32 can adapt any type of data receivers / sinks, actuators, control devices for parameterization, including mobile devices such as smartphones.
  • a numerical code that, for example, reproduces a sequence of parameters (in the data flow graph (a) - the parameters which later control the program sequence are coded in the numbers) can be converted into executable program logic, which then runs in a continuous loop the device (in the data flow graph (A)).
  • a compiler which translates program code (e.g. C ++) into machine language, which can then be executed on hardware.
  • the difference between the FRGRA and a compiler is that no executable machine code is generated.
  • the FPGRA is also not an interpreter, since the code is not converted directly into a high-level language equivalent and executed. As with the compiler, no “build-up phase” is necessary.
  • a logic is built up in the existing program code by means of skillful pointer arithmetic and class structures which are able to control the program sequence and which is kept in the volatile memory.
  • This procedure means that the energy-intensive flash process for changing structures in the non-volatile memory (EEPROM) can be dispensed with, and it is still possible to reprogram the device completely Turing.
  • the user defines the program sequence that the device should follow later. This can be done by "clicking together" a graph that contains the rules and courses of action; but also z. E.g. using a kind of scripting language with which the process rules can be defined ("If X, then Y, otherwise Z -> Then A").
  • the interface also defines the possible actions of the device or the outputs.
  • An action can, for example, be a hardware function ("Send XY", "Set Time N to X”), but also simply a function call in the software. This preselection is necessary because, on the one hand, the number of action nodes (which make the available actions in the device available in the device) is technically limited - since in reality the available memory is always limited - and, on the other hand, the outputs and actions that can be carried out are hardware-specific ( For example, a device that does not have an actuator may not be provided with a set of rules that ultimately wants to operate an actuator).
  • a graph that evaluates a temperature sensor in the input may only be transferred to devices that have such a sensor, or WiFi communication only to WiFi-enabled devices.
  • Exemplary embodiments are based on representing the part of the instructions (program code) to be executed that is relevant for the specific application of the device as a rule tree, which means that the implemented functions can be represented as a rule tree.
  • a graph can be represented by a special structure in the program code and can be reassembled at any time by means of a configuration message, which contains considerably less information for transmission than normal program code, in order to represent a different program.
  • this type of representation can be Turing-complete, whereby effectively any program can be represented as long as it can be stored in memory. Nodes of the graph can be understood as something like the smallest possible subroutines that are possible on the hardware.
  • a step 1710 comprises storing a plurality of executable process parts in a data memory, each process part describing at least one operating instruction.
  • a step 1720 includes receiving a configuration signal with an input interface.
  • a step 1730 comprises creating a course of action which comprises a sequence of sequence parts of the plurality of stored sequence parts that are specified in the configuration signal.
  • a step 1740 comprises addressing a periphery in accordance with the course of action using an interface which is designed to communicate with the periphery.
  • FIG. 18 shows a schematic flow diagram of a method 1800 for providing a configuration signal that can be carried out using device 155, for example.
  • a step 1810 includes providing a configuration signal using a signal generator, so that the configuration signal describes a sequence of executable process parts from a plurality of executable process parts, the sequence of process parts clearly describing a course of action with a plurality of operational regulations.
  • a step 1820 includes sending the configuration signal with an output interface.
  • FIG. 19 shows a schematic block diagram of a device 190 according to an exemplary embodiment in which the inputs 28i are set up for connection to a loT modem 108, for example for communication via the resource-limited medium 106.
  • the loT modem 108 can alternatively also be an internal device.
  • the inputs can be configured to be connected to one or more sensors 74, for example a MEMS sensor. This can be set up, for example, as an acceleration sensor.
  • the output 28s can be set up for communication with a server of the peripherals 32.
  • the device can be designed to create the course of action in response to a received configuration signal in such a way that, in response to a corresponding signal from sensor 74, what a movement or a lack of movement or may be a corresponding acceleration, a message is sent to the server which indicates a position of the device 190, for example specifying a radio cell used by the modem 108 in which the device is currently located.
  • the device 190 can function as a movement tracker, for example for goods to be transported by a logistics company.
  • An acceleration sensor (“MEMS") and the currently received radio cell of the NB-loT modem serve as inputs.
  • MEMS acceleration sensor
  • the user could, for example, configure the device in such a way that after a movement was initially detected via the MEMS, the device falls into a “transport state” (which is solved via an internal variable).
  • the device checks at regular intervals whether it is still moving. As soon as no movement is detected n times, the "transport status" is ended and the device sends the currently connected radio cell to a server.
  • the threshold values can of course be freely selected and can be set using the configuration signal or changed using new configuration signals. More complex nesting with other states is also possible.
  • FIG. 20 shows a schematic block diagram of a device 200 according to an exemplary embodiment, in which the inputs 28i are set up for connection to a mobile device 112, for example a smartphone / mobile phone, a tablet computer or the like.
  • the mobile device 112 can have a positioning device 114 via which a position can be determined, for example by means of a Global Positioning System (GPS), Galileo or Glonass.
  • GPS Global Positioning System
  • Galileo Galileo
  • Glonass Alternatively, a corresponding positioning device can also be provided as an independent device and can be connected to the device 200 via the inputs 28i.
  • the device 200 can be designed to create the course of action in response to a configuration signal in such a way that one or more devices or components are addressed via the outputs 28s.
  • a derver 32i can receive a message with a position of the device 200, for example at predetermined intervals and / or if the position received by means of the positioning device 114 deviates from a predetermined position or area stored in the device 200 or received externally.
  • the mobile device 112 can be informed accordingly, for example an application (application; App) that runs there.
  • the device 200 can be designed to control a display device 32 2 in order to display a status.
  • the device 200 can function as an anti-theft device, for example for bicycles or vehicles.
  • the backup is activated, for example, via an app in the mobile phone 1 12 (the status in the app is sent to the device and is stored internally in a variable that can be set as an input for the course of action); this is also visualized via a connected LED .
  • the device notes its current position via a GPS module 114. This is updated at a regular interval specified by the user. In the event of a change, the device immediately reports its current position back to the user's smartphone 112 and / or a server 32i at a regular interval.
  • FIG. 21 shows a schematic block diagram of a device 210 in accordance with an exemplary embodiment which is configured to be connected to different devices or devices via the inputs 28i in order to receive input signals.
  • a wireless interface 116 such as Bluetooth® or another wireless technology
  • a timer or clock 118 a signal generator for user input, such as a switch or button 122 and / or other sensors such as a heart rate monitor 124.
  • LCD Liquid Crystal Display
  • the device 210 can be designed to switch, for example, based on the user input between two or more operating modes in which different information is displayed on the display device 126, for example information received via the interface 116, a time of the timer 118 and / or information from the Sensors 124 and / or information derived therefrom. This information can be transmitted via the outputs 28s, for example using the interface 116, and alternatively or additionally be displayed.
  • the device 210 can provide a type of intelligent heart rate watch.
  • a button 122 can be used to switch over what the LCD display 126 is to show.
  • the device can receive information from other devices (for example the associated chest strap for differential pulse measurement or the speedometer of a bicycle or a smartphone) or send it to other devices.
  • the via bluetooth 116 received information can be used, for example, to display an alarm on the display 126 if a value set by the user is exceeded.
  • the devices described herein can be programmed or reprogrammed using configuration signals. Corresponding partial courses of action can be stored in the device and re-linked or configured by means of the configuration signal.
  • the drainage parts can be different according to the hardware belonging to the device or provided or possible, but the configuration of the generator can be the same or have the same effect.
  • Sequence parts described here can be understood as predefined and / or parameterizable and / or adaptable code modules that can be combined to form an overall code, the course of action, in a selection and / or property and / or sequence determined by the configuration signal.
  • aspects have been described in connection with a device, it goes without saying that these aspects also represent a description of the corresponding method, so that a block or a component of a device is also to be understood as a corresponding method step or as a feature of a method step. Analogously, aspects that have been described in connection with or as a method step also represent a description of a corresponding block or details or features of a corresponding device.
  • embodiments of the invention can be implemented in hardware or in software.
  • the implementation can be carried out using a digital storage medium such as a floppy disk, a DVD, a Blu-ray disc, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or other magnetic memory or optical memory, on which electronically readable control signals are stored, which can interact or cooperate with a programmable computer system in such a way that the respective method is carried out. Therefore, the digital storage medium can be computer readable.
  • Some embodiments according to the invention thus include a data carrier that has electronically readable control signals that are able to communicate with a programmable com to cooperate computer system in such a way that one of the methods described herein is carried out.
  • exemplary embodiments of the present invention can be implemented as a computer program product with a program code, the program code being effective to carry out one of the methods when the computer program product runs on a computer.
  • the program code can for example also be stored on a machine-readable carrier.
  • exemplary embodiments include the computer program for carrying out one of the methods described herein, the computer program being stored on a machine-readable carrier.
  • an exemplary embodiment of the method according to the invention is thus a computer program which has a program code for carrying out one of the methods described here when the computer program runs on a computer.
  • a further exemplary embodiment of the method according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the methods described herein is recorded.
  • a further exemplary embodiment of the method according to the invention is thus a data stream or a sequence of signals which represents or represents the computer program for performing one of the methods described herein.
  • the data stream or the sequence of signals can, for example, be configured to be transferred via a data communication connection, for example via the Internet.
  • Another exemplary embodiment comprises a processing device, for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.
  • a processing device for example a computer or a programmable logic component, which is configured or adapted to carry out one of the methods described herein.
  • Another exemplary embodiment comprises a computer on which the computer program for performing one of the methods described herein is installed.
  • a programmable logic component for example a field-programmable gate array, an FPGA
  • a field-programmable gate array can interact with a microprocessor in order to carry out one of the methods described herein.
  • the methods are performed by any hardware device. This can be universally applicable hardware such as a computer processor (CPU) or hardware specific to the method such as an ASIC.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Stored Programmes (AREA)

Abstract

L'invention concerne un dispositif comprenant une interface de saisie conçue pour recevoir un signal de configuration, une mémoire de données, dans laquelle est enregistrée une pluralité de programmes exécutables, chaque programme décrivant au moins une procédure, un générateur conçu pour établir un processus opérationnel qui comprend une succession de programmes indiqués dans le signal de configuration parmi la pluralité de programmes enregistrés, une interface conçue pour communiquer avec un périphérique et un processeur configuré pour adresser le périphérique en fonction du processus opérationnel.
PCT/EP2020/057130 2019-03-18 2020-03-16 Dispositif et procédé pour la programmation à distance WO2020187843A1 (fr)

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EP1315055A2 (fr) * 2001-11-27 2003-05-28 Rockwell Automation Technologies, Inc. Système et procédé pour génération d'ordre d'execution pour bloc fonctionnel
EP2357541A1 (fr) * 2010-02-12 2011-08-17 Rockwell Automation Technologies, Inc. Bloc de fonction macro pour logique intégrée au niveau d'un dispositif d'encapsulation
EP2790076A1 (fr) * 2013-04-10 2014-10-15 Siemens Aktiengesellschaft Procédé de commande d'une machine de production ou d'une machine-outil, programme informatique pour l'implémentation du procédé et dispositif de commande doté d'un tel programme informatique

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EP1315055A2 (fr) * 2001-11-27 2003-05-28 Rockwell Automation Technologies, Inc. Système et procédé pour génération d'ordre d'execution pour bloc fonctionnel
EP2357541A1 (fr) * 2010-02-12 2011-08-17 Rockwell Automation Technologies, Inc. Bloc de fonction macro pour logique intégrée au niveau d'un dispositif d'encapsulation
EP2790076A1 (fr) * 2013-04-10 2014-10-15 Siemens Aktiengesellschaft Procédé de commande d'une machine de production ou d'une machine-outil, programme informatique pour l'implémentation du procédé et dispositif de commande doté d'un tel programme informatique

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WO2024093926A1 (fr) * 2022-11-04 2024-05-10 北京镁伽机器人科技有限公司 Procédé et appareil de commande de système automatique, et dispositif électronique et support de stockage

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