WO2020186512A1 - 光电二极管的制备方法、光电二极管和cmos图像传感器 - Google Patents

光电二极管的制备方法、光电二极管和cmos图像传感器 Download PDF

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Publication number
WO2020186512A1
WO2020186512A1 PCT/CN2019/079052 CN2019079052W WO2020186512A1 WO 2020186512 A1 WO2020186512 A1 WO 2020186512A1 CN 2019079052 W CN2019079052 W CN 2019079052W WO 2020186512 A1 WO2020186512 A1 WO 2020186512A1
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Prior art keywords
photoresist
shielding layer
thickness
predetermined position
layer
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PCT/CN2019/079052
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English (en)
French (fr)
Inventor
姚国峰
沈健
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2019/079052 priority Critical patent/WO2020186512A1/zh
Priority to CN201980000504.4A priority patent/CN110088917B/zh
Publication of WO2020186512A1 publication Critical patent/WO2020186512A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8033—Photosensitive area
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • This application relates to the technical field of image sensor manufacturing, and in particular to a method for manufacturing a photodiode, a photodiode, and a CMOS image sensor.
  • CMOS image Sensor is a sensor that can convert incident light signals into electrical signals, and is widely used in smart phones, digital cameras, driving recorders, and security monitoring equipment.
  • the CMOS image sensor is composed of multiple pixel units, that is, a pixel array, and each pixel unit corresponds to at least one photodiode.
  • the working principle of the CMOS image sensor is: when light is irradiated to the pixel unit of the image sensor, the photodiode corresponding to the pixel unit generates a corresponding amount of electric charge according to the incident light intensity. These electric charges are transferred to the pixel unit after analog-to-digital conversion and signal processing. The corresponding chromaticity is output at the corresponding position, and the images corresponding to all pixel units are added together to obtain the overall image.
  • the full well capacity refers to the maximum amount of charge that each pixel unit can store. Since the charge is mainly stored in the depletion area of the photodiode, an important factor in determining the full well capacity is the area of the photodiode.
  • the area of the photodiode corresponding to the pixel unit also decreases, resulting in a decrease in the full well capacity.
  • the low full well capacity will reduce the dynamic range of the detectable light of the pixel unit, which will seriously reduce the quality of the image.
  • the method of increasing the doping concentration of the photodiode is adopted to increase the full well capacity.
  • this method will make it difficult to deplete the carriers in the central area of the photodiode, so that there are carriers remaining, making it difficult for the pixel unit to transfer all the carriers when outputting an image, resulting in a decline in the quality of the output image, such as image smearing , Excessive dark current or white spots.
  • the present application provides a method for manufacturing a photodiode, a photodiode, and a CMOS image sensor, which increase the contact area between a substrate with a first doping type and a region with a second doping type, and improve the full well capacity of the photodiode .
  • the first aspect of the present application provides a method for manufacturing a photodiode, including:
  • a shielding layer is formed on a substrate, the substrate has a first doping type, a preset position is provided on the substrate, and the preset position is a position where the doping type is the second doping type.
  • the first doping type is different from the second doping type, the shielding layer is used to shield ions injected into the substrate, and the shielding strength of the shielding layer is related to the thickness of the shielding layer;
  • the method further includes:
  • the photoresist layer is processed, the thickness of the photoresist layer above the preset position is less than the thickness of the photoresist layer above the preset position, and the photoresist layer above the preset position
  • the surface is curved;
  • the processing the shielding layer includes:
  • the etching process is performed on the photoresist layer.
  • the processing the shielding layer includes:
  • the photoresist layer is processed.
  • processing the photoresist layer includes:
  • the photoresist in the photoresist layer is a positive photoresist
  • the light transmittance of the gray-scale mask above the predetermined position is greater than that of the gray mask above the predetermined position
  • the transmittance of the gray-scale mask, and the difference in the transmittance of the gray-scale mask above the predetermined position is negatively related to the thickness of the photoresist above the predetermined position; if said If the photoresist in the photoresist layer is a negative photoresist, the light transmittance of the gray-scale mask above the preset position is smaller than that of the gray-scale mask located above the non-predetermined position.
  • the light transmittance of the film plate, the light transmittance of the gray-scale mask above the predetermined position is proportional to the thickness of the photoresist above the predetermined position.
  • processing the photoresist layer includes:
  • the photoresist in the photoresist layer is a positive photoresist
  • direct-write photolithography is used to perform photolithography processing on the photoresist layer
  • the photolithography intensity above the preset position Is greater than the lithography intensity above the predetermined position, the difference in the lithography intensity above the predetermined position is negatively related to the thickness of the photoresist above the predetermined position; if the photoresist in the photoresist layer If the resist is a negative photoresist, the lithography intensity above the predetermined position is less than the lithography intensity above the predetermined position, and the lithography intensity above the predetermined position is the same as that above the predetermined position.
  • the thickness of the photoresist is positively correlated.
  • processing the photoresist layer includes:
  • the photoresist layer is imprinted by nanoimprinting, the imprinting depth above the preset position is greater than the imprinting depth above the preset position, and the imprinting depth above the preset position is greater than the imprinting depth above the preset position.
  • the thickness of the photoresist above the preset position is negatively correlated.
  • the processing the shielding layer includes:
  • the masking layer is imprinted by nanoimprinting, the imprinting depth above the preset position is greater than the imprinting depth above the preset position, and the imprinting depth above the preset position is greater than the imprinting depth above the preset position. It is assumed that the thickness of the photoresist above the position is negatively correlated.
  • the upper surface of the shielding layer is a spherical coronal curved surface or a comb-shaped curved surface.
  • the second aspect of the present application provides a photodiode, including:
  • a third aspect of the present application provides a CMOS image sensor, including: at least one photodiode as described in the second aspect.
  • the present application provides a method for manufacturing a photodiode, a photodiode, and a CMOS image sensor.
  • the method includes: forming a shielding layer on a substrate, the substrate has a first doping type, and a preset position is provided on the substrate.
  • the doping type is different from the second doping type; the shielding layer is processed, the thickness of the shielding layer above the preset position is smaller than the thickness of the shielding layer above the non-preset position, and the upper surface of the shielding layer above the preset position is curved Ion implantation to the substrate, so that the implanted ions form a region with a curved bottom surface and a second doping type to increase the contact area between the substrate and the region; remove the shielding layer to obtain a photodiode.
  • the application increases the contact area between the substrate with the first doping type and the region with the second doping type, and improves the full well capacity.
  • Fig. 1 is a schematic diagram 1 of a photodiode in the prior art
  • Figure 2 is a second schematic diagram of a photodiode in the prior art
  • Fig. 3 is a third schematic diagram of a photodiode in the prior art
  • FIG. 4 is a schematic diagram 1 of the process of manufacturing a photodiode provided by this application.
  • FIG. 5 is a schematic diagram 1 of the manufacturing process of the photodiode provided by this application.
  • Figure 6 is a schematic diagram of the imprint mold provided by this application.
  • FIG. 7 is a schematic diagram 2 of the process of manufacturing a photodiode provided by this application.
  • FIG. 8 is a second schematic diagram of the manufacturing process of the photodiode provided by this application.
  • FIG. 1 is a schematic diagram 1 of a photodiode in the prior art.
  • the photodiode forms an n-type doped region 101 on the p-type substrate 100
  • the depletion region of the photodiode is the contact area between the p-type substrate 100 and the n-type doped region 101, as shown in the figure.
  • the 103 is shown.
  • the area of the photodiode corresponding to the pixel unit also decreases.
  • the area of the depletion region in the photodiode is also reduced, resulting in a reduction in the full well capacity, thereby causing a problem of deterioration of image quality. It is worth noting that the schematic diagrams of the photodiodes shown in this application are all side views.
  • the method of increasing the doping concentration of the photodiode is used to increase the full well capacity.
  • this method may cause problems such as image smearing, excessive dark current, or white spots.
  • FIG. 2 is a second schematic diagram of a photodiode in the prior art.
  • the way to form a photodiode with multiple npn junctions is: inserting the p-type doped region 202 into the n-type doped region 101 to form a U-shaped structure, which can make the photodiode generate additional consumption. Exhaust areas 203a and 203b. Compared with FIG. 1, the area of the depletion region of the photodiode is increased, and the full well capacity of the photodiode is improved.
  • FIG. 3 is a third schematic diagram of a photodiode in the prior art. As shown in FIG. 3, by forming a deeper n-type doped region 302 under the n-type doped region 101, an additional depletion region 303 can be generated in the photodiode to increase the full well capacity.
  • the structure of the photodiode in FIGS. 2 and 3 formed by the above method does not affect the quality of the output image, the two methods require multiple ion implantation steps on the substrate, and the process is complicated.
  • the present application provides a method for manufacturing a photodiode. Not only can the area of the depletion region of the photodiode be increased, but also only one ion implantation is used, and the process is simple.
  • FIG. 4 is a schematic flow chart 1 of the method for manufacturing a photodiode provided by this application.
  • the execution subject of the method flow shown in FIG. 4 may be a photodiode manufacturing device.
  • the photodiode manufacturing method provided in this embodiment may include:
  • the shielding layer is used to shield the ions injected into the substrate, and the shielding strength of the shielding layer is related to the thickness of the shielding layer.
  • the photodiode preparation device in this embodiment can be a device that integrates coating, photolithography, etching, ion implantation and other functions into one, which can realize the formation of the shielding layer of the substrate and the coating of the photoresist layer. The process of cloth and so on. It can also be a device that integrates multiple modules that realize multiple functions such as coating, photolithography, etching, and ion implantation.
  • the photodiode in this embodiment may be a photodiode in a CMOS image sensor.
  • a substrate with the first doping type is provided.
  • the substrate may be a silicon wafer or epitaxial silicon grown on the silicon wafer.
  • the first doping type may be p-type doping or n-type doping.
  • a preset position is provided on the substrate, and the preset position is a position where the doping type is the second doping type, wherein ions with the second doping type are injected into the substrate at the preset position, and the substrate A region with the second doping type is formed in the bottom.
  • the first doping type is different from the second doping type, and the area where the area with the second doping type is in contact with the substrate is the depletion area.
  • the shielding layer is used to shield the ions injected into the substrate, and the shielding strength of the shielding layer is related to the thickness of the shielding layer. The greater the thickness of the shielding layer, the stronger the shielding strength for ions. Since a preset position is provided on the substrate, the preset position is a position where a region with the second doping type is formed after ion implantation; the non-preset position is a position where the first doping type of the substrate is maintained after ion implantation.
  • the shielding layer in this embodiment can be, but is not limited to, a photoresist layer formed of photoresist, a silicon dioxide layer formed of silicon dioxide, or PDMS formed of polydimethylsiloxane (PDMS). Floor.
  • FIG. 5 is a schematic diagram 1 of the manufacturing process of the photodiode provided by this application.
  • a shielding layer 501 is formed on the substrate 100, wherein the position between A and B of the substrate is a preset position of the substrate.
  • the shielding layer 501 has the same thickness for illustration. It is conceivable that the shielding layer 501 formed on the substrate 100 in this embodiment may have different thicknesses.
  • S402 Process the shielding layer so that the thickness of the shielding layer above the preset position is smaller than the thickness of the shielding layer above the non-preset position, and the upper surface of the shielding layer above the preset position is a curved surface.
  • the preset position is a position where a region with the second doping type is formed after ion implantation
  • the non-preset position is a position where the first doping type of the substrate is maintained after ion implantation, under the premise of the same ion implantation energy .
  • the thickness of the shielding layer above the preset position needs to be smaller than the thickness of the shielding layer above the non-preset position. Only in this way, the shielding layer above the non-preset position can effectively shield the ion implantation into the substrate.
  • the upper surface of the shielding layer above the preset position is a curved surface.
  • the curved surface is not limited to a spherical crown curved surface or a comb-like curved surface; the spherical crown curved surface may be a spherical crown convex surface or a spherical crown concave surface.
  • the processing method for the shielding layer in this embodiment can be different according to the shielding layer.
  • the thickness of the shielding layer above the preset position can be obtained by nanoimprinting less than the shielding layer above the non-preset position.
  • the thickness of the layer, and the upper surface of the shielding layer above the preset position is a curved photoresist layer. In order to make the thickness of the photoresist layer above the non-predetermined position greater than the thickness of the photoresist layer above the preset position, and the upper surface of the photoresist layer above the preset position is curved.
  • the negative correlation between the embossing depth at the preset position and the thickness of the photoresist above the preset position means that the greater the thickness of the photoresist above the preset position, the smaller the embossing depth.
  • Fig. 6 is a schematic diagram of the imprinting mold provided by this application. As shown in FIG. 6, the positions on both sides of the imprinting mold correspond to non-preset positions on the substrate, and the position in the middle of the imprinting mold corresponds to the preset position on the substrate. It can be seen that the imprint depth on both sides of the imprint mold is smaller than the imprint depth in the middle of the imprint mold, and the imprint depth in the middle of the imprint mold is set according to the shape of the finally formed curved surface.
  • Fig. 6 exemplarily shows that the pattern on the imprint mold corresponding to the preset position on the substrate is comb-shaped. It is conceivable that the embossing depth at the position of the protruding teeth in the comb tooth shape is smaller than the embossing depth at the position of the recessed teeth on the imprinting mold.
  • the pattern on the imprinting mold can be transferred to the photoresist layer by means of nanoimprinting, and the shielding layer can be obtained.
  • the thickness of the photoresist layer 5011b above the non-preset position is greater than the thickness of the photoresist layer 5011a above the preset position, and the thickness of the photoresist layer 5011a above the preset position
  • the upper surface is a curved photoresist layer.
  • the thickness of the masking layer above the preset position can be directly obtained by the method of nanoimprinting, which is less than the thickness of the masking layer above the non-predetermined position, and above the preset position
  • the upper surface of the shielding layer is a curved shielding layer.
  • the shielding layer can be obtained by etching, photolithography, etc. in the prior art, which will not be repeated here.
  • ion implantation is performed on the substrate through the shielding layer.
  • the implanted ions have the second doping type.
  • the shielding layer above the non-predetermined area can completely shield the implanted ions, so that the ions implanted at the non-predetermined position do not enter the substrate. Since the thickness of the shielding layer above the preset area is less than the thickness of the shielding layer, the injected ions can penetrate the shielding layer and enter the substrate, starting from the inner surface above the substrate, extending downward to form a second doping type area.
  • the shielding strength for the implanted ions is different.
  • the shielding strength of the shielding layer is related to the thickness of the shielding layer, the lower surface of the region with the second doping type is also a curved surface, and the curved surface has the same shape as the curved surface of the upper surface of the shielding layer above the preset position.
  • the lower surface of the region with the second doping type formed in this embodiment is a curved surface, and has a larger contact area with the substrate, and therefore has a larger area of depletion region than in the prior art.
  • the lower surface of the region with the second doping type as shown in FIG. 1 is a plane parallel to the horizontal plane, and its depletion region is shown by the depletion region in the dashed frame.
  • the region 502 with the second doping type formed in the substrate in this embodiment is shown in c in FIG. 5, and the lower surface of the region is comb-shaped, compared to the lower surface of the region in FIG. 1, It has a larger contact area with the substrate.
  • the area in the dashed frame in c in FIG. 5 is the depletion area.
  • the shielding layer can be removed by an etching method to obtain a photodiode with a larger depletion region.
  • the present application removes the photoresist layer to obtain a substrate 100 having the first doping type, and forming a comb-shaped lower surface with a second doping type Of the photodiode in the area 502.
  • the photoresist above the preset position area can be further etched so that the thickness of the photoresist 5011a above the preset position area is lithographically 0, such as As shown in e in Figure 5.
  • the manufacturing method of the photodiode provided in this embodiment includes: forming a shielding layer on a substrate, the substrate has a first doping type, a preset position is provided on the substrate, the first doping type and the second doping type Different; the shielding layer is processed so that the thickness of the shielding layer above the preset position is smaller than the thickness of the shielding layer above the non-preset position, and the upper surface of the shielding layer above the preset position is curved; ion implantation is performed on the substrate, The implanted ions form a region with a curved bottom surface and the second doping type to increase the contact area between the substrate and the region, remove the shielding layer, and obtain a photodiode.
  • the contact area between the substrate with the first doping type and the region with the second doping type is increased, that is, it increases.
  • the area of the depletion region increases the full well capacity.
  • the processing method for the shielding layer in this application is different.
  • the processing method of the shielding layer will be described in accordance with the characteristics of the shielding layer. Specifically, the method of processing the shielding layer will be explained mainly based on the hardness characteristics of the shielding layer.
  • the photodiode manufacturing device in this embodiment stores a preset hardness, and the hardness of the shielding layer can be input to the photodiode manufacturing device before the photodiode is manufactured, so that the photodiode manufacturing device can obtain the hardness of the shielding layer.
  • the material of the shielding layer is a material with a hardness less than or equal to the preset hardness.
  • the material of the shielding layer can be, but is not limited to, photoresist or polydimethylsiloxane. Since the hardness of the masking layer is relatively small, the masking layer can be imprinted by nano-imprinting. The embossing depth above the preset position is greater than the embossing depth above the non-preset position, and the embossing depth above the preset position is negatively related to the thickness of the photoresist above the preset position.
  • the thickness of the imprint mold above the preset position is greater than the thickness of the imprint mold above the non-preset position, and the thickness of the imprint mold above the preset position is negatively related to the thickness of the photoresist above the preset position. Exemplarily, it may be as shown in FIG. 6.
  • processing the shielding layer is processing the photoresist layer.
  • the photoresist layer is processed, in addition to the nanoimprinting method described above, the photoresist layer may also be processed by variable dose photolithography.
  • a gray-scale mask is placed on the photoresist layer, and the photoresist layer is exposed.
  • the transmittance of the gray-scale mask above the preset position is greater than the transmittance of the gray-scale mask located above the non-preset position, and the transmittance of the gray-scale mask above the preset position is higher than that of the preset position. It is assumed that the thickness of the photoresist above the position is negatively correlated. For example, the greater the light transmittance of the gray mask above the preset position, the smaller the thickness of the photoresist above the preset position, and vice versa, the greater the thickness of the photoresist above the preset position.
  • the transmittance of gray-scale masks can be between 0% and 100% Arbitrary setting, that is, when the photoresist is exposed, the exposure dose is adjustable, and the size of the exposure dose determines the thickness of the photoresist after development.
  • the photoresist can be divided into positive photoresist and negative photoresist according to the development characteristics of the photoresist.
  • the photoresist in the photoresist layer is a positive photoresist
  • the light transmittance of the gray mask above the preset position is greater than that of the gray mask located above the non-preset position
  • the exposure dose of the photoresist above the preset position is greater than the exposure dose of the photoresist above the non-preset position, that is, the thickness of the photoresist above the preset position can be made smaller than the photoresist above the non-preset position The thickness of the glue.
  • the transmittance of the gray-scale mask above the preset position is negatively related to the thickness of the photoresist above the preset position, that is, the exposure dose of the photoresist above the preset position and the photoresist above the preset position
  • the thickness is negatively related, that is, the larger the exposure dose, the smaller the thickness of the photoresist above the preset position, so that the upper surface of the photoresist above the preset position is curved.
  • the photoresist in the photoresist layer is a negative photoresist
  • the light transmittance of the gray-scale mask above the preset position is smaller than that of the gray-scale mask located above the non-preset position.
  • the light rate is such that the exposure dose of the photoresist above the preset position is less than the exposure dose of the photoresist above the non-predetermined position, that is, the thickness of the photoresist above the preset position can be made smaller than the light The thickness of the resist.
  • the light transmittance of the gray mask above the preset position is positively related to the thickness of the photoresist above the preset position, that is, the exposure dose of the photoresist above the preset position and the photoresist above the preset position
  • the thickness is positively correlated, that is, the greater the exposure dose, the greater the thickness of the photoresist above the preset position, so that the upper surface of the photoresist above the preset position is a curved surface.
  • the photoresist can be divided into positive photoresist and negative photoresist according to the development characteristics of the photoresist.
  • direct writing lithography can be used to perform photolithography processing on the photoresist layer.
  • the photolithography intensity above the preset position is greater than the photolithography intensity above the non-predetermined position, and the photolithography intensity above the preset position is equal to the preset
  • the thickness of the photoresist above the position is negatively correlated, that is, the greater the photolithography intensity, the smaller the thickness of the photoresist above the preset position.
  • Direct-write lithography can directly change the intensity or energy of the laser or electron beam in the micro area, thereby changing the exposure dose, and then achieving the same effect as the gray-scale mask mentioned above, that is, obtaining the thickness of the photoresist above the preset position It is less than the thickness of the photoresist above the non-predetermined position, and the upper surface of the photoresist above the preset position is curved.
  • the photoresist in the photoresist layer is negative photoresist
  • the photolithography intensity above the preset position is less than the photolithography intensity above the non-predetermined position
  • the photolithography intensity above the preset position is compared with the It is assumed that the thickness of the photoresist above the position is positively correlated.
  • the material of the shielding layer is a material with a hardness greater than the preset hardness
  • the material of the shielding layer may be but not limited to silicon dioxide. Due to the high hardness of silica, it cannot be directly processed by nanoimprinting.
  • FIG. 7 is a description of the method for manufacturing the photodiode provided by the application Flow chart two, as shown in FIG. 7, the manufacturing method of the photodiode provided in this embodiment may include:
  • the hardness of the shielding layer is greater than the preset hardness, a photoresist layer needs to be formed on the shielding layer.
  • the method of forming the photoresist layer may be to coat photoresist on the shielding layer to obtain the photoresist layer. .
  • S703 Process the photoresist layer so that the thickness of the photoresist layer above the preset position is smaller than the thickness of the photoresist layer above the non-preset position, and the upper surface of the photoresist layer above the preset position is curved .
  • variable-dose lithography can be used, such as setting a gray-scale mask or using direct-write lithography to process the photoresist layer to obtain that the thickness of the photoresist layer above the preset position is less than the non-preset
  • the thickness of the photoresist layer above the position, and the upper surface of the photoresist layer above the preset position is a curved photoresist layer.
  • nanoimprinting can also be used to imprint the photoresist layer to obtain that the thickness of the photoresist layer above the preset position is less than the thickness of the photoresist layer above the non-preset position
  • the thickness of the adhesive layer, the upper surface of the photoresist layer above the preset position is a curved photoresist layer.
  • FIG. 8 is a second schematic diagram of the manufacturing process of the photodiode provided by this application.
  • a silicon dioxide layer 5012 is formed on the substrate 100, and a photoresist layer 5011 is formed on the silicon dioxide layer 5012.
  • the photoresist layer 5011 is processed.
  • the thickness of the photoresist layer 5011a above the preset position is smaller than the thickness of the photoresist layer 5011b above the non-predetermined position, and the upper surface of the photoresist layer 5011a above the preset position is spherical.
  • the shape of the photoresist layer can be transferred to the shielding layer by etching the photoresist layer.
  • the thickness of the silicon dioxide layer 5012a above the preset position is smaller than the thickness of the silicon dioxide layer 5012b above the non-preset position, and
  • the upper surface of the silicon dioxide layer 5012a above the preset position is a spherical crown.
  • the thickness of the photoresist layer 5011b above the non-predetermined position is large, after the photoresist layer is etched, a part of the photoresist layer 5011b may remain.
  • S705 Perform ion implantation on the substrate through the shielding layer, so that the implanted ions form a region with a curved lower surface and a second doping type.
  • the lining can be A region 802 with the second doping type whose lower surface is curved is obtained from the bottom. Since the lower surface is a curved surface, under the same other conditions, compared to the area with the second doping type in FIG. 1, the contact surface of the substrate and the area 802 increases, and the depletion area of the photodiode increases. This increases the full well capacity of the photodiode.
  • the dashed frame in d in Figure 8 is the depletion zone.
  • the shielding layer is removed. If there is an unetched photoresist layer, it can also be removed together to obtain the photoelectricity of the second doping type region 802 with a curved bottom surface. diode.
  • a photoresist layer can be formed on the shielding layer, and a variable dose photolithography or nanoimprint method is used to obtain a curved surface above the preset position.
  • the photoresist layer is then etched to obtain a curved shielding layer above the preset position, and then ion implantation is used to form a second doping type region with a curved bottom surface in the substrate, which increases the photodiode’s
  • the depletion region increases, thereby increasing the full well capacity of the photodiode.
  • This application also provides a photodiode, as shown in d in FIG. 5 or e in FIG. 8, the photodiode includes:
  • the photodiode in this embodiment is prepared by the above-mentioned photodiode manufacturing method. Since the lower surface of the region with the second doping type in the substrate in the photodiode is curved, the depletion region in the photodiode is increased The area improves the full well capacity of the photodiode.
  • the application also provides a CMOS image sensor.
  • the CMOS image sensor includes at least one photodiode manufactured by the photodiode manufacturing method in the foregoing embodiment.
  • CMOS image sensor provided by the present application has the same technical effects as the manufacturing method of the photodiode in the foregoing embodiment, and will not be repeated here.
  • a person of ordinary skill in the art can understand that all or part of the steps in the foregoing method embodiments can be implemented by a program instructing relevant hardware.
  • the aforementioned program can be stored in a computer readable storage medium.
  • the steps including the foregoing method embodiments are executed; and the foregoing storage medium includes: ROM, RAM, magnetic disk, or optical disk and other media that can store program codes.

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Abstract

本申请提供一种光电二极管的制备方法、光电二极管和CMOS图像传感器，该方法包括：在衬底上形成遮蔽层，衬底具有第一掺杂类型，衬底上设置有预设位置，第一掺杂类型和第二掺杂类型不同；对遮蔽层进行处理，使预设位置上方的遮蔽层的厚度小于非预设位置上方的遮蔽层的厚度；对衬底进行离子注入，使注入的离子形成下表面为曲面的且具有第二掺杂类型的区域，以增加衬底与区域的接触面积；去除遮蔽层，得到光电二极管。本申请增加了具有第一掺杂类型的衬底与具有第二掺杂类型的区域的接触面积，提高了满阱容量。

Description

光电二极管的制备方法、光电二极管和CMOS图像传感器 技术领域
本申请涉及图像传感器制造技术领域，尤其涉及一种光电二极管的制备方法、光电二极管和CMOS图像传感器。
背景技术
金属互补氧化物半导体(CMOS)固态图像传感器(CMOS Image Sensor)是一种可将入射光信号转换为电信号的传感器，广泛应用于智能手机、数码相机、行车记录仪以及安防监控等设备中。CMOS图像传感器是由多个像素单元，即像素阵列组成的，每个像素单元对应至少一个光电二极管。
CMOS图像传感器的工作原理是：当光照射到图像传感器的像素单元时，该像素单元对应的光电二极管根据入射光强产生相应数量的电荷，这些电荷经过模数转换以及信号处理后在该像素单元对应的位置处输出对应的色度，而所有像素单元对应的图像加在一起便得到了整体的图像。满阱容量指的是每个像素单元能够存储的电荷最大数量，由于电荷主要贮存在光电二极管的耗尽区，因此决定满阱容量的一个重要因素就是光电二极管的面积。然而，随着CMOS图像传感器的像素单元的尺寸的减小，使得像素单元对应的光电二极管的面积也减小，导致满阱容量降低。而低的满阱容量会降低像素单元的可探测光的动态范围，这会严重降低图像的质量。
现有技术中，采用增加光电二极管的掺杂浓度的方式，提高满阱容量。然而这种方式会导致光电二极管的中心区域载流子难以耗尽，从而有载流子残留，使得像素单元在输出图像时难以转移全部载流子，导致输出图像质量下降，例如发生图像拖尾、暗电流过大或白点等问题。
发明内容
本申请提供一种光电二极管的制备方法、光电二极管和CMOS图像传感器，增加了具有第一掺杂类型的衬底与具有第二掺杂类型的区域的接触面积，提高了光电二极管的满阱容量。
本申请的第一方面提供一种光电二极管的制备方法，包括：
在衬底上形成遮蔽层，所述衬底具有第一掺杂类型，所述衬底上设置有预设位置，所述预设位置为形成掺杂类型为第二掺杂类型的位置，所述第一掺杂类型和所述第二掺杂类型不同，所述遮蔽层用于遮挡注入所述衬底的离子，所述遮蔽层的遮挡强度与所述遮蔽层的厚度相关；
对所述遮蔽层进行处理，使所述预设位置上方的遮蔽层的厚度小于非所述预设位置上方的遮蔽层的厚度，所述预设位置上方的遮蔽层的上表面为曲面；
通过所述遮蔽层对所述衬底进行离子注入，使注入的离子形成下表面为曲面的且具有第二掺杂类型的区域，以增加所述衬底与所述区域的接触面积；
去除遮蔽层，得到光电二极管。
可选的，当所述遮蔽层的材料为硬度大于预设硬度的材料时，所述对所述遮蔽层进行处理之前，还包括：
在所述遮蔽层上形成光刻胶层；
对光刻胶层进行处理，所述预设位置上方的光刻胶层的厚度小于非所述预设位置上方的光刻胶层的厚度，所述预设位置上方的光刻胶层的上表面为曲面；
所述对所述遮蔽层进行处理，包括：
对所述光刻胶层进行刻蚀处理。
可选的，当所述遮蔽层的材料为硬度小于或等于预设硬度的材料，且所述材料为光刻胶时，所述对所述遮蔽层进行处理，包括：
对光刻胶层进行处理。
可选的，所述对光刻胶层进行处理，包括：
在所述光刻胶层上放置灰度掩膜版，并对所述光刻胶层进行曝光处理；
其中，若所述光刻胶层中的光刻胶为正性光刻胶，则所述预设位置上方的所述灰度掩膜版的透光率大于位于非所述预设位置上方的所述灰度掩膜版的透光率，所述预设位置上方的所述灰度掩膜版的透光率不同与所述预设位置上方的光刻胶的厚度负相关；若所述光刻胶层中的光刻胶为负性光刻胶，则所述预设位置上方的所述灰度掩膜版的透光率小于位于非所述预设位置上方的所述灰度掩膜版的透光率，所述预设位置上方的所述灰度掩膜版的透光 率与所述预设位置上方的光刻胶的厚度正比关。
可选的，所述对光刻胶层进行处理，包括：
其中，若所述光刻胶层中的光刻胶为正性光刻胶，则采用直写式光刻对所述光刻胶层进行光刻处理；所述预设位置上方的光刻强度大于非所述预设位置上方的光刻强度，所述预设位置上方的光刻强度不同与所述预设位置上方的光刻胶的厚度负相关；若所述光刻胶层中的光刻胶为负性光刻胶，则所述预设位置上方的光刻强度小于非所述预设位置上方的光刻强度，所述预设位置上方的光刻强度与所述预设位置上方的光刻胶的厚度正相关。
可选的，所述对光刻胶层进行处理，包括：
采用纳米压印对所述光刻胶层进行压印，所述预设位置上方的压印深度大于非所述预设位置上方的压印深度，所述预设位置上方的压印深度与所述预设位置上方的光刻胶的厚度负相关。
可选的，当所述遮蔽层的材料硬度为小于或等于预设硬度的材料，且所述材料为非光刻胶时，所述对所述遮蔽层进行处理，包括：
采用纳米压印对所述遮蔽层进行压印，所述预设位置上方的压印深度大于非所述预设位置上方的压印深度，所述预设位置上方的压印深度与所述预设位置上方的光刻胶的厚度负相关。
可选的，所述遮蔽层的上表面为球冠状曲面或梳齿形曲面。
本申请的第二方面提供一种光电二极管，包括：
具有第一掺杂类型的衬底，以及，在所述衬底中形成的具有第二掺杂类型的区域，所述区域自所述衬底上方的内表面向下伸出，所述区域的下表面为曲平面，所述第一掺杂类型和所述第二掺杂类型不同。
本申请的第三方面提供一种CMOS图像传感器，包括：至少一个如上述第二方面所述的光电二极管。
本申请提供一种光电二极管的制备方法、光电二极管和CMOS图像传感器，该方法包括：在衬底上形成遮蔽层，衬底具有第一掺杂类型，衬底上设置有预设位置，第一掺杂类型和第二掺杂类型不同；对遮蔽层进行处理，预设位置上方的遮蔽层的厚度小于非预设位置上方的遮蔽层的厚度，预设位置上方的遮蔽层的上表面为曲面；对衬底进行离子注入，使注入的离子形成下表面为曲面的且具有第二掺杂类型的区域，以增加衬底与区域的接触面积； 去除遮蔽层，得到光电二极管。本申请增加了具有第一掺杂类型的衬底与具有第二掺杂类型的区域的接触面积，提高了满阱容量。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中的光电二极管的示意图一；
图2为现有技术中的光电二极管的示意图二；
图3为现有技术中的光电二极管的示意图三；
图4为本申请提供的光电二极管的制备方法的流程示意图一；
图5为本申请提供的光电二极管的制备流程示意图一；
图6为本申请提供的压印模具的示意图；
图7为本申请提供的光电二极管的制备方法的流程示意图二；
图8为本申请提供的光电二极管的制备流程示意图二。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的本申请的实施例，例如能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出 的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
图1为现有技术中的光电二极管的示意图一。如图1所示，光电二极管在p型衬底100上形成一个n型掺杂区域101，光电二极管的耗尽区为p型衬底100与n型掺杂区域101的接触区域，如图中的103所示。目前，随着CMOS图像传感器的像素单元的尺寸的减小，使得像素单元对应的光电二极管的面积也减小。相应的，光电二极管中的耗尽区的面积也减小，导致满阱容量降低，由此产生图像品质恶化的问题。值得注意的是，本申请中所示的光电二极管的示意图均为侧视图。
现有技术中，采用增加光电二极管的掺杂浓度的方式，提高满阱容量，然而这种方式会发生图像拖尾、暗电流过大或白点等问题。
另外，现有技术中还采用形成多重n-p-n结的方式提高满阱容量。图2为现有技术中的光电二极管的示意图二。如图2所示，形成多重n-p-n结的光电二极管的方式为：将p型掺杂区域202插入到n型掺杂区域101之中，从而形成一个U型结构，可以使光电二极管产生额外的耗尽区203a和203b。相较于图1，增加了光电二极管的耗尽区的面积，提高了光电二极管的满阱容量。
进一步的，现有技术中还通过在图1形成n型掺杂区域101的基础上，形成一深度更深的n型掺杂区域，以增加光电二极管的耗尽区的面积，提高满阱容量。图3为现有技术中的光电二极管的示意图三。如图3所示，通过在n型掺杂区域101下方形成深度更深的n型掺杂区域302，可以使光电二极管产生额外的耗尽区303，提高满阱容量。采用上述方式形成的图2和图3中的光电二极管的结构，虽然不影响输出图像的品质，但但这两种方式需要对衬底进行多道离子注入步骤，工序复杂。
为了解决上述问题，本申请提供了一种光电二极管的制备方法。不仅能够增加光电二级管的耗尽区的面积，且仅采用一次离子注入，工序简单。
图4为本申请提供的光电二极管的制备方法的流程示意图一。图4所示方法流程的执行主体可以为光电二极管的制备装置，如图4所示，本实施例提供的光电二极管的制备方法可以包括：
S401，在衬底上形成遮蔽层，衬底具有第一掺杂类型，衬底上设置有预设位置，预设位置为形成掺杂类型为第二掺杂类型的位置，第一掺杂类型和 第二掺杂类型不同，遮蔽层用于遮挡注入衬底的离子，遮蔽层的遮挡强度与遮蔽层的厚度相关。
本实施例中的光电二极管的制备装置可以为集成涂布、光刻、刻蚀、离子注入等多种功能为一体的装置，能够实现对衬底的遮蔽层的形成、光刻胶层的涂布等过程。也可以是将实现涂布、光刻、刻蚀、离子注入等多种功能的多个模块集成为一体的装置。
可选的，本实施例中的光电二极管可以为CMOS图像传感器中的光电二极管。
本实施例中提供具有第一掺杂类型的衬底，该衬底可以为硅晶圆或是生长于硅晶圆上方的外延硅。其中，第一掺杂类型可以为p型掺杂或者n型掺杂。衬底上设置有预设位置，该预设位置为形成掺杂类型为第二掺杂类型的位置，其中，将具有第二掺杂类型的离子在预设位置注入衬底中，可以在衬底中形成具有第二掺杂类型的区域。其中，第一掺杂类型和第二掺杂类型不同，具有第二掺杂类型的区域与衬底接触的区域为耗尽区。
本实施例中，遮蔽层用于遮挡注入衬底的离子，遮蔽层的遮挡强度与遮蔽层的厚度相关，遮蔽层的厚度越大，则对离子的遮挡强度越强。由于衬底上设置有预设位置，预设位置为注入离子后形成具有第二掺杂类型的区域的位置；而非预设位置为注入离子后保持衬底的第一掺杂类型的位置。
本实施例中的遮蔽层可以但不限于为由光刻胶形成的光刻胶层，由二氧化硅形成的二氧化硅层，由聚二甲基硅氧烷(polydimethylsiloxane，PDMS)形成的PDMS层。
图5为本申请提供的光电二极管的制备流程示意图一。如图5中的a所示，在衬底100上形成遮蔽层501，其中，衬底的A、B之间的位置为衬底的预设位置。图5中以遮蔽层501具有相同厚度进行示例说明，可以想到的是，本实施例在衬底100上形成的遮蔽层501可以具有不同的厚度。
S402，对遮蔽层进行处理，使预设位置上方的遮蔽层的厚度小于非预设位置上方的遮蔽层的厚度，预设位置上方的遮蔽层的上表面为曲面。
由于预设位置为注入离子后形成具有第二掺杂类型的区域的位置，而非预设位置为注入离子后保持衬底的第一掺杂类型的位置，因此在离子注入能量相同的前提下，需要预设位置上方的遮蔽层的厚度小于非预设位置上方的 遮蔽层的厚度。只有这样，非预设位置上方的遮蔽层能够有效遮挡离子注入至衬底中。
其中，预设位置上方的遮蔽层的上表面为曲面。可选的，该曲面不限于为球冠状曲面、或梳齿性曲面；球冠状曲面可以为球冠状凸面或球冠状凹面。
本实施例中对遮蔽层进行处理方式可以根据遮蔽层的不同而不同。
示例性的，遮蔽层为光刻胶层5011时，由于光刻胶层的硬度较小，可以采用纳米压印的方式获取上述预设位置上方的遮蔽层的厚度小于非预设位置上方的遮蔽层的厚度，且预设位置上方的遮蔽层的上表面为曲面的光刻胶层。为了使得非预设位置上方的光刻胶层厚度大于预设位置上方的光刻胶层的厚度，且预设位置上方的光刻胶层的上表面为曲面。可以设置预设位置处压印深度大，而非预设位置处压印深度小，且在预设位置处的压印深度与预设位置上方的光刻胶的厚度负相关的压印模具。预设位置处的压印深度与预设位置上方的光刻胶的厚度负相关指的是：预设位置上方的光刻胶的厚度越大，则压印深度越小。
图6为本申请提供的压印模具的示意图。如图6所示，压印模具两侧的位置对应的是衬底上的非预设位置，压印模具中间的位置对应的是衬底上的预设位置。可以看出，压印模具两侧的压印深度小于压印模具中间的压印深度，且压印模具中间的压印深度根据最终形成的曲面的形状设置。图6中示例性的示出了衬底上预设位置对应的压印模具上的图形为梳齿形。可以想到的是，压印模具上，梳齿形中凸出的齿的位置处的压印深度小于凹进的齿的位置处的压印深度。
本实施例中，通过纳米压印的方式可以将压印模具上的图形转移到光刻胶层上，可以得到遮蔽层。如图5中的b所示，形成了非预设位置上方的光刻胶层5011b的厚度大于预设位置上方的光刻胶层5011a的厚度，且预设位置上方的光刻胶层5011a的上表面为曲面的光刻胶层。
值得注意的是，对于材料硬度较小的遮蔽层，均可直接采用纳米压印的方式获取预设位置上方的遮蔽层的厚度小于非预设位置上方的遮蔽层的厚度，且预设位置上方的遮蔽层的上表面为曲面的遮蔽层。对于材料硬度较大的遮蔽层，可以在遮蔽层上涂布光刻胶层后，采用相同的纳米压印的方式获取上述遮蔽层。
本实施例中，根据遮蔽层的材料的不同，可以采用现有技术中的刻蚀、光刻等方式获取遮蔽层，在此不做赘述。
S403，通过遮蔽层对衬底进行离子注入，使注入的离子形成下表面为曲面的且具有第二掺杂类型的区域，以增加衬底与区域的接触面积。
本实施例中，通过遮蔽层对衬底进行离子注入。其中，注入的离子具有第二掺杂类型。具体的，本实施例中非预设区域上方的遮蔽层能够完全对注入的离子进行遮挡，使得在该非预设位置注入的离子不进入衬底中。由于预设区域上方的遮蔽层的厚度小于遮蔽层的厚度，因此注入的离子可以穿透遮蔽层进入衬底，从衬底的上方的内表面开始，向下延伸形成具有第二掺杂类型的区域。
由于预设位置上方的遮蔽层的上表面为曲面，因此对注入的离子的遮挡强度不同。且由于遮蔽层的遮挡强度与遮蔽层的厚度相关，因此具有第二掺杂类型的区域的下表面也为曲面，且该曲面与预设位置上方的遮蔽层的上表面的曲面的形状相同。
本实施例中形成的具有第二掺杂类型的区域的下表面为曲面，与衬底具有更大接触面积，因此相较于现有技术中具有更大面积的耗尽区。在其他条件相同的情况下，如图1所示的具有第二掺杂类型的区域的下表面为与水平面平行的平面，其耗尽区如虚线框中的耗尽区所示。本实施例中在衬底中形成的具有第二掺杂类型的区域502如图5中的c所示，该区域的下表面为梳齿形，相较于图1中的区域的下表面，与衬底具有更大的接触面积。图5中的c中的虚线框中的区域为耗尽区。
S404，去除遮蔽层，得到光电二极管。
本实施例中，可以采用刻蚀的方法将遮蔽层去除，得到具有较大面积的耗尽区的光电二极管。
示例性的，如图5中的d所示，本申请将光刻胶层去除，得到在具有第一掺杂类型的衬底100中，形成下表面为梳齿形的具有第二掺杂类型的区域502的光电二极管。
可选的，为了使得获取的下表面为梳齿形的区域502的下表面的梳齿的凹凸面具有更大的深度差值，即具有更大的耗尽区。在进行离子注入前，即图5中的c之前，还可以将预设位置区域上方的光刻胶进行进一步刻蚀，使 得预设位置区域上方的光刻胶5011a的厚度光刻为0，如图5中的e所示。
本实施例中提供的光电二极管的制备方法包括：在衬底上形成遮蔽层，衬底具有第一掺杂类型，衬底上设置有预设位置，第一掺杂类型和第二掺杂类型不同；对遮蔽层进行处理，使预设位置上方的遮蔽层的厚度小于非预设位置上方的遮蔽层的厚度，预设位置上方的遮蔽层的上表面为曲面；对衬底进行离子注入，注入的离子形成下表面为曲面的且具有第二掺杂类型的区域，以增加衬底与区域的接触面积，去除遮蔽层，得到光电二极管。本实施例中通过形成下表面为与曲面的且具有第二掺杂类型的区域，进而增加了具有第一掺杂类型的衬底与具有第二掺杂类型的区域的接触面积，即增加了耗尽区的面积，提高了满阱容量。
由于遮蔽层的不同，本申请中对遮蔽层的处理方法不同。下述实施例中依照遮蔽层的特性，对遮蔽层的处理方法进行说明。具体的，主要以遮蔽层的硬度特性，对遮蔽层的处理方法进行说明。
本实施例中的光电二极管的制备装置中存储有预设硬度，遮蔽层的硬度在制备光电二极管之前可以输入至光电二极管的制备装置，以使光电二极管的制备装置获取遮蔽层的硬度。
其中，当遮蔽层的材料为硬度小于或等于预设硬度的材料时。可选的，遮蔽层的材料可以但不限制于为光刻胶或者聚二甲基硅氧烷。由于遮蔽层的硬度较小，可以采用纳米压印的方式对遮蔽层进行压印。其中，预设位置上方的压印深度大于非预设位置上方的压印深度，预设位置上方的压印深度与预设位置上方的光刻胶的厚度负相关。相应的，预设位置上方的压印模具的厚度大于非预设位置上方的压印模具的厚度，预设位置上方的压印模具的厚度与预设位置上方的光刻胶的厚度负相关。示例性的，可以如图6所示。
可选的，当遮蔽层的材料为硬度小于或等于预设硬度的材料，且材料为光刻胶时，对遮蔽层进行处理，即为对光刻胶层进行处理。
本实施例中对光刻胶层进行处理，除了上述可以采用纳米压印的方式外，还可以采用变剂量光刻的方式对光刻胶层进行处理。
其中，一种可行的方式为：
在光刻胶层上放置灰度掩膜版，并对光刻胶层进行曝光处理。其中，预 设位置上方的灰度掩膜版的透光率大于位于非预设位置上方的灰度掩膜版的透光率，预设位置上方的灰度掩膜版的透光率与预设位置上方的光刻胶的厚度负相关。例如，预设位置上方的灰度掩膜版的透光率越大，则预设位置上方的光刻胶的厚度越小，反之预设位置上方的光刻胶的厚度越大。
相对于普通的掩膜版，只有透光率为0％(完全不透)或者透光率为100％(完全透光)，而灰度掩膜版的透光率可以在0％-100％之间任意设置，即对光刻胶进行曝光时，曝光剂量是可调的，而曝光剂量的大小决定了光刻胶显影后的厚度。
本实施例中，可以根据光刻胶的显影特征，将光刻胶分为正性光刻胶和负性光刻胶。
其中，若光刻胶层中的光刻胶为正性光刻胶，则预设位置上方的灰度掩膜版的透光率大于位于非预设位置上方的灰度掩膜版的透光率，使得预设位置上方的光刻胶的曝光剂量大于非预设位置上方的光刻胶的曝光剂量，即可以使得预设位置上方的光刻胶的厚度小于非预设位置上方的光刻胶的厚度。预设位置上方的灰度掩膜版的透光率与预设位置上方的光刻胶的厚度负相关，即预设位置上方的光刻胶的曝光剂量与预设位置上方的光刻胶的厚度负相关，即曝光剂量越大，则预设位置上方的光刻胶的厚度越小，进而使得预设位置上方的光刻胶的上表面为曲面。
对应的，若光刻胶层中的光刻胶为负性光刻胶，则预设位置上方的灰度掩膜版的透光率小于位于非预设位置上方的灰度掩膜版的透光率，使得预设位置上方的光刻胶的曝光剂量小于非预设位置上方的光刻胶的曝光剂量，即可以使得预设位置上方的光刻胶的厚度小于非预设位置上方的光刻胶的厚度。预设位置上方的灰度掩膜版的透光率与预设位置上方的光刻胶的厚度正相关，即预设位置上方的光刻胶的曝光剂量与预设位置上方的光刻胶的厚度正相关，即曝光剂量越大，则预设位置上方的光刻胶的厚度越大，进而使得预设位置上方的光刻胶的上表面为曲面。
另一种可行的方式为：
本实施例中，可以根据光刻胶的显影特征，将光刻胶分为正性光刻胶和负性光刻胶。本实施例中可以采用直写式光刻对光刻胶层进行光刻处理。
其中，若光刻胶层中的光刻胶为正性光刻胶，则预设位置上方的光刻强 度大于非预设位置上方的光刻强度，预设位置上方的光刻强度与预设位置上方的光刻胶的厚度负相关，即光刻强度越大则预设位置上方的光刻胶的厚度越小。直写式光刻可以直接改变微区域内激光或电子束的强度或能量，从而改变曝光剂量，进而达到与上述灰度掩膜版相同的效果，即获取预设位置上方的光刻胶的厚度小于非预设位置上方的光刻胶的厚度，且预设位置上方的光刻胶的上表面为曲面的效果。
对应的，若光刻胶层中的光刻胶为负性光刻胶，则预设位置上方的光刻强度小于非预设位置上方的光刻强度，预设位置上方的光刻强度与预设位置上方的光刻胶的厚度正相关。同样的，也可以达到获取预设位置上方的光刻胶的厚度小于非预设位置上方的光刻胶的厚度，且预设位置上方的光刻胶的上表面为曲面的效果。
当遮蔽层的材料为硬度大于预设硬度的材料时，例如，遮蔽层的材料可以但不限制于为二氧化硅。由于二氧化硅的硬度大，不能直接采用纳米压印等方式将进行处理。具体的，下面结合图7对本申请提供的对遮蔽层的材料为硬度大于预设硬度的材料时，如何对遮蔽层进行处理的过程进行说明；图7为本申请提供的光电二极管的制备方法的流程示意图二，如图7所示，本实施例提供的光电二极管的制备方法可以包括：
S701，在衬底上形成遮蔽层。
S702，在遮蔽层上形成光刻胶层。
本实施例中，由于遮蔽层的硬度大于预设硬度，需要在遮蔽层上形成光刻胶层，形成光刻胶层的方式可以为在遮蔽层上涂布光刻胶，获取光刻胶层。
S703，对光刻胶层进行处理，使预设位置上方的光刻胶层的厚度小于非预设位置上方的光刻胶层的厚度，预设位置上方的光刻胶层的上表面为曲面。
本实施例中，对光刻胶层进行处理方式可以参照上述实施例中的相关描述。具体可以采用变剂量光刻的方式，如设置灰度掩膜版或者采用直写式光刻的方式对光刻胶层进行处理，获取预设位置上方的光刻胶层的厚度小于非预设位置上方的光刻胶层的厚度，预设位置上方的光刻胶层的上表面为曲面的光刻胶层。此外，由于光刻胶层的硬度较小，也可采用纳米压印的方式对光刻胶层进行压印，获取预设位置上方的光刻胶层的厚度小于非预设位置上 方的光刻胶层的厚度，预设位置上方的光刻胶层的上表面为曲面的光刻胶层。
图8为本申请提供的光电二极管的制备流程示意图二。如图8中的a所示，在衬底100上形成二氧化硅层5012，在二氧化硅层5012上形成光刻胶层5011。如图8中的b所示，对光刻胶层5011进行处理。其中，预设位置上方的光刻胶层5011a的厚度小于非预设位置上方的光刻胶层5011b的厚度，且预设位置上方的光刻胶层5011a的上表面为球冠状。
S704，对遮蔽层进行处理。
本实施例中，通过对光刻胶层的刻蚀处理可以将光刻胶层的形状转移至遮蔽层。
示例性的，如图8中的c所示，对光刻胶层进行处理后，预设位置上方的二氧化硅层5012a的厚度小于非预设位置上方的二氧化硅层5012b的厚度，且预设位置上方的二氧化硅层5012a的上表面为球冠状。
可选的，当非预设位置上方的光刻胶层5011b的厚度较大时，在对光刻胶层进行刻蚀后，可以还保留一部分的光刻胶层5011b。
S705，通过遮蔽层对衬底进行离子注入，使注入的离子形成下表面为曲面且具有第二掺杂类型的区域。
示例性的，如图8中的d所示，由于预设位置上方的二氧化硅层5012a的上表面为球冠状，因此在进行离子注射时，根据遮蔽层对离子的遮挡作用，可以在衬底中得到下表面为曲面的具有第二掺杂类型的区域802。由于下表面为曲面，在其他条件相同的情况下，相对于图1中的具有第二掺杂类型的区域，衬底与该区域802的接触面接增大，光电二极管的耗尽区增大，由此增加光电二极管的满阱容量。图8中的d中的虚线框为耗尽区。
S706，去除遮蔽层，得到光电二极管。
示例性的，如图8中的e所示，去除遮蔽层，若有未刻蚀完的光刻胶层，也可以一起去除，得到下表面为曲面的第二掺杂类型的区域802的光电二极管。
其中，本实施例中S701、S705-S706中的具体实施方式可以参照上述实施例中的S401、S403-S404中的相关描述，在此不做赘述。
本实施例中，当遮蔽层的材料为硬度大于预设硬度的材料时，可以在遮蔽层上形成光刻胶层，采用变剂量光刻或者纳米压印的方式获取预设位置上 方为曲面的光刻胶层，进而通过刻蚀获取预设位置上方为曲面的的遮蔽层，进而通过离子注入，在衬底中形成下表面为曲面的具有第二掺杂类型的区域，增加了光电二极管的耗尽区增大，由此增加光电二极管的满阱容量。
本申请中还提供一种光电二极管，如图5中的d或如图8中的e所示，光电二极管包括：
具有第一掺杂类型的衬底，以及，在衬底中形成的具有第二掺杂类型的区域，该区域自衬底上方的内表面向下伸出，该区域的下表面为曲面，且第一掺杂类型和第二掺杂类型不同。
本实施例中的光电二极管由上述光电二极管的制备方法进行制备，由于光电二极管中的衬底中的具有第二掺杂类型的区域的下表面为曲面，增大了光电二极管中耗尽区的面积，提高了光电二极管的满阱容量。
本申请中还提供一种CMOS图像传感器，具体的，该CMOS图像传感器包括至少一个由上述实施例中的光电二极管的制备方法制备的光电二极管。
本申请提供的CMOS图像传感器具有与上述实施例中的光电二极管的制备方法相同的技术效果，在此不做赘述。
本领域普通技术人员可以理解：实现上述各方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成。前述的程序可以存储于一计算机可读取存储介质中。该程序在执行时，执行包括上述各方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种光电二极管的制备方法，其特征在于，包括：
    在衬底上形成遮蔽层，所述衬底具有第一掺杂类型，所述衬底上设置有预设位置，所述预设位置为形成掺杂类型为第二掺杂类型的位置，所述第一掺杂类型和所述第二掺杂类型不同，所述遮蔽层用于遮挡注入所述衬底的离子，所述遮蔽层的遮挡强度与所述遮蔽层的厚度相关；
    对所述遮蔽层进行处理，使所述预设位置上方的遮蔽层的厚度小于非所述预设位置上方的遮蔽层的厚度，所述预设位置上方的遮蔽层的上表面为曲面；
    通过所述遮蔽层对所述衬底进行离子注入，使注入的离子形成下表面为曲面的且具有第二掺杂类型的区域，以增加所述衬底与所述区域的接触面积；
    去除所述遮蔽层，得到光电二极管。
  2. 根据权利要求1所述的方法，其特征在于，当所述遮蔽层的材料为硬度大于预设硬度的材料时，所述对所述遮蔽层进行处理之前，还包括：
    在所述遮蔽层上形成光刻胶层；
    对光刻胶层进行处理，使所述预设位置上方的光刻胶层的厚度小于非所述预设位置上方的光刻胶层的厚度，所述预设位置上方的光刻胶层的上表面为曲面；
    所述对所述遮蔽层进行处理，包括：
    对所述光刻胶层进行刻蚀处理。
  3. 根据权利要求1所述的方法，其特征在于，当所述遮蔽层的材料为硬度小于或等于预设硬度的材料，且所述材料为光刻胶时，所述对所述遮蔽层进行处理，包括：
    对光刻胶层进行处理。
  4. 根据权利要求2或3所述的方法，其特征在于，所述对光刻胶层进行处理，包括：
    在所述光刻胶层上放置灰度掩膜版，并对所述光刻胶层进行曝光处理；
    其中，若所述光刻胶层中的光刻胶为正性光刻胶，则使所述预设位置上方的所述灰度掩膜版的透光率大于位于非所述预设位置上方的所述灰度掩膜版的透光率，所述预设位置上方的所述灰度掩膜版的透光率与所述预设位置 上方的光刻胶层的厚度负相关；若所述光刻胶层中的光刻胶为负性光刻胶，则使所述预设位置上方的所述灰度掩膜版的透光率小于位于非所述预设位置上方的所述灰度掩膜版的透光率，所述预设位置上方的所述灰度掩膜版的透光率与所述预设位置上方的光刻胶层的厚度正比关。
  5. 根据权利要求2或3所述的方法，其特征在于，所述对光刻胶层进行处理，包括：
    采用直写式光刻对所述光刻胶层进行光刻处理；
    其中，若所述光刻胶层中的光刻胶为正性光刻胶，则使所述预设位置上方的光刻强度大于非所述预设位置上方的光刻强度，所述预设位置上方的光刻强度与所述预设位置上方的光刻胶层的厚度负相关；若所述光刻胶层中的光刻胶为负性光刻胶，则使所述预设位置上方的光刻强度小于非所述预设位置上方的光刻强度，所述预设位置上方的光刻强度与所述预设位置上方的光刻胶层的厚度正相关。
  6. 根据权利要求2或3所述的方法，其特征在于，所述对光刻胶层进行处理，包括：
    采用纳米压印对所述光刻胶层进行压印，使所述预设位置上方的压印深度大于非所述预设位置上方的压印深度，所述预设位置上方的压印深度与所述预设位置上方的光刻胶层的厚度负相关。
  7. 根据权利要求1所述的方法，其特征在于，当所述遮蔽层的材料硬度为小于或等于预设硬度的材料，且所述材料为非光刻胶时，所述对所述遮蔽层进行处理，包括：
    采用纳米压印对所述遮蔽层进行压印，使所述预设位置上方的压印深度大于非所述预设位置上方的压印深度，所述预设位置上方的压印深度与所述预设位置上方的光刻胶层的厚度负相关。
  8. 根据权利要求1所述的方法，其特征在于，所述遮蔽层的上表面为球冠状曲面或梳齿形曲面。
  9. 一种光电二极管，其特征在于，包括：
    具有第一掺杂类型的衬底，以及，在所述衬底中形成的具有第二掺杂类型的区域，所述区域自所述衬底上方的内表面向下伸出，所述区域的下表面为曲面，所述第一掺杂类型和所述第二掺杂类型不同。
  10. 一种CMOS图像传感器，其特征在于，包括：至少一个如权利要求9中所述的光电二极管。
PCT/CN2019/079052 2019-03-21 2019-03-21 光电二极管的制备方法、光电二极管和cmos图像传感器 Ceased WO2020186512A1 (zh)

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CN113140450B (zh) * 2020-01-19 2022-04-05 济南晶正电子科技有限公司 一种制备薄膜的方法及应用
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030155593A1 (en) * 2002-02-18 2003-08-21 Hwa-Young Kang Photodiode and method of manufacturing the same
CN101471365A (zh) * 2007-12-27 2009-07-01 东部高科股份有限公司 图像传感器及其制造方法
CN104517896A (zh) * 2014-12-12 2015-04-15 深圳市华星光电技术有限公司 一种阵列基板的掺杂方法及制造设备
CN104517841A (zh) * 2013-09-27 2015-04-15 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法
CN105590966A (zh) * 2014-10-23 2016-05-18 无锡华润华晶微电子有限公司 一种肖特基二极管

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01184878A (ja) * 1988-01-13 1989-07-24 Mitsubishi Electric Corp 横型ｐｉｎフオトダイオードの製造方法
KR100606954B1 (ko) * 2004-07-08 2006-08-01 동부일렉트로닉스 주식회사 씨모스 이미지 센서의 포토다이오드 제조방법
EP2109143B1 (en) * 2008-04-09 2013-05-29 Sony Corporation Solid-state imaging device, production method thereof, and electronic device
CN103066086B (zh) * 2012-12-18 2017-05-31 上海集成电路研发中心有限公司 一种cmos图像传感器像素阵列及其制造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030155593A1 (en) * 2002-02-18 2003-08-21 Hwa-Young Kang Photodiode and method of manufacturing the same
CN101471365A (zh) * 2007-12-27 2009-07-01 东部高科股份有限公司 图像传感器及其制造方法
CN104517841A (zh) * 2013-09-27 2015-04-15 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法
CN105590966A (zh) * 2014-10-23 2016-05-18 无锡华润华晶微电子有限公司 一种肖特基二极管
CN104517896A (zh) * 2014-12-12 2015-04-15 深圳市华星光电技术有限公司 一种阵列基板的掺杂方法及制造设备

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