WO2020186471A1 - Circuit de retard et dispositif d'entraînement - Google Patents

Circuit de retard et dispositif d'entraînement Download PDF

Info

Publication number
WO2020186471A1
WO2020186471A1 PCT/CN2019/078806 CN2019078806W WO2020186471A1 WO 2020186471 A1 WO2020186471 A1 WO 2020186471A1 CN 2019078806 W CN2019078806 W CN 2019078806W WO 2020186471 A1 WO2020186471 A1 WO 2020186471A1
Authority
WO
WIPO (PCT)
Prior art keywords
input
register
tube
branch
delay circuit
Prior art date
Application number
PCT/CN2019/078806
Other languages
English (en)
Chinese (zh)
Inventor
李进
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2019/078806 priority Critical patent/WO2020186471A1/fr
Priority to CN201980094218.9A priority patent/CN113574801A/zh
Publication of WO2020186471A1 publication Critical patent/WO2020186471A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors

Definitions

  • This application relates to the field of electricity, in particular to a delay circuit and a driving device.
  • the circuit can be designed in parallel or serially.
  • a circuit designed in a data parallel manner requires multiple transmission routes, a large number of chip package pins, and a complex layout on the circuit board.
  • parallel mode due to the presence of multiple lines, there is signal coupling and interference between signals between multiple lines, which will affect the transmission speed and transmission distance of parallel transmission.
  • parallel data transmission needs to transmit a synchronous clock, and clock skew occurs when the line is long.
  • the circuit designed in serial mode only needs a pair of transmission lines at least, and does not need to transmit a synchronous clock. Therefore, the serial data transmission method is more suitable for high-speed communication systems.
  • the input signal can be delayed by a buffer.
  • the buffer circuit is provided with a plurality of metal oxide semiconductor (MOS) transistors, and the MOS transistors have a delay effect on the input signal.
  • MOS metal oxide semiconductor
  • the delay circuit may include at least two branches, at least two branches are connected in parallel, and each of the at least two branches has Different delays; the delay circuit includes at least one register, at least one register is used to control one of the at least two branches to be turned on, so that the delay circuit generates a delay corresponding to the turned on branch.
  • the delay circuit provided in the embodiment of the present application can provide different delays, which is equivalent to the output signal having A variety of different slew rates, by adjusting the slew rate of the output signal, the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.
  • the number and/or size of the MOS transistors included in each of the at least two branches are different, so that the at least The two branches have different delays.
  • the number and/or size of the MOS transistors included in each branch can be changed so that each of the at least two branches has a different extension. Time.
  • At least one register includes the first register, and at least two branches include the first branch and For the second branch, the first register is used to control the connection of one of the first branch and the second branch.
  • only one register is needed to control the connection of one of the first branch and the second branch, and only one register can be used to reduce the cost.
  • the first register includes a first input and a second input, and the first input and the second input are inversely Phase
  • the first branch includes a first PMOS tube and a second PMOS tube, the source of the first PMOS tube is connected to the power supply voltage, the drain of the first PMOS tube is connected to the source of the second PMOS tube, and the gate of the first PMOS tube The pole is connected to the input signal, the gate of the second PMOS tube is connected to the first input of the first register;
  • the first branch also includes a first NMOS tube and a second NMOS tube, the source of the first NMOS tube is grounded, and the first NMOS tube
  • the drain of the second NMOS tube is connected to the source of the second NMOS tube, the gate of the first NMOS tube is connected to the input signal, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second NMOS
  • the second branch includes a third PMOS tube and a fourth PMOS tube, and the third PMOS tube
  • the source of the third PMOS tube is connected to the power supply voltage
  • the drain of the third PMOS tube is connected to the source of the fourth PMOS tube
  • the gate of the third PMOS tube is connected to the input signal
  • the gate of the fourth PMOS tube is connected to the second input of the first register
  • the second branch also includes a third NMOS tube and a fourth NMOS tube.
  • the source of the third NMOS tube is grounded, the drain of the third NMOS tube is connected to the source of the fourth NMOS tube, and the gate of the third NMOS tube is connected to the input.
  • the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, and the gate of the fourth NMOS tube is connected to the first input of the first register.
  • the on-off of the second branch can be controlled through the reversed first input and second input in the first register.
  • the first input of the first register is 0, the second input is 1, and the second PMOS The tube and the second NMOS tube are both turned on, the fourth PMOS tube and the fourth NMOS tube are both turned off, and the first branch is turned on; or, the first input of the first register is 1, the second input is 0, and the second PMOS tube Both the second NMOS transistor and the second NMOS transistor are turned off, the fourth PMOS transistor and the fourth NMOS transistor are both turned on, and the second branch is turned on.
  • one of the first branch and the second branch can be controlled to be connected through the first input and the second input reversed in the first register.
  • At least one register includes a first register and a second register
  • at least two branches include the first The branch and the second branch
  • the first register controls the first branch
  • the second register controls the second branch
  • the first branch is connected to one of the second branches.
  • one of the first branch and the second branch can be controlled to be connected through the first register and the second register.
  • one register controls one branch, the design is simple and not easy to make mistakes.
  • the first register includes a first input and a second input, and the first input and the second input
  • the first branch includes a first PMOS tube and a second PMOS tube.
  • the source of the first PMOS tube is connected to the power supply voltage, and the drain of the first PMOS tube is connected to the source of the second PMOS tube.
  • the gate is connected to the input signal, the gate of the second PMOS tube is connected to the first input of the first register; the first branch also includes a first NMOS tube and a second NMOS tube, the source of the first NMOS tube is grounded, and the first NMOS tube
  • the drain of the tube is connected to the source of the second NMOS tube, the gate of the first NMOS tube is connected to the input signal, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second NMOS tube is connected to the first The second input of the register.
  • the first register can control the on-off of the first branch.
  • the second register includes a third input and a fourth input, and the third input and the fourth input
  • the second branch includes a third PMOS tube and a fourth PMOS tube.
  • the source of the third PMOS tube is connected to the power supply voltage, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, and the source of the third PMOS tube is The gate is connected to the input signal, the gate of the fourth PMOS tube is connected to the third input of the second register; the second branch also includes a third NMOS tube and a fourth NMOS tube, the source of the third NMOS tube is grounded, and the third NMOS tube
  • the drain of the tube is connected to the source of the fourth NMOS tube, the gate of the third NMOS tube is connected to the input signal, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, and the gate of the fourth NMOS tube is connected to the second The fourth input of the register.
  • the second register can control the on-off of the second branch.
  • the ninth possible implementation manner of the first aspect when the first register controls the second PMOS transistor and the second NMOS transistor to be turned on, and the first When the second register controls the fourth PMOS transistor and the fourth NMOS transistor to turn off, the first branch is turned on; or, when the first register controls the second PMOS transistor and the second NMOS transistor to turn off, and the second register controls the fourth PMOS When both the tube and the fourth NMOS tube are turned on, the second branch is turned on.
  • the first register and the second register can control one of the first branch and the second branch to be connected.
  • the first input of the first register is 0, the second input is 1, and the second register The third input is 1, the fourth input is 0, the second PMOS tube and the second NMOS tube are both turned on, the fourth PMOS tube and the fourth NMOS tube are both turned off, and the first branch is turned on; or, the first register The first input is 1, the second input is 0, the third input of the second register is 0, the fourth input is 1, the second PMOS tube and the second NMOS tube are both turned off, the fourth PMOS tube and the fourth NMOS tube are both Open, the second branch is connected.
  • the first register and the second register can control the first branch and the second register by changing the values of the first input, the second input, the third input, and the fourth input. One of the second branches is connected.
  • a second aspect of the embodiments of the present application provides a driving device
  • the driving device may include: N stages such as the first aspect and any one of the possible implementations of the first aspect of the delay circuit and the N-stage driving circuit, where N is greater than An integer of 1; where the output of the N-1th stage delay circuit is connected to the input of the Nth stage delay circuit and the input of the N-1th stage drive circuit respectively; the output of the Nth stage delay circuit is connected to the Nth stage drive The input of the circuit; the N output signals from the first-level driving circuit to the Nth-level driving circuit together constitute the output of the driving device; the driving circuit includes at least one PMOS tube, at least one NMOS tube, a first resistor and a second resistor, at least one The PMOS tube is connected in series with the first resistor and the gate of at least one PMOS tube is connected to the input signal. At least one NMOS tube is connected in series with the second resistance and the gate of the at least one NMOS tube is connected to the input signal.
  • the driving device includes N stages such as the delay circuit in the first aspect and any one of the possible implementations of the first aspect, and the delay of the driving device can be adjusted by adjusting the number of stages of the N-stage driving circuit; at the same time, the driving The device contains an N-level drive circuit.
  • the resistance of the N-level drive circuit can be adjusted to match the resistance of the drive circuit with the resistance of the load to reduce the impact of signal reflection on the signal quality. Furthermore, the N-level drive circuit can enhance the signal quality. Drive capability.
  • the delay between the output and the input signal of the driving device is related to the number of MOS tubes in the driving device, the size of the MOS tubes, and N
  • the stage delay circuit is related to at least one of the number of stages of the N stage drive circuit, the delay of the branch connected to each stage of the N stage delay circuit, or the delay of the N stage drive circuit.
  • the delay between the output of the driving device and the input signal includes the delay of the N-stage delay circuit Delay and the delay of the N-stage drive circuit.
  • the delay of the N-stage delay circuit is related to the number of stages of the N-stage delay circuit and the delay of the branch connected to each stage of the N-stage delay circuit. Time is related.
  • the output and input signal of the driving device The delay between is a*(T 1 +T 2 + whil+T N )+T load , where a is the correction coefficient, and T 1 is the delay of the first-stage delay circuit in the N-stage delay circuit , T 2 is the delay of the second-stage delay circuit in the N-stage delay circuit, ..., T N is the delay of the N-th stage delay circuit in the N-stage delay circuit, and T load is the delay of the N-stage drive circuit Delay.
  • the output and input signal of the driving device The delay between is a*N*T d + T load , where a is the correction coefficient, N is the number of stages of the N-stage delay circuit, and T d is the delay circuit of each stage of the N-stage delay circuit Delay, T load is the delay of the N-level drive circuit.
  • the embodiments of the present application provide a delay circuit and a driving device.
  • the circuit may include at least two branches, the at least two branches are connected in parallel, and each branch of the at least two branches has a different delay;
  • the delay circuit includes at least one register for controlling one of the at least two branches to be turned on, so that the delay circuit generates a delay corresponding to the turned-on branch. Since the greater the delay of the input signal, the smaller the slew rate, so the slew rate of the input signal through any one of the at least two branches is different.
  • the slew rate of the output signal can be adjusted by controlling one of the at least two branches through at least one register, so that the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.
  • Fig. 1 is a schematic diagram of a delay circuit provided in the prior art
  • Figure 2 is another schematic diagram of a delay circuit provided in the prior art
  • FIG. 3 is a schematic diagram of an embodiment of a delay circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of another embodiment of a delay circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of an embodiment of a driving device provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of an embodiment of a driving circuit provided by an embodiment of the application.
  • At least one (item) refers to one or more, and “multiple” refers to two or more.
  • the term “and/or” in this application can be an association relationship describing associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, and both A and B exist , There are three cases of B alone.
  • the character “/” in this application generally indicates that the associated objects before and after are in an "or” relationship.
  • “The following at least one item (a)” or similar expressions refers to any combination of these items, including any combination of a single item (a) or plural items (a).
  • At least one (a) of a, b or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ", where a, b, and c can be single or multiple.
  • the input signal can be delayed by a buffer.
  • the buffer circuit is provided with multiple MOS transistors, and the MOS transistors have a delay effect on the input signal. Since the number and size of the MOS tube in each buffer are determined, the slew rate of the output signal through the buffer circuit is determined.
  • the input signal is sampled by the high-speed clock signal, so that the input signal passes through an M-level data flip-flop (DFF) in turn to delay the input signal.
  • the delay generated by the circuit is M*T, where T is the period of the high-speed clock signal.
  • T is the period of the high-speed clock signal.
  • the delay of the circuit is determined by the period of the high-speed clock signal.
  • the delay of the circuit is determined. Therefore, the circuit can only satisfy one protocol or one working mode in a certain protocol, and cannot be compatible with multiple protocols or multiple working modes under one protocol.
  • this method requires the introduction of high-speed clocks, which wastes chip area and increases some unpredictable risks.
  • Embodiment 1 of the present application provides a delay circuit, as shown in Fig. 3:
  • the delay circuit may include at least two branches.
  • Fig. 3 shows two branches of the first branch and the second branch. However, it is not limited to only two branches, and a third branch can exist. The first branch is connected in parallel with the second branch. If there is a third branch, the third branch is also connected in parallel with the first branch and the second branch. Each of the at least two branches has a different delay. In Figure 3, the first branch and the second branch have different delays.
  • the number of MOS tubes included in the first branch and the second branch are different.
  • the The sizes of the MOS transistors included in the first branch and the second branch are different, and optionally, the numbers and sizes of the MOS transistors included in the first branch and the second branch are different.
  • the first branch has more MOS than the second branch, so that the delays of the first branch and the second branch are different.
  • the at least two branches include at least one register, and the at least one register is used to control one of the at least two branches to be turned on, so that the delay circuit generates a delay corresponding to the turned-on branch.
  • the delay circuit only includes a first register, the first register includes a first input and a second input, and the first input and the second input are reversed.
  • the first branch includes a first PMOS tube, a second PMOS tube, a first NMOS tube, and a second NMOS tube.
  • the source of the first PMOS tube is connected to the power supply voltage
  • the drain of the first PMOS tube is connected to the source of the second PMOS tube
  • the gate of the first PMOS tube is connected to the input signal
  • the drain of the second PMOS tube is connected to the The drain of the second NMOS tube
  • the gate of the second PMOS tube is connected to the first input of the first register
  • the source of the first NMOS tube is grounded, and the drain of the first NMOS tube is connected to the second NMOS tube.
  • the source is connected, the gate of the first NMOS tube is connected to the input signal, and the gate of the second NMOS tube is connected to the second input of the first register.
  • the second branch includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube, and a fourth NMOS tube.
  • the source of the third PMOS tube is connected to the power supply voltage
  • the drain of the third PMOS tube is connected to the source of the fourth PMOS tube
  • the gate of the third PMOS tube is connected to the input signal
  • the drain of the fourth PMOS tube is connected to the The drains of the four NMOS transistors are connected, the gate of the fourth PMOS transistor is connected to the second input of the first register;
  • the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor
  • the gate of the third NMOS tube is connected to the input signal, and the gate of the fourth NMOS tube is connected to the first input of the first register.
  • the first branch is turned on.
  • the first branch is turned on and the input signal is low, the first PMOS tube is turned on, and the input signal reaches the output node of the delay circuit through the first PMOS tube and the second PMOS tube; when the first branch is turned on and When the input signal is at a high level, the first NMOS tube is turned on, and the input signal reaches the output node of the delay circuit through the first NMOS tube and the second NMOS tube.
  • the first input of the first register is 1, the second input is 0, the second PMOS tube and the second NMOS tube are both turned off, the fourth PMOS tube and the fourth NMOS tube are both turned on, and the second branch is turned on.
  • the third PMOS transistor is turned on, and the input signal reaches the output node of the delay circuit through the third and fourth PMOS transistors;
  • the second branch is turned on and When the input signal is at a high level, the third NMOS transistor is turned on, and the input signal reaches the output node of the delay circuit through the third NMOS transistor and the fourth NMOS transistor.
  • the first embodiment of the present invention provides a delay circuit, which may include a first branch and a second branch; the delay circuit includes a first register, and the first register controls the first branch and the second branch One of the branches is connected, so that the delay circuit is generated by the delay corresponding to the connected branch. Since the greater the delay of the input signal, the smaller the slew rate, so the slew rate of the input signal through the first branch and the second branch is different.
  • the output delay of the delay circuit can be controlled by controlling the connection of one of the first branch and the second branch through the first input and the second input of the first register. At the same time, only one register can be used to reduce cost.
  • the delay circuit provided in the first embodiment only includes one register.
  • the delay circuit can also include two registers, as shown in Figure 4, the second embodiment provides Another delay circuit.
  • the delay circuit includes at least two branches, and the delays of the at least two branches are different.
  • the at least two branches may include two registers, and the two registers are used to control one of the at least two branches.
  • the branch is connected, so that the delay circuit generates a delay corresponding to the connected branch.
  • the delay circuit shown in Figure 4 includes a first register and a second register. The first register controls the first branch and the second register controls the second branch. If there is a third branch, the third register is required to control the second branch. Three branches, each register controls one branch.
  • the first register includes a first input and a second input
  • the second register includes a third input and a fourth input
  • the first input and the second input are inverted
  • the third input and the fourth input are inverted.
  • the first branch includes a first PMOS tube, a second PMOS tube, a first NMOS tube, and a second NMOS tube.
  • the source of the first PMOS tube is connected to the power supply voltage
  • the drain of the first PMOS tube is connected to the source of the second PMOS tube
  • the gate of the first PMOS tube is connected to the input signal
  • the drain of the second PMOS tube is connected to the The drain of the second NMOS tube
  • the gate of the second PMOS tube is connected to the first input of the first register
  • the source of the first NMOS tube is grounded, and the drain of the first NMOS tube is connected to the second NMOS tube.
  • the source is connected, the gate of the first NMOS tube is connected to the input signal, and the gate of the second NMOS tube is connected to the second input of the first register.
  • the second branch includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube, and a fourth NMOS tube.
  • the source of the third PMOS tube is connected to the power supply voltage
  • the drain of the third PMOS tube is connected to the source of the fourth PMOS tube
  • the gate of the third PMOS tube is connected to the input signal
  • the drain of the fourth PMOS tube is connected to the The drains of the four NMOS transistors are connected, the gate of the fourth PMOS transistor is connected to the third input of the second register;
  • the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor ,
  • the gate of the third NMOS transistor is connected to the input signal, and the gate of the fourth NMOS transistor is connected to the fourth input of the second register.
  • the second input of the first register When the first input of the first register is 0, the second input is 1, the third input of the second register is 1, and the fourth input is 0, the second PMOS tube and the second NMOS tube are both turned on, and the fourth PMOS tube Both the fourth NMOS transistor and the fourth NMOS transistor are turned off, and the first branch is turned on.
  • the first branch When the first branch is turned on and the input signal is low, the first PMOS tube is turned on, and the input signal reaches the output node of the delay circuit through the first PMOS tube and the second PMOS tube; when the first branch is turned on and When the input signal is at a high level, the first NMOS tube is turned on, and the input signal reaches the output node of the delay circuit through the first NMOS tube and the second NMOS tube.
  • the second branch is turned on.
  • the third PMOS transistor is turned on, and the input signal reaches the output node of the delay circuit through the third and fourth PMOS transistors;
  • the second branch is turned on and When the input signal is at a high level, the third NMOS transistor is turned on, and the input signal reaches the output node of the delay circuit through the third NMOS transistor and the fourth NMOS transistor.
  • the second embodiment of the present invention provides a delay circuit, which may include a first branch and a second branch; the delay circuit includes a first register and a second register, the first register controls the first branch, The second register controls the second branch. If there is a third branch in the delay circuit, the delay circuit further includes a third register, and the third register controls the third branch.
  • each branch includes at least one register, and the at least one register controls the on-off of the branch.
  • only one branch is connected at a time, so that the delay circuit is generated by the delay corresponding to the connected branch.
  • the delay circuit provided by this embodiment may include two or more branches, each branch has a different delay, and each branch is provided with at least one register to control the communication of the branch. Off, can cause the delay circuit to produce two or more delays. As the delay is larger, the slew rate is smaller.
  • the delay circuit can adapt to the requirements of multiple protocols or different working modes of the same protocol for the slew rate of the circuit.
  • the above two embodiments introduced a delay circuit, and a driving device is introduced below.
  • the driving device may include the delay circuit described in the first or second embodiment.
  • the third embodiment provides a driving device.
  • the driving device includes N-stage delay circuits and N-stage drive circuits as described in the first or second embodiment, where N is an integer greater than 1, wherein the output of the N-1th stage delay circuit is respectively connected to the Nth stage The input of the delay circuit and the input of the N-1th stage drive circuit; the output of the Nth stage delay circuit is connected to the input of the Nth stage drive circuit; the N output signals of the first stage drive circuit to the Nth stage drive circuit are common It constitutes the output of the driving device.
  • the driving device when N is equal to 2, includes a two-stage delay circuit and a two-stage drive circuit.
  • the output of the first-stage delay circuit is respectively connected to the input of the second-stage delay circuit and the first-stage drive circuit.
  • the output of the second-stage delay circuit is connected to the input of the second-stage driving circuit, and the two output signals of the first-stage driving circuit and the second-stage driving circuit together constitute the output of the driving device.
  • the driving circuit includes at least one PMOS tube, at least one NMOS tube, a first resistor and a second resistor.
  • the at least one PMOS tube is connected in series with the first resistor, and the gate of the at least one PMOS tube is connected to the input signal. If there are multiple PMOS tubes, the plurality of PMOS tubes are connected in series and the gates are connected to the input signal.
  • the at least one NMOS transistor is connected in series with the second resistor, and the gate of the at least one NMOS transistor is connected to the input signal. If there are multiple NMOS transistors, the multiple NMOS transistors are connected in series.
  • the structure of the driving circuit may be a circuit structure as shown in FIG. 6, and the driving circuit may include a PMOS tube, an NMOS tube, a first resistor and a second resistor.
  • the PMOS tube is connected in series with the first resistor, the gate of the PMOS tube is connected to the input signal, the source is connected to the power supply voltage, and the drain is connected to the first resistor;
  • the NMOS tube is connected in series with the second resistor, and the gate of the NMOS tube is connected When a signal is input, the source is grounded, and the drain is connected to a second resistor, and the first resistor is connected to the second resistor.
  • the PMOS transistor When the input signal is low level, the PMOS transistor is turned on, and the input signal reaches the output node of the driving circuit through the PMOS transistor and the first resistor; when the input signal is high level, the NMOS transistor is turned on, and the input signal passes through the The NMOS tube and the second resistor reach the output node of the driving circuit.
  • the drive circuit can enhance the drive capability of the input signal.
  • the delay between the output and input signal of the driving device and the number of MOS tubes in the driving device, the size of the MOS tubes, the number of stages of the N-stage delay circuit and the N-stage drive circuit, and the number of stages in the N-stage delay circuit At least one of the delay of the branch connected by the delay circuit of each stage or the delay of the N-stage drive circuit is related.
  • the delay between the output of the driving device and the input signal may specifically be the sum of the delay of the N-stage delay circuit and the delay of the N-stage driving circuit, and the delay between the output of the driving device and the input signal is a*(T 1 +T 2 + whil+T N )+T load , where a is the correction coefficient, which is related to the size and/or quantity of the MOS tube.
  • a is the correction coefficient, which is related to the size and/or quantity of the MOS tube.
  • T 1 is the delay of the first-stage delay circuit in the N-stage delay circuit
  • T 2 is the delay of the second-stage delay circuit in the N-stage delay circuit
  • T N is the delay of the N-stage delay circuit
  • T load is the delay of the N stage drive circuit.
  • each delay circuit in the N-stage delay circuit selects the branch with the same delay
  • the delay of each delay circuit in the N-stage delay circuit is T d
  • the output of the driving device can be a*N*T d +T load .
  • a is the correction coefficient
  • N is the number of stages of the N-stage delay circuit
  • T d is the delay of each stage of the N-stage delay circuit
  • T load is the delay of the N-stage drive circuit.
  • the sum of the resistance of the N-level driving circuit can be equal to the resistance of the transmission line to reduce signal reflection.
  • the transmission line includes a section of metal wire through which the signal passes through the package and board-level wiring to the load. High-speed signals are likely to cause reflection problems, thereby affecting signal quality. If the resistance of the N-level drive circuit is not equal to the impedance of the transmission line, a part of the high-speed signals will undergo secondary reflection. When the resistance of the N-level drive circuit is equal to the impedance of the transmission line, the reflected energy will be absorbed, so that no secondary reflection will occur.
  • the driving device can also be combined with chips, transmission lines, and terminal devices to form a complete product.
  • the delay generated by the product includes not only the delay generated by the driving device, but also chips, transmission lines, and terminal devices. The delay caused by the component.
  • the size of the current is determined by the number and size of the MOS tube in the driving device. The number and size of the MOS tube in the driving device also have a certain influence on the output impedance. Therefore, on the premise that the driving device satisfies a specific protocol or the working mode of a certain protocol of the protocol, the output impedance of the driving device may not meet the conditions.
  • the third embodiment of the present invention provides a driving device, which may include an N-stage delay circuit and an N-stage driving circuit.
  • the N-level delay circuit can delay the input signal, and the N-level drive circuit can strengthen the driving ability of the input signal, so that the output of the driving device can meet different protocols or different modes of the same protocol.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)

Abstract

La présente invention concerne un circuit de retard et un dispositif d'entraînement, le circuit de retard pouvant comprendre au moins deux branches, les deux ou plus de deux branches étant connectées en parallèle, et chacune des deux ou plus de deux branches ayant un retard différent ; et le circuit de retard comprend au moins un registre, et le registre est utilisé pour commander l'une des deux branches ou plus à activer de telle sorte que le circuit de retard génère un retard correspondant à la branche qui est activée. Plus le retard d'un signal d'entrée est grand, plus la vitesse de balayage est faible. Par conséquent, la vitesse de balayage du signal d'entrée traversant l'une quelconque des deux branches ou plus est différente. Au moyen du ou des registres commandant l'une des deux branches ou plus à activer, la vitesse de balayage d'un signal de sortie peut être ajustée de telle sorte que la vitesse de balayage du signal de sortie peut être compatible avec différents protocoles ou différents modes dans le même protocole.
PCT/CN2019/078806 2019-03-20 2019-03-20 Circuit de retard et dispositif d'entraînement WO2020186471A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2019/078806 WO2020186471A1 (fr) 2019-03-20 2019-03-20 Circuit de retard et dispositif d'entraînement
CN201980094218.9A CN113574801A (zh) 2019-03-20 2019-03-20 一种延时电路以及驱动装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/078806 WO2020186471A1 (fr) 2019-03-20 2019-03-20 Circuit de retard et dispositif d'entraînement

Publications (1)

Publication Number Publication Date
WO2020186471A1 true WO2020186471A1 (fr) 2020-09-24

Family

ID=72519506

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/078806 WO2020186471A1 (fr) 2019-03-20 2019-03-20 Circuit de retard et dispositif d'entraînement

Country Status (2)

Country Link
CN (1) CN113574801A (fr)
WO (1) WO2020186471A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1612266A (zh) * 2003-10-29 2005-05-04 海力士半导体有限公司 延迟锁定环及其控制方法
CN102771049A (zh) * 2010-03-26 2012-11-07 古河电气工业株式会社 延迟控制装置
CN104299640A (zh) * 2014-09-29 2015-01-21 灿芯半导体(上海)有限公司 压摆率自适应调整的输出电路
CN104467769A (zh) * 2014-12-10 2015-03-25 芯原微电子(上海)有限公司 片上开关逐级控制电路及方法、片上信号管脚驱动电路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1612266A (zh) * 2003-10-29 2005-05-04 海力士半导体有限公司 延迟锁定环及其控制方法
CN102771049A (zh) * 2010-03-26 2012-11-07 古河电气工业株式会社 延迟控制装置
CN104299640A (zh) * 2014-09-29 2015-01-21 灿芯半导体(上海)有限公司 压摆率自适应调整的输出电路
CN104467769A (zh) * 2014-12-10 2015-03-25 芯原微电子(上海)有限公司 片上开关逐级控制电路及方法、片上信号管脚驱动电路

Also Published As

Publication number Publication date
CN113574801A (zh) 2021-10-29

Similar Documents

Publication Publication Date Title
EP3248290B1 (fr) Émetteur à conversion parallèle-série
US8415980B2 (en) Serializing transmitter
US9065399B2 (en) Programmable high-speed voltage-mode differential driver
US10943558B2 (en) EDP MIPI DSI combination architecture
US8610462B1 (en) Input-output circuit and method of improving input-output signals
US7777521B2 (en) Method and circuitry to translate a differential logic signal to a CMOS logic signal
JP2007036848A (ja) ドライバ回路
Menolfi et al. A 28Gb/s source-series terminated TX in 32nm CMOS SOI
JP2010028751A (ja) コンプリメンタリー光配線装置
US5896044A (en) Universal logic level shifting circuit and method
JP2003069413A (ja) 半導体装置、その駆動方法及びその設定方法
US6847225B2 (en) CML (current mode logic) OCD (off chip driver)—ODT (on die termination) circuit for bidirectional data transmission
US7545205B2 (en) Low power on-chip global interconnects
US6661274B1 (en) Level converter circuit
CN107210761B (zh) 串行化发射机
WO2020186471A1 (fr) Circuit de retard et dispositif d'entraînement
US5831447A (en) Output buffer with noisy/quiet voltage sources and feedback patch for noise reduction
US20130135006A1 (en) High-speed driver circuit
CN106612109A (zh) 一种振荡电路和路由设备
JP3038757B2 (ja) シフトレジスタ回路
JPH10242835A (ja) 出力回路、半導体集積回路、及び電子回路装置
CN106209068B (zh) 一种基于NoC互连的差分电荷重分布容性发送器
WO2022237886A1 (fr) Circuit de retard, circuit de génération d'impulsions, puce et serveur
US20240005965A1 (en) Circuit for receiving data, system for receiving data, and memory device
JP2001068988A (ja) 差動信号出力回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19920297

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19920297

Country of ref document: EP

Kind code of ref document: A1