WO2020182599A1 - Verfahren und vorrichtung zum betreiben einer nichtflüchtigen speichereinrichtung - Google Patents
Verfahren und vorrichtung zum betreiben einer nichtflüchtigen speichereinrichtung Download PDFInfo
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- WO2020182599A1 WO2020182599A1 PCT/EP2020/055820 EP2020055820W WO2020182599A1 WO 2020182599 A1 WO2020182599 A1 WO 2020182599A1 EP 2020055820 W EP2020055820 W EP 2020055820W WO 2020182599 A1 WO2020182599 A1 WO 2020182599A1
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- WIPO (PCT)
- Prior art keywords
- memory
- programming
- memory cells
- checking
- memory cell
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
Definitions
- the disclosure relates to a method for operating a memory device having a plurality of memory cells for non-volatile
- non-volatile storage device Storage of data (“non-volatile storage device”).
- the disclosure also relates to a device for operating a memory device having a plurality of memory cells for the non-volatile storage of data.
- Preferred embodiments relate to a method for operating a memory device having a plurality of memory cells for the non-volatile storage of data, in particular for a motor vehicle, having the following steps: checking a specifiable number of memory cells, a test result being obtained and, depending on the test result, optionally programming at least one memory cell of the predefinable number of memory cells, the steps of checking and optionally programming during operation of the
- Storage device are executed. This allows the content of
- Memory cells of the memory device are advantageously checked efficiently. In particular, errors or impending or future
- the prescribable number of memory cells comprises one or more memory cells.
- the steps of checking and / or possibly programming can thus, for example, be carried out on a single one
- Memory cell are applied.
- the steps of checking and / or possibly programming can be performed on comparatively few memory cells, in particular two to eight
- the steps of checking and / or possibly programming are carried out in test cycles, with a test cycle for example including checking and / or possibly programming at least one single memory cell.
- a test cycle for example including checking and / or possibly programming at least one single memory cell.
- a single memory cell can be checked in a test cycle.
- a comparatively small prescribable number of memory cells e.g. two to eight memory cells are checked.
- test cycles in particular chronologically one after the other (e.g. directly following one another and / or with (constant or variable) waiting times between two
- successive test cycles each of which is e.g. to a single memory cell or a comparatively small predeterminable number of memory cells or a larger number (e.g. more than eight)
- each memory cell of the memory device is subjected to a test cycle at least once, preferably several times, in particular during an operating phase (operation without intermediate deactivation) of the memory device.
- the entire memory is tested for minutes, hours, days, weeks, months and, if necessary, faulty bit cells are corrected.
- At least one further unit for example a computing device such as e.g. a computing core of a microcontroller or the like that can access the memory device.
- a computing device such as e.g. a computing core of a microcontroller or the like that can access the memory device.
- the step of checking is performed by a circuit, in particular a hardware circuit, for checking the checksum, e.g. by a bus master such as other cores in the system or DMA (direct memory access,
- Direct memory access - expansions are carried out - in particular independently of a microcontroller.
- Checking comprises the determination of at least one first variable which characterizes data receipt of at least one memory cell of the predeterminable number of memory cells. This makes it possible to assess whether programming or reprogramming should be carried out after the checking step, e.g. because an error or an impending or possibly future error was detected during the checking.
- the first variable has at least one of the following elements: a) a checksum of one associated with the at least one memory cell
- measures a), b) can also be combined with one another, e.g. the error-correcting code and the variable characterizing the electrical charge are evaluated.
- the method further comprises: comparing the first variable with a first threshold value, and, if the first variable falls below the first threshold value, programming, in particular post-programming, the at least one memory cell, in particular if the first variable does not fall below the first threshold value or is equal to the is the first threshold value, no programming, in particular post-programming, which is carried out at least one memory cell.
- the comparing can e.g. comprise determining whether by a
- the programming step in particular reprogramming, is carried out only for that memory cell or those memory cells of the predeterminable number of memory cells for which the first variable falls below the first threshold value.
- the programming step in particular reprogramming, is carried out for a single memory cell of the prescribable number of memory cells, in particular for the at least one memory cell of the prescribable number of memory cells.
- the steps of checking and / or programming, if necessary, are coordinated, in particular synchronized, with another operation of the memory device, in particular with possible accesses of the further unit to the memory device, in particular in such a way that no access conflicts with regard to the checking and / or possibly the programming with the possible accesses of the further unit occur.
- Time window is determined in which no accesses by the further unit to the memory device, in particular to at least the predeterminable number of memory cells, are carried out and / or for which no accesses by the further unit to the memory device, in particular to at least the predefinable number of memory cells, are planned are, in particular the steps of checking and / or possibly programming are carried out in the time window.
- the programming step in particular reprogramming, is carried out for a single memory cell of the prescribable number of memory cells, in particular for the at least one memory cell of the prescribable number of memory cells.
- Test result is obtained, and, depending on the test result, optionally programming at least one memory cell of the predeterminable number of memory cells, the steps of checking and optionally programming being carried out during operation of the memory device, with at least one further unit in particular during operation of the memory device can access the storage device.
- Device for performing the method is designed according to the embodiments.
- Storage Device at least partially, preferably completely, in the Storage device is integrated, for example on the same
- Semiconductor substrate is arranged as the memory device.
- the storage device is a flash memory, in particular flash EEPROM, or a phase change memory, PCM (phase change memory), FRAM
- RRAM Resistive Random Access Memory
- CBRAM conductive-bridging RAM
- MRAM magnetoresistive random access memory
- the method according to the embodiments can advantageously be used for all memories or memory types with insufficient intrinsic values (e.g. for a specifiable purpose)
- the at least one memory cell has a storage capacity of 1 bit, i.e. e.g. can assume two different states.
- the method can also be used for 3 or more bits per cell and can also be advantageously used in multilevel cell memories which, in principle, have a higher intrinsic error rate.
- the at least one memory cell has a storage capacity of more than 1 bit, e.g. 2 bits, e.g. can assume four different states.
- the system is a control device for a motor vehicle.
- Storage cell of a or the storage device Storage cell of a or the storage device.
- Figure 1 schematically shows a block diagram of a memory device according to
- FIG. 2 schematically shows a simplified flow diagram of a method according to further preferred embodiments
- FIG. 3 schematically shows a simplified flow diagram of a method according to further preferred embodiments
- FIG. 4 schematically shows a simplified flow diagram of a method according to further preferred embodiments
- FIG. 5 schematically shows a simplified flow diagram of a method according to further preferred embodiments
- Figure 6 schematically shows a time diagram according to further preferred
- FIG. 7 schematically shows a block diagram according to further preferred ones
- FIG. 1 schematically shows a block diagram of a memory device 100 according to preferred embodiments.
- the memory device 100 has a plurality of memory cells which are jointly designated by the reference symbol 102. Some of the memory cells 102 are also individually designated with the reference symbols 102a, 102b,..., 102h.
- the memory device 100 is provided for the non-volatile storage of data.
- the memory device 100 can be provided for use in a motor vehicle, e.g. assigned to a control unit for the motor vehicle.
- At least one further unit 300 for example a computing device such as e.g. a computing core of a
- Microcontrollers or the like can access the memory device 100, in particular data D in the
- Storage device 100 is a semiconductor memory, in particular a flash memory, in particular flash EEPROM, or a phase change memory, PCM (phase change memory), or an MRAM (magnetoresistive random access memory). Further technologies for providing memory cells 102 for non-volatile storage of information can also be used in further preferred embodiments.
- At least one memory cell in particular all memory cells 102, has a storage capacity of 1 bit, that is to say, for example, can assume two different states.
- at least one Memory cell in particular all memory cells 102, has a storage capacity of more than 1 bit, for example 2 bits, that is to say for example can assume four different states.
- Preferred embodiments relate to a method for operating the memory device 100, having the following steps, cf. the flowchart from FIG. 2: checking 200 a predeterminable number A1 (FIG. 1) of memory cells, with a test result PE (FIG. 2) being obtained, and, depending on the test result PE, possibly programming 202 at least one memory cell 102a, 102b, 102c, 102d of the predeterminable number A1 of memory cells.
- the programming 202 is therefore optional, in particular as a function of the test result PE.
- Storage device 100 is set up to receive and store data from the further unit 300 (FIG. 1) and / or to process read accesses from the further unit to at least some of the memory cells 102.
- the content of memory cells 102 of memory device 100 can advantageously be checked efficiently, in particular without the operation of memory device 100 being restricted in relation to the exchange D of data with further unit 300.
- the predeterminable number A1 of memory cells comprises one or more memory cells.
- a group of four is shown in FIG. 1 as an example
- Memory cells 102a, 102b, 102c, 102d combined to form the predeterminable number A1.
- the steps of checking 200 and / or possibly programming 202 can be applied, for example, to the four memory cells 102a, 102b, 102c, 102d. In further preferred embodiments, this does not restrict accesses (reading and / or writing) by the further unit 300 (FIG. 1) to other memory cells 102e, 102f,... Of the memory device 100.
- the steps of checking 200 and / or possibly programming 202 can be applied, for example, to the four memory cells 102a, 102b, 102c, 102d. In further preferred embodiments, this does not restrict accesses (reading and / or writing) by the further unit 300 (FIG. 1) to other memory cells 102e, 102f,... Of the memory device 100.
- Checking 200 and / or possibly programming 202 also for e.g. a single memory cell 102a can be employed.
- Other preferred programming 202 also for e.g. a single memory cell 102a can be employed.
- Embodiments can include the steps of checking and / or possibly
- Programming can be applied to comparatively few memory cells, in particular two to eight memory cells.
- the steps of checking 200 and / or possibly programming 202 are carried out in test cycles, with a test cycle for example including checking 200 and / or possibly programming 202 at least one single memory cell 102a.
- a test cycle for example including checking 200 and / or possibly programming 202 at least one single memory cell 102a.
- a single memory cell 102a can be checked in a test cycle. This also makes it possible to program or re-program, in particular, an individual memory cell 102a in a targeted manner, thereby increasing the reliability of the
- Memory device 100 is increased and the memory cells 102 are spared overall, since programming or programming that is not required per se.
- Memory cell of the relevant block would have to be programmed), is not applicable.
- a comparatively small prescribable number of memory cells e.g. two to eight memory cells are checked.
- test cycles in particular chronologically one after the other (e.g. directly following one another and / or with (constant or variable) waiting times between two
- successive test cycles which each relate, for example, to a single memory cell 102a or a comparatively small predeterminable number of memory cells or also a larger number (for example more than eight) memory cells of the memory device.
- at least two different test cycles relate to a different number of memory cells.
- Memory cell 102 of the memory device 100 at least once, preferably several times, in particular during an operating phase (operation without intermediate deactivation) of the memory device 100, a test cycle (e.g. comprising checking 200 (FIG. 2) and, if necessary, an
- the checking 200 includes the determination of at least one first variable G1, which characterizes a data receipt of at least one memory cell 102a of the predeterminable number A1 of memory cells. This makes it possible to assess particularly precisely whether programming 202 or reprogramming (i.e. re-programming with the same content or a new, corrected content, such as was determined after the application of an error-correcting code, e.g. ECC, for example) after the Step of checking 200 should be performed.
- ECC error-correcting code
- the first variable G1 has at least one of the following elements: a) a checksum of one associated with the at least one memory cell 102a
- a correct content of the relevant memory cell 102a can be determined for example by means of the error-correcting code and the step of (post- ) Programming 202 can be performed to refresh memory cell 102a with the proper data content.
- the first variable G1 can also be a Be a two-valued quantity that indicates whether there is an error or not.
- the comparison 201 can be correspondingly simple.
- the electrical charge of a semiconductor component e.g. a floating gate electrode of a flash memory cell
- G1 the electrical charge of a semiconductor component
- the method further comprises: comparing 201 (FIG. 3) the first variable with a first threshold value T 1, and, if the first variable G1 falls below the first threshold value T 1, programming 202, in particular reprogramming, the at least one memory cell 102a.
- This enables a reliable correction of a possibly already defective memory cell 102a or a refreshing of a memory cell 102a, which possibly threatens to become defective in the future (for example by reducing the electrical charge on the floating gate electrode of a flash memory cell, so that future Read access, for example, could lead to incorrectly read data values (eg "0" instead of "1").
- step 204 Post-programming that at least one memory cell 102a is executed.
- the at least one memory cell 102a is considered to be correct, and a branch is made to step 204 in accordance with FIG. represents an end of the current test cycle 200, 201.
- step 204 in further preferred embodiments, e.g. another test cycle take place, e.g. for a further specifiable number of (preferably different) memory cells 102e, 102f, 102g, 102h (FIG. 1)
- the step of programming 200 is only carried out for that memory cell or those memory cells of the predeterminable number A1 of memory cells for which the first variable G1 falls below the first threshold value T 1.
- writing that requires resources and may burden the relevant memory cell (s) is only carried out for those memory cells that require programming or post-programming, for example in the sense of a refresh, but not for those memory cells in which these steps 200 are not (already) required.
- This further advantageously reduces wear (for example damage to an oxide layer insulating the floating gate electrode in the case of writing or programming flash memory cells) of the memory cells.
- Storage device 100 coordinated, in particular synchronized, in particular in such a way that no access conflicts arise with regard to the checking 200 and / or the (possibly) programming 202 with the possible accesses D of the further unit 300.
- Figure 4 shows an example of this
- step 210 the coordination or synchronization described above takes place, in the case of which it is determined in the present example that the memory device 100 is currently not being acted upon by the further unit 300 in such a way that e.g. the predeterminable number A1 of memory cells can be used by the further unit 300.
- steps 200 of checking and, if necessary, of programming 202, consequently a test cycle for the prescribable number A1 of memory cells can be carried out.
- the further unit 300 can again access the prescribable number A1 of memory cells, cf. the optional step 214 from FIG. 4.
- a time window is determined, cf. Step 220, in which the further unit 300 (FIG. 1) does not access the memory device 100, in particular to at least the predeterminable number A1 of memory cells, and / or for which the further unit 300 does not access the
- Memory device 100 in particular for at least the predeterminable number A1 of memory cells, are planned, with the steps of checking 200 and / or possibly programming 202 being carried out in the time window, cf. Step 222 from FIG. 5.
- FIG. 6 shows a time diagram for this.
- An operating phase of the memory device 100 is identified with the reference symbol B. During the entire operating phase B, the further unit 300 can access the
- Access memory device 100 From time t0, two accesses 214a, 214b by the further unit 300 to the memory device 100 are shown, e.g. to the memory cells 102a, .., 102d, which last up to the time t3. From time t4, there is another access 214c by the further unit 300 to the memory device 100, e.g. back to the memory cells 102a, .., 102d.
- a time window ZF is determined between the times t1, t2 with t1> t3 and t2 ⁇ t4, in which the method according to the embodiments, cf. e.g. 2, or one or more corresponding test cycles, in particular with regard to the memory cells 102a,..., 102d, can be executed, so that the accesses 214a, 214b, 214c are not impaired.
- FIG. 1 For example, the functionality of the device 400 can also be implemented by an existing memory controller (not shown) of the memory device 100, which can be expanded accordingly for this purpose.
- FIG. 1 Further preferred embodiments relate to a system 1000 (FIG. 1) having at least one memory device 100 having a plurality of memory cells 102 and at least one device 400 according to the embodiments.
- the system 1000 is a control unit for a motor vehicle.
- the further unit 300 can be a computing core of a
- the method (cf., for example, FIG. 2) is carried out during ongoing operation of the system 1000, in particular without (additional) blocks - this can advantageously be achieved by coupling the sequence according to e.g. 2 with the running system 1000 or the access of the further unit 300.
- an error counter for a range from 1 to 0 secured by an error-correcting code, e.g. ECC reset.
- the step of checking 200 can thus include the use of a DECTED-ECC method.
- Embodiments can be carried out during operation of the memory device 100 or the system 1000 is: - Easier to set up a safety ASILD (Automotive Safety Integrity Level D) system, since the
- Output error rate for bit error consideration is significantly lower, - the risk of failures is lower - since you no longer have to wait until the control unit 1000 is in the after-run or in the start phase in order to refresh (re-program), example: a car drives a few hours - at
- Storage devices 100 is the intrinsic data retention time at higher temperatures and longer
- Run times for a number of cells in the ppm range are lower and can therefore be refreshed beforehand without them failing - possible, new non-volatile storage technologies e.g. to be used with shorter data retention times.
- error-correcting codes ECC
- DECTED-ECC triple-bit error detection and double-bit error correction
- test memory cells 102 in particular continuously, and / or a
- ECC error-correcting code
- statuses are searched for in the running system 1000 in which it is ensured that the memory does not have to be accessed for a predeterminable time (e.g. 30ps (microseconds) for PCM memory cells) (e.g. by the further unit 300), cf. . also the time window ZF shown by way of example in FIG. 6. This time window is used in further preferred embodiments in order to avoid the faulty or
- a correction of memory cells recognized as faulty or suspicious takes place before a second or third cell in the same e.g. area A1 (FIG. 1) secured by ECC, in particular DECTED-ECC, is defective.
- the entire memory area of the memory device 100 is checked over time, e.g. in the form of test cycles that only consider one or a few memory cells, which advantageously means shorter ones
- Memory cell technologies with inherently less data retention than e.g. Flash memory can be compensated.
- the method according to the embodiments, cf. e.g. steps 200, 202 of Figure 2 are executed at a rate of 120 bytes per second, e.g. a memory area of 8 MB
- error correcting codes can also be used in conjunction with margin read techniques, e.g. for the step of checking 200 (Fig. 2).
- (only) margin read techniques can also be used for the step of checking 200 (FIG. 2). At these variants do not require an evaluation or provision of an error-correcting code.
- SECDED Single Error Correction and Double Error Detection
- error-correcting codes i.a. can be used for checking 200 (FIG. 2) which allow a correction of more than two bits.
- the method according to Figure 2 can e.g. be executed in a start or run-up of the system or control device 1000.
- FIG. 7 schematically shows a block diagram according to further preferred embodiments.
- the primary execution unit 500 is e.g. a first kernel, e.g. a microcontroller.
- a DMA (direct memory access) unit 504 is provided, which can read data from the memory device 502 in a known manner and / or write it into the memory device 502, in particular without (support from) the
- a checksum unit (“CRC unit”) 506 is provided which - possibly in connection with the DMA unit 504 - accesses data, in particular a predeterminable number A1 (FIG. 1) of memory cells in the memory device 502, and in particular can carry out the step of checking 200 (FIG. 2) and / or of programming 202.
- at least one secondary execution unit 508 e.g. a further computing kernel
- the primary execution unit - can load program code and / or data from the memory device (e.g. also using the DMA unit 504) and / or can perform.
- at least one is the
- Execution units 500, 508 designed to execute the method according to the embodiments (cf., for example, FIG. 2).
- the checksum unit 506 and / or the DMA unit 504 is designed to carry out the method according to the embodiments (cf., for example, FIG. 2).
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
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Abstract
Description
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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KR1020217032229A KR20210136090A (ko) | 2019-03-12 | 2020-03-05 | 비휘발성 메모리 장치를 작동하는 방법 및 장치 |
CN202080020450.0A CN113508433A (zh) | 2019-03-12 | 2020-03-05 | 用于运行非易失性存储装置的方法和设备 |
US17/434,586 US20220137861A1 (en) | 2019-03-12 | 2020-03-05 | Method and device for operating a nonvolatile memory device |
JP2021554612A JP2022524535A (ja) | 2019-03-12 | 2020-03-05 | 不揮発性メモリ機構の動作のための方法および装置 |
EP20710105.6A EP3939043A1 (de) | 2019-03-12 | 2020-03-05 | Verfahren und vorrichtung zum betreiben einer nichtflüchtigen speichereinrichtung |
Applications Claiming Priority (2)
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DE102019203351.2A DE102019203351A1 (de) | 2019-03-12 | 2019-03-12 | Verfahren und Vorrichtung zum Betreiben einer nichtflüchtigen Speichereinrichtung |
DE102019203351.2 | 2019-03-12 |
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WO2020182599A1 true WO2020182599A1 (de) | 2020-09-17 |
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PCT/EP2020/055820 WO2020182599A1 (de) | 2019-03-12 | 2020-03-05 | Verfahren und vorrichtung zum betreiben einer nichtflüchtigen speichereinrichtung |
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US (1) | US20220137861A1 (de) |
EP (1) | EP3939043A1 (de) |
JP (1) | JP2022524535A (de) |
KR (1) | KR20210136090A (de) |
CN (1) | CN113508433A (de) |
DE (1) | DE102019203351A1 (de) |
WO (1) | WO2020182599A1 (de) |
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DE19964012A1 (de) * | 1999-12-30 | 2001-07-12 | Bosch Gmbh Robert | Verfahren und Einrichtung zum Refresh des Speicherinhalts einer Speicherzelle eines Festwertspeichers |
JP2002074999A (ja) * | 2000-08-23 | 2002-03-15 | Sharp Corp | 不揮発性半導体記憶装置 |
US6731557B2 (en) * | 2001-06-21 | 2004-05-04 | Stmicroelectronics S.R.L. | Method of refreshing an electrically erasable and programmable non-volatile memory |
JP6479617B2 (ja) * | 2015-09-15 | 2019-03-06 | ラピスセミコンダクタ株式会社 | 不揮発性メモリのデータ回復方法及びメモリ制御装置 |
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2019
- 2019-03-12 DE DE102019203351.2A patent/DE102019203351A1/de not_active Withdrawn
-
2020
- 2020-03-05 US US17/434,586 patent/US20220137861A1/en not_active Abandoned
- 2020-03-05 JP JP2021554612A patent/JP2022524535A/ja active Pending
- 2020-03-05 CN CN202080020450.0A patent/CN113508433A/zh active Pending
- 2020-03-05 WO PCT/EP2020/055820 patent/WO2020182599A1/de unknown
- 2020-03-05 EP EP20710105.6A patent/EP3939043A1/de not_active Withdrawn
- 2020-03-05 KR KR1020217032229A patent/KR20210136090A/ko unknown
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US7079422B1 (en) * | 2000-04-25 | 2006-07-18 | Samsung Electronics Co., Ltd. | Periodic refresh operations for non-volatile multiple-bit-per-cell memory |
EP1271552A2 (de) * | 2001-06-21 | 2003-01-02 | STMicroelectronics S.r.l. | Verfahren zur Auffrischung der Daten in einem elektrisch lösch- und programmierbaren nichtflüchtigen Speicher |
US20090327581A1 (en) * | 2008-06-30 | 2009-12-31 | Coulson Richard L | Nand memory |
Also Published As
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US20220137861A1 (en) | 2022-05-05 |
JP2022524535A (ja) | 2022-05-06 |
CN113508433A (zh) | 2021-10-15 |
KR20210136090A (ko) | 2021-11-16 |
DE102019203351A1 (de) | 2020-09-17 |
EP3939043A1 (de) | 2022-01-19 |
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