WO2020182000A1

WO2020182000A1 - Shift register unit, gate driving circuit and display apparatus

Info

Publication number: WO2020182000A1
Application number: PCT/CN2020/077220
Authority: WO
Inventors: 冯雪欢; 李永谦
Original assignee: 京东方科技集团股份有限公司; 合肥京东方卓印科技有限公司
Priority date: 2019-03-14
Filing date: 2020-02-28
Publication date: 2020-09-17
Also published as: CN110010078A; CN110010078B

Abstract

Provided in the present disclosure are a shift register unit, a gate driving circuit and a display apparatus. The shift register unit comprises a substrate, and a first charging transistor, first discharging transistor and first storage capacitor that are disposed on the substrate. The channel width-to-length ratio of the first discharging transistor is smaller than the channel width-to-length ratio of the first charging transistor. The substrate comprises a first rectangular region, which is provided with the length in a first direction and the width in a second direction perpendicular to the first direction. The orthographic projection of the first discharging transistor on the substrate and the orthographic projection of the first storage capacitor on the substrate are arranged in the first rectangular region along the first direction, and the orthographic projections of the first discharging transistor and the first storage capacitor on the substrate and the orthographic projection of the first charging transistor on the substrate are arranged in the first rectangular region along the second direction.

Description

Shift register unit, gate drive circuit and display device

This application claims the priority of the Chinese patent application filed on March 14, 2019 with the application number 201910192964.3, the entire content of which is incorporated into this application by reference.

Technical field

The present disclosure relates to the field of display technology, in particular to a shift register unit, a gate driving circuit and a display device.

Background technique

In thin film transistor (TFT)-based liquid crystal displays (Liquid Crystal Device, LCD) or active matrix organic light emitting displays (Active Matrix Organic Light Emitting Display, AMOLED), the array substrate gate drive circuit (Gate Drive On Array (GOA) is formed at the frame of the display panel to provide gate drive signals to each pixel row. GOA includes a plurality of cascaded shift register units, and each shift register unit is used to drive a pixel row. The size of the shift register unit in the pixel row arrangement direction is limited by the pixel size.

Summary of the invention

The present disclosure proposes a shift register unit, a gate driving circuit and a display device.

According to an aspect of the present disclosure, a shift register unit is provided. The shift register unit includes a substrate, and a first charging transistor, a first discharging transistor, and a first storage capacitor provided on the substrate. The channel aspect ratio of the first discharge transistor is smaller than the channel aspect ratio of the first charge transistor. The substrate includes a first rectangular area having a length in a first direction and a width in a second direction perpendicular to the first direction. The orthographic projection of the first discharge transistor on the substrate and the orthographic projection of the first storage capacitor on the substrate are arranged in the first rectangular area along the first direction, and the first discharge transistor and the first storage The orthographic projection of the capacitor on the substrate and the orthographic projection of the first charging transistor on the substrate are arranged in the first rectangular area along the second direction.

In some embodiments, the orthographic projections of the first discharge transistor and the first charge transistor on the substrate partially overlap in the first rectangular area.

In some embodiments, the channel of the first discharge transistor is a strip structure extending along the first direction.

In some embodiments, the channel of the first charging transistor is a strip structure extending along the first direction.

In some embodiments, the channel of the first charging transistor is an interdigital structure including a plurality of strip-shaped structures extending along the first direction.

In some embodiments, the first direction is an arrangement direction of pixels in a pixel row used for driving by the shift register unit, the second direction is perpendicular to the arrangement direction, and the width of the first rectangular area is Equal to the width of the pixels in the pixel row in the second direction.

In some embodiments, one of the first electrode and the second electrode of the first discharging transistor is multiplexed as a part of one of the first electrode and the second electrode of the first charging transistor.

In some embodiments, the shift register unit further includes a charging node, a first output signal terminal, a first charging signal terminal, and a first discharging signal terminal. The control electrode of the first charging transistor is electrically connected to the charging node, the first electrode of the first charging transistor is electrically connected to the first charging signal terminal, and the second electrode of the first charging transistor is electrically connected to the first output signal terminal. The transistor is configured to transmit the first charging signal from the first charging signal terminal to the first output signal terminal under the control of the voltage of the charging node. The control electrode of the first discharge transistor is electrically connected to the discharge node, the first electrode of the first discharge transistor is electrically connected to the first discharge signal terminal, and the second electrode of the first discharge transistor is electrically connected to the first output signal terminal. The transistor is configured to transmit the first discharge signal from the first discharge signal terminal to the first output signal terminal under the control of the voltage of the discharge node. The first terminal of the first storage capacitor is electrically connected to the charging node, and the second terminal of the first storage capacitor is electrically connected to the first output signal terminal.

In some embodiments, the shift register unit further includes a first additional discharge transistor. The orthographic projection of the first additional discharge transistor on the substrate and the orthographic projection of the first discharge transistor on the substrate are arranged in the first rectangular area along the second direction. The first discharge transistor and the first additional The orthographic projection of the discharge transistor on the substrate and the orthographic projection of the first storage capacitor on the substrate are arranged in the first rectangular area along the first direction, and the first discharge transistor and the first additional discharge transistor And the orthographic projection of the first storage capacitor on the substrate and the orthographic projection of the first charging transistor on the substrate are arranged in the first rectangular area along the second direction.

In some embodiments, the orthographic projections of the first discharge transistor, the first additional discharge transistor, and the first charge transistor on the substrate partially overlap in the first rectangular area.

In some embodiments, the channel of the first additional discharge transistor is a strip structure extending along the first direction.

In some embodiments, one of the first pole and the second pole of the first additional discharge transistor is multiplexed as one of the first pole and the second pole of the first discharge transistor.

In some embodiments, the other of the first electrode and the second electrode of the first discharging transistor is multiplexed as a part of one of the first electrode and the second electrode of the first charging transistor.

In some embodiments, the shift register unit further includes an additional discharge node and a first additional discharge signal terminal. The control electrode of the first additional discharge transistor is electrically connected to the additional discharge node, the first electrode of the first additional discharge transistor is electrically connected to the first additional discharge signal terminal, and the second electrode of the first additional discharge transistor is electrically connected to the first output signal terminal. Connected, the first additional discharge transistor is configured to transmit the first additional discharge signal from the first additional discharge signal terminal to the first output signal terminal under the control of the voltage of the additional discharge node.

In some embodiments, the shift register unit further includes a second charging transistor, a second discharging transistor, and a second storage capacitor disposed on the substrate. The channel aspect ratio of the second discharge transistor is smaller than the channel aspect ratio of the second charge transistor. The substrate further includes a second rectangular area, the second rectangular area and the first rectangular area have a common side, and the first rectangular area and the second rectangular area are mirror-symmetrical with respect to the common side. The arrangement of the second charging transistor, the second discharging transistor, and the second storage capacitor in the second rectangular area is relative to the arrangement of the first charging transistor, the first discharging transistor, and the first storage capacitor in the first rectangular area. The edges are mirror-symmetrical.

According to another aspect of the present disclosure, a gate driving circuit is provided. The gate driving circuit includes a plurality of cascaded shift register units according to any one of the above embodiments.

According to another aspect of the present disclosure, a display device is provided. The display device includes the gate driving circuit according to any one of the above embodiments.

Description of the drawings

In order to explain the embodiments of the present disclosure or the technical solutions in the prior art more clearly, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.

Fig. 1A shows a schematic circuit diagram of a single thin film transistor.

FIG. 1B shows a schematic layered structure diagram of a thin film transistor.

Figure 1C shows a schematic layout of a thin film transistor.

FIG. 1D shows another schematic layout of a thin film transistor.

Fig. 2A shows a schematic circuit diagram of a shift register unit according to an embodiment of the present disclosure.

FIG. 2B shows a schematic component layout of the output sub-circuit of the shift register unit shown in FIG. 2A.

FIG. 2C shows another schematic element layout of the output sub-circuit of the shift register unit shown in FIG. 2A.

Fig. 2D shows a schematic layout of the output sub-circuit under the component layout shown in Fig. 2C.

Fig. 3A shows a schematic circuit diagram of an output sub-circuit of a shift register unit according to another embodiment of the present disclosure.

FIG. 3B shows a schematic element layout of the output sub-circuit of the shift register unit shown in FIG. 3A.

FIG. 3C shows a schematic layout of the output sub-circuit under the component layout shown in FIG. 3B.

FIG. 4A shows a schematic circuit diagram of a first output sub-circuit and a second output sub-circuit of a shift register unit according to another embodiment of the present disclosure.

FIG. 4B shows a schematic element layout of the first output sub-circuit and the second output sub-circuit shown in FIG. 4A.

Fig. 4C shows a schematic layout of the first output sub-circuit and the second output sub-circuit in the layout shown in Fig. 4B.

FIG. 5 shows a schematic diagram of a display device according to an embodiment of the present disclosure.

detailed description

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, but not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar reference signs. In the following description, some specific embodiments are only used for descriptive purposes, and should not be construed as limiting the present disclosure, but are merely examples of the embodiments of the present disclosure. When it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted. It should be noted that the shape and size of each component in the figure do not reflect the actual size and ratio, but merely illustrate the content of the embodiment of the present disclosure.

Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The "first", "second" and similar words used in the embodiments of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components.

In addition, in the description of the embodiments of the present disclosure, the term “connected” or “electrically connected” can refer to two components directly connected or electrically connected, or can refer to two components being connected or connected via one or more other components. Electric connection. In addition, these two components can be connected or electrically connected in a wired or wireless manner.

The transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. The transistor used in the present disclosure includes a "control electrode", a "first electrode" and a "second electrode". In the embodiment using thin film transistors, the control electrode refers to the gate of the thin film transistor, the first electrode refers to one of the source and drain of the thin film transistor, and the second electrode refers to the source and drain of the thin film transistor. The other one. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged. In the following examples, an N-type thin film transistor is used as an example for description. Similarly, in other embodiments, P-type thin film transistors can also be used to implement the technical solutions of the present disclosure.

In the example of the present disclosure using N-type thin film transistors for description, the term “pull-up” is used to define transistors, nodes, signal terminals, etc. (for example, upper Pull-down transistor), the term “pull-down” is used to define transistors, nodes, signal terminals, etc. (for example, pull-down transistors) used to provide a constant low level signal to the output signal terminal. It should be understood that in the example using P-type thin film transistors, "pull up" and "pull down" should be interchanged. Those skilled in the art should understand that in the embodiments of the present disclosure, the limited term "pull up" can be interchanged with the limited term "charge", and the limited term "pull down" can be interchanged with the limited term "discharge".

The present disclosure will be described in detail below with reference to the drawings.

FIG. 1A shows a schematic circuit diagram of a single thin film transistor T1.

In FIG. 1A, the control pole of T1 is connected to the control signal terminal CON, the first pole is connected to the input signal terminal IN, and the second pole is connected to the output signal terminal OUT. T1 transmits the signal from the input signal terminal IN to the output signal terminal OUT under the control of the control signal from the control signal terminal CON.

Figure 1B shows a schematic hierarchical structure diagram of T1. In the structure shown in FIG. 1B, the substrate 110, the interlayer dielectric layer 130 and the cover layer 140 are sequentially stacked. T1 (as indicated by the dashed frame) is formed in this laminated structure, so this laminated structure can be called an array substrate. It should be understood that FIG. 1B is only an exemplary laminated structure. In other embodiments, some layers in the structure shown in FIG. 1B may be removed, or new layers may be added, which is not limited in the present disclosure.

The specific structure of T1 includes an active layer formed on the substrate 110, and the active layer includes a channel 131 and doped regions 132 located on both sides of the channel 131. A gate insulating layer 133 is formed on the active layer, and a gate 134 is formed on the gate insulating layer 133, both of which are covered on the active layer by the interlayer dielectric layer 130. The orthographic projection of the channel 131 of the active layer on the substrate 110 corresponds to the orthographic projection of the gate 134 on the substrate 110. The interlayer dielectric layer 130 also has a through hole at a position above the doped region 132, and a first electrode 135 and a second electrode 136 are formed in the through hole. The first pole 135 and the second pole 136 are respectively electrically connected to the doped regions 132 on both sides of the channel 131. As shown in FIG. 1B, in this embodiment, the transistor T1 is exemplified as having a top gate structure, but it should be understood that in other embodiments, the transistor T1 may also have a bottom gate structure or other suitable structures, neither It will affect the implementation of the embodiments of the present disclosure.

It should be pointed out that when the thin film transistor T1 is turned on, a current will be generated along the direction in which the channel 131 in FIG. 1B extends (ie, the y direction in FIG. 1B). The distance that electrons must move is defined as the channel length of the transistor T1 (ie The length of the channel 131), this direction is also referred to as the length direction of the transistor T1.

Figure 1C shows a schematic layout of T1. In the layout, the structure of the thin film transistor T1 is indicated by the channel 131, the first electrode 135 and the second electrode 136. FIG. 1C also shows a plurality of contact holes by black squares, so that the first pole 135 and the second pole 136 can be electrically connected to other layers. For example, the first pole 135 is electrically connected to the input signal terminal IN through the contact hole, and the second pole 136 is electrically connected to the output signal terminal OUT through the contact hole. In addition, the channel 131 is also electrically connected to the control signal terminal CON.

The dimension of the channel 131 in the x direction perpendicular to the y direction is called the channel width of the transistor T1, and this direction is also called the width direction of the transistor T1. The ratio of the channel width to the channel length is the channel width to length ratio of the transistor T1.

In FIG. 1C, the channel of the transistor T1 has a single stripe structure along the x direction. In other embodiments, the transistor T1 can be implemented in other layout structures.

FIG. 1D shows a layout of a thin film transistor T1 having an interdigital structure according to another embodiment. As shown in FIG. 1D, the first pole 135, the second pole 136 and the channel 131 of T1 each have an interdigital structure. The first pole 135 includes two fingers, the second pole 136 includes two fingers, and the channel 131 includes three fingers. Among them, each finger extends along the x direction.

Assuming that the channel width corresponding to each contact hole is the same, it can be seen that the channel width of the thin film transistor T1 shown in FIG. 1D is three times the channel width of the thin film transistor T1 shown in FIG. 1C.

FIG. 2A shows a schematic circuit diagram of a shift register unit 200 according to an embodiment of the present disclosure. It should be understood that the circuit structure in FIG. 2A is only an example, and in other embodiments of the present disclosure, the shift register unit may have any suitable structure. The present disclosure focuses on the structure of the output sub-circuit 210 of the shift register unit 200. The output sub-circuit 210 shown in FIG. 2A includes a first pull-up transistor Tu1, a first pull-down transistor Td1, and a first storage capacitor C1. Generally, the channel width to length ratio of the first pull-up transistor Tu1 is often much larger than that of the first pull-down transistor Td1.

Generally, the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 are sequentially arranged on the substrate along the direction in which the pixel rows on the panel extend. For example, as shown in FIG. 2B, the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 are sequentially arranged in the x direction, and the size of each element in the y direction is limited by the pixel size. Wherein, the x direction corresponds to the arrangement direction of the pixels in the pixel rows on the panel, and the y direction is perpendicular to the arrangement direction of the pixels in the pixel rows. The so-called pixel size refers to the width of the pixels in the pixel row in the y direction.

When the pixel size is determined, in order to achieve a narrower frame, it is desirable that each element of the output sub-circuit 210 covers a smaller length in the x direction (the shift register unit is located in the frame area of the panel). Therefore, the panel space utilization rate of the output sub-circuit 210 should be optimized as much as possible, that is, the area of the panel covered by the output sub-circuit 210 where no components are arranged should be reduced. In the component layout shown in FIG. 2B, in order to achieve higher space utilization, each component needs to cover the pixel size in the y direction. This requires the first pull-up transistor Tu1 and the first pull-down transistor Td1 to be implemented as an interdigital structure with multiple fingers, where each finger extends in the x direction, and the multiple fingers in each finger structure Arrange along the y direction and cover the pixel size.

On the one hand, for the first pull-down transistor Td1 with a relatively small channel width and length, in order to ensure the stability of the transistor performance, it is often undesirable to implement it as an interdigital structure with multiple short fingers, which results in the first pull-down transistor The regional space of Td1 cannot be fully utilized; on the other hand, for each transistor, the more the number of fingers in the finger structure, the shorter the length of each finger, which is not conducive to the heat dissipation of the transistor.

FIG. 2C shows another schematic component layout of the output sub-circuit 210 of the shift register unit 200 shown in FIG. 2A. The difference between the component layout in FIG. 2B is that the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 in FIG. 2C are not arranged in sequence along the x direction. In FIG. 2C, the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 in the output sub-circuit 210 are arranged in the first rectangular area 220 on the substrate.

In the first rectangular area 220, the first pull-down transistor Td1 and the first storage capacitor C1 are arranged along the x direction, and the entirety of the first pull-down transistor Td1 and the first storage capacitor C1 and the first pull-up transistor Tu1 are along the y direction. Layout. In this way, the range of each of the first pull-up transistor Tu1 and the first pull-down transistor Td1 is elongated, which not only improves the space utilization of the first pull-down transistor Td1, but also improves the first pull-up transistor Tu1 and the first pull-up transistor Td1. The heat dissipation capability of a pull-down transistor Td1. Due to the improved space utilization, the length of the output sub-circuit 210 in the x direction can be shorter, which is more conducive to the realization of a narrow frame.

It should be understood that although FIG. 2C shows the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 as non-overlapping blocks, this is to clearly illustrate the first pull-up transistor Tu1, the The positional relationship between the pull-down transistor Td1 and the first storage capacitor C1 in the first rectangular area 220 is not a specific layout. Regarding the layout of the output sub-circuit, the following will further describe in detail with reference to FIG. 2D.

FIG. 2D shows a schematic layout of the output sub-circuit 210 in the component layout shown in FIG. 2C.

As shown in FIG. 2D, the orthographic projection of the first pull-down transistor Td1 on the substrate and the orthographic projection of the first storage capacitor C1 on the substrate are arranged in the first rectangular area 220 along the x direction, and the first pull-down transistor The orthographic projection of Td1 and the first storage capacitor C1 on the substrate and the orthographic projection of the first pull-up transistor Tu1 on the substrate are arranged in the first rectangular area 220 along the y direction. The orthographic projections of the first pull-up transistor Tu1 and the first pull-down transistor Td1 on the substrate partially overlap in the first rectangular area 220, so that the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 The first rectangular area 220 is tightly covered. It should be understood that "the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 closely cover the first rectangular area 220" here does not mean that the first pull-up transistor Tu1, the first pull-down transistor Td1 and the first storage capacitor C1 are seamlessly arranged on the first rectangular area 220, but refer to the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first storage capacitor C1 when the process and structure allow The bottom is as close as possible to each other in the first rectangular area 220 without intentionally leaving blank areas on the first rectangular area 220. In fact, as shown in FIG. 2D below, for example, the first pull-up transistor Tu1, the first pull-down transistor Td1 and the first storage capacitor C1 also need to be provided with connection lines for electrical connection. "Tightly covering" does not mean that no space is provided for the connection line, but it means that the first pull-up transistor Tu1, the first pull-down transistor Td1, and the A storage capacitor C1 occupies the largest area of the first rectangular area 220 as much as possible. The "tight coverage" in the following should also be understood similarly, and will not be repeated.

In the embodiment shown in FIG. 2D, one of the first electrode and the second electrode of the first pull-down transistor Td1 (that is, the electrode of the first pull-down transistor Td1 closer to the bottom in FIG. 2D) and the first upper A part of one of the first pole and the second pole of the pull-up transistor Tu1 (ie, the electrode closer to the upper side of the first pull-up transistor Tu1 in FIG. 2D) reuses the same electrode structure. In FIG. 2D, this multiplexing The electrode structure of is shown by the overlapping part of the dashed frame representing Td1 and the dashed frame representing Tu1.

In FIG. 2D, since the channel aspect ratio of the first pull-down transistor Td1 is much smaller than that of the first pull-up transistor Tu1, it is implemented as a single finger similar to the structure in FIG. 1C. Structure, wherein the channel of the first pull-down transistor Td1 is a strip structure extending in the x direction, and one end of the channel is connected to the pull-down node PD.

In FIG. 2D, the first pull-up transistor Tu1 with a relatively large channel width and length is implemented as an interdigital structure similar to the structure in FIG. 1D, wherein the channel of the first pull-up transistor Tu1 includes a plurality of channels along the first direction. An extended strip structure (ie, interdigital), each interdigital is connected to the pull-up node PU. It should be understood that in other embodiments, the first pull-up transistor Tu1 can also be implemented as a single-finger structure.

The first pull-down transistor Td1 and the partially multiplexed electrode of the first pull-up transistor Tu1 are electrically connected to the first output signal terminal OUT1. The other electrode of the first and second electrodes of the first pull-down transistor Td1 is electrically connected to the pull-down signal terminal (ie, VSS) (in other embodiments, it may be connected to another pull-down signal terminal different from VSS). The other electrode of the first pole and the second pole of the first pull-up transistor Tu1 is electrically connected to the first pull-up signal terminal (ie, CLK1).

One end of the first storage capacitor C1 is electrically connected to the pull-up node PU, and the other end of the first storage capacitor C1 is electrically connected to the first output signal terminal OUT1. The size of the first storage capacitor C1 can be adjusted according to various factors such as the area of the orthographic projection of C1 on the substrate, the material used for making C1, and the distance between the layers.

It should be understood that the structure in FIG. 2D is only to illustrate the exemplary positional relationship between the various elements in the embodiments of the present disclosure, and the wiring connection positions between each element and each signal terminal are exemplary, and are not used to compare the present disclosure. The scope of the embodiment is limited.

FIG. 3A shows a schematic circuit diagram of the output sub-circuit 310 of the shift register unit according to another embodiment of the present disclosure. Compared with the output sub-circuit 210 shown in FIG. 2A, the output sub-circuit 310 in FIG. 3A further includes a first additional pull-down transistor Tda1. The channel width-to-length ratio of Tda1 is the same as or close to that of Td1.

As shown in FIG. 3A, the control electrode of the first additional pull-down transistor Tda1 is electrically connected to the additional pull-down node PDa, and the first electrode is electrically connected to the pull-down signal terminal VSS (in other embodiments, it may also be connected to other pull-downs different from VSS). Signal terminal), the second pole is electrically connected to the first output signal terminal OUT1. The first additional pull-down transistor Tda1 is configured to transmit the signal from the first pull-down signal terminal VSS to the first output signal terminal OUT1 under the control of the voltage of the additional pull-down node PDa.

FIG. 3B shows a schematic element layout of the output sub-circuit 310 shown in FIG. 3A. In FIG. 3B, the first pull-up transistor Tu1, the first pull-down transistor Td1, the first additional pull-down transistor Tda1, and the first storage capacitor C1 in the output sub-circuit 310 are arranged in the first rectangular area 320 on the substrate.

The orthographic projection of the first additional pull-down transistor Tda1 on the substrate and the orthographic projection of the first pull-down transistor Td1 on the substrate are arranged in the first rectangular area 320 along the y direction. Furthermore, the orthographic projection of the first pull-down transistor Td1 and the first additional pull-down transistor Tda1 on the substrate and the orthographic projection of the first storage capacitor C1 on the substrate are arranged in the first rectangular area 320 along the x direction. In addition, the orthographic projection of the first pull-down transistor Td1, the first additional pull-down transistor Tda1, and the first storage capacitor C1 on the substrate and the orthographic projection of the first pull-up transistor Tu1 on the substrate are arranged in the first rectangle along the y direction. In area 320.

It should be understood that although FIG. 3B shows the first pull-up transistor Tu1, the first pull-down transistor Td1, the first additional pull-down transistor Tda1, and the first storage capacitor C1 as non-overlapping blocks, this is to clearly illustrate the first The positional relationship of the pull-up transistor Tu1, the first pull-down transistor Td1, the first additional pull-down transistor Tda1, and the first storage capacitor C1 in the first rectangular area 220 is not a specific layout. Regarding the layout of the output sub-circuit, the following will further describe in detail with reference to FIG. 3C.

FIG. 3C shows a schematic layout under the component layout shown in FIG. 3B.

As shown in FIG. 3C, the orthographic projections of the first pull-up transistor Tu1, the first pull-down transistor Td1, and the first additional pull-down transistor Tda1 on the substrate partially overlap in the first rectangular region 320, so that the first pull-up transistor Tu1, the first pull-down transistor Td1, the first additional pull-down transistor Tda1, and the first storage capacitor C1 closely cover the first rectangular area 320.

In the embodiment shown in FIG. 3C, one of the first pole and the second pole of the first additional pull-down transistor Tda1 (ie, the electrode of the first additional pull-down transistor Tda1 closer to the bottom in FIG. 3C) is One of the first electrode and the second electrode of the pull-down transistor Td1 (ie, the electrode closer to the upper side of the first pull-down transistor Td1 in FIG. 3C) multiplexes the same electrode structure. In FIG. 3C, this multiplexed electrode structure is shown by the overlapping part of the dashed frame representing Tda1 and the dashed frame representing Td1.

The other electrode of the first and second electrodes of the first pull-down transistor Td1 (ie, the electrode of the first pull-down transistor Td1 closer to the bottom in FIG. 3C) and the first electrode of the first pull-up transistor Tu1 The same electrode structure is reused with a part of one of the second electrodes (ie, the electrode of the first pull-up transistor Tu1 closer to the upper side in FIG. 3C). In FIG. 3C, this multiplexed electrode structure is shown by the overlapping part of the dashed frame representing Td1 and the dashed frame representing Tu1.

In FIG. 3C, since the channel aspect ratio of the first pull-down transistor Td1 and the first additional pull-down transistor Tda1 is much smaller than that of the first pull-up transistor Tu1, the two are implemented as a single Refers to a structure, where the channel of the first additional pull-down transistor Tda1 is a strip structure along the x direction, one end of which is connected to the additional pull-down node PDa; the channel of the first pull-down transistor Td1 is a strip structure along the x direction, One end is connected to the pull-down node PD.

In FIG. 3C, the first pull-up transistor Tu1 with a relatively large channel width and length is implemented as an interdigitated structure, wherein the channel of the first pull-up transistor Tu1 includes a plurality of strip-shaped structures extending in the first direction (ie, crossed Finger), each finger is connected to the pull-up node PU. It should be understood that in other embodiments, the first pull-up transistor Tu1 can also be implemented as a single-finger structure.

The first additional pull-down transistor Tda1 and the multiplexed electrode in the first pull-down transistor Td1 are electrically connected to the pull-down signal terminal VSS. The other of the first pole and the second pole of the first additional pull-down transistor Tda1 is connected to the first output signal terminal OUT1.

The first pull-down transistor Td1 and the partially multiplexed electrode of the first pull-up transistor Tu1 are electrically connected to the first output signal terminal OUT1. The other electrode of the first electrode and the second electrode of the first pull-down transistor Td1 is electrically connected to the pull-down signal terminal VSS.

The other electrode of the first pole and the second pole of the first pull-up transistor Tu1 is electrically connected to the first pull-up signal terminal CLK1.

It should be understood that the structure in FIG. 3C is only to illustrate the exemplary positional relationship between the various elements in the embodiments of the present disclosure, and the wiring connection positions between each element and each signal terminal are exemplary, and are not used for comparison of the present disclosure. The scope of the embodiment is limited.

4A shows a schematic circuit diagram of the first output sub-circuit 410 and the second output sub-circuit 420 of the shift register unit according to another embodiment of the present disclosure. The first output sub-circuit 410 is the same as the output sub-circuit 210 shown in FIG. 2A. The second output sub-circuit 420 and the first output sub-circuit 410 have the same circuit structure. The second output sub-circuit 420 includes a second pull-up transistor Tu2, a second pull-down transistor Td2, and a second storage capacitor C2 provided on the substrate. The second pull-up transistor Tu2, the second pull-down transistor Td2, and the second storage capacitor C2 in the second output sub-circuit 420 respectively correspond to the first pull-up transistor Tu1 and the first pull-down transistor Td1 in the first output sub-circuit 420. And the first storage capacitor C1.

FIG. 4B shows a schematic element layout of the first output sub-circuit 410 and the second output sub-circuit 420 shown in FIG. 4A.

As shown in FIG. 4B, the substrate includes a first rectangular area 430 and a second rectangular area 440. The second rectangular area 440 and the first rectangular area 430 have a common side, and the first rectangular area 430 and the second rectangular area 440 are mirror-symmetrical with respect to the common side.

The first output sub-circuit 410 is arranged in the first rectangular area 430 and the second output sub-circuit 420 is arranged in the second rectangular area 440. The arrangement of the first output sub-circuit 410 in the first rectangular area 430 is the same as the arrangement of the output sub-circuit 210 in the first rectangular area 220 in FIG. 2C, which will not be repeated here. The arrangement of the second output sub-circuit 420 in the second rectangular area 440 and the arrangement of the first output sub-circuit 410 in the first rectangular area 430 are mirror-symmetrical with respect to the common side.

FIG. 4C shows a schematic layout of the first output sub-circuit 410 and the second output sub-circuit 420 in the component layout shown in FIG. 4B.

In FIG. 4C, the layout of the first output sub-circuit 410 is the same as the layout of the output sub-circuit 210 in FIG. 2D, and the layout of the second output sub-circuit 420 and the layout of the first output sub-circuit 410 are mirror-symmetrical. Therefore, the above explanation and description of the output sub-circuit 210 with reference to FIG. 2D are also adaptively used here, and will not be repeated.

The present disclosure also proposes a gate drive circuit including a plurality of shift register units according to embodiments of the present disclosure. Each shift register unit may include the output sub-circuit 210 described with reference to FIGS. 2A, 2C, and 2D or the output sub-circuit 310 described with reference to FIGS. 3A, 3B, and 3C, or may include the first output circuit described with reference to FIGS. The output sub-circuit 410 and the second output sub-circuit 420.

Fig. 5 shows a schematic block diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 5, the display device 500 includes a gate driving circuit 510. The gate driving circuit 510 may be implemented by the gate driving circuit according to the present disclosure as described above. The display device 500 according to the embodiment of the present disclosure may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.

The above detailed description has explained numerous embodiments by using schematic diagrams, flowcharts, and/or examples. In the case where such schematic diagrams, flowcharts and/or examples contain one or more functions and/or operations, those skilled in the art should understand that each function and/or operation in such schematic diagrams, flowcharts or examples can It can be implemented individually and/or together through various structures, hardware, software, firmware or substantially any combination of them.

Although the present disclosure has been described with reference to a few typical embodiments, it should be understood that the terms used are illustrative and exemplary rather than restrictive. Since the present disclosure can be implemented in various forms without departing from the spirit or essence of the disclosure, it should be understood that the above-mentioned embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all changes and modifications falling within the scope of the claims or their equivalents shall be covered by the appended claims.

Claims

A shift register unit includes a substrate, and a first charging transistor, a first discharging transistor, and a first storage capacitor arranged on the substrate, wherein the channel aspect ratio of the first discharging transistor is smaller than that of the first charging transistor The channel width to length ratio, where,

The substrate includes a first rectangular area having a length in a first direction and a width in a second direction perpendicular to the first direction,

The orthographic projection of the first discharge transistor on the substrate and the orthographic projection of the first storage capacitor on the substrate are arranged in the first rectangular area along the first direction, and the first discharge transistor and the first storage The orthographic projection of the capacitor on the substrate and the orthographic projection of the first charging transistor on the substrate are arranged in the first rectangular area along the second direction.
The shift register unit according to claim 1, wherein the orthographic projections of the first discharging transistor and the first charging transistor on the substrate partially overlap in the first rectangular area.
4. The shift register unit according to claim 1, wherein the channel of the first discharge transistor is a strip structure extending along the first direction.
The shift register unit according to claim 1, wherein the channel of the first charging transistor is a strip structure extending along the first direction.
4. The shift register unit according to claim 1, wherein the channel of the first charging transistor is an interdigital structure including a plurality of strip structures extending along the first direction.
3. The shift register unit according to claim 1, wherein the first direction is an arrangement direction of pixels in a pixel row used for driving by the shift register unit, and the second direction is perpendicular to the arrangement direction, The width of the first rectangular area is equal to the width of the pixels in the pixel row in the second direction.
The shift register unit according to claim 1, wherein one of the first electrode and the second electrode of the first discharge transistor is multiplexed as a part of one of the first electrode and the second electrode of the first charge transistor .
The shift register unit according to claim 1, further comprising a charging node, a first output signal terminal, a first charging signal terminal and a first discharging signal terminal,

The control electrode of the first charging transistor is electrically connected to the charging node, the first electrode of the first charging transistor is electrically connected to the first charging signal terminal, and the second electrode of the first charging transistor is electrically connected to the first output signal terminal. The transistor is configured to transmit the first charging signal from the first charging signal terminal to the first output signal terminal under the control of the voltage of the charging node,

The control electrode of the first discharge transistor is electrically connected to the discharge node, the first electrode of the first discharge transistor is electrically connected to the first discharge signal terminal, and the second electrode of the first discharge transistor is electrically connected to the first output signal terminal. The transistor is configured to transmit the first discharge signal from the first discharge signal terminal to the first output signal terminal under the control of the voltage of the discharge node,

The first terminal of the first storage capacitor is electrically connected to the charging node, and the second terminal of the first storage capacitor is electrically connected to the first output signal terminal.
The shift register unit according to claim 1, further comprising a first additional discharge transistor, wherein,

The orthographic projection of the first additional discharge transistor on the substrate and the orthographic projection of the first discharge transistor on the substrate are arranged in the first rectangular area along the second direction. The first discharge transistor and the first additional The orthographic projection of the discharge transistor on the substrate and the orthographic projection of the first storage capacitor on the substrate are arranged in the first rectangular area along the first direction, and the first discharge transistor and the first additional discharge transistor And the orthographic projection of the first storage capacitor on the substrate and the orthographic projection of the first charging transistor on the substrate are arranged in the first rectangular area along the second direction.
The shift register unit according to claim 9, wherein the orthographic projection of the first discharge transistor, the first additional discharge transistor, and the first charge transistor on the substrate is partially in the first rectangular region. overlapping.
9. The shift register unit according to claim 9, wherein the channel of the first additional discharging transistor has a strip structure extending in the first direction.
9. The shift register unit according to claim 9, wherein one of the first electrode and the second electrode of the first additional discharge transistor is multiplexed as one of the first electrode and the second electrode of the first discharge transistor.
11. The shift register unit according to claim 11, wherein the other of the first electrode and the second electrode of the first discharging transistor is multiplexed as one of the first electrode and the second electrode of the first charging transistor a part of.
The shift register unit according to claim 9, further comprising an additional discharge node and a first additional discharge signal terminal,

The control electrode of the first additional discharge transistor is electrically connected to the additional discharge node, the first electrode of the first additional discharge transistor is electrically connected to the first additional discharge signal terminal, and the second electrode of the first additional discharge transistor is electrically connected to the first output signal terminal. Connected, the first additional discharge transistor is configured to transmit the first additional discharge signal from the first additional discharge signal terminal to the first output signal terminal under the control of the voltage of the additional discharge node.
The shift register unit according to claim 1, further comprising a second charging transistor, a second discharging transistor, and a second storage capacitor disposed on the substrate, wherein the channel aspect ratio of the second discharging transistor is smaller than the second The channel width to length ratio of the charging transistor, where,

The substrate further includes a second rectangular area, the second rectangular area and the first rectangular area have a common side, and the first rectangular area and the second rectangular area are mirror-symmetrical with respect to the common side, and

The arrangement of the second charging transistor, the second discharging transistor, and the second storage capacitor in the second rectangular area is relative to the arrangement of the first charging transistor, the first discharging transistor, and the first storage capacitor in the first rectangular area. The edges are mirror-symmetrical.
A gate drive circuit comprising a plurality of cascaded shift register units according to any one of claims 1-15.
A display device comprising the gate driving circuit according to claim 16.