WO2020177222A1

WO2020177222A1 - Gate chip

Info

Publication number: WO2020177222A1
Application number: PCT/CN2019/087936
Authority: WO
Inventors: 徐京
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2019-03-06
Filing date: 2019-05-22
Publication date: 2020-09-10
Also published as: CN109859711A; CN109859711B

Abstract

Provided is a gate chip (20); by means of configuring an enable signal (EN), according to the enable signal (EN), internal control signals (DIO', CPV', UD', OE', XON') or external input signals (DIO, CPV, UD, OE, XON) of an input gate chip (20) are selected to control a shift register (21) and a logic control unit (22); thus abnormal output of the gate chip (20) when in a floating state, caused by the external input signal (DIO, CPV, UD, OE, XON) inputted to the gate chip (20), is prevented, ensuring that the gate chip (20) is in a normal state after being powered on, preventing the phenomenon of a large current in a high-level signal after power-on, effectively protecting the gate chip (20).

Description

A gate chip

Technical field

This application relates to the technical field of liquid crystal panels, and in particular to a gate chip.

Background technique

The LCD panel is deeply loved by people because of its small size, light weight and superior display quality. The circuit driving system of the liquid crystal panel generally includes a timing controller (TCON), a driver chip (Driver IC), a power manager (PWN) and a programmable gamma correction buffer circuit (P-Gamma IC). The timing controller outputs video signals to The driver chip, the power manager output voltage to the driver chip and the programmable gamma correction buffer circuit. The driving chip further includes a gate chip (Gate IC) for providing line scan signals to the liquid crystal panel and a source chip (Source IC) for providing data signals to the liquid crystal panel.

technical problem

1A and FIG. 1B, FIG. 1A is a structural diagram of a conventional gate chip, and FIG. 1B is a working sequence of the gate chip shown in FIG. 1A.

As shown in FIG. 1A, the existing gate chip 10 mainly includes a shift register (Shift Register) 11, a logic control unit (Logic Control) 12, and an output stage (Output Stage) 13. The shift register 11 is connected to the logic control unit 12, and the logic control unit 12 is connected to the output stage 13. The gate chip 10 receives input signals DIO (generally a gate start signal), CPV (generally a gate shift clock signal), and UD (generally a display mode control signal) provided by a timing controller (not shown in the figure) , OE (generally the gate output control signal) and XON (generally the fast discharge control signal), under the control of the input signals DIO, CPV, UD, OE and XON, the gate chip 10 will output rows in sequence The scan signals G1 to Gn are sequentially provided to n gate lines (not shown in the figure). Wherein, the shift register 11 sequentially shifts the gate start signal DIO according to the gate shift clock signal CPV. The logic control unit 12 performs logic operations on the output signal of the shift register 11 and the gate output control signal OE provided by the timing controller to generate an output signal. The output stage 13 uses externally input high-level signals VGH and low-level signals VGL to convert the output signal from the logic control unit 12 into an analog voltage signal suitable for driving the gate line.

In existing applications, the activation of the input signal provided by the timing controller is later than the power supply of the gate chip. That is, after the gate chip is reset, and the timing controller has not started, the external input signal input to the gate chip is in a floating state. If external interference or noise is introduced into the pin, it may cause abnormal output of the gate chip. For example, if the gate start signal DIO and the gate shift clock signal CPV are in an indeterminate state, the shift register 11 may start abnormally; the fast discharge control signal XON is in an indeterminate state, and the logic control unit 12 may output abnormally. If the pin level is higher than VIH (generally greater than 2.0V), the gate chip will recognize it as a valid high level; if the pin level is lower than VIL (generally less than 0.8V), the gate chip will recognize It is a valid low level. All of the above conditions will cause abnormal output of the gate chip, turning on multiple gate lines at the same time, resulting in a large current in the high-level signal VGH after the gate chip is powered on, which may burn the gate chip.

As shown in Figure 1B, when the power supply voltage VDD adopts 1.8V design, the gate chip will reset (Reset) when the power supply voltage VDD is powered on (Power On). When the power supply voltage VDD reaches the rated value, the reset is completed and it switches to normal State, the internal reset signal Rst (Internal Reset) of the gate chip becomes high. Since the reset of the gate chip is completed in a short time, the gate chip can work normally after the power-on is completed. Before the input signals DIO, CPV and OE provided by the timing controller arrive, the pins of the gate chip are in a floating state. Due to external interference or noise, the pins are introduced, and the pin level is higher than VIH or lower than VIL , Causing the pins to receive the actual input signals DIO', CPV' and OE' to present corresponding high/low levels. The shift register 11 starts abnormally (as shown in the figure, the output signals SR1~SR4 of the shift register 11 are high), resulting in abnormal output of the gate chip (as shown in the figure, the row scan signals G1~G4 of the gate chip are High level) to turn on multiple gate lines at the same time.

Therefore, how to avoid abnormal output of the gate chip, ensure that the gate chip is in a normal state after being powered on, and avoid the phenomenon of large current in the high-level signal after the gate chip is powered on, has become a technical problem to be solved urgently.

Technical solutions

The purpose of this application is to provide a gate chip that can avoid abnormal output of the gate chip, ensure that the gate chip is in a normal state after power-on, and avoid the phenomenon of large current in high-level signals after the gate chip is powered on, thereby effectively protecting Gate chip.

To achieve the above objective, the present application provides a gate chip, the gate chip includes: an enable unit, a shift register, a logic control unit, and an output stage; the enable unit is connected to the shift register and The logic control unit, the shift register is connected to the logic control unit, and the logic control unit is connected to the output stage; the enable unit is used to receive an enable signal and input all external components of the gate chip Input signal, the enabling unit includes a plurality of data selectors, each of the data selectors respectively receives the enable signal and an external input signal; by configuring the enable signal, the data selector will The external input signal is converted into a corresponding initial state, as the internal control signal and output, to select the internal control signal to control the shift register and the logic control unit; or by configuring the enable signal, the The data selector outputs the same control signal as the external input signal to select the external input signal to control the shift register and the logic control unit.

To achieve the above objective, the present application also provides a gate chip, the gate chip includes: an enable unit, a shift register, a logic control unit, and an output stage; the enable unit is respectively connected to the shift register And the logic control unit, the shift register is connected to the logic control unit, and the logic control unit is connected to the output stage; the enable unit is used to receive an enable signal and input all of the gate chip According to the external input signal, the internal control signal controls the shift register and the logic control unit, or the external input signal controls the shift register and the logic control unit according to the enable signal.

Beneficial effect

This application controls the shift register and logic control unit by configuring the enable signal and selecting the internal control signal or the external input signal input to the gate chip according to the enable signal to avoid inputting the external input of the gate chip The abnormal output of the gate chip caused by the signal in the floating state ensures that the gate chip is in a normal state after power-on, avoids the phenomenon of large current in the high-level signal after power-on, and effectively protects the gate chip.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

Fig. 1A, the structure diagram of the existing gate chip;

FIG. 1B is a working sequence of the gate chip shown in FIG. 1A;

FIG. 2A, the structure diagram of the gate chip of the present application;

FIG. 2B is a working sequence of the gate chip shown in FIG. 2A;

Fig. 3 is a circuit diagram of the first embodiment of the enabling unit of the present application;

Fig. 4 is a circuit diagram of the second embodiment of the enabling unit of the present application;

Fig. 5 is a circuit diagram of the third embodiment of the enabling unit of the present application.

Implementation of this application

The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions. The following embodiments described with reference to the accompanying drawings are exemplary, and are only used to explain the present application, and cannot be understood as a limitation to the present application.

In this application, unless expressly stipulated and defined otherwise, the "on" or "under" of the first feature of the second feature may include the first and second features in direct contact, or may include the first and second features Not in direct contact but through other features between them. Moreover, "above", "above" and "above" the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or it simply means that the level of the first feature is higher than the second feature. The "below", "below" and "below" the first feature of the second feature include the first feature directly below and obliquely below the second feature, or it simply means that the first feature has a lower level than the second feature.

The following disclosure provides many different embodiments or examples for realizing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the application. In addition, the present application may repeat reference numerals and/or reference letters in different examples. Such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and/or settings discussed. In addition, this application provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and/or the use of other materials.

The gate chip of this application adds an enabling unit connected to the shift register and the logic control unit. By configuring the enable signal, the internal control signal or the external input of the gate chip is selected according to the enable signal. Input signal, control shift register and logic control unit. When the external input signal input to the gate chip is in a floating state, the control signal corresponding to the initial state of the external input signal is output by the enabling unit to avoid the gate chip caused by the external input signal in the floating state. The output of the pole chip is abnormal to ensure that the gate chip is in a normal state after power-on, to avoid the phenomenon of large current in the high-level signal after power-on, and effectively protect the gate chip.

2A-2B, wherein FIG. 2A is a structural diagram of the gate chip of the present application, and FIG. 2B is a working sequence of the gate chip shown in FIG. 2A.

As shown in FIG. 2A, the gate chip 20 of the present application includes: an enabling unit 24, a shift register 21, a logic control unit 22, and an output stage 23. The enabling unit 24 is respectively connected to the shift register 21 and the The logic control unit 22, the shift register 21 is connected to the logic control unit 22, and the logic control unit 22 is connected to the output stage 23. The enabling unit 24 is configured to receive the enable signal EN and all external input signals input to the gate chip 20, and select the internal control signal or the external input signal according to the enable signal EN. The bit register 21 and the logic control unit 22.

The external input signal is the input signal DIO (generally the gate start signal), CPV (generally the gate shift clock signal), UD (generally the display mode control signal) provided by the timing controller (not shown in the figure) ), OE (generally the gate output control signal) and XON (generally the fast discharge control signal); under the control of the input signals DIO, CPV, UD, OE and XON, the gate chip 20 will sequentially output row by row The row scanning signals G1 to Gn are sequentially supplied to n gate lines (not shown in the figure).

The internal control signals may be the initial state control signals DIO', CPV', UD', OE', and XON' corresponding to the input signals DIO, CPV, UD, OE, and XON provided by the timing controller; in the internal control Under signal control, after the gate chip 20 is reset, the gate chip 20 is controlled not to start during a period of time when the timing controller has not started.

The shift register 21 is used to generate an output signal shifted clock by clock, the logic control unit 22 is used to perform a combinational logic operation on the input signal and then output, and the output stage 23 is used to input its own digital circuit. The flat signal is converted into a corresponding analog voltage signal to drive the corresponding gate line. Preferably, the output stage 23 may further include a level converter and an output amplifier; the level converter is used to convert the input digital level signal into a corresponding analog voltage signal, and the output amplifier is used to enhance the The driving capability of the analog voltage signal is to enhance the driving capability of the row scan signal output by the gate chip.

By configuring the enabling signal EN, the enabling unit 24 selects to convert all the external input signals into the corresponding initial state as the internal control signal and outputs it so that the shift register 21 and the The logic control unit 22 is controlled by a corresponding internal control signal; or by configuring the enable signal EN, the enable unit 24 selects and outputs the same control signal as all the external input signals, so that the shift register 21 and The logic control unit 22 is controlled by a corresponding external input signal. That is, after the gate chip 20 is reset, but the timing controller has not yet started, the external input signal is converted into a corresponding initial state by configuring the enable signal EN to control the gate chip 20 Not working. When the input signal provided by the timing controller has arrived and the gate chip 20 enters the normal state, the enable signal EN is configured to output the same control signal as all the external input signals; the external input signals DIO, CPV, Under the control of UD, OE and XON, the gate chip 20 will sequentially output row scanning signals G1 to Gn row by row. This ensures that when the external input signal is in a floating state, the gate chip 20 is in a stable state controlled by the internal control signal, the gate chip 20 will not start abnormally, and there is no abnormal waveform output, so as to avoid high-level signals after power-on. The current phenomenon effectively protects the gate chip.

As shown in Fig. 2B, when the power supply voltage VDD is designed with 1.8V, the gate chip 20 will be reset during the power-on phase of the power supply voltage VDD. When the power supply voltage VDD reaches the rated value, the reset is completed and it switches to In a normal state, the internal reset signal Rst (Internal Reset) of the gate chip 20 becomes a high level. Before the input signals provided by the timing controller (only DIO, CPV and OE are shown in the figure), the pins of the gate chip 20 are in a floating state, and the enable signal EN is configured (in this embodiment, the configuration The enable signal EN is at a high level), and the external input signals DIO, CPV, and OE are converted into corresponding initial states DIO', CPV', and OE' to control the gate chip 20 not to work. When the input signal provided by the timing controller has arrived and the gate chip 20 enters the normal state, the enable signal EN is configured (in this embodiment, the enable signal EN is configured to be low level), and the output is The external input signals have the same control signal (ie DIO'=DIO, CPV'=CPV and OE'=OE); under the control of the external input signals DIO, CPV, UD, OE and XON, the gate chip 20 will follow The line scan signals G1 to Gn are output sequentially and line by line. This ensures that when the external input signal is in a floating state, the gate chip 20 is in a stable state controlled by the internal control signal, the gate chip 20 will not start abnormally, and there is no abnormal waveform output, so as to avoid high-level signals after power-on. The current phenomenon effectively protects the gate chip.

Specifically, the enabling unit 24 may include a plurality of data selectors, and each of the data selectors receives the enable signal EN and an external input signal respectively, and selects the enable signal EN according to the enable signal EN. The external input signal is converted into a corresponding initial state as the internal control signal and output; or the same control signal as all the external input signals is selected to be output. Optionally, the enabling unit 24 may include a pull-up unit or a pull-down unit connected to the data selector, and the pull-up unit is configured to pull up the external input signal according to the enable signal to The external input signal is converted into a corresponding initial state as the internal control signal and output; the pull-down unit is used to pull down the external input signal according to the enable signal to convert the external input signal into a corresponding The initial state of is used as the internal control signal and output.

3, the circuit diagram of the first embodiment of the enabling unit of the present application. In this embodiment, the gate output control signal OE is taken as an example to illustrate the circuit connection mode and working principle of a data selector MUX1. Specifically, the data selector MUX1 receives the enable signal EN and the gate output control signal OE respectively, and is connected to a pull-up unit 31. After the gate chip 20 is reset, but the timing controller has not yet started, the configuration enable signal EN is high to select the gate output control signal OE to be pulled up by the pull-up unit 31 , The gate output control signal OE is converted into a high-level initial state as the internal control signal OE' and output (OE' is the initial state of OE); and the input signal provided by the timing controller has arrived When the gate chip 20 enters a normal state, the enable signal EN is configured to be a low level to select and output the same control signal (OE'=OE) as the gate output control signal OE. In other embodiments, after the gate chip 20 is reset, but the timing controller has not been activated, the configuration enable signal EN is low level to select the pull-up unit 31. The gate output control signal OE converts the gate output control signal OE into a high-level initial state as the internal control signal OE' and outputs it; and when the input signal provided by the timing controller has arrived, When the gate chip 20 enters a normal state, the enable signal EN is configured to be at a high level to select and output the same control signal as the gate output control signal OE.

In this embodiment, the pull-up unit 31 includes a pull-up resistor R1. The first end of the pull-up resistor R1 is connected to the data selector MUX1, and the second end receives a supply voltage VCC.

Referring to FIG. 4, a circuit diagram of the second embodiment of the enabling unit of the present application. The difference from the embodiment shown in FIG. 3 is that in this embodiment, the data selector MUX1 receives the enable signal EN and the gate output control signal OE respectively, and is connected to the pull-down unit 41 of. After the gate chip 20 is reset, and the timing controller has not yet started, the configuration enable signal EN is high to select the gate output control signal OE to be pulled down by the pull-down unit 41, and The gate output control signal OE is converted into a low-level initial state as the internal control signal OE' and output; and when the input signal provided by the timing controller has arrived and the gate chip 20 enters the normal state, pass The enable signal EN is configured to be a low level, so as to select and output the same control signal as the gate output control signal OE. In other embodiments, after the gate chip 20 is reset and the timing controller has not been started, the configuration enable signal EN is low level to select the pull-down unit 41 to pull down the The gate output control signal OE converts the gate output control signal OE into a low-level initial state as the internal control signal OE' and outputs it; and when the input signal provided by the timing controller has arrived, the gate When the chip 20 enters the normal state, the enable signal EN is configured to be at a high level to select and output the same control signal as the gate output control signal OE.

In this embodiment, the pull-down unit 41 includes a pull-down resistor R2, the first end of the pull-down resistor R2 is connected to the data selector MUX1, and the second end is grounded (GND).

Referring to FIG. 5, a circuit diagram of the third embodiment of the enabling unit of the present application. In this embodiment, the enabling unit 24 is connected to a gate array AND1, and the AND gate array AND1 receives the enable signal EN and all the external input signals DIO, CPV, UD, OE and XON, and combines All the external input signals DIO, CPV, UD, OE, and XON are ANDed with the enable signal EN to output corresponding control signals DIO', CPV', UD', OE', and XON'. By configuring the enable signal EN, the AND gate array AND1 can select to convert all the external input signals DIO, CPV, UD, OE, and XON into corresponding initial states as the corresponding internal control signals DIO', CPV ', UD', OE' and XON' are output. Under the control of the internal control signal, after the gate chip 20 is reset, the control gate chip 20 does not start during the period when the timing controller has not started By configuring the enable signal EN, the AND gate array AND1 can choose to output the same control signals DIO', CPV', UD', OE' and the external input signals DIO, CPV, UD, OE and XON XON', that is, directly output all the external input signals; at this time, the input signal provided by the timing controller has arrived and the gate chip 20 enters the normal state.

Industrial applicability

The subject of this application can be manufactured and used in industry and has industrial applicability.

Claims

A gate chip, wherein the gate chip includes: an enable unit, a shift register, a logic control unit, and an output stage; the enable unit is respectively connected to the shift register and the logic control unit, so The shift register is connected to the logic control unit, and the logic control unit is connected to the output stage; the enable unit is used to receive an enable signal and input all external input signals of the gate chip, the enable The unit includes a plurality of data selectors, each of the data selectors respectively receives the enable signal and an external input signal; by configuring the enable signal, the data selector converts the external input signal into a corresponding As the internal control signal and output to select the internal control signal to control the shift register and the logic control unit; or by configuring the enable signal, the data selector output The external input signal is the same control signal to select the external input signal to control the shift register and the logic control unit.
8. The gate chip of claim 1, wherein the enabling unit further comprises a pull-up unit connected to the data selector, and the pull-up unit is configured to pull up the external device according to the enable signal. The input signal is used to convert the external input signal into a corresponding initial state as the internal control signal and output.
3. The gate chip of claim 2, wherein the pull-up unit comprises a pull-up resistor, a first end of the pull-up resistor is connected to the data selector, and a second end of the pull-up resistor receives a supply voltage.
8. The gate chip of claim 1, wherein the enabling unit further comprises a pull-down unit connected to the data selector, the pull-down unit being configured to pull down the external input signal according to the enable signal, The external input signal is converted into a corresponding initial state as the internal control signal and output.
7. The gate chip of claim 4, wherein the pull-down unit comprises a pull-down resistor, a first end of the pull-down resistor is connected to the data selector, and a second end of the pull-down resistor is grounded.
The gate chip of claim 1, wherein the shift register is used to generate an output signal shifted clock by clock, and the logic control unit is used to perform a combinational logic operation on the input signal and then output it, the The output stage is used to convert the input digital level signal into a corresponding analog voltage signal to drive the corresponding gate line.
The gate chip according to claim 6, wherein the output stage comprises a level converter and an output amplifier; the level converter is used to convert the digital level signal input into the corresponding analog voltage signal , The output amplifier is used to enhance the driving capability of the analog voltage signal.
A gate chip, wherein the gate chip includes: an enable unit, a shift register, a logic control unit, and an output stage; the enable unit is respectively connected to the shift register and the logic control unit, so The shift register is connected to the logic control unit, and the logic control unit is connected to the output stage; the enabling unit is used to receive an enable signal and all external input signals input to the gate chip, according to the enable The signal can be selected to control the shift register and the logic control unit by an internal control signal, or control the shift register and the logic control unit by the external input signal.
8. The gate chip according to claim 8, wherein by configuring the enabling signal, the enabling unit selects to convert all the external input signals into corresponding initial states as the internal control signals and outputs them; Or by configuring the enabling signal, the enabling unit selects and outputs the same control signal as all the external input signals.
8. The gate chip according to claim 8, wherein the enabling unit comprises a plurality of data selectors, each of the data selectors respectively receiving the enabling signal and an external input signal, and according to the enabling unit The enable signal selects to convert the external input signal into a corresponding initial state as the internal control signal and outputs it; or selects and outputs the same control signal as all the external input signals according to the enable signal.
10. The gate chip of claim 10, wherein the enabling unit further comprises a pull-up unit connected to the data selector, and the pull-up unit is configured to pull up the external device according to the enable signal. The input signal is used to convert the external input signal into a corresponding initial state as the internal control signal and output.
11. The gate chip of claim 11, wherein the pull-up unit comprises a pull-up resistor, a first end of the pull-up resistor is connected to the data selector, and a second end of the pull-up resistor receives a supply voltage.
11. The gate chip of claim 10, wherein the enabling unit further comprises a pull-down unit connected to the data selector, and the pull-down unit is configured to pull down the external input signal according to the enable signal, The external input signal is converted into a corresponding initial state as the internal control signal and output.
15. The gate chip of claim 13, wherein the pull-down unit comprises a pull-down resistor, a first end of the pull-down resistor is connected to the data selector, and a second end of the pull-down resistor is grounded.
8. The gate chip of claim 8, wherein the enabling unit comprises an AND gate array, and the AND gate array receives the enable signal and all the external input signals, and transmits all the external input signals The signal and the enable signal are respectively ANDed and output.
8. The gate chip of claim 8, wherein the shift register is used to generate an output signal shifted clock by clock, and the logic control unit is used to perform a combinational logic operation on the input signal and then output it, the The output stage is used to convert the input digital level signal into a corresponding analog voltage signal to drive the corresponding gate line.
The gate chip according to claim 16, wherein the output stage includes a level shifter and an output amplifier; the level shifter is used to convert the digital level signal input into the corresponding analog voltage signal, so The output amplifier is used to enhance the driving capability of the analog voltage signal.